seeq8005.c revision 1.9
1 /* $NetBSD: seeq8005.c,v 1.9 2001/03/24 00:16:41 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Ben Harris 5 * Copyright (c) 1995 Mark Brinicombe 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Mark Brinicombe. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 */ 35 /* 36 * seeq8005.c - SEEQ 8005 device driver 37 */ 38 /* 39 * This driver currently supports the following chip: 40 * SEEQ 8005 Advanced Ethernet Data Link Controller 41 */ 42 /* 43 * This driver is based on the arm32 ea(4) driver, hence the names of many 44 * of the functions. 45 */ 46 /* 47 * Bugs/possible improvements: 48 * - Does not currently support DMA 49 * - Does not currently support multicasts 50 * - Does not transmit multiple packets in one go 51 * - Does not support big-endian hosts 52 * - Does not support 8-bit busses 53 */ 54 55 #include "opt_inet.h" 56 #include "opt_ns.h" 57 58 #include <sys/types.h> 59 #include <sys/param.h> 60 61 __RCSID("$NetBSD: seeq8005.c,v 1.9 2001/03/24 00:16:41 bjh21 Exp $"); 62 63 #include <sys/systm.h> 64 #include <sys/endian.h> 65 #include <sys/errno.h> 66 #include <sys/ioctl.h> 67 #include <sys/mbuf.h> 68 #include <sys/socket.h> 69 #include <sys/syslog.h> 70 #include <sys/device.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_types.h> 75 #include <net/if_ether.h> 76 77 #ifdef INET 78 #include <netinet/in.h> 79 #include <netinet/in_systm.h> 80 #include <netinet/in_var.h> 81 #include <netinet/ip.h> 82 #include <netinet/if_inarp.h> 83 #endif 84 85 #ifdef NS 86 #include <netns/ns.h> 87 #include <netns/ns_if.h> 88 #endif 89 90 #include "bpfilter.h" 91 #if NBPFILTER > 0 92 #include <net/bpf.h> 93 #include <net/bpfdesc.h> 94 #endif 95 96 #include <machine/bus.h> 97 #include <machine/intr.h> 98 99 #include <dev/ic/seeq8005reg.h> 100 #include <dev/ic/seeq8005var.h> 101 102 #ifndef EA_TIMEOUT 103 #define EA_TIMEOUT 60 104 #endif 105 106 #define EA_TX_BUFFER_SIZE 0x4000 107 #define EA_RX_BUFFER_SIZE 0xC000 108 109 /*#define EA_TX_DEBUG*/ 110 /*#define EA_RX_DEBUG*/ 111 /*#define EA_DEBUG*/ 112 /*#define EA_PACKET_DEBUG*/ 113 114 /* for debugging convenience */ 115 #ifdef EA_DEBUG 116 #define dprintf(x) printf x 117 #else 118 #define dprintf(x) 119 #endif 120 121 /* 122 * prototypes 123 */ 124 125 static int ea_init(struct ifnet *); 126 static int ea_ioctl(struct ifnet *, u_long, caddr_t); 127 static void ea_start(struct ifnet *); 128 static void ea_watchdog(struct ifnet *); 129 static void ea_chipreset(struct seeq8005_softc *); 130 static void ea_ramtest(struct seeq8005_softc *); 131 static int ea_stoptx(struct seeq8005_softc *); 132 static int ea_stoprx(struct seeq8005_softc *); 133 static void ea_stop(struct ifnet *, int); 134 static void ea_await_fifo_empty(struct seeq8005_softc *); 135 static void ea_await_fifo_full(struct seeq8005_softc *); 136 static void ea_writebuf(struct seeq8005_softc *, u_char *, u_int, size_t); 137 static void ea_readbuf(struct seeq8005_softc *, u_char *, u_int, size_t); 138 static void ea_select_buffer(struct seeq8005_softc *, int); 139 static void ea_set_address(struct seeq8005_softc *, int, const u_int8_t *); 140 static void earead(struct seeq8005_softc *, int, int); 141 static struct mbuf *eaget(struct seeq8005_softc *, int, int, struct ifnet *); 142 static void eagetpackets(struct seeq8005_softc *); 143 static void eatxpacket(struct seeq8005_softc *); 144 static void ea_mc_reset(struct seeq8005_softc *); 145 146 147 #ifdef EA_PACKET_DEBUG 148 void ea_dump_buffer(struct seeq8005_softc *, int); 149 #endif 150 151 152 #ifdef EA_PACKET_DEBUG 153 /* 154 * Dump the interface buffer 155 */ 156 157 void 158 ea_dump_buffer(struct seeq8005_softc *sc, u_int offset) 159 { 160 bus_space_tag_t iot = sc->sc_iot; 161 bus_space_handle_t ioh = sc->sc_ioh; 162 u_int addr; 163 int loop, ctrl, ptr; 164 size_t size; 165 166 addr = offset; 167 168 do { 169 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 170 sc->sc_command | EA_CMD_FIFO_READ); 171 bus_space_write_2(iot, ioh, EA_8005_CONFIG1, 172 sc->sc_config1 | EA_BUFCODE_LOCAL_MEM); 173 bus_space_write_2(iot, ioh, EA_8005_DMA_ADDR, addr); 174 175 ptr = bus_space_read_2(iot, ioh, EA_8005_BUFWIN); 176 ctrl = bus_space_read_2(iot, ioh, EA_8005_BUFWIN); 177 ptr = ((ptr & 0xff) << 8) | ((ptr >> 8) & 0xff); 178 179 if (ptr == 0) break; 180 size = ptr - addr; 181 182 printf("addr=%04x size=%04x ", addr, size); 183 printf("cmd=%02x st=%02x\n", ctrl & 0xff, ctrl >> 8); 184 185 for (loop = 0; loop < size - 4; loop += 2) 186 printf("%04x ", 187 bus_space_read_2(iot, ioh, EA_8005_BUFWIN)); 188 printf("\n"); 189 addr = ptr; 190 } while (size != 0); 191 } 192 #endif 193 194 /* 195 * Attach chip. 196 */ 197 198 void 199 seeq8005_attach(struct seeq8005_softc *sc, const u_int8_t *myaddr) 200 { 201 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 202 u_int id; 203 204 printf(" address %s", ether_sprintf(myaddr)); 205 206 /* Stop the board. */ 207 208 ea_chipreset(sc); 209 210 /* Get the product ID */ 211 212 ea_select_buffer(sc, EA_BUFCODE_PRODUCTID); 213 id = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EA_8005_BUFWIN); 214 215 if ((id & 0xf0) == 0xa0) { 216 sc->sc_flags |= SEEQ8005_80C04; 217 printf(", SEEQ 80C04 rev %02x", id); 218 } else 219 printf(", SEEQ 8005"); 220 221 /* Initialise ifnet structure. */ 222 223 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 224 ifp->if_softc = sc; 225 ifp->if_start = ea_start; 226 ifp->if_ioctl = ea_ioctl; 227 ifp->if_init = ea_init; 228 ifp->if_stop = ea_stop; 229 ifp->if_watchdog = ea_watchdog; 230 ifp->if_flags = IFF_BROADCAST | IFF_MULTICAST | IFF_NOTRAILERS; 231 IFQ_SET_READY(&ifp->if_snd); 232 233 /* Now we can attach the interface. */ 234 235 if_attach(ifp); 236 ether_ifattach(ifp, myaddr); 237 238 /* Test the RAM */ 239 ea_ramtest(sc); 240 241 printf("\n"); 242 } 243 244 245 /* 246 * Test the RAM on the ethernet card. 247 */ 248 249 void 250 ea_ramtest(struct seeq8005_softc *sc) 251 { 252 bus_space_tag_t iot = sc->sc_iot; 253 bus_space_handle_t ioh = sc->sc_ioh; 254 int loop; 255 u_int sum = 0; 256 257 /* dprintf(("ea_ramtest()\n"));*/ 258 259 /* 260 * Test the buffer memory on the board. 261 * Write simple pattens to it and read them back. 262 */ 263 264 /* Set up the whole buffer RAM for writing */ 265 266 ea_select_buffer(sc, EA_BUFCODE_TX_EAP); 267 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, (EA_BUFFER_SIZE >> 8) - 1); 268 bus_space_write_2(iot, ioh, EA_8005_TX_PTR, 0x0000); 269 bus_space_write_2(iot, ioh, EA_8005_RX_PTR, EA_BUFFER_SIZE - 2); 270 271 #define EA_RAMTEST_LOOP(value) \ 272 do { \ 273 /* Set the write start address and write a pattern */ \ 274 ea_writebuf(sc, NULL, 0x0000, 0); \ 275 for (loop = 0; loop < EA_BUFFER_SIZE; loop += 2) \ 276 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, (value)); \ 277 \ 278 /* Set the read start address and verify the pattern */ \ 279 ea_readbuf(sc, NULL, 0x0000, 0); \ 280 for (loop = 0; loop < EA_BUFFER_SIZE; loop += 2) \ 281 if (bus_space_read_2(iot, ioh, EA_8005_BUFWIN) != (value)) \ 282 ++sum; \ 283 if (sum != 0) \ 284 dprintf(("sum=%d\n", sum)); \ 285 } while (/*CONSTCOND*/0) 286 287 EA_RAMTEST_LOOP(loop); 288 EA_RAMTEST_LOOP(loop ^ (EA_BUFFER_SIZE - 1)); 289 EA_RAMTEST_LOOP(0xaa55); 290 EA_RAMTEST_LOOP(0x55aa); 291 292 /* Report */ 293 294 if (sum > 0) 295 printf("%s: buffer RAM failed self test, %d faults\n", 296 sc->sc_dev.dv_xname, sum); 297 } 298 299 300 /* 301 * Stop the tx interface. 302 * 303 * Returns 0 if the tx was already stopped or 1 if it was active 304 */ 305 306 static int 307 ea_stoptx(struct seeq8005_softc *sc) 308 { 309 bus_space_tag_t iot = sc->sc_iot; 310 bus_space_handle_t ioh = sc->sc_ioh; 311 int timeout; 312 int status; 313 314 dprintf(("ea_stoptx()\n")); 315 316 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 317 if (!(status & EA_STATUS_TX_ON)) 318 return 0; 319 320 /* Stop any tx and wait for confirmation */ 321 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 322 sc->sc_command | EA_CMD_TX_OFF); 323 324 timeout = 20000; 325 do { 326 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 327 } while ((status & EA_STATUS_TX_ON) && --timeout > 0); 328 if (timeout == 0) 329 dprintf(("ea_stoptx: timeout waiting for tx termination\n")); 330 331 /* Clear any pending tx interrupt */ 332 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 333 sc->sc_command | EA_CMD_TX_INTACK); 334 return 1; 335 } 336 337 338 /* 339 * Stop the rx interface. 340 * 341 * Returns 0 if the tx was already stopped or 1 if it was active 342 */ 343 344 static int 345 ea_stoprx(struct seeq8005_softc *sc) 346 { 347 bus_space_tag_t iot = sc->sc_iot; 348 bus_space_handle_t ioh = sc->sc_ioh; 349 int timeout; 350 int status; 351 352 dprintf(("ea_stoprx()\n")); 353 354 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 355 if (!(status & EA_STATUS_RX_ON)) 356 return 0; 357 358 /* Stop any rx and wait for confirmation */ 359 360 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 361 sc->sc_command | EA_CMD_RX_OFF); 362 363 timeout = 20000; 364 do { 365 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 366 } while ((status & EA_STATUS_RX_ON) && --timeout > 0); 367 if (timeout == 0) 368 dprintf(("ea_stoprx: timeout waiting for rx termination\n")); 369 370 /* Clear any pending rx interrupt */ 371 372 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 373 sc->sc_command | EA_CMD_RX_INTACK); 374 return 1; 375 } 376 377 378 /* 379 * Stop interface. 380 * Stop all IO and shut the interface down 381 */ 382 383 static void 384 ea_stop(struct ifnet *ifp, int disable) 385 { 386 struct seeq8005_softc *sc = ifp->if_softc; 387 bus_space_tag_t iot = sc->sc_iot; 388 bus_space_handle_t ioh = sc->sc_ioh; 389 390 dprintf(("ea_stop()\n")); 391 392 /* Stop all IO */ 393 ea_stoptx(sc); 394 ea_stoprx(sc); 395 396 /* Disable rx and tx interrupts */ 397 sc->sc_command &= (EA_CMD_RX_INTEN | EA_CMD_TX_INTEN); 398 399 /* Clear any pending interrupts */ 400 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 401 sc->sc_command | EA_CMD_RX_INTACK | 402 EA_CMD_TX_INTACK | EA_CMD_DMA_INTACK | 403 EA_CMD_BW_INTACK); 404 dprintf(("st=%08x", bus_space_read_2(iot, ioh, EA_8005_STATUS))); 405 406 /* Cancel any watchdog timer */ 407 sc->sc_ethercom.ec_if.if_timer = 0; 408 } 409 410 411 /* 412 * Reset the chip 413 * Following this the software registers are reset 414 */ 415 416 static void 417 ea_chipreset(struct seeq8005_softc *sc) 418 { 419 bus_space_tag_t iot = sc->sc_iot; 420 bus_space_handle_t ioh = sc->sc_ioh; 421 422 dprintf(("ea_chipreset()\n")); 423 424 /* Reset the controller. Min of 4us delay here */ 425 426 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, EA_CFG2_RESET); 427 delay(4); 428 429 sc->sc_command = 0; 430 sc->sc_config1 = 0; 431 sc->sc_config2 = 0; 432 } 433 434 435 /* 436 * If the DMA FIFO's in write mode, wait for it to empty. Needed when 437 * switching the FIFO from write to read. We also use it when changing 438 * the address for writes. 439 */ 440 static void 441 ea_await_fifo_empty(struct seeq8005_softc *sc) 442 { 443 bus_space_tag_t iot = sc->sc_iot; 444 bus_space_handle_t ioh = sc->sc_ioh; 445 int timeout; 446 447 timeout = 20000; 448 if ((bus_space_read_2(iot, ioh, EA_8005_STATUS) & 449 EA_STATUS_FIFO_DIR) != 0) 450 return; /* FIFO is reading anyway. */ 451 while ((bus_space_read_2(iot, ioh, EA_8005_STATUS) & 452 EA_STATUS_FIFO_EMPTY) == 0 && 453 --timeout > 0) 454 continue; 455 } 456 457 /* 458 * Wait for the DMA FIFO to fill before reading from it. 459 */ 460 static void 461 ea_await_fifo_full(struct seeq8005_softc *sc) 462 { 463 bus_space_tag_t iot = sc->sc_iot; 464 bus_space_handle_t ioh = sc->sc_ioh; 465 int timeout; 466 467 timeout = 20000; 468 while ((bus_space_read_2(iot, ioh, EA_8005_STATUS) & 469 EA_STATUS_FIFO_FULL) == 0 && 470 --timeout > 0) 471 continue; 472 } 473 474 /* 475 * write to the buffer memory on the interface 476 * 477 * The buffer address is set to ADDR. 478 * If len != 0 then data is copied from the address starting at buf 479 * to the interface buffer. 480 * BUF must be usable as a u_int16_t *. 481 * If LEN is odd, it must be safe to overwrite one extra byte. 482 */ 483 484 static void 485 ea_writebuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len) 486 { 487 bus_space_tag_t iot = sc->sc_iot; 488 bus_space_handle_t ioh = sc->sc_ioh; 489 490 dprintf(("writebuf: st=%04x\n", 491 bus_space_read_2(iot, ioh, EA_8005_STATUS))); 492 493 #ifdef DIAGNOSTIC 494 if (__predict_false(!ALIGNED_POINTER(buf, u_int16_t))) 495 panic("%s: unaligned writebuf", sc->sc_dev.dv_xname); 496 #endif 497 if (__predict_false(addr >= EA_BUFFER_SIZE)) 498 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 499 500 /* Assume that copying too much is safe. */ 501 if (len % 2 != 0) 502 len++; 503 504 ea_await_fifo_empty(sc); 505 506 ea_select_buffer(sc, EA_BUFCODE_LOCAL_MEM); 507 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 508 sc->sc_command | EA_CMD_FIFO_WRITE); 509 bus_space_write_2(iot, ioh, EA_8005_DMA_ADDR, addr); 510 511 if (len > 0) 512 bus_space_write_multi_2(iot, ioh, EA_8005_BUFWIN, 513 (u_int16_t *)buf, len / 2); 514 /* Leave FIFO to empty in the background */ 515 } 516 517 518 /* 519 * read from the buffer memory on the interface 520 * 521 * The buffer address is set to ADDR. 522 * If len != 0 then data is copied from the interface buffer to the 523 * address starting at buf. 524 * BUF must be usable as a u_int16_t *. 525 * If LEN is odd, it must be safe to overwrite one extra byte. 526 */ 527 528 static void 529 ea_readbuf(struct seeq8005_softc *sc, u_char *buf, u_int addr, size_t len) 530 { 531 532 bus_space_tag_t iot = sc->sc_iot; 533 bus_space_handle_t ioh = sc->sc_ioh; 534 535 dprintf(("readbuf: st=%04x addr=%04x len=%d\n", 536 bus_space_read_2(iot, ioh, EA_8005_STATUS), addr, len)); 537 538 #ifdef DIAGNOSTIC 539 if (!ALIGNED_POINTER(buf, u_int16_t)) 540 panic("%s: unaligned readbuf", sc->sc_dev.dv_xname); 541 #endif 542 if (addr >= EA_BUFFER_SIZE) 543 panic("%s: writebuf out of range", sc->sc_dev.dv_xname); 544 545 /* Assume that copying too much is safe. */ 546 if (len % 2 != 0) 547 len++; 548 549 ea_await_fifo_empty(sc); 550 551 ea_select_buffer(sc, EA_BUFCODE_LOCAL_MEM); 552 bus_space_write_2(iot, ioh, EA_8005_DMA_ADDR, addr); 553 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 554 sc->sc_command | EA_CMD_FIFO_READ); 555 556 ea_await_fifo_full(sc); 557 558 if (len > 0) 559 bus_space_read_multi_2(iot, ioh, EA_8005_BUFWIN, 560 (u_int16_t *)buf, len / 2); 561 } 562 563 static void 564 ea_select_buffer(struct seeq8005_softc *sc, int bufcode) 565 { 566 567 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EA_8005_CONFIG1, 568 sc->sc_config1 | bufcode); 569 } 570 571 /* Must be called at splnet */ 572 static void 573 ea_set_address(struct seeq8005_softc *sc, int which, u_int8_t const *ea) 574 { 575 int i; 576 577 ea_select_buffer(sc, EA_BUFCODE_STATION_ADDR0 + which); 578 for (i = 0; i < ETHER_ADDR_LEN; ++i) 579 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EA_8005_BUFWIN, 580 ea[i]); 581 } 582 583 /* 584 * Initialize interface. 585 * 586 * This should leave the interface in a state for packet reception and 587 * transmission. 588 */ 589 590 static int 591 ea_init(struct ifnet *ifp) 592 { 593 struct seeq8005_softc *sc = ifp->if_softc; 594 bus_space_tag_t iot = sc->sc_iot; 595 bus_space_handle_t ioh = sc->sc_ioh; 596 int s; 597 598 dprintf(("ea_init()\n")); 599 600 s = splnet(); 601 602 /* First, reset the board. */ 603 604 ea_chipreset(sc); 605 606 /* Set up defaults for the registers */ 607 608 sc->sc_command = 0x00; 609 sc->sc_config1 = 0x00; /* XXX DMA settings? */ 610 #if BYTE_ORDER == BIG_ENDIAN 611 sc->sc_config2 = EA_CFG2_BYTESWAP 612 #else 613 sc->sc_config2 = 0; 614 #endif 615 616 bus_space_write_2(iot, ioh, EA_8005_COMMAND, sc->sc_command); 617 bus_space_write_2(iot, ioh, EA_8005_CONFIG1, sc->sc_config1); 618 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 619 620 /* Split board memory into Rx and Tx. */ 621 ea_select_buffer(sc, EA_BUFCODE_TX_EAP); 622 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 623 (EA_TX_BUFFER_SIZE >> 8) - 1); 624 625 /* Write the station address - the receiver must be off */ 626 ea_set_address(sc, 0, LLADDR(ifp->if_sadl)); 627 628 /* Configure rx. */ 629 dprintf(("Configuring rx...\n")); 630 if (ifp->if_flags & IFF_PROMISC) 631 sc->sc_config1 = EA_CFG1_PROMISCUOUS; 632 else if (ifp->if_flags & IFF_ALLMULTI) 633 sc->sc_config1 = EA_CFG1_MULTICAST; 634 else 635 sc->sc_config1 = EA_CFG1_BROADCAST; 636 sc->sc_config1 |= EA_CFG1_STATION_ADDR0; 637 bus_space_write_2(iot, ioh, EA_8005_CONFIG1, sc->sc_config1); 638 639 /* Setup the Rx pointers */ 640 sc->sc_rx_ptr = EA_TX_BUFFER_SIZE; 641 642 bus_space_write_2(iot, ioh, EA_8005_RX_PTR, sc->sc_rx_ptr); 643 bus_space_write_2(iot, ioh, EA_8005_RX_END, sc->sc_rx_ptr >> 8); 644 645 646 /* Place a NULL header at the beginning of the receive area */ 647 ea_writebuf(sc, NULL, sc->sc_rx_ptr, 0); 648 649 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 650 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 651 652 653 /* Turn on Rx */ 654 sc->sc_command |= EA_CMD_RX_INTEN; 655 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 656 sc->sc_command | EA_CMD_RX_ON); 657 658 659 /* Configure TX. */ 660 dprintf(("Configuring tx...\n")); 661 662 bus_space_write_2(iot, ioh, EA_8005_TX_PTR, 0x0000); 663 664 sc->sc_config2 |= EA_CFG2_OUTPUT; 665 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 666 667 668 /* Place a NULL header at the beginning of the transmit area */ 669 ea_writebuf(sc, NULL, 0x0000, 0); 670 671 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 672 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 673 674 sc->sc_command |= EA_CMD_TX_INTEN; 675 bus_space_write_2(iot, ioh, EA_8005_COMMAND, sc->sc_command); 676 677 /* TX_ON gets set by ea_txpacket when there's something to transmit. */ 678 679 680 /* Set flags appropriately. */ 681 ifp->if_flags |= IFF_RUNNING; 682 ifp->if_flags &= ~IFF_OACTIVE; 683 684 dprintf(("init: st=%04x\n", 685 bus_space_read_2(iot, ioh, EA_8005_STATUS))); 686 687 688 /* And start output. */ 689 ea_start(ifp); 690 691 splx(s); 692 return 0; 693 } 694 695 696 /* 697 * Start output on interface. Get datagrams from the queue and output them, 698 * giving the receiver a chance between datagrams. Call only from splnet or 699 * interrupt level! 700 */ 701 702 static void 703 ea_start(struct ifnet *ifp) 704 { 705 struct seeq8005_softc *sc = ifp->if_softc; 706 int s; 707 708 s = splnet(); 709 #ifdef EA_TX_DEBUG 710 dprintf(("ea_start()...\n")); 711 #endif 712 713 /* Don't do anything if output is active. */ 714 715 if (ifp->if_flags & IFF_OACTIVE) 716 return; 717 718 /* Mark interface as output active */ 719 720 ifp->if_flags |= IFF_OACTIVE; 721 722 /* tx packets */ 723 724 eatxpacket(sc); 725 splx(s); 726 } 727 728 729 /* 730 * Transfer a packet to the interface buffer and start transmission 731 * 732 * Called at splnet() 733 */ 734 735 void 736 eatxpacket(struct seeq8005_softc *sc) 737 { 738 bus_space_tag_t iot = sc->sc_iot; 739 bus_space_handle_t ioh = sc->sc_ioh; 740 struct mbuf *m, *m0; 741 struct ifnet *ifp; 742 int len, nextpacket; 743 u_int8_t hdr[4]; 744 745 ifp = &sc->sc_ethercom.ec_if; 746 747 /* Dequeue the next packet. */ 748 IFQ_DEQUEUE(&ifp->if_snd, m0); 749 750 /* If there's nothing to send, return. */ 751 if (!m0) { 752 ifp->if_flags &= ~IFF_OACTIVE; 753 sc->sc_config2 |= EA_CFG2_OUTPUT; 754 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 755 #ifdef EA_TX_DEBUG 756 dprintf(("tx finished\n")); 757 #endif 758 return; 759 } 760 761 #if NBPFILTER > 0 762 /* Give the packet to the bpf, if any. */ 763 if (ifp->if_bpf) 764 bpf_mtap(ifp->if_bpf, m0); 765 #endif 766 767 #ifdef EA_TX_DEBUG 768 dprintf(("Tx new packet\n")); 769 #endif 770 771 sc->sc_config2 &= ~EA_CFG2_OUTPUT; 772 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 773 774 /* 775 * Copy the frame to the start of the transmit area on the card, 776 * leaving four bytes for the transmit header. 777 */ 778 len = 0; 779 for (m = m0; m; m = m->m_next) { 780 if (m->m_len == 0) 781 continue; 782 ea_writebuf(sc, mtod(m, caddr_t), 4 + len, m->m_len); 783 len += m->m_len; 784 } 785 m_freem(m0); 786 787 788 /* If packet size is odd round up to the next 16 bit boundry */ 789 if (len % 2) 790 ++len; 791 792 len = max(len, ETHER_MIN_LEN); 793 794 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN)) 795 log(LOG_WARNING, "%s: oversize packet = %d bytes\n", 796 sc->sc_dev.dv_xname, len); 797 798 #if 0 /*def EA_TX_DEBUG*/ 799 dprintf(("ea: xfr pkt length=%d...\n", len)); 800 801 dprintf(("%s-->", ether_sprintf(sc->sc_pktbuf+6))); 802 dprintf(("%s\n", ether_sprintf(sc->sc_pktbuf))); 803 #endif 804 805 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));*/ 806 807 /* Follow it with a NULL packet header */ 808 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 809 bus_space_write_2(iot, ioh, EA_8005_BUFWIN, 0x0000); 810 811 812 /* Write the packet header */ 813 814 nextpacket = len + 4; 815 hdr[0] = (nextpacket >> 8) & 0xff; 816 hdr[1] = nextpacket & 0xff; 817 hdr[2] = EA_PKTHDR_TX | EA_PKTHDR_DATA_FOLLOWS | 818 EA_TXHDR_XMIT_SUCCESS_INT | EA_TXHDR_COLLISION_INT; 819 hdr[3] = 0; /* Status byte -- will be update by hardware. */ 820 ea_writebuf(sc, hdr, 0x0000, 4); 821 822 bus_space_write_2(iot, ioh, EA_8005_TX_PTR, 0x0000); 823 824 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));*/ 825 826 #ifdef EA_PACKET_DEBUG 827 ea_dump_buffer(sc, 0); 828 #endif 829 830 831 /* Now transmit the datagram. */ 832 /* dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS)));*/ 833 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 834 sc->sc_command | EA_CMD_TX_ON); 835 #ifdef EA_TX_DEBUG 836 dprintf(("st=%04x\n", bus_space_read_2(iot, ioh, EA_8005_STATUS))); 837 dprintf(("tx: queued\n")); 838 #endif 839 } 840 841 842 /* 843 * Ethernet controller interrupt. 844 */ 845 846 int 847 seeq8005intr(void *arg) 848 { 849 struct seeq8005_softc *sc = arg; 850 bus_space_tag_t iot = sc->sc_iot; 851 bus_space_handle_t ioh = sc->sc_ioh; 852 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 853 int status, s, handled; 854 u_int8_t txhdr[4]; 855 u_int txstatus; 856 857 handled = 0; 858 dprintf(("eaintr: ")); 859 860 861 /* Get the controller status */ 862 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 863 dprintf(("st=%04x ", status)); 864 865 866 /* Tx interrupt ? */ 867 if (status & EA_STATUS_TX_INT) { 868 dprintf(("txint ")); 869 handled = 1; 870 871 /* Acknowledge the interrupt */ 872 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 873 sc->sc_command | EA_CMD_TX_INTACK); 874 875 ea_readbuf(sc, txhdr, 0x0000, 4); 876 877 #ifdef EA_TX_DEBUG 878 dprintf(("txstatus=%02x %02x %02x %02x\n", 879 txhdr[0], txhdr[1], txhdr[2], txhdr[3])); 880 #endif 881 txstatus = txhdr[3]; 882 883 /* 884 * Did it succeed ? Did we collide ? 885 * 886 * The exact proceedure here is not clear. We should get 887 * an interrupt on a sucessfull tx or on a collision. 888 * The done flag is set after successfull tx or 16 collisions 889 * We should thus get a interrupt for each of collision 890 * and the done bit should not be set. However it does appear 891 * to be set at the same time as the collision bit ... 892 * 893 * So we will count collisions and output errors and will 894 * assume that if the done bit is set the packet was 895 * transmitted. Stats may be wrong if 16 collisions occur on 896 * a packet as the done flag should be set but the packet 897 * may not have been transmitted. so the output count might 898 * not require incrementing if the 16 collisions flags is 899 * set. I don;t know abou this until it happens. 900 */ 901 902 if (txstatus & EA_TXHDR_COLLISION) 903 ifp->if_collisions++; 904 else if (txstatus & EA_TXHDR_ERROR_MASK) 905 ifp->if_oerrors++; 906 907 #if 0 908 if (txstatus & EA_TXHDR_ERROR_MASK) 909 log(LOG_WARNING, "tx packet error =%02x\n", txstatus); 910 #endif 911 912 if (txstatus & EA_PKTHDR_DONE) { 913 ifp->if_opackets++; 914 915 /* Tx next packet */ 916 917 s = splnet(); 918 eatxpacket(sc); 919 splx(s); 920 } 921 } 922 923 924 /* Rx interrupt ? */ 925 if (status & EA_STATUS_RX_INT) { 926 dprintf(("rxint ")); 927 handled = 1; 928 929 /* Acknowledge the interrupt */ 930 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 931 sc->sc_command | EA_CMD_RX_INTACK); 932 933 /* Install a watchdog timer needed atm to fixed rx lockups */ 934 ifp->if_timer = EA_TIMEOUT; 935 936 /* Processes the received packets */ 937 eagetpackets(sc); 938 939 940 #if 0 941 /* Make sure the receiver is on */ 942 if ((status & EA_STATUS_RX_ON) == 0) { 943 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 944 sc->sc_command | EA_CMD_RX_ON); 945 printf("rxintr: rx is off st=%04x\n",status); 946 } 947 #endif 948 } 949 950 #ifdef EA_DEBUG 951 status = bus_space_read_2(iot, ioh, EA_8005_STATUS); 952 dprintf(("st=%04x\n", status)); 953 #endif 954 955 return handled; 956 } 957 958 959 void 960 eagetpackets(struct seeq8005_softc *sc) 961 { 962 bus_space_tag_t iot = sc->sc_iot; 963 bus_space_handle_t ioh = sc->sc_ioh; 964 u_int addr; 965 int len; 966 int ctrl; 967 int ptr; 968 int pack; 969 int status; 970 u_int8_t rxhdr[4]; 971 struct ifnet *ifp; 972 973 ifp = &sc->sc_ethercom.ec_if; 974 975 976 /* We start from the last rx pointer position */ 977 addr = sc->sc_rx_ptr; 978 sc->sc_config2 &= ~EA_CFG2_OUTPUT; 979 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 980 981 do { 982 /* Read rx header */ 983 ea_readbuf(sc, rxhdr, addr, 4); 984 985 /* Split the packet header */ 986 ptr = (rxhdr[0] << 8) | rxhdr[1]; 987 ctrl = rxhdr[2]; 988 status = rxhdr[3]; 989 990 #ifdef EA_RX_DEBUG 991 dprintf(("addr=%04x ptr=%04x ctrl=%02x status=%02x\n", 992 addr, ptr, ctrl, status)); 993 #endif 994 995 996 /* Zero packet ptr ? then must be null header so exit */ 997 if (ptr == 0) break; 998 999 1000 /* Get packet length */ 1001 len = (ptr - addr) - 4; 1002 1003 if (len < 0) 1004 len += EA_RX_BUFFER_SIZE; 1005 1006 #ifdef EA_RX_DEBUG 1007 dprintf(("len=%04x\n", len)); 1008 #endif 1009 1010 1011 /* Has the packet rx completed ? if not then exit */ 1012 if ((status & EA_PKTHDR_DONE) == 0) 1013 break; 1014 1015 /* 1016 * Did we have any errors? then note error and go to 1017 * next packet 1018 */ 1019 if (__predict_false(status & 0x0f)) { 1020 ++ifp->if_ierrors; 1021 log(LOG_WARNING, 1022 "%s: rx packet error (%02x) - dropping packet\n", 1023 sc->sc_dev.dv_xname, status & 0x0f); 1024 sc->sc_config2 |= EA_CFG2_OUTPUT; 1025 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, 1026 sc->sc_config2); 1027 ea_init(ifp); 1028 return; 1029 } 1030 1031 /* 1032 * Is the packet too big ? - this will probably be trapped 1033 * above as a receive error 1034 */ 1035 if (__predict_false(len > (ETHER_MAX_LEN - ETHER_CRC_LEN))) { 1036 ++ifp->if_ierrors; 1037 log(LOG_WARNING, "%s: rx packet size error len=%d\n", 1038 sc->sc_dev.dv_xname, len); 1039 sc->sc_config2 |= EA_CFG2_OUTPUT; 1040 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, 1041 sc->sc_config2); 1042 ea_init(ifp); 1043 return; 1044 } 1045 1046 ifp->if_ipackets++; 1047 /* Pass data up to upper levels. */ 1048 earead(sc, addr + 4, len); 1049 1050 addr = ptr; 1051 ++pack; 1052 } while (len != 0); 1053 1054 sc->sc_config2 |= EA_CFG2_OUTPUT; 1055 bus_space_write_2(iot, ioh, EA_8005_CONFIG2, sc->sc_config2); 1056 1057 #ifdef EA_RX_DEBUG 1058 dprintf(("new rx ptr=%04x\n", addr)); 1059 #endif 1060 1061 1062 /* Store new rx pointer */ 1063 sc->sc_rx_ptr = addr; 1064 bus_space_write_2(iot, ioh, EA_8005_RX_END, sc->sc_rx_ptr >> 8); 1065 1066 /* Make sure the receiver is on */ 1067 bus_space_write_2(iot, ioh, EA_8005_COMMAND, 1068 sc->sc_command | EA_CMD_RX_ON); 1069 1070 } 1071 1072 1073 /* 1074 * Pass a packet up to the higher levels. 1075 */ 1076 1077 static void 1078 earead(struct seeq8005_softc *sc, int addr, int len) 1079 { 1080 struct mbuf *m; 1081 struct ifnet *ifp; 1082 1083 ifp = &sc->sc_ethercom.ec_if; 1084 1085 /* Pull packet off interface. */ 1086 m = eaget(sc, addr, len, ifp); 1087 if (m == 0) 1088 return; 1089 1090 #ifdef EA_RX_DEBUG 1091 dprintf(("%s-->", ether_sprintf(eh->ether_shost))); 1092 dprintf(("%s\n", ether_sprintf(eh->ether_dhost))); 1093 #endif 1094 1095 #if NBPFILTER > 0 1096 /* 1097 * Check if there's a BPF listener on this interface. 1098 * If so, hand off the raw packet to bpf. 1099 */ 1100 if (ifp->if_bpf) 1101 bpf_mtap(ifp->if_bpf, m); 1102 #endif 1103 1104 (*ifp->if_input)(ifp, m); 1105 } 1106 1107 /* 1108 * Pull read data off a interface. Len is length of data, with local net 1109 * header stripped. We copy the data into mbufs. When full cluster sized 1110 * units are present we copy into clusters. 1111 */ 1112 1113 struct mbuf * 1114 eaget(struct seeq8005_softc *sc, int addr, int totlen, struct ifnet *ifp) 1115 { 1116 struct mbuf *top, **mp, *m; 1117 int len; 1118 u_int cp, epkt; 1119 1120 cp = addr; 1121 epkt = cp + totlen; 1122 1123 MGETHDR(m, M_DONTWAIT, MT_DATA); 1124 if (m == 0) 1125 return 0; 1126 m->m_pkthdr.rcvif = ifp; 1127 m->m_pkthdr.len = totlen; 1128 m->m_len = MHLEN; 1129 top = 0; 1130 mp = ⊤ 1131 1132 while (totlen > 0) { 1133 if (top) { 1134 MGET(m, M_DONTWAIT, MT_DATA); 1135 if (m == 0) { 1136 m_freem(top); 1137 return 0; 1138 } 1139 m->m_len = MLEN; 1140 } 1141 len = min(totlen, epkt - cp); 1142 if (len >= MINCLSIZE) { 1143 MCLGET(m, M_DONTWAIT); 1144 if (m->m_flags & M_EXT) 1145 m->m_len = len = min(len, MCLBYTES); 1146 else 1147 len = m->m_len; 1148 } else { 1149 /* 1150 * Place initial small packet/header at end of mbuf. 1151 */ 1152 if (len < m->m_len) { 1153 if (top == 0 && len + max_linkhdr <= m->m_len) 1154 m->m_data += max_linkhdr; 1155 m->m_len = len; 1156 } else 1157 len = m->m_len; 1158 } 1159 if (top == 0) { 1160 /* Make sure the payload is aligned */ 1161 caddr_t newdata = (caddr_t) 1162 ALIGN(m->m_data + sizeof(struct ether_header)) - 1163 sizeof(struct ether_header); 1164 len -= newdata - m->m_data; 1165 m->m_len = len; 1166 m->m_data = newdata; 1167 } 1168 ea_readbuf(sc, mtod(m, u_char *), 1169 cp < EA_BUFFER_SIZE ? cp : cp - EA_RX_BUFFER_SIZE, 1170 len); 1171 cp += len; 1172 *mp = m; 1173 mp = &m->m_next; 1174 totlen -= len; 1175 if (cp == epkt) 1176 cp = addr; 1177 } 1178 1179 return top; 1180 } 1181 1182 /* 1183 * Process an ioctl request. Mostly boilerplate. 1184 */ 1185 static int 1186 ea_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1187 { 1188 struct seeq8005_softc *sc = ifp->if_softc; 1189 int s, error = 0; 1190 1191 s = splnet(); 1192 switch (cmd) { 1193 1194 default: 1195 error = ether_ioctl(ifp, cmd, data); 1196 if (error == ENETRESET) { 1197 /* 1198 * Multicast list has changed; set the hardware filter 1199 * accordingly. 1200 */ 1201 ea_mc_reset(sc); 1202 error = 0; 1203 } 1204 break; 1205 } 1206 1207 splx(s); 1208 return error; 1209 } 1210 1211 /* Must be called at splnet() */ 1212 static void 1213 ea_mc_reset(struct seeq8005_softc *sc) 1214 { 1215 struct ether_multi *enm; 1216 struct ether_multistep step; 1217 int naddr, maxaddrs; 1218 1219 naddr = 0; 1220 maxaddrs = (sc->sc_flags & SEEQ8005_80C04) ? 5 : 0; 1221 ETHER_FIRST_MULTI(step, &sc->sc_ethercom, enm); 1222 while (enm != NULL) { 1223 /* Have we got space? */ 1224 if (naddr >= maxaddrs || 1225 bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1226 sc->sc_ethercom.ec_if.if_flags |= IFF_ALLMULTI; 1227 ea_ioctl(&sc->sc_ethercom.ec_if, SIOCSIFFLAGS, NULL); 1228 return; 1229 } 1230 ea_set_address(sc, naddr, enm->enm_addrlo); 1231 sc->sc_config1 |= EA_CFG1_STATION_ADDR0 << naddr; 1232 naddr++; 1233 ETHER_NEXT_MULTI(step, enm); 1234 } 1235 for (; naddr < maxaddrs; naddr++) 1236 sc->sc_config1 &= ~(EA_CFG1_STATION_ADDR0 << naddr); 1237 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EA_8005_CONFIG1, 1238 sc->sc_config1); 1239 } 1240 1241 /* 1242 * Device timeout routine. 1243 * 1244 * Ok I am not sure exactly how the device timeout should work.... 1245 * Currently what will happens is that that the device timeout is only 1246 * set when a packet it received. This indicates we are on an active 1247 * network and thus we should expect more packets. If non arrive in 1248 * in the timeout period then we reinitialise as we may have jammed. 1249 * We zero the timeout at this point so that we don't end up with 1250 * an endless stream of timeouts if the network goes down. 1251 */ 1252 1253 static void 1254 ea_watchdog(struct ifnet *ifp) 1255 { 1256 struct seeq8005_softc *sc = ifp->if_softc; 1257 1258 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1259 ifp->if_oerrors++; 1260 dprintf(("ea_watchdog: ")); 1261 dprintf(("st=%04x\n", 1262 bus_space_read_2(sc->sc_iot, sc->sc_ioh, EA_8005_STATUS))); 1263 1264 /* Kick the interface */ 1265 1266 ea_init(ifp); 1267 1268 /* ifp->if_timer = EA_TIMEOUT;*/ 1269 ifp->if_timer = 0; 1270 } 1271 1272 /* End of if_ea.c */ 1273
Indexes created Tue Sep 30 07:10:03 GMT 2025