sgec.c revision 1.3
1 /* $NetBSD: sgec.c,v 1.3 2000/05/20 18:33:18 matt Exp $ */ 2 /* 3 * Copyright (c) 1999 Ludd, University of Lule}, Sweden. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed at Ludd, University of 16 * Lule}, Sweden and its contributors. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the SGEC (Second Generation Ethernet Controller), sitting 34 * on for example the VAX 4000/300 (KA670). 35 * 36 * The SGEC looks like a mixture of the DEQNA and the TULIP. Fun toy. 37 * 38 * Even though the chip is capable to use virtual addresses (read the 39 * System Page Table directly) this driver doesn't do so, and there 40 * is no benefit in doing it either in NetBSD of today. 41 * 42 * Things that is still to do: 43 * Collect statistics. 44 * Use imperfect filtering when many multicast addresses. 45 */ 46 47 #include "opt_inet.h" 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/mbuf.h> 52 #include <sys/socket.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 #include <sys/sockio.h> 56 57 #include <net/if.h> 58 #include <net/if_ether.h> 59 #include <net/if_dl.h> 60 61 #include <netinet/in.h> 62 #include <netinet/if_inarp.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #include <net/bpfdesc.h> 67 #endif 68 69 #include <machine/bus.h> 70 71 #include <dev/ic/sgecreg.h> 72 #include <dev/ic/sgecvar.h> 73 74 static void zeinit __P((struct ze_softc *)); 75 static void zestart __P((struct ifnet *)); 76 static int zeioctl __P((struct ifnet *, u_long, caddr_t)); 77 static int ze_add_rxbuf __P((struct ze_softc *, int)); 78 static void ze_setup __P((struct ze_softc *)); 79 static void zetimeout __P((struct ifnet *)); 80 static int zereset __P((struct ze_softc *)); 81 82 #define ZE_WCSR(csr, val) \ 83 bus_space_write_4(sc->sc_iot, sc->sc_ioh, csr, val) 84 #define ZE_RCSR(csr) \ 85 bus_space_read_4(sc->sc_iot, sc->sc_ioh, csr) 86 87 /* 88 * Interface exists: make available by filling in network interface 89 * record. System will initialize the interface when it is ready 90 * to accept packets. 91 */ 92 void 93 sgec_attach(sc) 94 struct ze_softc *sc; 95 { 96 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 97 struct ze_tdes *tp; 98 struct ze_rdes *rp; 99 bus_dma_segment_t seg; 100 int i, rseg, error; 101 102 /* 103 * Allocate DMA safe memory for descriptors and setup memory. 104 */ 105 if ((error = bus_dmamem_alloc(sc->sc_dmat, 106 sizeof(struct ze_cdata), NBPG, 0, &seg, 1, &rseg, 107 BUS_DMA_NOWAIT)) != 0) { 108 printf(": unable to allocate control data, error = %d\n", 109 error); 110 goto fail_0; 111 } 112 113 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 114 sizeof(struct ze_cdata), (caddr_t *)&sc->sc_zedata, 115 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 116 printf(": unable to map control data, error = %d\n", error); 117 goto fail_1; 118 } 119 120 if ((error = bus_dmamap_create(sc->sc_dmat, 121 sizeof(struct ze_cdata), 1, 122 sizeof(struct ze_cdata), 0, BUS_DMA_NOWAIT, 123 &sc->sc_cmap)) != 0) { 124 printf(": unable to create control data DMA map, error = %d\n", 125 error); 126 goto fail_2; 127 } 128 129 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmap, 130 sc->sc_zedata, sizeof(struct ze_cdata), NULL, 131 BUS_DMA_NOWAIT)) != 0) { 132 printf(": unable to load control data DMA map, error = %d\n", 133 error); 134 goto fail_3; 135 } 136 137 /* 138 * Zero the newly allocated memory. 139 */ 140 bzero(sc->sc_zedata, sizeof(struct ze_cdata)); 141 /* 142 * Create the transmit descriptor DMA maps. 143 */ 144 for (i = 0; i < TXDESCS; i++) { 145 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 146 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 147 &sc->sc_xmtmap[i]))) { 148 printf(": unable to create tx DMA map %d, error = %d\n", 149 i, error); 150 goto fail_4; 151 } 152 } 153 154 /* 155 * Create receive buffer DMA maps. 156 */ 157 for (i = 0; i < RXDESCS; i++) { 158 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 159 MCLBYTES, 0, BUS_DMA_NOWAIT, 160 &sc->sc_rcvmap[i]))) { 161 printf(": unable to create rx DMA map %d, error = %d\n", 162 i, error); 163 goto fail_5; 164 } 165 } 166 /* 167 * Pre-allocate the receive buffers. 168 */ 169 for (i = 0; i < RXDESCS; i++) { 170 if ((error = ze_add_rxbuf(sc, i)) != 0) { 171 printf(": unable to allocate or map rx buffer %d\n," 172 " error = %d\n", i, error); 173 goto fail_6; 174 } 175 } 176 177 /* 178 * Create ring loops of the buffer chains. 179 * This is only done once. 180 */ 181 sc->sc_pzedata = (struct ze_cdata *)sc->sc_cmap->dm_segs[0].ds_addr; 182 183 rp = sc->sc_zedata->zc_recv; 184 rp[RXDESCS].ze_framelen = ZE_FRAMELEN_OW; 185 rp[RXDESCS].ze_rdes1 = ZE_RDES1_CA; 186 rp[RXDESCS].ze_bufaddr = (char *)sc->sc_pzedata->zc_recv; 187 188 tp = sc->sc_zedata->zc_xmit; 189 tp[TXDESCS].ze_tdr = ZE_TDR_OW; 190 tp[TXDESCS].ze_tdes1 = ZE_TDES1_CA; 191 tp[TXDESCS].ze_bufaddr = (char *)sc->sc_pzedata->zc_xmit; 192 193 if (zereset(sc)) 194 return; 195 196 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 197 ifp->if_softc = sc; 198 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 199 ifp->if_start = zestart; 200 ifp->if_ioctl = zeioctl; 201 ifp->if_watchdog = zetimeout; 202 203 /* 204 * Attach the interface. 205 */ 206 if_attach(ifp); 207 ether_ifattach(ifp, sc->sc_enaddr); 208 209 #if NBPFILTER > 0 210 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 211 #endif 212 printf("\n%s: hardware address %s\n", sc->sc_dev.dv_xname, 213 ether_sprintf(sc->sc_enaddr)); 214 return; 215 216 /* 217 * Free any resources we've allocated during the failed attach 218 * attempt. Do this in reverse order and fall through. 219 */ 220 fail_6: 221 for (i = 0; i < RXDESCS; i++) { 222 if (sc->sc_rxmbuf[i] != NULL) { 223 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 224 m_freem(sc->sc_rxmbuf[i]); 225 } 226 } 227 fail_5: 228 for (i = 0; i < RXDESCS; i++) { 229 if (sc->sc_xmtmap[i] != NULL) 230 bus_dmamap_destroy(sc->sc_dmat, sc->sc_xmtmap[i]); 231 } 232 fail_4: 233 for (i = 0; i < TXDESCS; i++) { 234 if (sc->sc_rcvmap[i] != NULL) 235 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]); 236 } 237 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmap); 238 fail_3: 239 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmap); 240 fail_2: 241 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_zedata, 242 sizeof(struct ze_cdata)); 243 fail_1: 244 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 245 fail_0: 246 return; 247 } 248 249 /* 250 * Initialization of interface. 251 */ 252 void 253 zeinit(sc) 254 struct ze_softc *sc; 255 { 256 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 257 struct ze_cdata *zc = sc->sc_zedata; 258 int i; 259 260 /* 261 * Reset the interface. 262 */ 263 if (zereset(sc)) 264 return; 265 266 sc->sc_nexttx = sc->sc_inq = sc->sc_lastack = 0; 267 /* 268 * Release and init transmit descriptors. 269 */ 270 for (i = 0; i < TXDESCS; i++) { 271 if (sc->sc_txmbuf[i]) { 272 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 273 m_freem(sc->sc_txmbuf[i]); 274 sc->sc_txmbuf[i] = 0; 275 } 276 zc->zc_xmit[i].ze_tdr = 0; /* Clear valid bit */ 277 } 278 279 280 /* 281 * Init receive descriptors. 282 */ 283 for (i = 0; i < RXDESCS; i++) 284 zc->zc_recv[i].ze_framelen = ZE_FRAMELEN_OW; 285 sc->sc_nextrx = 0; 286 287 ZE_WCSR(ZE_CSR6, ZE_NICSR6_IE|ZE_NICSR6_BL_8|ZE_NICSR6_ST| 288 ZE_NICSR6_SR|ZE_NICSR6_DC); 289 290 ifp->if_flags |= IFF_RUNNING; 291 ifp->if_flags &= ~IFF_OACTIVE; 292 293 /* 294 * Send a setup frame. 295 * This will start the transmit machinery as well. 296 */ 297 ze_setup(sc); 298 299 } 300 301 /* 302 * Start output on interface. 303 */ 304 void 305 zestart(ifp) 306 struct ifnet *ifp; 307 { 308 struct ze_softc *sc = ifp->if_softc; 309 struct ze_cdata *zc = sc->sc_zedata; 310 paddr_t buffer; 311 struct mbuf *m, *m0; 312 int idx, len, s, i, totlen, error; 313 short orword; 314 315 s = splimp(); 316 while (sc->sc_inq < (TXDESCS - 1)) { 317 318 if (sc->sc_setup) { 319 ze_setup(sc); 320 continue; 321 } 322 idx = sc->sc_nexttx; 323 IF_DEQUEUE(&sc->sc_if.if_snd, m); 324 if (m == 0) 325 goto out; 326 /* 327 * Count number of mbufs in chain. 328 * Always do DMA directly from mbufs, therefore the transmit 329 * ring is really big. 330 */ 331 for (m0 = m, i = 0; m0; m0 = m0->m_next) 332 if (m0->m_len) 333 i++; 334 if (i >= TXDESCS) 335 panic("zestart"); /* XXX */ 336 337 if ((i + sc->sc_inq) >= (TXDESCS - 1)) { 338 IF_PREPEND(&sc->sc_if.if_snd, m); 339 ifp->if_flags |= IFF_OACTIVE; 340 goto out; 341 } 342 343 #if NBPFILTER > 0 344 if (ifp->if_bpf) 345 bpf_mtap(ifp->if_bpf, m); 346 #endif 347 /* 348 * m now points to a mbuf chain that can be loaded. 349 * Loop around and set it. 350 */ 351 totlen = 0; 352 for (m0 = m; m0; m0 = m0->m_next) { 353 error = bus_dmamap_load(sc->sc_dmat, sc->sc_xmtmap[idx], 354 mtod(m0, void *), m0->m_len, 0, 0); 355 buffer = sc->sc_xmtmap[idx]->dm_segs[0].ds_addr; 356 len = m0->m_len; 357 if (len == 0) 358 continue; 359 360 totlen += len; 361 /* Word alignment calc */ 362 orword = 0; 363 if (totlen == len) 364 orword = ZE_TDES1_FS; 365 if (totlen == m->m_pkthdr.len) { 366 if (totlen < ETHER_MIN_LEN) 367 len += (ETHER_MIN_LEN - totlen); 368 orword |= ZE_TDES1_LS; 369 sc->sc_txmbuf[idx] = m; 370 } 371 zc->zc_xmit[idx].ze_bufsize = len; 372 zc->zc_xmit[idx].ze_bufaddr = (char *)buffer; 373 zc->zc_xmit[idx].ze_tdes1 = orword | ZE_TDES1_IC; 374 zc->zc_xmit[idx].ze_tdr = ZE_TDR_OW; 375 376 if (++idx == TXDESCS) 377 idx = 0; 378 sc->sc_inq++; 379 } 380 #ifdef DIAGNOSTIC 381 if (totlen != m->m_pkthdr.len) 382 panic("zestart: len fault"); 383 #endif 384 385 /* 386 * Kick off the transmit logic, if it is stopped. 387 */ 388 if ((ZE_RCSR(ZE_CSR5) & ZE_NICSR5_TS) != ZE_NICSR5_TS_RUN) 389 ZE_WCSR(ZE_CSR1, -1); 390 sc->sc_nexttx = idx; 391 } 392 if (sc->sc_inq == (TXDESCS - 1)) 393 ifp->if_flags |= IFF_OACTIVE; 394 395 out: if (sc->sc_inq) 396 ifp->if_timer = 5; /* If transmit logic dies */ 397 splx(s); 398 } 399 400 int 401 sgec_intr(sc) 402 struct ze_softc *sc; 403 { 404 struct ze_cdata *zc = sc->sc_zedata; 405 struct ifnet *ifp = &sc->sc_if; 406 struct ether_header *eh; 407 struct mbuf *m; 408 int csr, len; 409 410 csr = ZE_RCSR(ZE_CSR5); 411 if ((csr & ZE_NICSR5_IS) == 0) /* Wasn't we */ 412 return 0; 413 ZE_WCSR(ZE_CSR5, csr); 414 415 if (csr & ZE_NICSR5_RI) 416 while ((zc->zc_recv[sc->sc_nextrx].ze_framelen & 417 ZE_FRAMELEN_OW) == 0) { 418 419 ifp->if_ipackets++; 420 m = sc->sc_rxmbuf[sc->sc_nextrx]; 421 len = zc->zc_recv[sc->sc_nextrx].ze_framelen; 422 ze_add_rxbuf(sc, sc->sc_nextrx); 423 m->m_pkthdr.rcvif = ifp; 424 m->m_pkthdr.len = m->m_len = len; 425 if (++sc->sc_nextrx == RXDESCS) 426 sc->sc_nextrx = 0; 427 eh = mtod(m, struct ether_header *); 428 #if NBPFILTER > 0 429 if (ifp->if_bpf) { 430 bpf_mtap(ifp->if_bpf, m); 431 if ((ifp->if_flags & IFF_PROMISC) != 0 && 432 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 433 ETHER_ADDR_LEN) != 0 && 434 ((eh->ether_dhost[0] & 1) == 0)) { 435 m_freem(m); 436 continue; 437 } 438 } 439 #endif 440 /* 441 * ALLMULTI means PROMISC in this driver. 442 */ 443 if ((ifp->if_flags & IFF_ALLMULTI) && 444 ((eh->ether_dhost[0] & 1) == 0) && 445 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 446 ETHER_ADDR_LEN)) { 447 m_freem(m); 448 continue; 449 } 450 (*ifp->if_input)(ifp, m); 451 } 452 453 if (csr & ZE_NICSR5_TI) { 454 while ((zc->zc_xmit[sc->sc_lastack].ze_tdr & ZE_TDR_OW) == 0) { 455 int idx = sc->sc_lastack; 456 457 if (sc->sc_lastack == sc->sc_nexttx) 458 break; 459 sc->sc_inq--; 460 if (++sc->sc_lastack == TXDESCS) 461 sc->sc_lastack = 0; 462 463 /* XXX collect statistics */ 464 ifp->if_opackets++; 465 if ((zc->zc_xmit[idx].ze_tdes1 & ZE_TDES1_DT) == 466 ZE_TDES1_DT_SETUP) 467 continue; 468 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[idx]); 469 if (sc->sc_txmbuf[idx]) { 470 m_freem(sc->sc_txmbuf[idx]); 471 sc->sc_txmbuf[idx] = 0; 472 } 473 } 474 ifp->if_timer = 0; 475 ifp->if_flags &= ~IFF_OACTIVE; 476 zestart(ifp); /* Put in more in queue */ 477 } 478 return 1; 479 } 480 481 /* 482 * Process an ioctl request. 483 */ 484 int 485 zeioctl(ifp, cmd, data) 486 struct ifnet *ifp; 487 u_long cmd; 488 caddr_t data; 489 { 490 struct ze_softc *sc = ifp->if_softc; 491 struct ifreq *ifr = (struct ifreq *)data; 492 struct ifaddr *ifa = (struct ifaddr *)data; 493 int s = splnet(), error = 0; 494 495 switch (cmd) { 496 497 case SIOCSIFADDR: 498 ifp->if_flags |= IFF_UP; 499 switch(ifa->ifa_addr->sa_family) { 500 #ifdef INET 501 case AF_INET: 502 zeinit(sc); 503 arp_ifinit(ifp, ifa); 504 break; 505 #endif 506 } 507 break; 508 509 case SIOCSIFFLAGS: 510 if ((ifp->if_flags & IFF_UP) == 0 && 511 (ifp->if_flags & IFF_RUNNING) != 0) { 512 /* 513 * If interface is marked down and it is running, 514 * stop it. (by disabling receive mechanism). 515 */ 516 ZE_WCSR(ZE_CSR6, ZE_RCSR(ZE_CSR6) & 517 ~(ZE_NICSR6_ST|ZE_NICSR6_SR)); 518 ifp->if_flags &= ~IFF_RUNNING; 519 } else if ((ifp->if_flags & IFF_UP) != 0 && 520 (ifp->if_flags & IFF_RUNNING) == 0) { 521 /* 522 * If interface it marked up and it is stopped, then 523 * start it. 524 */ 525 zeinit(sc); 526 } else if ((ifp->if_flags & IFF_UP) != 0) { 527 /* 528 * Send a new setup packet to match any new changes. 529 * (Like IFF_PROMISC etc) 530 */ 531 ze_setup(sc); 532 } 533 break; 534 535 case SIOCADDMULTI: 536 case SIOCDELMULTI: 537 /* 538 * Update our multicast list. 539 */ 540 error = (cmd == SIOCADDMULTI) ? 541 ether_addmulti(ifr, &sc->sc_ec): 542 ether_delmulti(ifr, &sc->sc_ec); 543 544 if (error == ENETRESET) { 545 /* 546 * Multicast list has changed; set the hardware filter 547 * accordingly. 548 */ 549 ze_setup(sc); 550 error = 0; 551 } 552 break; 553 554 default: 555 error = EINVAL; 556 557 } 558 splx(s); 559 return (error); 560 } 561 562 /* 563 * Add a receive buffer to the indicated descriptor. 564 */ 565 int 566 ze_add_rxbuf(sc, i) 567 struct ze_softc *sc; 568 int i; 569 { 570 struct mbuf *m; 571 struct ze_rdes *rp; 572 int error; 573 574 MGETHDR(m, M_DONTWAIT, MT_DATA); 575 if (m == NULL) 576 return (ENOBUFS); 577 578 MCLGET(m, M_DONTWAIT); 579 if ((m->m_flags & M_EXT) == 0) { 580 m_freem(m); 581 return (ENOBUFS); 582 } 583 584 if (sc->sc_rxmbuf[i] != NULL) 585 bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]); 586 587 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rcvmap[i], 588 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 589 if (error) 590 panic("%s: can't load rx DMA map %d, error = %d\n", 591 sc->sc_dev.dv_xname, i, error); 592 sc->sc_rxmbuf[i] = m; 593 594 bus_dmamap_sync(sc->sc_dmat, sc->sc_rcvmap[i], 0, 595 sc->sc_rcvmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 596 597 /* 598 * We know that the mbuf cluster is page aligned. Also, be sure 599 * that the IP header will be longword aligned. 600 */ 601 m->m_data += 2; 602 rp = &sc->sc_zedata->zc_recv[i]; 603 rp->ze_bufsize = (m->m_ext.ext_size - 2); 604 rp->ze_bufaddr = (char *)sc->sc_rcvmap[i]->dm_segs[0].ds_addr + 2; 605 rp->ze_framelen = ZE_FRAMELEN_OW; 606 607 return (0); 608 } 609 610 /* 611 * Create a setup packet and put in queue for sending. 612 */ 613 void 614 ze_setup(sc) 615 struct ze_softc *sc; 616 { 617 struct ether_multi *enm; 618 struct ether_multistep step; 619 struct ze_cdata *zc = sc->sc_zedata; 620 struct ifnet *ifp = &sc->sc_if; 621 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 622 int j, idx, s, reg; 623 624 s = splimp(); 625 if (sc->sc_inq == (TXDESCS - 1)) { 626 sc->sc_setup = 1; 627 splx(s); 628 return; 629 } 630 sc->sc_setup = 0; 631 /* 632 * Init the setup packet with valid info. 633 */ 634 memset(zc->zc_setup, 0xff, sizeof(zc->zc_setup)); /* Broadcast */ 635 bcopy(enaddr, zc->zc_setup, ETHER_ADDR_LEN); 636 637 /* 638 * Multicast handling. The SGEC can handle up to 16 direct 639 * ethernet addresses. 640 */ 641 j = 16; 642 ifp->if_flags &= ~IFF_ALLMULTI; 643 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 644 while (enm != NULL) { 645 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 646 ifp->if_flags |= IFF_ALLMULTI; 647 break; 648 } 649 bcopy(enm->enm_addrlo, &zc->zc_setup[j], ETHER_ADDR_LEN); 650 j += 8; 651 ETHER_NEXT_MULTI(step, enm); 652 if ((enm != NULL)&& (j == 128)) { 653 ifp->if_flags |= IFF_ALLMULTI; 654 break; 655 } 656 } 657 658 /* 659 * Fiddle with the receive logic. 660 */ 661 reg = ZE_RCSR(ZE_CSR6); 662 DELAY(10); 663 ZE_WCSR(ZE_CSR6, reg & ~ZE_NICSR6_SR); /* Stop rx */ 664 reg &= ~ZE_NICSR6_AF; 665 if (ifp->if_flags & IFF_PROMISC) 666 reg |= ZE_NICSR6_AF_PROM; 667 else if (ifp->if_flags & IFF_ALLMULTI) 668 reg |= ZE_NICSR6_AF_ALLM; 669 DELAY(10); 670 ZE_WCSR(ZE_CSR6, reg); 671 /* 672 * Only send a setup packet if needed. 673 */ 674 if ((ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) == 0) { 675 idx = sc->sc_nexttx; 676 zc->zc_xmit[idx].ze_tdes1 = ZE_TDES1_DT_SETUP; 677 zc->zc_xmit[idx].ze_bufsize = 128; 678 zc->zc_xmit[idx].ze_bufaddr = sc->sc_pzedata->zc_setup; 679 zc->zc_xmit[idx].ze_tdr = ZE_TDR_OW; 680 681 if ((ZE_RCSR(ZE_CSR5) & ZE_NICSR5_TS) != ZE_NICSR5_TS_RUN) 682 ZE_WCSR(ZE_CSR1, -1); 683 684 sc->sc_inq++; 685 if (++sc->sc_nexttx == TXDESCS) 686 sc->sc_nexttx = 0; 687 } 688 splx(s); 689 } 690 691 /* 692 * Check for dead transmit logic. 693 */ 694 void 695 zetimeout(ifp) 696 struct ifnet *ifp; 697 { 698 struct ze_softc *sc = ifp->if_softc; 699 700 if (sc->sc_inq == 0) 701 return; 702 703 printf("%s: xmit logic died, resetting...\n", sc->sc_dev.dv_xname); 704 /* 705 * Do a reset of interface, to get it going again. 706 * Will it work by just restart the transmit logic? 707 */ 708 zeinit(sc); 709 } 710 711 /* 712 * Reset chip: 713 * Set/reset the reset flag. 714 * Write interrupt vector. 715 * Write ring buffer addresses. 716 * Write SBR. 717 */ 718 int 719 zereset(sc) 720 struct ze_softc *sc; 721 { 722 int reg, i, s; 723 724 ZE_WCSR(ZE_CSR6, ZE_NICSR6_RE); 725 DELAY(50000); 726 if (ZE_RCSR(ZE_CSR6) & ZE_NICSR5_SF) { 727 printf("%s: selftest failed\n", sc->sc_dev.dv_xname); 728 return 1; 729 } 730 731 /* 732 * Get the vector that were set at match time, and remember it. 733 * WHICH VECTOR TO USE? Take one unused. XXX 734 * Funny way to set vector described in the programmers manual. 735 */ 736 reg = ZE_NICSR0_IPL14 | sc->sc_intvec | 0x1fff0003; /* SYNC/ASYNC??? */ 737 i = 10; 738 s = splimp(); 739 do { 740 if (i-- == 0) { 741 printf("Failing SGEC CSR0 init\n"); 742 splx(s); 743 return 1; 744 } 745 ZE_WCSR(ZE_CSR0, reg); 746 } while (ZE_RCSR(ZE_CSR0) != reg); 747 splx(s); 748 749 ZE_WCSR(ZE_CSR3, (vaddr_t)sc->sc_pzedata->zc_recv); 750 ZE_WCSR(ZE_CSR4, (vaddr_t)sc->sc_pzedata->zc_xmit); 751 return 0; 752 } 753
Indexes created Fri Sep 26 20:09:58 GMT 2025