sgec.c revision 1.4
1 /* $NetBSD: sgec.c,v 1.4 2000/05/27 04:26:32 matt Exp $ */ 2 /* 3 * Copyright (c) 1999 Ludd, University of Lule}, Sweden. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed at Ludd, University of 16 * Lule}, Sweden and its contributors. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the SGEC (Second Generation Ethernet Controller), sitting 34 * on for example the VAX 4000/300 (KA670). 35 * 36 * The SGEC looks like a mixture of the DEQNA and the TULIP. Fun toy. 37 * 38 * Even though the chip is capable to use virtual addresses (read the 39 * System Page Table directly) this driver doesn't do so, and there 40 * is no benefit in doing it either in NetBSD of today. 41 * 42 * Things that is still to do: 43 * Collect statistics. 44 * Use imperfect filtering when many multicast addresses. 45 */ 46 47 #include "opt_inet.h" 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/mbuf.h> 52 #include <sys/socket.h> 53 #include <sys/device.h> 54 #include <sys/systm.h> 55 #include <sys/sockio.h> 56 57 #include <net/if.h> 58 #include <net/if_ether.h> 59 #include <net/if_dl.h> 60 61 #include <netinet/in.h> 62 #include <netinet/if_inarp.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #include <net/bpfdesc.h> 67 #endif 68 69 #include <machine/bus.h> 70 71 #include <dev/ic/sgecreg.h> 72 #include <dev/ic/sgecvar.h> 73 74 static void zeinit __P((struct ze_softc *)); 75 static void zestart __P((struct ifnet *)); 76 static int zeioctl __P((struct ifnet *, u_long, caddr_t)); 77 static int ze_add_rxbuf __P((struct ze_softc *, int)); 78 static void ze_setup __P((struct ze_softc *)); 79 static void zetimeout __P((struct ifnet *)); 80 static int zereset __P((struct ze_softc *)); 81 82 #define ZE_WCSR(csr, val) \ 83 bus_space_write_4(sc->sc_iot, sc->sc_ioh, csr, val) 84 #define ZE_RCSR(csr) \ 85 bus_space_read_4(sc->sc_iot, sc->sc_ioh, csr) 86 87 /* 88 * Interface exists: make available by filling in network interface 89 * record. System will initialize the interface when it is ready 90 * to accept packets. 91 */ 92 void 93 sgec_attach(sc) 94 struct ze_softc *sc; 95 { 96 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 97 struct ze_tdes *tp; 98 struct ze_rdes *rp; 99 bus_dma_segment_t seg; 100 int i, rseg, error; 101 102 /* 103 * Allocate DMA safe memory for descriptors and setup memory. 104 */ 105 if ((error = bus_dmamem_alloc(sc->sc_dmat, 106 sizeof(struct ze_cdata), NBPG, 0, &seg, 1, &rseg, 107 BUS_DMA_NOWAIT)) != 0) { 108 printf(": unable to allocate control data, error = %d\n", 109 error); 110 goto fail_0; 111 } 112 113 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 114 sizeof(struct ze_cdata), (caddr_t *)&sc->sc_zedata, 115 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 116 printf(": unable to map control data, error = %d\n", error); 117 goto fail_1; 118 } 119 120 if ((error = bus_dmamap_create(sc->sc_dmat, 121 sizeof(struct ze_cdata), 1, 122 sizeof(struct ze_cdata), 0, BUS_DMA_NOWAIT, 123 &sc->sc_cmap)) != 0) { 124 printf(": unable to create control data DMA map, error = %d\n", 125 error); 126 goto fail_2; 127 } 128 129 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmap, 130 sc->sc_zedata, sizeof(struct ze_cdata), NULL, 131 BUS_DMA_NOWAIT)) != 0) { 132 printf(": unable to load control data DMA map, error = %d\n", 133 error); 134 goto fail_3; 135 } 136 137 /* 138 * Zero the newly allocated memory. 139 */ 140 bzero(sc->sc_zedata, sizeof(struct ze_cdata)); 141 /* 142 * Create the transmit descriptor DMA maps. 143 */ 144 for (i = 0; i < TXDESCS; i++) { 145 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 146 1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW, 147 &sc->sc_xmtmap[i]))) { 148 printf(": unable to create tx DMA map %d, error = %d\n", 149 i, error); 150 goto fail_4; 151 } 152 } 153 154 /* 155 * Create receive buffer DMA maps. 156 */ 157 for (i = 0; i < RXDESCS; i++) { 158 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 159 MCLBYTES, 0, BUS_DMA_NOWAIT, 160 &sc->sc_rcvmap[i]))) { 161 printf(": unable to create rx DMA map %d, error = %d\n", 162 i, error); 163 goto fail_5; 164 } 165 } 166 /* 167 * Pre-allocate the receive buffers. 168 */ 169 for (i = 0; i < RXDESCS; i++) { 170 if ((error = ze_add_rxbuf(sc, i)) != 0) { 171 printf(": unable to allocate or map rx buffer %d\n," 172 " error = %d\n", i, error); 173 goto fail_6; 174 } 175 } 176 177 /* 178 * Create ring loops of the buffer chains. 179 * This is only done once. 180 */ 181 sc->sc_pzedata = (struct ze_cdata *)sc->sc_cmap->dm_segs[0].ds_addr; 182 183 rp = sc->sc_zedata->zc_recv; 184 rp[RXDESCS].ze_framelen = ZE_FRAMELEN_OW; 185 rp[RXDESCS].ze_rdes1 = ZE_RDES1_CA; 186 rp[RXDESCS].ze_bufaddr = (char *)sc->sc_pzedata->zc_recv; 187 188 tp = sc->sc_zedata->zc_xmit; 189 tp[TXDESCS].ze_tdr = ZE_TDR_OW; 190 tp[TXDESCS].ze_tdes1 = ZE_TDES1_CA; 191 tp[TXDESCS].ze_bufaddr = (char *)sc->sc_pzedata->zc_xmit; 192 193 if (zereset(sc)) 194 return; 195 196 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 197 ifp->if_softc = sc; 198 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 199 ifp->if_start = zestart; 200 ifp->if_ioctl = zeioctl; 201 ifp->if_watchdog = zetimeout; 202 203 /* 204 * Attach the interface. 205 */ 206 if_attach(ifp); 207 ether_ifattach(ifp, sc->sc_enaddr); 208 209 #if NBPFILTER > 0 210 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 211 #endif 212 printf("\n%s: hardware address %s\n", sc->sc_dev.dv_xname, 213 ether_sprintf(sc->sc_enaddr)); 214 return; 215 216 /* 217 * Free any resources we've allocated during the failed attach 218 * attempt. Do this in reverse order and fall through. 219 */ 220 fail_6: 221 for (i = 0; i < RXDESCS; i++) { 222 if (sc->sc_rxmbuf[i] != NULL) { 223 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 224 m_freem(sc->sc_rxmbuf[i]); 225 } 226 } 227 fail_5: 228 for (i = 0; i < RXDESCS; i++) { 229 if (sc->sc_xmtmap[i] != NULL) 230 bus_dmamap_destroy(sc->sc_dmat, sc->sc_xmtmap[i]); 231 } 232 fail_4: 233 for (i = 0; i < TXDESCS; i++) { 234 if (sc->sc_rcvmap[i] != NULL) 235 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]); 236 } 237 bus_dmamap_unload(sc->sc_dmat, sc->sc_cmap); 238 fail_3: 239 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cmap); 240 fail_2: 241 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_zedata, 242 sizeof(struct ze_cdata)); 243 fail_1: 244 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 245 fail_0: 246 return; 247 } 248 249 /* 250 * Initialization of interface. 251 */ 252 void 253 zeinit(sc) 254 struct ze_softc *sc; 255 { 256 struct ifnet *ifp = (struct ifnet *)&sc->sc_if; 257 struct ze_cdata *zc = sc->sc_zedata; 258 int i; 259 260 /* 261 * Reset the interface. 262 */ 263 if (zereset(sc)) 264 return; 265 266 sc->sc_nexttx = sc->sc_inq = sc->sc_lastack = 0; 267 /* 268 * Release and init transmit descriptors. 269 */ 270 for (i = 0; i < TXDESCS; i++) { 271 if (sc->sc_txmbuf[i]) { 272 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]); 273 m_freem(sc->sc_txmbuf[i]); 274 sc->sc_txmbuf[i] = 0; 275 } 276 zc->zc_xmit[i].ze_tdr = 0; /* Clear valid bit */ 277 } 278 279 280 /* 281 * Init receive descriptors. 282 */ 283 for (i = 0; i < RXDESCS; i++) 284 zc->zc_recv[i].ze_framelen = ZE_FRAMELEN_OW; 285 sc->sc_nextrx = 0; 286 287 ZE_WCSR(ZE_CSR6, ZE_NICSR6_IE|ZE_NICSR6_BL_8|ZE_NICSR6_ST| 288 ZE_NICSR6_SR|ZE_NICSR6_DC); 289 290 ifp->if_flags |= IFF_RUNNING; 291 ifp->if_flags &= ~IFF_OACTIVE; 292 293 /* 294 * Send a setup frame. 295 * This will start the transmit machinery as well. 296 */ 297 ze_setup(sc); 298 299 } 300 301 /* 302 * Start output on interface. 303 */ 304 void 305 zestart(ifp) 306 struct ifnet *ifp; 307 { 308 struct ze_softc *sc = ifp->if_softc; 309 struct ze_cdata *zc = sc->sc_zedata; 310 paddr_t buffer; 311 struct mbuf *m, *m0; 312 int idx, len, s, i, totlen, error; 313 int old_inq = sc->sc_inq; 314 short orword; 315 316 s = splimp(); 317 while (sc->sc_inq < (TXDESCS - 1)) { 318 319 if (sc->sc_setup) { 320 ze_setup(sc); 321 continue; 322 } 323 idx = sc->sc_nexttx; 324 IF_DEQUEUE(&sc->sc_if.if_snd, m); 325 if (m == 0) 326 goto out; 327 /* 328 * Count number of mbufs in chain. 329 * Always do DMA directly from mbufs, therefore the transmit 330 * ring is really big. 331 */ 332 for (m0 = m, i = 0; m0; m0 = m0->m_next) 333 if (m0->m_len) 334 i++; 335 if (i >= TXDESCS) 336 panic("zestart"); /* XXX */ 337 338 if ((i + sc->sc_inq) >= (TXDESCS - 1)) { 339 IF_PREPEND(&sc->sc_if.if_snd, m); 340 ifp->if_flags |= IFF_OACTIVE; 341 goto out; 342 } 343 344 #if NBPFILTER > 0 345 if (ifp->if_bpf) 346 bpf_mtap(ifp->if_bpf, m); 347 #endif 348 /* 349 * m now points to a mbuf chain that can be loaded. 350 * Loop around and set it. 351 */ 352 totlen = 0; 353 for (m0 = m; m0; m0 = m0->m_next) { 354 error = bus_dmamap_load(sc->sc_dmat, sc->sc_xmtmap[idx], 355 mtod(m0, void *), m0->m_len, 0, 0); 356 buffer = sc->sc_xmtmap[idx]->dm_segs[0].ds_addr; 357 len = m0->m_len; 358 if (len == 0) 359 continue; 360 361 totlen += len; 362 /* Word alignment calc */ 363 orword = 0; 364 if (totlen == len) 365 orword = ZE_TDES1_FS; 366 if (totlen == m->m_pkthdr.len) { 367 if (totlen < ETHER_MIN_LEN) 368 len += (ETHER_MIN_LEN - totlen); 369 orword |= ZE_TDES1_LS; 370 sc->sc_txmbuf[idx] = m; 371 } 372 zc->zc_xmit[idx].ze_bufsize = len; 373 zc->zc_xmit[idx].ze_bufaddr = (char *)buffer; 374 zc->zc_xmit[idx].ze_tdes1 = orword | ZE_TDES1_IC; 375 zc->zc_xmit[idx].ze_tdr = ZE_TDR_OW; 376 377 if (++idx == TXDESCS) 378 idx = 0; 379 sc->sc_inq++; 380 } 381 #ifdef DIAGNOSTIC 382 if (totlen != m->m_pkthdr.len) 383 panic("zestart: len fault"); 384 #endif 385 386 /* 387 * Kick off the transmit logic, if it is stopped. 388 */ 389 if ((ZE_RCSR(ZE_CSR5) & ZE_NICSR5_TS) != ZE_NICSR5_TS_RUN) 390 ZE_WCSR(ZE_CSR1, -1); 391 sc->sc_nexttx = idx; 392 } 393 if (sc->sc_inq == (TXDESCS - 1)) 394 ifp->if_flags |= IFF_OACTIVE; 395 396 out: if (old_inq < sc->sc_inq) 397 ifp->if_timer = 5; /* If transmit logic dies */ 398 splx(s); 399 } 400 401 int 402 sgec_intr(sc) 403 struct ze_softc *sc; 404 { 405 struct ze_cdata *zc = sc->sc_zedata; 406 struct ifnet *ifp = &sc->sc_if; 407 struct ether_header *eh; 408 struct mbuf *m; 409 int csr, len; 410 411 csr = ZE_RCSR(ZE_CSR5); 412 if ((csr & ZE_NICSR5_IS) == 0) /* Wasn't we */ 413 return 0; 414 ZE_WCSR(ZE_CSR5, csr); 415 416 if (csr & ZE_NICSR5_RI) 417 while ((zc->zc_recv[sc->sc_nextrx].ze_framelen & 418 ZE_FRAMELEN_OW) == 0) { 419 420 ifp->if_ipackets++; 421 m = sc->sc_rxmbuf[sc->sc_nextrx]; 422 len = zc->zc_recv[sc->sc_nextrx].ze_framelen; 423 ze_add_rxbuf(sc, sc->sc_nextrx); 424 m->m_pkthdr.rcvif = ifp; 425 m->m_pkthdr.len = m->m_len = len; 426 if (++sc->sc_nextrx == RXDESCS) 427 sc->sc_nextrx = 0; 428 eh = mtod(m, struct ether_header *); 429 #if NBPFILTER > 0 430 if (ifp->if_bpf) { 431 bpf_mtap(ifp->if_bpf, m); 432 if ((ifp->if_flags & IFF_PROMISC) != 0 && 433 ((eh->ether_dhost[0] & 1) == 0) && 434 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 435 ETHER_ADDR_LEN) != 0) { 436 m_freem(m); 437 continue; 438 } 439 } 440 #endif 441 /* 442 * ALLMULTI means PROMISC in this driver. 443 */ 444 if ((ifp->if_flags & IFF_ALLMULTI) && 445 ((eh->ether_dhost[0] & 1) == 0) && 446 bcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 447 ETHER_ADDR_LEN)) { 448 m_freem(m); 449 continue; 450 } 451 (*ifp->if_input)(ifp, m); 452 } 453 454 if (csr & ZE_NICSR5_TI) { 455 while ((zc->zc_xmit[sc->sc_lastack].ze_tdr & ZE_TDR_OW) == 0) { 456 int idx = sc->sc_lastack; 457 458 if (sc->sc_lastack == sc->sc_nexttx) 459 break; 460 sc->sc_inq--; 461 if (++sc->sc_lastack == TXDESCS) 462 sc->sc_lastack = 0; 463 464 if ((zc->zc_xmit[idx].ze_tdes1 & ZE_TDES1_DT) == 465 ZE_TDES1_DT_SETUP) 466 continue; 467 /* XXX collect statistics */ 468 if (zc->zc_xmit[idx].ze_tdes1 & ZE_TDES1_LS) 469 ifp->if_opackets++; 470 bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[idx]); 471 if (sc->sc_txmbuf[idx]) { 472 m_freem(sc->sc_txmbuf[idx]); 473 sc->sc_txmbuf[idx] = 0; 474 } 475 } 476 if (sc->sc_inq == 0) 477 ifp->if_timer = 0; 478 ifp->if_flags &= ~IFF_OACTIVE; 479 zestart(ifp); /* Put in more in queue */ 480 } 481 return 1; 482 } 483 484 /* 485 * Process an ioctl request. 486 */ 487 int 488 zeioctl(ifp, cmd, data) 489 struct ifnet *ifp; 490 u_long cmd; 491 caddr_t data; 492 { 493 struct ze_softc *sc = ifp->if_softc; 494 struct ifreq *ifr = (struct ifreq *)data; 495 struct ifaddr *ifa = (struct ifaddr *)data; 496 int s = splnet(), error = 0; 497 498 switch (cmd) { 499 500 case SIOCSIFADDR: 501 ifp->if_flags |= IFF_UP; 502 switch(ifa->ifa_addr->sa_family) { 503 #ifdef INET 504 case AF_INET: 505 zeinit(sc); 506 arp_ifinit(ifp, ifa); 507 break; 508 #endif 509 } 510 break; 511 512 case SIOCSIFFLAGS: 513 if ((ifp->if_flags & IFF_UP) == 0 && 514 (ifp->if_flags & IFF_RUNNING) != 0) { 515 /* 516 * If interface is marked down and it is running, 517 * stop it. (by disabling receive mechanism). 518 */ 519 ZE_WCSR(ZE_CSR6, ZE_RCSR(ZE_CSR6) & 520 ~(ZE_NICSR6_ST|ZE_NICSR6_SR)); 521 ifp->if_flags &= ~IFF_RUNNING; 522 } else if ((ifp->if_flags & IFF_UP) != 0 && 523 (ifp->if_flags & IFF_RUNNING) == 0) { 524 /* 525 * If interface it marked up and it is stopped, then 526 * start it. 527 */ 528 zeinit(sc); 529 } else if ((ifp->if_flags & IFF_UP) != 0) { 530 /* 531 * Send a new setup packet to match any new changes. 532 * (Like IFF_PROMISC etc) 533 */ 534 ze_setup(sc); 535 } 536 break; 537 538 case SIOCADDMULTI: 539 case SIOCDELMULTI: 540 /* 541 * Update our multicast list. 542 */ 543 error = (cmd == SIOCADDMULTI) ? 544 ether_addmulti(ifr, &sc->sc_ec): 545 ether_delmulti(ifr, &sc->sc_ec); 546 547 if (error == ENETRESET) { 548 /* 549 * Multicast list has changed; set the hardware filter 550 * accordingly. 551 */ 552 ze_setup(sc); 553 error = 0; 554 } 555 break; 556 557 default: 558 error = EINVAL; 559 560 } 561 splx(s); 562 return (error); 563 } 564 565 /* 566 * Add a receive buffer to the indicated descriptor. 567 */ 568 int 569 ze_add_rxbuf(sc, i) 570 struct ze_softc *sc; 571 int i; 572 { 573 struct mbuf *m; 574 struct ze_rdes *rp; 575 int error; 576 577 MGETHDR(m, M_DONTWAIT, MT_DATA); 578 if (m == NULL) 579 return (ENOBUFS); 580 581 MCLGET(m, M_DONTWAIT); 582 if ((m->m_flags & M_EXT) == 0) { 583 m_freem(m); 584 return (ENOBUFS); 585 } 586 587 if (sc->sc_rxmbuf[i] != NULL) 588 bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]); 589 590 error = bus_dmamap_load(sc->sc_dmat, sc->sc_rcvmap[i], 591 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT); 592 if (error) 593 panic("%s: can't load rx DMA map %d, error = %d\n", 594 sc->sc_dev.dv_xname, i, error); 595 sc->sc_rxmbuf[i] = m; 596 597 bus_dmamap_sync(sc->sc_dmat, sc->sc_rcvmap[i], 0, 598 sc->sc_rcvmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD); 599 600 /* 601 * We know that the mbuf cluster is page aligned. Also, be sure 602 * that the IP header will be longword aligned. 603 */ 604 m->m_data += 2; 605 rp = &sc->sc_zedata->zc_recv[i]; 606 rp->ze_bufsize = (m->m_ext.ext_size - 2); 607 rp->ze_bufaddr = (char *)sc->sc_rcvmap[i]->dm_segs[0].ds_addr + 2; 608 rp->ze_framelen = ZE_FRAMELEN_OW; 609 610 return (0); 611 } 612 613 /* 614 * Create a setup packet and put in queue for sending. 615 */ 616 void 617 ze_setup(sc) 618 struct ze_softc *sc; 619 { 620 struct ether_multi *enm; 621 struct ether_multistep step; 622 struct ze_cdata *zc = sc->sc_zedata; 623 struct ifnet *ifp = &sc->sc_if; 624 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 625 int j, idx, s, reg; 626 627 s = splimp(); 628 if (sc->sc_inq == (TXDESCS - 1)) { 629 sc->sc_setup = 1; 630 splx(s); 631 return; 632 } 633 sc->sc_setup = 0; 634 /* 635 * Init the setup packet with valid info. 636 */ 637 memset(zc->zc_setup, 0xff, sizeof(zc->zc_setup)); /* Broadcast */ 638 bcopy(enaddr, zc->zc_setup, ETHER_ADDR_LEN); 639 640 /* 641 * Multicast handling. The SGEC can handle up to 16 direct 642 * ethernet addresses. 643 */ 644 j = 16; 645 ifp->if_flags &= ~IFF_ALLMULTI; 646 ETHER_FIRST_MULTI(step, &sc->sc_ec, enm); 647 while (enm != NULL) { 648 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 649 ifp->if_flags |= IFF_ALLMULTI; 650 break; 651 } 652 bcopy(enm->enm_addrlo, &zc->zc_setup[j], ETHER_ADDR_LEN); 653 j += 8; 654 ETHER_NEXT_MULTI(step, enm); 655 if ((enm != NULL)&& (j == 128)) { 656 ifp->if_flags |= IFF_ALLMULTI; 657 break; 658 } 659 } 660 661 /* 662 * Fiddle with the receive logic. 663 */ 664 reg = ZE_RCSR(ZE_CSR6); 665 DELAY(10); 666 ZE_WCSR(ZE_CSR6, reg & ~ZE_NICSR6_SR); /* Stop rx */ 667 reg &= ~ZE_NICSR6_AF; 668 if (ifp->if_flags & IFF_PROMISC) 669 reg |= ZE_NICSR6_AF_PROM; 670 else if (ifp->if_flags & IFF_ALLMULTI) 671 reg |= ZE_NICSR6_AF_ALLM; 672 DELAY(10); 673 ZE_WCSR(ZE_CSR6, reg); 674 /* 675 * Only send a setup packet if needed. 676 */ 677 if ((ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) == 0) { 678 idx = sc->sc_nexttx; 679 zc->zc_xmit[idx].ze_tdes1 = ZE_TDES1_DT_SETUP; 680 zc->zc_xmit[idx].ze_bufsize = 128; 681 zc->zc_xmit[idx].ze_bufaddr = sc->sc_pzedata->zc_setup; 682 zc->zc_xmit[idx].ze_tdr = ZE_TDR_OW; 683 684 if ((ZE_RCSR(ZE_CSR5) & ZE_NICSR5_TS) != ZE_NICSR5_TS_RUN) 685 ZE_WCSR(ZE_CSR1, -1); 686 687 sc->sc_inq++; 688 if (++sc->sc_nexttx == TXDESCS) 689 sc->sc_nexttx = 0; 690 } 691 splx(s); 692 } 693 694 /* 695 * Check for dead transmit logic. 696 */ 697 void 698 zetimeout(ifp) 699 struct ifnet *ifp; 700 { 701 struct ze_softc *sc = ifp->if_softc; 702 703 if (sc->sc_inq == 0) 704 return; 705 706 printf("%s: xmit logic died, resetting...\n", sc->sc_dev.dv_xname); 707 /* 708 * Do a reset of interface, to get it going again. 709 * Will it work by just restart the transmit logic? 710 */ 711 zeinit(sc); 712 } 713 714 /* 715 * Reset chip: 716 * Set/reset the reset flag. 717 * Write interrupt vector. 718 * Write ring buffer addresses. 719 * Write SBR. 720 */ 721 int 722 zereset(sc) 723 struct ze_softc *sc; 724 { 725 int reg, i, s; 726 727 ZE_WCSR(ZE_CSR6, ZE_NICSR6_RE); 728 DELAY(50000); 729 if (ZE_RCSR(ZE_CSR6) & ZE_NICSR5_SF) { 730 printf("%s: selftest failed\n", sc->sc_dev.dv_xname); 731 return 1; 732 } 733 734 /* 735 * Get the vector that were set at match time, and remember it. 736 * WHICH VECTOR TO USE? Take one unused. XXX 737 * Funny way to set vector described in the programmers manual. 738 */ 739 reg = ZE_NICSR0_IPL14 | sc->sc_intvec | 0x1fff0003; /* SYNC/ASYNC??? */ 740 i = 10; 741 s = splimp(); 742 do { 743 if (i-- == 0) { 744 printf("Failing SGEC CSR0 init\n"); 745 splx(s); 746 return 1; 747 } 748 ZE_WCSR(ZE_CSR0, reg); 749 } while (ZE_RCSR(ZE_CSR0) != reg); 750 splx(s); 751 752 ZE_WCSR(ZE_CSR3, (vaddr_t)sc->sc_pzedata->zc_recv); 753 ZE_WCSR(ZE_CSR4, (vaddr_t)sc->sc_pzedata->zc_xmit); 754 return 0; 755 } 756
Indexes created Thu Sep 25 06:09:39 GMT 2025