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si4136reg.h revision 1.2.4.1
      1  1.2.4.1  rpaulo /* $NetBSD: si4136reg.h,v 1.2.4.1 2006/09/09 02:50:03 rpaulo Exp $ */
      2      1.1  dyoung 
      3      1.1  dyoung /*
      4      1.1  dyoung  * Copyright (c) 2005 David Young.  All rights reserved.
      5      1.1  dyoung  *
      6      1.1  dyoung  * This code was written by David Young.
      7      1.1  dyoung  *
      8      1.1  dyoung  * Redistribution and use in source and binary forms, with or without
      9      1.1  dyoung  * modification, are permitted provided that the following conditions
     10      1.1  dyoung  * are met:
     11      1.1  dyoung  * 1. Redistributions of source code must retain the above copyright
     12      1.1  dyoung  *    notice, this list of conditions and the following disclaimer.
     13      1.1  dyoung  * 2. Redistributions in binary form must reproduce the above copyright
     14      1.1  dyoung  *    notice, this list of conditions and the following disclaimer in the
     15      1.1  dyoung  *    documentation and/or other materials provided with the distribution.
     16      1.1  dyoung  * 3. Neither the name of the author nor the names of any co-contributors
     17      1.1  dyoung  *    may be used to endorse or promote products derived from this software
     18      1.1  dyoung  *    without specific prior written permission.
     19      1.1  dyoung  *
     20      1.1  dyoung  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
     21      1.1  dyoung  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     22      1.1  dyoung  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
     23      1.1  dyoung  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
     24      1.1  dyoung  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     25      1.1  dyoung  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
     26      1.1  dyoung  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     27      1.1  dyoung  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     28      1.1  dyoung  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     29      1.1  dyoung  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     30      1.1  dyoung  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
     31      1.1  dyoung  * OF SUCH DAMAGE.
     32      1.1  dyoung  */
     33      1.1  dyoung 
     34      1.1  dyoung #ifndef _DEV_IC_SI4136REG_H_
     35      1.1  dyoung #define	_DEV_IC_SI4136REG_H_
     36      1.1  dyoung 
     37      1.1  dyoung /*
     38      1.1  dyoung  * Serial bus format for Silicon Laboratories Si4126/Si4136 RF synthesizer.
     39      1.1  dyoung  */
     40  1.2.4.1  rpaulo #define SI4126_TWI_DATA_MASK	__BITS(21, 4)
     41  1.2.4.1  rpaulo #define SI4126_TWI_ADDR_MASK	__BITS(3, 0)
     42      1.1  dyoung 
     43      1.1  dyoung /*
     44      1.1  dyoung  * Registers for Silicon Laboratories Si4126/Si4136 RF synthesizer.
     45      1.1  dyoung  */
     46      1.1  dyoung #define SI4126_MAIN	0	/* main configuration */
     47  1.2.4.1  rpaulo #define	SI4126_MAIN_AUXSEL_MASK	__BITS(13, 12)	/* aux. output pin function */
     48      1.1  dyoung /* reserved */
     49  1.2.4.1  rpaulo #define	SI4126_MAIN_AUXSEL_RSVD		__SHIFTIN(0x0, SI4126_MAIN_AUXSEL_MASK)
     50      1.1  dyoung /* force low */
     51  1.2.4.1  rpaulo #define	SI4126_MAIN_AUXSEL_FRCLOW	__SHIFTIN(0x1, SI4126_MAIN_AUXSEL_MASK)
     52      1.1  dyoung /* Lock Detect (LDETB) */
     53  1.2.4.1  rpaulo #define	SI4126_MAIN_AUXSEL_LDETB	__SHIFTIN(0x3, SI4126_MAIN_AUXSEL_MASK)
     54      1.1  dyoung 
     55  1.2.4.1  rpaulo #define	SI4126_MAIN_IFDIV_MASK	__BITS(11, 10)	/* IFOUT = IFVCO
     56      1.1  dyoung 						 * frequency / 2**IFDIV.
     57      1.1  dyoung 						 */
     58      1.1  dyoung 
     59  1.2.4.1  rpaulo /* 1: divide crystal input (XIN) by 2 */
     60  1.2.4.1  rpaulo #define	SI4126_MAIN_XINDIV2	__BIT(6)
     61  1.2.4.1  rpaulo #define	SI4126_MAIN_LPWR	__BIT(5)	/* 1: low-power mode */
     62  1.2.4.1  rpaulo #define	SI4126_MAIN_AUTOPDB	__BIT(3)	/* 1: equivalent to
     63  1.2.4.1  rpaulo 						 *    reg[SI4126_POWER] <-
     64  1.2.4.1  rpaulo 						 *    SI4126_POWER_PDIB |
     65  1.2.4.1  rpaulo 						 *    SI4126_POWER_PDRB.
     66  1.2.4.1  rpaulo 						 *
     67  1.2.4.1  rpaulo 						 * 0: power-down under control
     68  1.2.4.1  rpaulo 						 *    of reg[SI4126_POWER].
     69  1.2.4.1  rpaulo 						 */
     70      1.1  dyoung 
     71      1.1  dyoung #define	SI4126_GAIN	1		/* phase detector gain */
     72  1.2.4.1  rpaulo #define	SI4126_GAIN_KPI_MASK	__BITS(5, 4)	/* IF phase detector gain */
     73  1.2.4.1  rpaulo #define	SI4126_GAIN_KP2_MASK	__BITS(3, 2)	/* RF2 phase detector gain */
     74  1.2.4.1  rpaulo #define	SI4126_GAIN_KP1_MASK	__BITS(1, 0)	/* RF1 phase detector gain */
     75      1.1  dyoung 
     76      1.1  dyoung #define	SI4126_POWER	2		/* powerdown */
     77  1.2.4.1  rpaulo #define	SI4126_POWER_PDIB	__BIT(1)	/* 1: IF synthesizer on */
     78  1.2.4.1  rpaulo #define	SI4126_POWER_PDRB	__BIT(0)	/* 1: RF synthesizer on */
     79      1.1  dyoung 
     80      1.1  dyoung #define	SI4126_RF1N	3		/* RF1 N divider */
     81      1.1  dyoung #define	SI4126_RF2N	4		/* RF2 N divider */
     82      1.1  dyoung #define	SI4126_IFN	5		/* IF N divider */
     83      1.1  dyoung #define	SI4126_RF1R	6		/* RF1 R divider */
     84      1.1  dyoung #define	SI4126_RF2R	7		/* RF2 R divider */
     85      1.1  dyoung #define	SI4126_IFR	8		/* IF R divider */
     86      1.1  dyoung 
     87      1.1  dyoung #endif /* _DEV_IC_SI4136REG_H_ */
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