siisata.c revision 1.1.2.2
1 1.1.2.2 mjf /* $NetBSD: siisata.c,v 1.1.2.2 2008/06/02 13:23:27 mjf Exp $ */ 2 1.1.2.2 mjf /* Id: siisata.c,v 1.28 2008/05/21 15:51:36 jakllsch Exp */ 3 1.1.2.2 mjf 4 1.1.2.2 mjf /* from ahcisata_core.c */ 5 1.1.2.2 mjf 6 1.1.2.2 mjf /* 7 1.1.2.2 mjf * Copyright (c) 2006 Manuel Bouyer. 8 1.1.2.2 mjf * 9 1.1.2.2 mjf * Redistribution and use in source and binary forms, with or without 10 1.1.2.2 mjf * modification, are permitted provided that the following conditions 11 1.1.2.2 mjf * are met: 12 1.1.2.2 mjf * 1. Redistributions of source code must retain the above copyright 13 1.1.2.2 mjf * notice, this list of conditions and the following disclaimer. 14 1.1.2.2 mjf * 2. Redistributions in binary form must reproduce the above copyright 15 1.1.2.2 mjf * notice, this list of conditions and the following disclaimer in the 16 1.1.2.2 mjf * documentation and/or other materials provided with the distribution. 17 1.1.2.2 mjf * 3. All advertising materials mentioning features or use of this software 18 1.1.2.2 mjf * must display the following acknowledgement: 19 1.1.2.2 mjf * This product includes software developed by Manuel Bouyer. 20 1.1.2.2 mjf * 4. The name of the author may not be used to endorse or promote products 21 1.1.2.2 mjf * derived from this software without specific prior written permission. 22 1.1.2.2 mjf * 23 1.1.2.2 mjf * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 1.1.2.2 mjf * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 1.1.2.2 mjf * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 1.1.2.2 mjf * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 1.1.2.2 mjf * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 1.1.2.2 mjf * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 1.1.2.2 mjf * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 1.1.2.2 mjf * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 1.1.2.2 mjf * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 1.1.2.2 mjf * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 1.1.2.2 mjf * 34 1.1.2.2 mjf */ 35 1.1.2.2 mjf 36 1.1.2.2 mjf /* from atapi_wdc.c */ 37 1.1.2.2 mjf 38 1.1.2.2 mjf /* 39 1.1.2.2 mjf * Copyright (c) 1998, 2001 Manuel Bouyer. 40 1.1.2.2 mjf * 41 1.1.2.2 mjf * Redistribution and use in source and binary forms, with or without 42 1.1.2.2 mjf * modification, are permitted provided that the following conditions 43 1.1.2.2 mjf * are met: 44 1.1.2.2 mjf * 1. Redistributions of source code must retain the above copyright 45 1.1.2.2 mjf * notice, this list of conditions and the following disclaimer. 46 1.1.2.2 mjf * 2. Redistributions in binary form must reproduce the above copyright 47 1.1.2.2 mjf * notice, this list of conditions and the following disclaimer in the 48 1.1.2.2 mjf * documentation and/or other materials provided with the distribution. 49 1.1.2.2 mjf * 3. All advertising materials mentioning features or use of this software 50 1.1.2.2 mjf * must display the following acknowledgement: 51 1.1.2.2 mjf * This product includes software developed by Manuel Bouyer. 52 1.1.2.2 mjf * 4. The name of the author may not be used to endorse or promote products 53 1.1.2.2 mjf * derived from this software without specific prior written permission. 54 1.1.2.2 mjf * 55 1.1.2.2 mjf * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 1.1.2.2 mjf * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 1.1.2.2 mjf * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 1.1.2.2 mjf * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 1.1.2.2 mjf * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 1.1.2.2 mjf * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 1.1.2.2 mjf * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 1.1.2.2 mjf * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 1.1.2.2 mjf * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 1.1.2.2 mjf * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 1.1.2.2 mjf */ 66 1.1.2.2 mjf 67 1.1.2.2 mjf /*- 68 1.1.2.2 mjf * Copyright (c) 2007, 2008 Jonathan A. Kollasch. 69 1.1.2.2 mjf * All rights reserved. 70 1.1.2.2 mjf * 71 1.1.2.2 mjf * Redistribution and use in source and binary forms, with or without 72 1.1.2.2 mjf * modification, are permitted provided that the following conditions 73 1.1.2.2 mjf * are met: 74 1.1.2.2 mjf * 1. Redistributions of source code must retain the above copyright 75 1.1.2.2 mjf * notice, this list of conditions and the following disclaimer. 76 1.1.2.2 mjf * 2. Redistributions in binary form must reproduce the above copyright 77 1.1.2.2 mjf * notice, this list of conditions and the following disclaimer in the 78 1.1.2.2 mjf * documentation and/or other materials provided with the distribution. 79 1.1.2.2 mjf * 80 1.1.2.2 mjf * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 81 1.1.2.2 mjf * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 82 1.1.2.2 mjf * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 83 1.1.2.2 mjf * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 84 1.1.2.2 mjf * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 85 1.1.2.2 mjf * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 86 1.1.2.2 mjf * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 87 1.1.2.2 mjf * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 88 1.1.2.2 mjf * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 89 1.1.2.2 mjf * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 90 1.1.2.2 mjf * 91 1.1.2.2 mjf */ 92 1.1.2.2 mjf 93 1.1.2.2 mjf #include <sys/types.h> 94 1.1.2.2 mjf #include <sys/malloc.h> 95 1.1.2.2 mjf #include <sys/param.h> 96 1.1.2.2 mjf #include <sys/kernel.h> 97 1.1.2.2 mjf #include <sys/systm.h> 98 1.1.2.2 mjf #include <sys/syslog.h> 99 1.1.2.2 mjf #include <sys/disklabel.h> 100 1.1.2.2 mjf #include <sys/buf.h> 101 1.1.2.2 mjf 102 1.1.2.2 mjf #include <uvm/uvm_extern.h> 103 1.1.2.2 mjf 104 1.1.2.2 mjf #include <dev/ic/wdcreg.h> 105 1.1.2.2 mjf #include <dev/ata/atareg.h> 106 1.1.2.2 mjf #include <dev/ata/satavar.h> 107 1.1.2.2 mjf #include <dev/ata/satareg.h> 108 1.1.2.2 mjf #include <dev/ic/siisatavar.h> 109 1.1.2.2 mjf 110 1.1.2.2 mjf #include "atapibus.h" 111 1.1.2.2 mjf 112 1.1.2.2 mjf #ifdef SIISATA_DEBUG 113 1.1.2.2 mjf #if 0 114 1.1.2.2 mjf int siisata_debug_mask = 0xffff; 115 1.1.2.2 mjf #else 116 1.1.2.2 mjf int siisata_debug_mask = 0; 117 1.1.2.2 mjf #endif 118 1.1.2.2 mjf #endif 119 1.1.2.2 mjf 120 1.1.2.2 mjf #define ATA_DELAY 10000 /* 10s for a drive I/O */ 121 1.1.2.2 mjf 122 1.1.2.2 mjf static void siisata_attach_port(struct siisata_softc *, int); 123 1.1.2.2 mjf static void siisata_intr_port(struct siisata_softc *, 124 1.1.2.2 mjf struct siisata_channel *); 125 1.1.2.2 mjf 126 1.1.2.2 mjf void siisata_probe_drive(struct ata_channel *); 127 1.1.2.2 mjf void siisata_setup_channel(struct ata_channel *); 128 1.1.2.2 mjf 129 1.1.2.2 mjf int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); 130 1.1.2.2 mjf void siisata_reset_drive(struct ata_drive_datas *, int); 131 1.1.2.2 mjf void siisata_reset_channel(struct ata_channel *, int); 132 1.1.2.2 mjf int siisata_ata_addref(struct ata_drive_datas *); 133 1.1.2.2 mjf void siisata_ata_delref(struct ata_drive_datas *); 134 1.1.2.2 mjf void siisata_killpending(struct ata_drive_datas *); 135 1.1.2.2 mjf 136 1.1.2.2 mjf void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 137 1.1.2.2 mjf int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 138 1.1.2.2 mjf void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 139 1.1.2.2 mjf void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 140 1.1.2.2 mjf 141 1.1.2.2 mjf void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 142 1.1.2.2 mjf int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 143 1.1.2.2 mjf void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 144 1.1.2.2 mjf int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); 145 1.1.2.2 mjf 146 1.1.2.2 mjf void siisata_timeout(void *); 147 1.1.2.2 mjf 148 1.1.2.2 mjf static void siisata_reinit_port(struct siisata_softc *, struct ata_channel *); 149 1.1.2.2 mjf static void siisata_device_reset(struct siisata_softc *, struct ata_channel *); 150 1.1.2.2 mjf static inline void siisata_activate_prb(struct siisata_softc *, 151 1.1.2.2 mjf int, int, bus_addr_t); 152 1.1.2.2 mjf static int siisata_dma_setup(struct ata_channel *chp, int slot, 153 1.1.2.2 mjf void *data, size_t, int); 154 1.1.2.2 mjf 155 1.1.2.2 mjf #if NATAPIBUS > 0 156 1.1.2.2 mjf void siisata_atapibus_attach(struct atabus_softc *); 157 1.1.2.2 mjf void siisata_atapi_probe_device(struct atapibus_softc *, int); 158 1.1.2.2 mjf void siisata_atapi_minphys(struct buf *); 159 1.1.2.2 mjf void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 160 1.1.2.2 mjf int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int slot); 161 1.1.2.2 mjf void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 162 1.1.2.2 mjf void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 163 1.1.2.2 mjf void siisata_atapi_reset(struct ata_channel *, struct ata_xfer *); 164 1.1.2.2 mjf void siisata_atapi_scsipi_request(struct scsipi_channel *, 165 1.1.2.2 mjf scsipi_adapter_req_t, void *); 166 1.1.2.2 mjf void siisata_atapi_kill_pending(struct scsipi_periph *); 167 1.1.2.2 mjf #endif /* NATAPIBUS */ 168 1.1.2.2 mjf 169 1.1.2.2 mjf const struct ata_bustype siisata_ata_bustype = { 170 1.1.2.2 mjf SCSIPI_BUSTYPE_ATA, 171 1.1.2.2 mjf siisata_ata_bio, 172 1.1.2.2 mjf siisata_reset_drive, 173 1.1.2.2 mjf siisata_reset_channel, 174 1.1.2.2 mjf siisata_exec_command, 175 1.1.2.2 mjf ata_get_params, 176 1.1.2.2 mjf siisata_ata_addref, 177 1.1.2.2 mjf siisata_ata_delref, 178 1.1.2.2 mjf siisata_killpending 179 1.1.2.2 mjf }; 180 1.1.2.2 mjf 181 1.1.2.2 mjf #if NATAPIBUS > 0 182 1.1.2.2 mjf static const struct scsipi_bustype siisata_atapi_bustype = { 183 1.1.2.2 mjf SCSIPI_BUSTYPE_ATAPI, 184 1.1.2.2 mjf atapi_scsipi_cmd, 185 1.1.2.2 mjf atapi_interpret_sense, 186 1.1.2.2 mjf atapi_print_addr, 187 1.1.2.2 mjf siisata_atapi_kill_pending 188 1.1.2.2 mjf }; 189 1.1.2.2 mjf #endif /* NATAPIBUS */ 190 1.1.2.2 mjf 191 1.1.2.2 mjf 192 1.1.2.2 mjf void 193 1.1.2.2 mjf siisata_attach(struct siisata_softc *sc) 194 1.1.2.2 mjf { 195 1.1.2.2 mjf int i; 196 1.1.2.2 mjf 197 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 198 1.1.2.2 mjf SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 199 1.1.2.2 mjf 200 1.1.2.2 mjf /* come out of reset state */ 201 1.1.2.2 mjf GRWRITE(sc, GR_GC, 0); 202 1.1.2.2 mjf 203 1.1.2.2 mjf sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 204 1.1.2.2 mjf sc->sc_atac.atac_pio_cap = 4; 205 1.1.2.2 mjf sc->sc_atac.atac_dma_cap = 2; 206 1.1.2.2 mjf sc->sc_atac.atac_udma_cap = 6; 207 1.1.2.2 mjf sc->sc_atac.atac_channels = sc->sc_chanarray; 208 1.1.2.2 mjf sc->sc_atac.atac_probe = siisata_probe_drive; 209 1.1.2.2 mjf sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 210 1.1.2.2 mjf sc->sc_atac.atac_set_modes = siisata_setup_channel; 211 1.1.2.2 mjf #if NATAPIBUS > 0 212 1.1.2.2 mjf sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 213 1.1.2.2 mjf #endif 214 1.1.2.2 mjf 215 1.1.2.2 mjf for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 216 1.1.2.2 mjf siisata_attach_port(sc, i); 217 1.1.2.2 mjf } 218 1.1.2.2 mjf 219 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 220 1.1.2.2 mjf SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 221 1.1.2.2 mjf DEBUG_FUNCS); 222 1.1.2.2 mjf return; 223 1.1.2.2 mjf } 224 1.1.2.2 mjf 225 1.1.2.2 mjf static void 226 1.1.2.2 mjf siisata_init_port(struct siisata_softc *sc, int port) 227 1.1.2.2 mjf { 228 1.1.2.2 mjf struct siisata_channel *schp; 229 1.1.2.2 mjf struct ata_channel *chp; 230 1.1.2.2 mjf 231 1.1.2.2 mjf schp = &sc->sc_channels[port]; 232 1.1.2.2 mjf chp = (struct ata_channel *)schp; 233 1.1.2.2 mjf 234 1.1.2.2 mjf /* come out of reset, 64-bit activation */ 235 1.1.2.2 mjf PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 236 1.1.2.2 mjf PR_PC_32BA | PR_PC_PORT_RESET); 237 1.1.2.2 mjf /* initialize port */ 238 1.1.2.2 mjf siisata_reinit_port(sc, chp); 239 1.1.2.2 mjf /* clear any interrupts */ 240 1.1.2.2 mjf PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 241 1.1.2.2 mjf /* enable CmdErrr+CmdCmpl interrupting */ 242 1.1.2.2 mjf PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 243 1.1.2.2 mjf PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 244 1.1.2.2 mjf /* enable port interrupt */ 245 1.1.2.2 mjf GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 246 1.1.2.2 mjf } 247 1.1.2.2 mjf 248 1.1.2.2 mjf static void 249 1.1.2.2 mjf siisata_attach_port(struct siisata_softc *sc, int port) 250 1.1.2.2 mjf { 251 1.1.2.2 mjf int j; 252 1.1.2.2 mjf bus_dma_segment_t seg; 253 1.1.2.2 mjf int dmasize; 254 1.1.2.2 mjf int error; 255 1.1.2.2 mjf int rseg; 256 1.1.2.2 mjf void *prbp; 257 1.1.2.2 mjf struct siisata_channel *schp; 258 1.1.2.2 mjf struct ata_channel *chp; 259 1.1.2.2 mjf 260 1.1.2.2 mjf schp = &sc->sc_channels[port]; 261 1.1.2.2 mjf chp = (struct ata_channel *)schp; 262 1.1.2.2 mjf sc->sc_chanarray[port] = chp; 263 1.1.2.2 mjf chp->ch_channel = port; 264 1.1.2.2 mjf chp->ch_atac = &sc->sc_atac; 265 1.1.2.2 mjf chp->ch_queue = malloc(sizeof(struct ata_queue), 266 1.1.2.2 mjf M_DEVBUF, M_NOWAIT); 267 1.1.2.2 mjf if (chp->ch_queue == NULL) { 268 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 269 1.1.2.2 mjf "port %d: can't allocate memory " 270 1.1.2.2 mjf "for command queue", chp->ch_channel); 271 1.1.2.2 mjf goto error_out; 272 1.1.2.2 mjf } 273 1.1.2.2 mjf 274 1.1.2.2 mjf 275 1.1.2.2 mjf dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 276 1.1.2.2 mjf 277 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 278 1.1.2.2 mjf __func__, dmasize), DEBUG_FUNCS); 279 1.1.2.2 mjf 280 1.1.2.2 mjf error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 281 1.1.2.2 mjf &seg, 1, &rseg, BUS_DMA_NOWAIT); 282 1.1.2.2 mjf if (error) { 283 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 284 1.1.2.2 mjf "unable to allocate PRB table memory, " 285 1.1.2.2 mjf "error=%d\n", error); 286 1.1.2.2 mjf goto error_out; 287 1.1.2.2 mjf } 288 1.1.2.2 mjf 289 1.1.2.2 mjf error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 290 1.1.2.2 mjf &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 291 1.1.2.2 mjf if (error) { 292 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 293 1.1.2.2 mjf "unable to map PRB table memory, " 294 1.1.2.2 mjf "error=%d\n", error); 295 1.1.2.2 mjf goto error_out; 296 1.1.2.2 mjf } 297 1.1.2.2 mjf 298 1.1.2.2 mjf error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 299 1.1.2.2 mjf BUS_DMA_NOWAIT, &schp->sch_prbd); 300 1.1.2.2 mjf if (error) { 301 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 302 1.1.2.2 mjf "unable to create PRB table map, " 303 1.1.2.2 mjf "error=%d\n", error); 304 1.1.2.2 mjf goto error_out; 305 1.1.2.2 mjf } 306 1.1.2.2 mjf 307 1.1.2.2 mjf error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 308 1.1.2.2 mjf prbp, dmasize, NULL, BUS_DMA_NOWAIT); 309 1.1.2.2 mjf if (error) { 310 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 311 1.1.2.2 mjf "unable to load PRB table map, " 312 1.1.2.2 mjf "error=%d\n", error); 313 1.1.2.2 mjf goto error_out; 314 1.1.2.2 mjf } 315 1.1.2.2 mjf 316 1.1.2.2 mjf for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 317 1.1.2.2 mjf schp->sch_prb[j] = (struct siisata_prb *) 318 1.1.2.2 mjf ((char *)prbp + SIISATA_CMD_SIZE * j); 319 1.1.2.2 mjf schp->sch_bus_prb[j] = 320 1.1.2.2 mjf schp->sch_prbd->dm_segs[0].ds_addr + 321 1.1.2.2 mjf SIISATA_CMD_SIZE * j; 322 1.1.2.2 mjf error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 323 1.1.2.2 mjf SIISATA_NSGE, MAXPHYS, 0, 324 1.1.2.2 mjf BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 325 1.1.2.2 mjf &schp->sch_datad[j]); 326 1.1.2.2 mjf if (error) { 327 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 328 1.1.2.2 mjf "couldn't create xfer DMA map, error=%d\n", 329 1.1.2.2 mjf error); 330 1.1.2.2 mjf goto error_out; 331 1.1.2.2 mjf } 332 1.1.2.2 mjf } 333 1.1.2.2 mjf 334 1.1.2.2 mjf chp->ch_ndrive = 1; 335 1.1.2.2 mjf if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 336 1.1.2.2 mjf PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 337 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 338 1.1.2.2 mjf "couldn't map port %d SStatus regs\n", 339 1.1.2.2 mjf chp->ch_channel); 340 1.1.2.2 mjf goto error_out; 341 1.1.2.2 mjf } 342 1.1.2.2 mjf if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 343 1.1.2.2 mjf PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 344 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 345 1.1.2.2 mjf "couldn't map port %d SControl regs\n", 346 1.1.2.2 mjf chp->ch_channel); 347 1.1.2.2 mjf goto error_out; 348 1.1.2.2 mjf } 349 1.1.2.2 mjf if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 350 1.1.2.2 mjf PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 351 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 352 1.1.2.2 mjf "couldn't map port %d SError regs\n", 353 1.1.2.2 mjf chp->ch_channel); 354 1.1.2.2 mjf goto error_out; 355 1.1.2.2 mjf } 356 1.1.2.2 mjf 357 1.1.2.2 mjf siisata_init_port(sc, port); 358 1.1.2.2 mjf 359 1.1.2.2 mjf ata_channel_attach(chp); 360 1.1.2.2 mjf error_out: 361 1.1.2.2 mjf return; 362 1.1.2.2 mjf } 363 1.1.2.2 mjf 364 1.1.2.2 mjf void 365 1.1.2.2 mjf siisata_resume(struct siisata_softc *sc) 366 1.1.2.2 mjf { 367 1.1.2.2 mjf int i; 368 1.1.2.2 mjf 369 1.1.2.2 mjf /* come out of reset state */ 370 1.1.2.2 mjf GRWRITE(sc, GR_GC, 0); 371 1.1.2.2 mjf 372 1.1.2.2 mjf for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 373 1.1.2.2 mjf siisata_init_port(sc, i); 374 1.1.2.2 mjf } 375 1.1.2.2 mjf 376 1.1.2.2 mjf } 377 1.1.2.2 mjf 378 1.1.2.2 mjf int 379 1.1.2.2 mjf siisata_intr(void *v) 380 1.1.2.2 mjf { 381 1.1.2.2 mjf struct siisata_softc *sc = v; 382 1.1.2.2 mjf uint32_t is; 383 1.1.2.2 mjf int i, r = 0; 384 1.1.2.2 mjf while ((is = GRREAD(sc, GR_GIS))) { 385 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 386 1.1.2.2 mjf SIISATANAME(sc), __func__, is), DEBUG_INTR); 387 1.1.2.2 mjf r = 1; 388 1.1.2.2 mjf for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 389 1.1.2.2 mjf if (is & GR_GIS_PXIS(i)) 390 1.1.2.2 mjf siisata_intr_port(sc, &sc->sc_channels[i]); 391 1.1.2.2 mjf } 392 1.1.2.2 mjf return r; 393 1.1.2.2 mjf } 394 1.1.2.2 mjf 395 1.1.2.2 mjf static void 396 1.1.2.2 mjf siisata_intr_port(struct siisata_softc *sc, struct siisata_channel *schp) 397 1.1.2.2 mjf { 398 1.1.2.2 mjf struct ata_channel *chp = &schp->ata_channel; 399 1.1.2.2 mjf struct ata_xfer *xfer = chp->ch_queue->active_xfer; 400 1.1.2.2 mjf int slot = SIISATA_NON_NCQ_SLOT; 401 1.1.2.2 mjf 402 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s port %d\n", 403 1.1.2.2 mjf SIISATANAME(sc), __func__, chp->ch_channel), DEBUG_INTR); 404 1.1.2.2 mjf 405 1.1.2.2 mjf if ((xfer != NULL) && (xfer->c_intr != NULL)) 406 1.1.2.2 mjf xfer->c_intr(chp, xfer, slot); 407 1.1.2.2 mjf #ifdef DIAGNOSTIC 408 1.1.2.2 mjf else 409 1.1.2.2 mjf log(LOG_WARNING, "%s: unable to handle interrupt\n", __func__); 410 1.1.2.2 mjf #endif 411 1.1.2.2 mjf 412 1.1.2.2 mjf /* clear some (ok, all) ints */ 413 1.1.2.2 mjf PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 414 1.1.2.2 mjf 415 1.1.2.2 mjf return; 416 1.1.2.2 mjf } 417 1.1.2.2 mjf 418 1.1.2.2 mjf void 419 1.1.2.2 mjf siisata_reset_drive(struct ata_drive_datas *drvp, int flags) 420 1.1.2.2 mjf { 421 1.1.2.2 mjf struct ata_channel *chp = drvp->chnl_softc; 422 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 423 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 424 1.1.2.2 mjf struct siisata_prb *prb; 425 1.1.2.2 mjf int slot = SIISATA_NON_NCQ_SLOT; 426 1.1.2.2 mjf 427 1.1.2.2 mjf /* wait for ready */ 428 1.1.2.2 mjf while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 429 1.1.2.2 mjf DELAY(10); 430 1.1.2.2 mjf 431 1.1.2.2 mjf prb = schp->sch_prb[slot]; 432 1.1.2.2 mjf memset(prb, 0, sizeof(struct siisata_prb)); 433 1.1.2.2 mjf prb->prb_control = 434 1.1.2.2 mjf htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 435 1.1.2.2 mjf 436 1.1.2.2 mjf SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 437 1.1.2.2 mjf siisata_activate_prb(sc, chp->ch_channel, 438 1.1.2.2 mjf slot, schp->sch_bus_prb[slot]); 439 1.1.2.2 mjf 440 1.1.2.2 mjf /* wait for completion */ 441 1.1.2.2 mjf while (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & PR_PXSS(slot)) 442 1.1.2.2 mjf DELAY(10); 443 1.1.2.2 mjf SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 444 1.1.2.2 mjf 445 1.1.2.2 mjf log(LOG_DEBUG, "%s: ch_status %x ch_error %x\n", 446 1.1.2.2 mjf __func__, chp->ch_status, chp->ch_error); 447 1.1.2.2 mjf 448 1.1.2.2 mjf #if 1 449 1.1.2.2 mjf /* attempt to downgrade signaling in event of CRC error */ 450 1.1.2.2 mjf /* XXX should be part of the MI (S)ATA subsystem */ 451 1.1.2.2 mjf if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 452 1.1.2.2 mjf bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 453 1.1.2.2 mjf SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 454 1.1.2.2 mjf DELAY(10); 455 1.1.2.2 mjf bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 456 1.1.2.2 mjf SControl_IPM_NONE | SControl_SPD_G1); 457 1.1.2.2 mjf DELAY(10); 458 1.1.2.2 mjf for (;;) { 459 1.1.2.2 mjf if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 460 1.1.2.2 mjf & SStatus_DET_mask) == SStatus_DET_DEV) 461 1.1.2.2 mjf break; 462 1.1.2.2 mjf DELAY(10); 463 1.1.2.2 mjf } 464 1.1.2.2 mjf } 465 1.1.2.2 mjf #endif 466 1.1.2.2 mjf 467 1.1.2.2 mjf #if 1 468 1.1.2.2 mjf chp->ch_status = 0; 469 1.1.2.2 mjf chp->ch_error = 0; 470 1.1.2.2 mjf #endif 471 1.1.2.2 mjf return; 472 1.1.2.2 mjf } 473 1.1.2.2 mjf 474 1.1.2.2 mjf void 475 1.1.2.2 mjf siisata_reset_channel(struct ata_channel *chp, int flags) 476 1.1.2.2 mjf { 477 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 478 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 479 1.1.2.2 mjf 480 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 481 1.1.2.2 mjf DEBUG_FUNCS); 482 1.1.2.2 mjf 483 1.1.2.2 mjf if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 484 1.1.2.2 mjf schp->sch_sstatus) != SStatus_DET_DEV) { 485 1.1.2.2 mjf log(LOG_CRIT, "%s port %d: reset failed\n", 486 1.1.2.2 mjf SIISATANAME(sc), chp->ch_channel); 487 1.1.2.2 mjf /* XXX and then ? */ 488 1.1.2.2 mjf } 489 1.1.2.2 mjf while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 490 1.1.2.2 mjf DELAY(10); 491 1.1.2.2 mjf PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 492 1.1.2.2 mjf PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 493 1.1.2.2 mjf if (chp->ch_queue->active_xfer) { 494 1.1.2.2 mjf chp->ch_queue->active_xfer->c_kill_xfer(chp, 495 1.1.2.2 mjf chp->ch_queue->active_xfer, KILL_RESET); 496 1.1.2.2 mjf } 497 1.1.2.2 mjf 498 1.1.2.2 mjf return; 499 1.1.2.2 mjf } 500 1.1.2.2 mjf 501 1.1.2.2 mjf int 502 1.1.2.2 mjf siisata_ata_addref(struct ata_drive_datas *drvp) 503 1.1.2.2 mjf { 504 1.1.2.2 mjf return 0; 505 1.1.2.2 mjf } 506 1.1.2.2 mjf 507 1.1.2.2 mjf void 508 1.1.2.2 mjf siisata_ata_delref(struct ata_drive_datas *drvp) 509 1.1.2.2 mjf { 510 1.1.2.2 mjf return; 511 1.1.2.2 mjf } 512 1.1.2.2 mjf 513 1.1.2.2 mjf void 514 1.1.2.2 mjf siisata_killpending(struct ata_drive_datas *drvp) 515 1.1.2.2 mjf { 516 1.1.2.2 mjf return; 517 1.1.2.2 mjf } 518 1.1.2.2 mjf 519 1.1.2.2 mjf void 520 1.1.2.2 mjf siisata_probe_drive(struct ata_channel *chp) 521 1.1.2.2 mjf { 522 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 523 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 524 1.1.2.2 mjf int i; 525 1.1.2.2 mjf int s; 526 1.1.2.2 mjf uint32_t sig; 527 1.1.2.2 mjf int slot = SIISATA_NON_NCQ_SLOT; 528 1.1.2.2 mjf struct siisata_prb *prb; 529 1.1.2.2 mjf 530 1.1.2.2 mjf DELAY(chp->ch_channel * 2048 + 1023); /* XXX */ 531 1.1.2.2 mjf 532 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 533 1.1.2.2 mjf __func__, chp->ch_channel), DEBUG_FUNCS); 534 1.1.2.2 mjf 535 1.1.2.2 mjf /* XXX This should be done by other code. */ 536 1.1.2.2 mjf for (i = 0; i < chp->ch_ndrive; i++) { 537 1.1.2.2 mjf chp->ch_drive[i].chnl_softc = chp; 538 1.1.2.2 mjf chp->ch_drive[i].drive = i; 539 1.1.2.2 mjf } 540 1.1.2.2 mjf 541 1.1.2.2 mjf switch (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 542 1.1.2.2 mjf schp->sch_sstatus)) { 543 1.1.2.2 mjf case SStatus_DET_DEV: 544 1.1.2.2 mjf /* wait for ready */ 545 1.1.2.2 mjf while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) 546 1.1.2.2 mjf & PR_PS_PORT_READY)) 547 1.1.2.2 mjf DELAY(10); 548 1.1.2.2 mjf 549 1.1.2.2 mjf prb = schp->sch_prb[slot]; 550 1.1.2.2 mjf memset(prb, 0, sizeof(struct siisata_prb)); 551 1.1.2.2 mjf prb->prb_control = 552 1.1.2.2 mjf htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 553 1.1.2.2 mjf 554 1.1.2.2 mjf SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 555 1.1.2.2 mjf siisata_activate_prb(sc, chp->ch_channel, 556 1.1.2.2 mjf slot, schp->sch_bus_prb[slot]); 557 1.1.2.2 mjf 558 1.1.2.2 mjf /* wait for completion */ 559 1.1.2.2 mjf while (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) 560 1.1.2.2 mjf & PR_PXSS(slot)) 561 1.1.2.2 mjf DELAY(10); 562 1.1.2.2 mjf SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 563 1.1.2.2 mjf 564 1.1.2.2 mjf /* read the signature out of the FIS */ 565 1.1.2.2 mjf sig = 0; 566 1.1.2.2 mjf sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 567 1.1.2.2 mjf PRSO_FIS+0x4)) & 0x00ffffff) << 8; 568 1.1.2.2 mjf sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 569 1.1.2.2 mjf PRSO_FIS+0xc)) & 0xff; 570 1.1.2.2 mjf 571 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 572 1.1.2.2 mjf __func__, sig), DEBUG_PROBE); 573 1.1.2.2 mjf 574 1.1.2.2 mjf /* some ATAPI devices have bogus lower two bytes, sigh */ 575 1.1.2.2 mjf if ((sig & 0xffff0000) == 0xeb140000) { 576 1.1.2.2 mjf sig &= 0xffff0000; 577 1.1.2.2 mjf sig |= 0x00000101; 578 1.1.2.2 mjf } 579 1.1.2.2 mjf 580 1.1.2.2 mjf s = splbio(); 581 1.1.2.2 mjf switch (sig) { 582 1.1.2.2 mjf case 0xeb140101: 583 1.1.2.2 mjf chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 584 1.1.2.2 mjf break; 585 1.1.2.2 mjf case 0x00000101: 586 1.1.2.2 mjf chp->ch_drive[0].drive_flags |= DRIVE_ATA; 587 1.1.2.2 mjf break; 588 1.1.2.2 mjf default: 589 1.1.2.2 mjf aprint_error_dev(sc->sc_atac.atac_dev, 590 1.1.2.2 mjf "%s: unknown device signature 0x%08x\n", 591 1.1.2.2 mjf __func__, sig); 592 1.1.2.2 mjf } 593 1.1.2.2 mjf splx(s); 594 1.1.2.2 mjf break; 595 1.1.2.2 mjf default: 596 1.1.2.2 mjf break; 597 1.1.2.2 mjf } 598 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 599 1.1.2.2 mjf __func__, chp->ch_channel), DEBUG_PROBE); 600 1.1.2.2 mjf return; 601 1.1.2.2 mjf } 602 1.1.2.2 mjf 603 1.1.2.2 mjf void 604 1.1.2.2 mjf siisata_setup_channel(struct ata_channel *chp) 605 1.1.2.2 mjf { 606 1.1.2.2 mjf return; 607 1.1.2.2 mjf } 608 1.1.2.2 mjf 609 1.1.2.2 mjf int 610 1.1.2.2 mjf siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 611 1.1.2.2 mjf { 612 1.1.2.2 mjf struct ata_channel *chp = drvp->chnl_softc; 613 1.1.2.2 mjf struct ata_xfer *xfer; 614 1.1.2.2 mjf int ret; 615 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 616 1.1.2.2 mjf int s; 617 1.1.2.2 mjf 618 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s begins\n", 619 1.1.2.2 mjf SIISATANAME(sc), __func__), DEBUG_FUNCS); 620 1.1.2.2 mjf 621 1.1.2.2 mjf xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? 622 1.1.2.2 mjf ATAXF_CANSLEEP : ATAXF_NOSLEEP); 623 1.1.2.2 mjf if (xfer == NULL) 624 1.1.2.2 mjf return ATACMD_TRY_AGAIN; 625 1.1.2.2 mjf if (ata_c->flags & AT_POLL) 626 1.1.2.2 mjf xfer->c_flags |= C_POLL; 627 1.1.2.2 mjf if (ata_c->flags & AT_WAIT) 628 1.1.2.2 mjf xfer->c_flags |= C_WAIT; 629 1.1.2.2 mjf xfer->c_drive = drvp->drive; 630 1.1.2.2 mjf xfer->c_databuf = ata_c->data; 631 1.1.2.2 mjf xfer->c_bcount = ata_c->bcount; 632 1.1.2.2 mjf xfer->c_cmd = ata_c; 633 1.1.2.2 mjf xfer->c_start = siisata_cmd_start; 634 1.1.2.2 mjf xfer->c_intr = siisata_cmd_complete; 635 1.1.2.2 mjf xfer->c_kill_xfer = siisata_cmd_kill_xfer; 636 1.1.2.2 mjf s = splbio(); 637 1.1.2.2 mjf ata_exec_xfer(chp, xfer); 638 1.1.2.2 mjf #ifdef DIAGNOSTIC 639 1.1.2.2 mjf if ((ata_c->flags & AT_POLL) != 0 && 640 1.1.2.2 mjf (ata_c->flags & AT_DONE) == 0) 641 1.1.2.2 mjf panic("%s: polled command not done", __func__); 642 1.1.2.2 mjf #endif 643 1.1.2.2 mjf if (ata_c->flags & AT_DONE) { 644 1.1.2.2 mjf ret = ATACMD_COMPLETE; 645 1.1.2.2 mjf } else { 646 1.1.2.2 mjf if (ata_c->flags & AT_WAIT) { 647 1.1.2.2 mjf while ((ata_c->flags & AT_DONE) == 0) { 648 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 649 1.1.2.2 mjf SIISATANAME(sc), __func__), DEBUG_FUNCS); 650 1.1.2.2 mjf tsleep(ata_c, PRIBIO, "siicmd", 0); 651 1.1.2.2 mjf } 652 1.1.2.2 mjf ret = ATACMD_COMPLETE; 653 1.1.2.2 mjf } else { 654 1.1.2.2 mjf ret = ATACMD_QUEUED; 655 1.1.2.2 mjf } 656 1.1.2.2 mjf } 657 1.1.2.2 mjf splx(s); 658 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 659 1.1.2.2 mjf ("%s: %s ends\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 660 1.1.2.2 mjf return ret; 661 1.1.2.2 mjf } 662 1.1.2.2 mjf 663 1.1.2.2 mjf void 664 1.1.2.2 mjf siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 665 1.1.2.2 mjf { 666 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 667 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 668 1.1.2.2 mjf struct ata_command *ata_c = xfer->c_cmd; 669 1.1.2.2 mjf int slot = SIISATA_NON_NCQ_SLOT; 670 1.1.2.2 mjf struct siisata_prb *prb; 671 1.1.2.2 mjf uint8_t *fis; 672 1.1.2.2 mjf int i; 673 1.1.2.2 mjf 674 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 675 1.1.2.2 mjf ("%s: %s port %d, slot %d\n", 676 1.1.2.2 mjf SIISATANAME(sc), __func__, chp->ch_channel, slot), 677 1.1.2.2 mjf DEBUG_FUNCS); 678 1.1.2.2 mjf 679 1.1.2.2 mjf #ifdef DIAGNOSTIC 680 1.1.2.2 mjf if (__predict_false(schp->sch_active_slots & __BIT(slot))) { 681 1.1.2.2 mjf panic("%s %s trying to use already active slot %d", 682 1.1.2.2 mjf SIISATANAME(sc), __func__, slot); 683 1.1.2.2 mjf } 684 1.1.2.2 mjf #endif 685 1.1.2.2 mjf 686 1.1.2.2 mjf prb = schp->sch_prb[slot]; 687 1.1.2.2 mjf memset(prb, 0, sizeof(struct siisata_prb)); 688 1.1.2.2 mjf fis = prb->prb_fis; 689 1.1.2.2 mjf 690 1.1.2.2 mjf /* XXX probably needs to be some common FIS-related code */ 691 1.1.2.2 mjf fis[0] = 0x27; /* host to device */ 692 1.1.2.2 mjf fis[1] = 0x80; /* command FIS (also, PMP) */ 693 1.1.2.2 mjf fis[2] = ata_c->r_command; 694 1.1.2.2 mjf fis[3] = ata_c->r_features; 695 1.1.2.2 mjf fis[4] = ata_c->r_sector; 696 1.1.2.2 mjf fis[5] = ata_c->r_cyl & 0xff; 697 1.1.2.2 mjf fis[6] = (ata_c->r_cyl >> 8) & 0xff; 698 1.1.2.2 mjf fis[7] = ata_c->r_head & 0x0f; 699 1.1.2.2 mjf fis[12] = ata_c->r_count; 700 1.1.2.2 mjf fis[15] = WDCTL_4BIT; 701 1.1.2.2 mjf 702 1.1.2.2 mjf memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 703 1.1.2.2 mjf 704 1.1.2.2 mjf if (siisata_dma_setup(chp, slot, 705 1.1.2.2 mjf (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 706 1.1.2.2 mjf ata_c->bcount, 707 1.1.2.2 mjf (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 708 1.1.2.2 mjf ata_c->flags |= AT_DF; 709 1.1.2.2 mjf siisata_cmd_complete(chp, xfer, slot); 710 1.1.2.2 mjf return; 711 1.1.2.2 mjf } 712 1.1.2.2 mjf 713 1.1.2.2 mjf if (xfer->c_flags & C_POLL) { 714 1.1.2.2 mjf /* polled command, disable interrupts */ 715 1.1.2.2 mjf GRWRITE(sc, GR_GC, 716 1.1.2.2 mjf GRREAD(sc, GR_GC) & ~(GR_GC_PXIE(chp->ch_channel))); 717 1.1.2.2 mjf } 718 1.1.2.2 mjf 719 1.1.2.2 mjf /* go for it */ 720 1.1.2.2 mjf SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 721 1.1.2.2 mjf siisata_activate_prb(sc, chp->ch_channel, 722 1.1.2.2 mjf slot, schp->sch_bus_prb[slot]); 723 1.1.2.2 mjf 724 1.1.2.2 mjf /* keep track of what's going on */ 725 1.1.2.2 mjf schp->sch_active_slots |= __BIT(slot); 726 1.1.2.2 mjf 727 1.1.2.2 mjf if ((ata_c->flags & AT_POLL) == 0) { 728 1.1.2.2 mjf chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 729 1.1.2.2 mjf callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 730 1.1.2.2 mjf siisata_timeout, chp); 731 1.1.2.2 mjf goto out; 732 1.1.2.2 mjf } 733 1.1.2.2 mjf 734 1.1.2.2 mjf for (i = 0; i < ata_c->timeout / 10; i++) { 735 1.1.2.2 mjf if (ata_c->flags & AT_DONE) 736 1.1.2.2 mjf break; 737 1.1.2.2 mjf siisata_intr_port(sc, schp); 738 1.1.2.2 mjf if (ata_c->flags & AT_WAIT) 739 1.1.2.2 mjf tsleep(&xfer, PRIBIO, "siipl", mstohz(10)); 740 1.1.2.2 mjf else 741 1.1.2.2 mjf DELAY(10000); 742 1.1.2.2 mjf } 743 1.1.2.2 mjf 744 1.1.2.2 mjf if ((ata_c->flags & AT_DONE) == 0) { 745 1.1.2.2 mjf ata_c->flags |= AT_TIMEOU; 746 1.1.2.2 mjf siisata_cmd_complete(chp, xfer, slot); 747 1.1.2.2 mjf } 748 1.1.2.2 mjf 749 1.1.2.2 mjf /* reenable interrupts */ 750 1.1.2.2 mjf GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 751 1.1.2.2 mjf out: 752 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 753 1.1.2.2 mjf ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 754 1.1.2.2 mjf return; 755 1.1.2.2 mjf } 756 1.1.2.2 mjf 757 1.1.2.2 mjf void 758 1.1.2.2 mjf siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 759 1.1.2.2 mjf int reason) 760 1.1.2.2 mjf { 761 1.1.2.2 mjf int slot = SIISATA_NON_NCQ_SLOT; 762 1.1.2.2 mjf 763 1.1.2.2 mjf struct ata_command *ata_c = xfer->c_cmd; 764 1.1.2.2 mjf switch (reason) { 765 1.1.2.2 mjf case KILL_GONE: 766 1.1.2.2 mjf ata_c->flags |= AT_GONE; 767 1.1.2.2 mjf break; 768 1.1.2.2 mjf case KILL_RESET: 769 1.1.2.2 mjf ata_c->flags |= AT_RESET; 770 1.1.2.2 mjf break; 771 1.1.2.2 mjf default: 772 1.1.2.2 mjf panic("%s: port %d: unknown reason %d", 773 1.1.2.2 mjf __func__, chp->ch_channel, reason); 774 1.1.2.2 mjf } 775 1.1.2.2 mjf siisata_cmd_done(chp, xfer, slot); 776 1.1.2.2 mjf } 777 1.1.2.2 mjf 778 1.1.2.2 mjf int 779 1.1.2.2 mjf siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 780 1.1.2.2 mjf { 781 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 782 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 783 1.1.2.2 mjf struct ata_command *ata_c = xfer->c_cmd; 784 1.1.2.2 mjf uint32_t pss, pis; 785 1.1.2.2 mjf uint8_t fis[4]; 786 1.1.2.2 mjf uint32_t *prbfis = (void *)fis; 787 1.1.2.2 mjf 788 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 789 1.1.2.2 mjf ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 790 1.1.2.2 mjf 791 1.1.2.2 mjf pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 792 1.1.2.2 mjf 793 1.1.2.2 mjf if ((xfer->c_flags & C_TIMEOU) != 0) 794 1.1.2.2 mjf goto command_done; 795 1.1.2.2 mjf 796 1.1.2.2 mjf if (pis & PR_PIS_CMDCMPL) { 797 1.1.2.2 mjf /* get slot status, clearing completion interrupt */ 798 1.1.2.2 mjf pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 799 1.1.2.2 mjf /* is this expected? */ 800 1.1.2.2 mjf if ((schp->sch_active_slots & __BIT(slot)) == 0) { 801 1.1.2.2 mjf log(LOG_WARNING, "%s: unexpected command " 802 1.1.2.2 mjf "completion on port %d slot %d\n", 803 1.1.2.2 mjf SIISATANAME(sc), chp->ch_channel, slot); 804 1.1.2.2 mjf return 0; 805 1.1.2.2 mjf } else 806 1.1.2.2 mjf goto command_done; 807 1.1.2.2 mjf } 808 1.1.2.2 mjf 809 1.1.2.2 mjf if (pis & PR_PIS_CMDERRR) { 810 1.1.2.2 mjf uint32_t ec; 811 1.1.2.2 mjf 812 1.1.2.2 mjf /* emulate a CRC error by default */ 813 1.1.2.2 mjf chp->ch_status = WDCS_ERR; 814 1.1.2.2 mjf chp->ch_error = WDCE_CRC; 815 1.1.2.2 mjf 816 1.1.2.2 mjf ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 817 1.1.2.2 mjf if (ec <= PR_PCE_DATAFISERROR) { 818 1.1.2.2 mjf if (ec != PR_PCE_DATAFISERROR) { 819 1.1.2.2 mjf /* read in specific information about error */ 820 1.1.2.2 mjf *prbfis = bus_space_read_stream_4( 821 1.1.2.2 mjf sc->sc_prt, sc->sc_prh, 822 1.1.2.2 mjf PRSX(chp->ch_channel, slot, PRSO_FIS)); 823 1.1.2.2 mjf chp->ch_status = fis[2]; 824 1.1.2.2 mjf chp->ch_error = fis[3]; 825 1.1.2.2 mjf } 826 1.1.2.2 mjf siisata_reinit_port(sc, chp); 827 1.1.2.2 mjf } else { 828 1.1.2.2 mjf /* okay, we have a "Fatal Error" */ 829 1.1.2.2 mjf siisata_device_reset(sc, chp); 830 1.1.2.2 mjf } 831 1.1.2.2 mjf goto command_done; 832 1.1.2.2 mjf } 833 1.1.2.2 mjf return 0; 834 1.1.2.2 mjf 835 1.1.2.2 mjf command_done: 836 1.1.2.2 mjf chp->ch_flags &= ~ATACH_IRQ_WAIT; 837 1.1.2.2 mjf if (xfer->c_flags & C_TIMEOU) 838 1.1.2.2 mjf ata_c->flags |= AT_TIMEOU; 839 1.1.2.2 mjf else 840 1.1.2.2 mjf callout_stop(&chp->ch_callout); 841 1.1.2.2 mjf 842 1.1.2.2 mjf 843 1.1.2.2 mjf if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 844 1.1.2.2 mjf siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); 845 1.1.2.2 mjf chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 846 1.1.2.2 mjf wakeup(&chp->ch_queue->active_xfer); 847 1.1.2.2 mjf return 0; 848 1.1.2.2 mjf } 849 1.1.2.2 mjf 850 1.1.2.2 mjf chp->ch_queue->active_xfer = NULL; 851 1.1.2.2 mjf 852 1.1.2.2 mjf if (pis) { 853 1.1.2.2 mjf ata_c->r_head = 0; 854 1.1.2.2 mjf ata_c->r_count = 0; 855 1.1.2.2 mjf ata_c->r_sector = 0; 856 1.1.2.2 mjf ata_c->r_cyl = 0; 857 1.1.2.2 mjf if (chp->ch_status & WDCS_BSY) { 858 1.1.2.2 mjf ata_c->flags |= AT_TIMEOU; 859 1.1.2.2 mjf } else if (chp->ch_status & WDCS_ERR) { 860 1.1.2.2 mjf ata_c->r_error = chp->ch_error; 861 1.1.2.2 mjf ata_c->flags |= AT_ERROR; 862 1.1.2.2 mjf } 863 1.1.2.2 mjf } 864 1.1.2.2 mjf siisata_cmd_done(chp, xfer, slot); 865 1.1.2.2 mjf return 0; 866 1.1.2.2 mjf } 867 1.1.2.2 mjf 868 1.1.2.2 mjf void 869 1.1.2.2 mjf siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 870 1.1.2.2 mjf { 871 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 872 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 873 1.1.2.2 mjf struct ata_command *ata_c = xfer->c_cmd; 874 1.1.2.2 mjf int i; 875 1.1.2.2 mjf uint16_t *idwordbuf; 876 1.1.2.2 mjf 877 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 878 1.1.2.2 mjf ("%s: %s.\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 879 1.1.2.2 mjf 880 1.1.2.2 mjf /* this comamnd is not active any more */ 881 1.1.2.2 mjf schp->sch_active_slots &= ~__BIT(slot); 882 1.1.2.2 mjf 883 1.1.2.2 mjf /* we're done with the prb */ 884 1.1.2.2 mjf SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 885 1.1.2.2 mjf 886 1.1.2.2 mjf if (ata_c->flags & (AT_READ | AT_WRITE)) { 887 1.1.2.2 mjf bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 888 1.1.2.2 mjf schp->sch_datad[slot]->dm_mapsize, 889 1.1.2.2 mjf (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 890 1.1.2.2 mjf BUS_DMASYNC_POSTWRITE); 891 1.1.2.2 mjf bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 892 1.1.2.2 mjf } 893 1.1.2.2 mjf 894 1.1.2.2 mjf idwordbuf = xfer->c_databuf; 895 1.1.2.2 mjf 896 1.1.2.2 mjf /* correct the endianess of IDENTIFY data */ 897 1.1.2.2 mjf if (ata_c->r_command == WDCC_IDENTIFY || 898 1.1.2.2 mjf ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 899 1.1.2.2 mjf for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 900 1.1.2.2 mjf idwordbuf[i] = le16toh(idwordbuf[i]); 901 1.1.2.2 mjf } 902 1.1.2.2 mjf } 903 1.1.2.2 mjf 904 1.1.2.2 mjf ata_c->flags |= AT_DONE; 905 1.1.2.2 mjf if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 906 1.1.2.2 mjf ata_c->flags |= AT_XFDONE; 907 1.1.2.2 mjf 908 1.1.2.2 mjf ata_free_xfer(chp, xfer); 909 1.1.2.2 mjf if (ata_c->flags & AT_WAIT) 910 1.1.2.2 mjf wakeup(ata_c); 911 1.1.2.2 mjf else if (ata_c->callback) 912 1.1.2.2 mjf ata_c->callback(ata_c->callback_arg); 913 1.1.2.2 mjf atastart(chp); 914 1.1.2.2 mjf return; 915 1.1.2.2 mjf } 916 1.1.2.2 mjf 917 1.1.2.2 mjf int 918 1.1.2.2 mjf siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 919 1.1.2.2 mjf { 920 1.1.2.2 mjf struct ata_channel *chp = drvp->chnl_softc; 921 1.1.2.2 mjf struct ata_xfer *xfer; 922 1.1.2.2 mjf 923 1.1.2.2 mjf #if 1 924 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 925 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 926 1.1.2.2 mjf ("%s: %s.\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 927 1.1.2.2 mjf #endif 928 1.1.2.2 mjf 929 1.1.2.2 mjf xfer = ata_get_xfer(ATAXF_NOSLEEP); 930 1.1.2.2 mjf if (xfer == NULL) 931 1.1.2.2 mjf return ATACMD_TRY_AGAIN; 932 1.1.2.2 mjf if (ata_bio->flags & ATA_POLL) 933 1.1.2.2 mjf xfer->c_flags |= C_POLL; 934 1.1.2.2 mjf xfer->c_drive = drvp->drive; 935 1.1.2.2 mjf xfer->c_cmd = ata_bio; 936 1.1.2.2 mjf xfer->c_databuf = ata_bio->databuf; 937 1.1.2.2 mjf xfer->c_bcount = ata_bio->bcount; 938 1.1.2.2 mjf xfer->c_start = siisata_bio_start; 939 1.1.2.2 mjf xfer->c_intr = siisata_bio_complete; 940 1.1.2.2 mjf xfer->c_kill_xfer = siisata_bio_kill_xfer; 941 1.1.2.2 mjf ata_exec_xfer(chp, xfer); 942 1.1.2.2 mjf return (ata_bio->flags & ATA_ITSDONE) ? 943 1.1.2.2 mjf ATACMD_COMPLETE : ATACMD_QUEUED; 944 1.1.2.2 mjf } 945 1.1.2.2 mjf 946 1.1.2.2 mjf void 947 1.1.2.2 mjf siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 948 1.1.2.2 mjf { 949 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 950 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 951 1.1.2.2 mjf struct siisata_prb *prb; 952 1.1.2.2 mjf struct ata_bio *ata_bio = xfer->c_cmd; 953 1.1.2.2 mjf int slot = SIISATA_NON_NCQ_SLOT; 954 1.1.2.2 mjf int nblks, i; 955 1.1.2.2 mjf uint8_t *fis; 956 1.1.2.2 mjf 957 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 958 1.1.2.2 mjf ("%s: %s port %d, slot %d\n", 959 1.1.2.2 mjf SIISATANAME(sc), __func__, chp->ch_channel, slot), 960 1.1.2.2 mjf DEBUG_FUNCS); 961 1.1.2.2 mjf 962 1.1.2.2 mjf #ifdef DIAGNOSTIC 963 1.1.2.2 mjf if (__predict_false(schp->sch_active_slots & __BIT(slot))) { 964 1.1.2.2 mjf panic("%s %s trying to use already active slot %d", 965 1.1.2.2 mjf SIISATANAME(sc), __func__, slot); 966 1.1.2.2 mjf } 967 1.1.2.2 mjf #endif 968 1.1.2.2 mjf 969 1.1.2.2 mjf prb = schp->sch_prb[slot]; 970 1.1.2.2 mjf memset(prb, 0, sizeof(struct siisata_prb)); 971 1.1.2.2 mjf fis = prb->prb_fis; 972 1.1.2.2 mjf 973 1.1.2.2 mjf nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 974 1.1.2.2 mjf 975 1.1.2.2 mjf /* XXX probably needs to be some common FIS-related code */ 976 1.1.2.2 mjf fis[0] = 0x27; /* host to device */ 977 1.1.2.2 mjf fis[1] = 0x80; /* command FIS (also, PMP) */ 978 1.1.2.2 mjf if (ata_bio->flags & ATA_LBA48) { 979 1.1.2.2 mjf fis[2] = (ata_bio->flags & ATA_READ) ? 980 1.1.2.2 mjf WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 981 1.1.2.2 mjf } else { 982 1.1.2.2 mjf fis[2] = 983 1.1.2.2 mjf (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 984 1.1.2.2 mjf } 985 1.1.2.2 mjf fis[4] = ata_bio->blkno & 0xff; 986 1.1.2.2 mjf fis[5] = (ata_bio->blkno >> 8) & 0xff; 987 1.1.2.2 mjf fis[6] = (ata_bio->blkno >> 16) & 0xff; 988 1.1.2.2 mjf if (ata_bio->flags & ATA_LBA48) { 989 1.1.2.2 mjf fis[7] = WDSD_LBA; 990 1.1.2.2 mjf fis[8] = (ata_bio->blkno >> 24) & 0xff; 991 1.1.2.2 mjf fis[9] = (ata_bio->blkno >> 32) & 0xff; 992 1.1.2.2 mjf fis[10] = (ata_bio->blkno >> 40) & 0xff; 993 1.1.2.2 mjf } else { 994 1.1.2.2 mjf fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 995 1.1.2.2 mjf } 996 1.1.2.2 mjf fis[12] = nblks & 0xff; 997 1.1.2.2 mjf fis[13] = (ata_bio->flags & ATA_LBA48) ? 998 1.1.2.2 mjf ((nblks >> 8) & 0xff) : 0; 999 1.1.2.2 mjf fis[15] = WDCTL_4BIT; 1000 1.1.2.2 mjf 1001 1.1.2.2 mjf memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 1002 1.1.2.2 mjf if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1003 1.1.2.2 mjf (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1004 1.1.2.2 mjf ata_bio->error = ERR_DMA; 1005 1.1.2.2 mjf ata_bio->r_error = 0; 1006 1.1.2.2 mjf siisata_bio_complete(chp, xfer, slot); 1007 1.1.2.2 mjf return; 1008 1.1.2.2 mjf } 1009 1.1.2.2 mjf 1010 1.1.2.2 mjf if (xfer->c_flags & C_POLL) { 1011 1.1.2.2 mjf /* polled command, disable interrupts */ 1012 1.1.2.2 mjf GRWRITE(sc, GR_GC, 1013 1.1.2.2 mjf GRREAD(sc, GR_GC) & ~(GR_GC_PXIE(chp->ch_channel))); 1014 1.1.2.2 mjf } 1015 1.1.2.2 mjf 1016 1.1.2.2 mjf SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1017 1.1.2.2 mjf siisata_activate_prb(sc, chp->ch_channel, 1018 1.1.2.2 mjf slot, schp->sch_bus_prb[slot]); 1019 1.1.2.2 mjf 1020 1.1.2.2 mjf /* keep track of what's going on */ 1021 1.1.2.2 mjf schp->sch_active_slots |= __BIT(slot); 1022 1.1.2.2 mjf 1023 1.1.2.2 mjf if ((xfer->c_flags & C_POLL) == 0) { 1024 1.1.2.2 mjf chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1025 1.1.2.2 mjf callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1026 1.1.2.2 mjf siisata_timeout, chp); 1027 1.1.2.2 mjf goto out; 1028 1.1.2.2 mjf } 1029 1.1.2.2 mjf 1030 1.1.2.2 mjf for (i = 0; i < ATA_DELAY / 10; i++) { 1031 1.1.2.2 mjf if (ata_bio->flags & ATA_ITSDONE) 1032 1.1.2.2 mjf break; 1033 1.1.2.2 mjf siisata_intr_port(sc, schp); 1034 1.1.2.2 mjf if (ata_bio->flags & ATA_NOSLEEP) 1035 1.1.2.2 mjf DELAY(10000); 1036 1.1.2.2 mjf else 1037 1.1.2.2 mjf tsleep(&xfer, PRIBIO, "siipl", mstohz(10)); 1038 1.1.2.2 mjf } 1039 1.1.2.2 mjf 1040 1.1.2.2 mjf GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1041 1.1.2.2 mjf out: 1042 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 1043 1.1.2.2 mjf ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1044 1.1.2.2 mjf return; 1045 1.1.2.2 mjf } 1046 1.1.2.2 mjf 1047 1.1.2.2 mjf void 1048 1.1.2.2 mjf siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1049 1.1.2.2 mjf int reason) 1050 1.1.2.2 mjf { 1051 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1052 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 1053 1.1.2.2 mjf struct ata_bio *ata_bio = xfer->c_cmd; 1054 1.1.2.2 mjf int drive = xfer->c_drive; 1055 1.1.2.2 mjf int slot = SIISATA_NON_NCQ_SLOT; 1056 1.1.2.2 mjf 1057 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", SIISATANAME(sc), 1058 1.1.2.2 mjf __func__, chp->ch_channel), DEBUG_FUNCS); 1059 1.1.2.2 mjf 1060 1.1.2.2 mjf /* mark slot inactive */ 1061 1.1.2.2 mjf schp->sch_active_slots &= ~__BIT(slot); 1062 1.1.2.2 mjf /* we're done with the prb */ 1063 1.1.2.2 mjf SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1064 1.1.2.2 mjf 1065 1.1.2.2 mjf ata_free_xfer(chp, xfer); 1066 1.1.2.2 mjf ata_bio->flags |= ATA_ITSDONE; 1067 1.1.2.2 mjf switch (reason) { 1068 1.1.2.2 mjf case KILL_GONE: 1069 1.1.2.2 mjf ata_bio->error = ERR_NODEV; 1070 1.1.2.2 mjf break; 1071 1.1.2.2 mjf case KILL_RESET: 1072 1.1.2.2 mjf ata_bio->error = ERR_RESET; 1073 1.1.2.2 mjf break; 1074 1.1.2.2 mjf default: 1075 1.1.2.2 mjf panic("%s: port %d: unknown reason %d", 1076 1.1.2.2 mjf __func__, chp->ch_channel, reason); 1077 1.1.2.2 mjf } 1078 1.1.2.2 mjf ata_bio->r_error = WDCE_ABRT; 1079 1.1.2.2 mjf (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1080 1.1.2.2 mjf } 1081 1.1.2.2 mjf 1082 1.1.2.2 mjf int 1083 1.1.2.2 mjf siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1084 1.1.2.2 mjf { 1085 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1086 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 1087 1.1.2.2 mjf struct ata_bio *ata_bio = xfer->c_cmd; 1088 1.1.2.2 mjf int drive = xfer->c_drive; 1089 1.1.2.2 mjf uint32_t pss, pis; 1090 1.1.2.2 mjf uint8_t fis[4]; 1091 1.1.2.2 mjf uint32_t *prbfis = (void *)fis; 1092 1.1.2.2 mjf 1093 1.1.2.2 mjf pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 1094 1.1.2.2 mjf 1095 1.1.2.2 mjf if (pis & PR_PIS_CMDCMPL) { 1096 1.1.2.2 mjf /* get slot status, clearing completion interrupt */ 1097 1.1.2.2 mjf pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 1098 1.1.2.2 mjf /* is this expected? */ 1099 1.1.2.2 mjf if ((schp->sch_active_slots & __BIT(slot)) == 0) { 1100 1.1.2.2 mjf log(LOG_WARNING, "%s: unexpected command " 1101 1.1.2.2 mjf "completion on port %d slot %d\n", 1102 1.1.2.2 mjf SIISATANAME(sc), chp->ch_channel, slot); 1103 1.1.2.2 mjf return 0; 1104 1.1.2.2 mjf } else { 1105 1.1.2.2 mjf if (ata_bio->flags & ATA_READ) 1106 1.1.2.2 mjf ata_bio->bcount -= PRREAD(sc, 1107 1.1.2.2 mjf PRSX(chp->ch_channel, slot, PRSO_RTC)); 1108 1.1.2.2 mjf else 1109 1.1.2.2 mjf ata_bio->bcount = 0; 1110 1.1.2.2 mjf 1111 1.1.2.2 mjf /* XXX is reseting these right? */ 1112 1.1.2.2 mjf chp->ch_status = 0; 1113 1.1.2.2 mjf chp->ch_error = 0; 1114 1.1.2.2 mjf ata_bio->error = 0; 1115 1.1.2.2 mjf goto command_done; 1116 1.1.2.2 mjf } 1117 1.1.2.2 mjf } 1118 1.1.2.2 mjf 1119 1.1.2.2 mjf if (pis & PR_PIS_CMDERRR) { 1120 1.1.2.2 mjf uint32_t ec; 1121 1.1.2.2 mjf 1122 1.1.2.2 mjf /* emulate a CRC error by default */ 1123 1.1.2.2 mjf chp->ch_status = WDCS_ERR; 1124 1.1.2.2 mjf chp->ch_error = WDCE_CRC; 1125 1.1.2.2 mjf 1126 1.1.2.2 mjf ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 1127 1.1.2.2 mjf if (ec <= PR_PCE_DATAFISERROR) { 1128 1.1.2.2 mjf if (ec != PR_PCE_DATAFISERROR) { 1129 1.1.2.2 mjf /* read in specific information about error */ 1130 1.1.2.2 mjf *prbfis = bus_space_read_stream_4( 1131 1.1.2.2 mjf sc->sc_prt, sc->sc_prh, 1132 1.1.2.2 mjf PRSX(chp->ch_channel, slot, PRSO_FIS)); 1133 1.1.2.2 mjf chp->ch_status = fis[2]; 1134 1.1.2.2 mjf chp->ch_error = fis[3]; 1135 1.1.2.2 mjf } 1136 1.1.2.2 mjf siisata_reinit_port(sc, chp); 1137 1.1.2.2 mjf } else { 1138 1.1.2.2 mjf /* okay, we have a "Fatal Error" */ 1139 1.1.2.2 mjf siisata_device_reset(sc, chp); 1140 1.1.2.2 mjf } 1141 1.1.2.2 mjf goto command_done; 1142 1.1.2.2 mjf } 1143 1.1.2.2 mjf return 0; 1144 1.1.2.2 mjf 1145 1.1.2.2 mjf command_done: 1146 1.1.2.2 mjf schp->sch_active_slots &= ~__BIT(slot); 1147 1.1.2.2 mjf chp->ch_flags &= ~ATACH_IRQ_WAIT; 1148 1.1.2.2 mjf callout_stop(&chp->ch_callout); 1149 1.1.2.2 mjf 1150 1.1.2.2 mjf chp->ch_queue->active_xfer = NULL; 1151 1.1.2.2 mjf 1152 1.1.2.2 mjf bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1153 1.1.2.2 mjf schp->sch_datad[slot]->dm_mapsize, 1154 1.1.2.2 mjf (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1155 1.1.2.2 mjf BUS_DMASYNC_POSTWRITE); 1156 1.1.2.2 mjf bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1157 1.1.2.2 mjf 1158 1.1.2.2 mjf if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1159 1.1.2.2 mjf siisata_bio_kill_xfer(chp, xfer, KILL_GONE); 1160 1.1.2.2 mjf chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1161 1.1.2.2 mjf wakeup(&chp->ch_queue->active_xfer); 1162 1.1.2.2 mjf return 0; 1163 1.1.2.2 mjf } 1164 1.1.2.2 mjf ata_free_xfer(chp, xfer); 1165 1.1.2.2 mjf ata_bio->flags |= ATA_ITSDONE; 1166 1.1.2.2 mjf if (chp->ch_status & WDCS_DWF) { 1167 1.1.2.2 mjf ata_bio->error = ERR_DF; 1168 1.1.2.2 mjf } else if (chp->ch_status & WDCS_ERR) { 1169 1.1.2.2 mjf ata_bio->error = ERROR; 1170 1.1.2.2 mjf ata_bio->r_error = chp->ch_error; 1171 1.1.2.2 mjf } else if (chp->ch_status & WDCS_CORR) 1172 1.1.2.2 mjf ata_bio->flags |= ATA_CORR; 1173 1.1.2.2 mjf 1174 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld\n", SIISATANAME(sc), 1175 1.1.2.2 mjf __func__, ata_bio->bcount), DEBUG_XFERS); 1176 1.1.2.2 mjf 1177 1.1.2.2 mjf (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1178 1.1.2.2 mjf 1179 1.1.2.2 mjf atastart(chp); 1180 1.1.2.2 mjf return 0; 1181 1.1.2.2 mjf } 1182 1.1.2.2 mjf 1183 1.1.2.2 mjf void 1184 1.1.2.2 mjf siisata_timeout(void *v) 1185 1.1.2.2 mjf { 1186 1.1.2.2 mjf struct ata_channel *chp = (struct ata_channel *)v; 1187 1.1.2.2 mjf struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1188 1.1.2.2 mjf int slot = SIISATA_NON_NCQ_SLOT; 1189 1.1.2.2 mjf int s = splbio(); 1190 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1191 1.1.2.2 mjf if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1192 1.1.2.2 mjf xfer->c_flags |= C_TIMEOU; 1193 1.1.2.2 mjf xfer->c_intr(chp, xfer, slot); 1194 1.1.2.2 mjf } 1195 1.1.2.2 mjf splx(s); 1196 1.1.2.2 mjf } 1197 1.1.2.2 mjf 1198 1.1.2.2 mjf static int 1199 1.1.2.2 mjf siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1200 1.1.2.2 mjf size_t count, int op) 1201 1.1.2.2 mjf { 1202 1.1.2.2 mjf 1203 1.1.2.2 mjf int error, seg; 1204 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1205 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 1206 1.1.2.2 mjf 1207 1.1.2.2 mjf struct siisata_prb *prbp; 1208 1.1.2.2 mjf 1209 1.1.2.2 mjf prbp = schp->sch_prb[slot]; 1210 1.1.2.2 mjf 1211 1.1.2.2 mjf if (data == NULL) { 1212 1.1.2.2 mjf goto end; 1213 1.1.2.2 mjf } 1214 1.1.2.2 mjf 1215 1.1.2.2 mjf error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1216 1.1.2.2 mjf data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1217 1.1.2.2 mjf if (error) { 1218 1.1.2.2 mjf log(LOG_ERR, "%s port %d: " 1219 1.1.2.2 mjf "failed to load xfer in slot %d: error %d\n", 1220 1.1.2.2 mjf SIISATANAME(sc), chp->ch_channel, slot, error); 1221 1.1.2.2 mjf return error; 1222 1.1.2.2 mjf } 1223 1.1.2.2 mjf 1224 1.1.2.2 mjf bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1225 1.1.2.2 mjf schp->sch_datad[slot]->dm_mapsize, 1226 1.1.2.2 mjf (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1227 1.1.2.2 mjf 1228 1.1.2.2 mjf /* make sure it's clean */ 1229 1.1.2.2 mjf memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1230 1.1.2.2 mjf 1231 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1232 1.1.2.2 mjf schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1233 1.1.2.2 mjf DEBUG_FUNCS | DEBUG_DEBUG); 1234 1.1.2.2 mjf 1235 1.1.2.2 mjf for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1236 1.1.2.2 mjf prbp->prb_sge[seg].sge_da = 1237 1.1.2.2 mjf htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1238 1.1.2.2 mjf prbp->prb_sge[seg].sge_dc = 1239 1.1.2.2 mjf htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1240 1.1.2.2 mjf prbp->prb_sge[seg].sge_flags = htole32(0); 1241 1.1.2.2 mjf } 1242 1.1.2.2 mjf prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1243 1.1.2.2 mjf end: 1244 1.1.2.2 mjf return 0; 1245 1.1.2.2 mjf } 1246 1.1.2.2 mjf 1247 1.1.2.2 mjf static inline void 1248 1.1.2.2 mjf siisata_activate_prb(struct siisata_softc *sc, int p, int s, bus_addr_t v) 1249 1.1.2.2 mjf { 1250 1.1.2.2 mjf bus_size_t o = PRO_CARX(p, s); 1251 1.1.2.2 mjf PRWRITE(sc, o, v); 1252 1.1.2.2 mjf o += 4; 1253 1.1.2.2 mjf #if 0 1254 1.1.2.2 mjf if (sizeof(bus_addr_t) == 8) 1255 1.1.2.2 mjf PRWRITE(sc, o, (v >> 32)); 1256 1.1.2.2 mjf else 1257 1.1.2.2 mjf #endif 1258 1.1.2.2 mjf PRWRITE(sc, o, 0); 1259 1.1.2.2 mjf } 1260 1.1.2.2 mjf 1261 1.1.2.2 mjf static void 1262 1.1.2.2 mjf siisata_reinit_port(struct siisata_softc *sc, struct ata_channel *chp) 1263 1.1.2.2 mjf { 1264 1.1.2.2 mjf PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 1265 1.1.2.2 mjf PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) | PR_PC_PORT_INITIALIZE); 1266 1.1.2.2 mjf while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 1267 1.1.2.2 mjf DELAY(10); 1268 1.1.2.2 mjf } 1269 1.1.2.2 mjf 1270 1.1.2.2 mjf static void 1271 1.1.2.2 mjf siisata_device_reset(struct siisata_softc *sc, struct ata_channel *chp) 1272 1.1.2.2 mjf { 1273 1.1.2.2 mjf PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 1274 1.1.2.2 mjf PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) | PR_PC_DEVICE_RESET); 1275 1.1.2.2 mjf while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 1276 1.1.2.2 mjf DELAY(10); 1277 1.1.2.2 mjf } 1278 1.1.2.2 mjf 1279 1.1.2.2 mjf 1280 1.1.2.2 mjf #if NATAPIBUS > 0 1281 1.1.2.2 mjf void 1282 1.1.2.2 mjf siisata_atapibus_attach(struct atabus_softc *ata_sc) 1283 1.1.2.2 mjf { 1284 1.1.2.2 mjf struct ata_channel *chp = ata_sc->sc_chan; 1285 1.1.2.2 mjf struct atac_softc *atac = chp->ch_atac; 1286 1.1.2.2 mjf struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1287 1.1.2.2 mjf struct scsipi_channel *chan = &chp->ch_atapi_channel; 1288 1.1.2.2 mjf 1289 1.1.2.2 mjf /* 1290 1.1.2.2 mjf * Fill in the scsipi_adapter. 1291 1.1.2.2 mjf */ 1292 1.1.2.2 mjf adapt->adapt_dev = atac->atac_dev; 1293 1.1.2.2 mjf adapt->adapt_nchannels = atac->atac_nchannels; 1294 1.1.2.2 mjf adapt->adapt_request = siisata_atapi_scsipi_request; 1295 1.1.2.2 mjf adapt->adapt_minphys = siisata_atapi_minphys; 1296 1.1.2.2 mjf atac->atac_atapi_adapter.atapi_probe_device = 1297 1.1.2.2 mjf siisata_atapi_probe_device; 1298 1.1.2.2 mjf 1299 1.1.2.2 mjf /* 1300 1.1.2.2 mjf * Fill in the scsipi_channel. 1301 1.1.2.2 mjf */ 1302 1.1.2.2 mjf memset(chan, 0, sizeof(*chan)); 1303 1.1.2.2 mjf chan->chan_adapter = adapt; 1304 1.1.2.2 mjf chan->chan_bustype = &siisata_atapi_bustype; 1305 1.1.2.2 mjf chan->chan_channel = chp->ch_channel; 1306 1.1.2.2 mjf chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1307 1.1.2.2 mjf chan->chan_openings = 1; 1308 1.1.2.2 mjf chan->chan_max_periph = 1; 1309 1.1.2.2 mjf chan->chan_ntargets = 1; 1310 1.1.2.2 mjf chan->chan_nluns = 1; 1311 1.1.2.2 mjf 1312 1.1.2.2 mjf chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1313 1.1.2.2 mjf atapiprint); 1314 1.1.2.2 mjf } 1315 1.1.2.2 mjf 1316 1.1.2.2 mjf void 1317 1.1.2.2 mjf siisata_atapi_minphys(struct buf *bp) 1318 1.1.2.2 mjf { 1319 1.1.2.2 mjf if (bp->b_bcount > MAXPHYS) 1320 1.1.2.2 mjf bp->b_bcount = MAXPHYS; 1321 1.1.2.2 mjf minphys(bp); 1322 1.1.2.2 mjf } 1323 1.1.2.2 mjf 1324 1.1.2.2 mjf /* 1325 1.1.2.2 mjf * Kill off all pending xfers for a periph. 1326 1.1.2.2 mjf * 1327 1.1.2.2 mjf * Must be called at splbio(). 1328 1.1.2.2 mjf */ 1329 1.1.2.2 mjf void 1330 1.1.2.2 mjf siisata_atapi_kill_pending(struct scsipi_periph *periph) 1331 1.1.2.2 mjf { 1332 1.1.2.2 mjf struct atac_softc *atac = 1333 1.1.2.2 mjf device_private(periph->periph_channel->chan_adapter->adapt_dev); 1334 1.1.2.2 mjf struct ata_channel *chp = 1335 1.1.2.2 mjf atac->atac_channels[periph->periph_channel->chan_channel]; 1336 1.1.2.2 mjf 1337 1.1.2.2 mjf ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1338 1.1.2.2 mjf } 1339 1.1.2.2 mjf 1340 1.1.2.2 mjf void 1341 1.1.2.2 mjf siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1342 1.1.2.2 mjf int reason) 1343 1.1.2.2 mjf { 1344 1.1.2.2 mjf struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1345 1.1.2.2 mjf 1346 1.1.2.2 mjf /* remove this command from xfer queue */ 1347 1.1.2.2 mjf switch (reason) { 1348 1.1.2.2 mjf case KILL_GONE: 1349 1.1.2.2 mjf sc_xfer->error = XS_DRIVER_STUFFUP; 1350 1.1.2.2 mjf break; 1351 1.1.2.2 mjf case KILL_RESET: 1352 1.1.2.2 mjf sc_xfer->error = XS_RESET; 1353 1.1.2.2 mjf break; 1354 1.1.2.2 mjf default: 1355 1.1.2.2 mjf panic("%s: port %d: unknown reason %d", 1356 1.1.2.2 mjf __func__, chp->ch_channel, reason); 1357 1.1.2.2 mjf } 1358 1.1.2.2 mjf ata_free_xfer(chp, xfer); 1359 1.1.2.2 mjf scsipi_done(sc_xfer); 1360 1.1.2.2 mjf } 1361 1.1.2.2 mjf 1362 1.1.2.2 mjf void 1363 1.1.2.2 mjf siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1364 1.1.2.2 mjf { 1365 1.1.2.2 mjf struct scsipi_channel *chan = sc->sc_channel; 1366 1.1.2.2 mjf struct scsipi_periph *periph; 1367 1.1.2.2 mjf struct ataparams ids; 1368 1.1.2.2 mjf struct ataparams *id = &ids; 1369 1.1.2.2 mjf struct siisata_softc *siic = 1370 1.1.2.2 mjf device_private(chan->chan_adapter->adapt_dev); 1371 1.1.2.2 mjf struct atac_softc *atac = &siic->sc_atac; 1372 1.1.2.2 mjf struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1373 1.1.2.2 mjf struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1374 1.1.2.2 mjf struct scsipibus_attach_args sa; 1375 1.1.2.2 mjf char serial_number[21], model[41], firmware_revision[9]; 1376 1.1.2.2 mjf int s; 1377 1.1.2.2 mjf 1378 1.1.2.2 mjf /* skip if already attached */ 1379 1.1.2.2 mjf if (scsipi_lookup_periph(chan, target, 0) != NULL) 1380 1.1.2.2 mjf return; 1381 1.1.2.2 mjf 1382 1.1.2.2 mjf /* if no ATAPI device detected at attach time, skip */ 1383 1.1.2.2 mjf if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1384 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: drive %d " 1385 1.1.2.2 mjf "not present\n", __func__, target), DEBUG_PROBE); 1386 1.1.2.2 mjf return; 1387 1.1.2.2 mjf } 1388 1.1.2.2 mjf 1389 1.1.2.2 mjf /* Some ATAPI devices need a bit more time after software reset. */ 1390 1.1.2.2 mjf delay(5000); 1391 1.1.2.2 mjf if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1392 1.1.2.2 mjf #ifdef ATAPI_DEBUG_PROBE 1393 1.1.2.2 mjf log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1394 1.1.2.2 mjf device_xname(sc->sc_dev), target, 1395 1.1.2.2 mjf id->atap_config & ATAPI_CFG_CMD_MASK, 1396 1.1.2.2 mjf id->atap_config & ATAPI_CFG_DRQ_MASK); 1397 1.1.2.2 mjf #endif 1398 1.1.2.2 mjf periph = scsipi_alloc_periph(M_NOWAIT); 1399 1.1.2.2 mjf if (periph == NULL) { 1400 1.1.2.2 mjf aprint_error_dev(sc->sc_dev, 1401 1.1.2.2 mjf "%s: unable to allocate periph for " 1402 1.1.2.2 mjf "channel %d drive %d", __func__, 1403 1.1.2.2 mjf chp->ch_channel, target); 1404 1.1.2.2 mjf return; 1405 1.1.2.2 mjf } 1406 1.1.2.2 mjf periph->periph_dev = NULL; 1407 1.1.2.2 mjf periph->periph_channel = chan; 1408 1.1.2.2 mjf periph->periph_switch = &atapi_probe_periphsw; 1409 1.1.2.2 mjf periph->periph_target = target; 1410 1.1.2.2 mjf periph->periph_lun = 0; 1411 1.1.2.2 mjf periph->periph_quirks = PQUIRK_ONLYBIG; 1412 1.1.2.2 mjf 1413 1.1.2.2 mjf #ifdef SCSIPI_DEBUG 1414 1.1.2.2 mjf if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1415 1.1.2.2 mjf SCSIPI_DEBUG_TARGET == target) 1416 1.1.2.2 mjf periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1417 1.1.2.2 mjf #endif 1418 1.1.2.2 mjf periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1419 1.1.2.2 mjf if (id->atap_config & ATAPI_CFG_REMOV) 1420 1.1.2.2 mjf periph->periph_flags |= PERIPH_REMOVABLE; 1421 1.1.2.2 mjf if (periph->periph_type == T_SEQUENTIAL) { 1422 1.1.2.2 mjf s = splbio(); 1423 1.1.2.2 mjf drvp->drive_flags |= DRIVE_ATAPIST; 1424 1.1.2.2 mjf splx(s); 1425 1.1.2.2 mjf } 1426 1.1.2.2 mjf 1427 1.1.2.2 mjf sa.sa_periph = periph; 1428 1.1.2.2 mjf sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1429 1.1.2.2 mjf sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1430 1.1.2.2 mjf T_REMOV : T_FIXED; 1431 1.1.2.2 mjf scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1432 1.1.2.2 mjf scsipi_strvis((u_char *)serial_number, 20, 1433 1.1.2.2 mjf id->atap_serial, 20); 1434 1.1.2.2 mjf scsipi_strvis((u_char *)firmware_revision, 8, 1435 1.1.2.2 mjf id->atap_revision, 8); 1436 1.1.2.2 mjf sa.sa_inqbuf.vendor = model; 1437 1.1.2.2 mjf sa.sa_inqbuf.product = serial_number; 1438 1.1.2.2 mjf sa.sa_inqbuf.revision = firmware_revision; 1439 1.1.2.2 mjf 1440 1.1.2.2 mjf /* 1441 1.1.2.2 mjf * Determine the operating mode capabilities of the device. 1442 1.1.2.2 mjf */ 1443 1.1.2.2 mjf if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1444 1.1.2.2 mjf == ATAPI_CFG_CMD_16) { 1445 1.1.2.2 mjf periph->periph_cap |= PERIPH_CAP_CMD16; 1446 1.1.2.2 mjf 1447 1.1.2.2 mjf /* configure port for packet length */ 1448 1.1.2.2 mjf PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1449 1.1.2.2 mjf PRREAD(siic, PRX(chp->ch_channel, PRO_PCS)) | 1450 1.1.2.2 mjf PR_PC_PACKET_LENGTH); 1451 1.1.2.2 mjf } 1452 1.1.2.2 mjf /* XXX This is gross. */ 1453 1.1.2.2 mjf periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1454 1.1.2.2 mjf 1455 1.1.2.2 mjf drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1456 1.1.2.2 mjf 1457 1.1.2.2 mjf if (drvp->drv_softc) 1458 1.1.2.2 mjf ata_probe_caps(drvp); 1459 1.1.2.2 mjf else { 1460 1.1.2.2 mjf s = splbio(); 1461 1.1.2.2 mjf drvp->drive_flags &= ~DRIVE_ATAPI; 1462 1.1.2.2 mjf splx(s); 1463 1.1.2.2 mjf } 1464 1.1.2.2 mjf } else { 1465 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1466 1.1.2.2 mjf "failed for drive %s:%d:%d: error 0x%x\n", 1467 1.1.2.2 mjf __func__, SIISATANAME(siic), chp->ch_channel, target, 1468 1.1.2.2 mjf chp->ch_error), DEBUG_PROBE); 1469 1.1.2.2 mjf s = splbio(); 1470 1.1.2.2 mjf drvp->drive_flags &= ~DRIVE_ATAPI; 1471 1.1.2.2 mjf splx(s); 1472 1.1.2.2 mjf } 1473 1.1.2.2 mjf } 1474 1.1.2.2 mjf 1475 1.1.2.2 mjf void 1476 1.1.2.2 mjf siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1477 1.1.2.2 mjf scsipi_adapter_req_t req, void *arg) 1478 1.1.2.2 mjf { 1479 1.1.2.2 mjf struct scsipi_adapter *adapt = chan->chan_adapter; 1480 1.1.2.2 mjf struct scsipi_periph *periph; 1481 1.1.2.2 mjf struct scsipi_xfer *sc_xfer; 1482 1.1.2.2 mjf struct siisata_softc *sc = device_private(adapt->adapt_dev); 1483 1.1.2.2 mjf struct atac_softc *atac = &sc->sc_atac; 1484 1.1.2.2 mjf struct ata_xfer *xfer; 1485 1.1.2.2 mjf int channel = chan->chan_channel; 1486 1.1.2.2 mjf int drive, s; 1487 1.1.2.2 mjf 1488 1.1.2.2 mjf switch (req) { 1489 1.1.2.2 mjf case ADAPTER_REQ_RUN_XFER: 1490 1.1.2.2 mjf sc_xfer = arg; 1491 1.1.2.2 mjf periph = sc_xfer->xs_periph; 1492 1.1.2.2 mjf drive = periph->periph_target; 1493 1.1.2.2 mjf 1494 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1495 1.1.2.2 mjf device_xname(atac->atac_dev), channel, drive), 1496 1.1.2.2 mjf DEBUG_XFERS); 1497 1.1.2.2 mjf 1498 1.1.2.2 mjf if (!device_is_active(atac->atac_dev)) { 1499 1.1.2.2 mjf sc_xfer->error = XS_DRIVER_STUFFUP; 1500 1.1.2.2 mjf scsipi_done(sc_xfer); 1501 1.1.2.2 mjf return; 1502 1.1.2.2 mjf } 1503 1.1.2.2 mjf xfer = ata_get_xfer(ATAXF_NOSLEEP); 1504 1.1.2.2 mjf if (xfer == NULL) { 1505 1.1.2.2 mjf sc_xfer->error = XS_RESOURCE_SHORTAGE; 1506 1.1.2.2 mjf scsipi_done(sc_xfer); 1507 1.1.2.2 mjf return; 1508 1.1.2.2 mjf } 1509 1.1.2.2 mjf 1510 1.1.2.2 mjf if (sc_xfer->xs_control & XS_CTL_POLL) 1511 1.1.2.2 mjf xfer->c_flags |= C_POLL; 1512 1.1.2.2 mjf xfer->c_drive = drive; 1513 1.1.2.2 mjf xfer->c_flags |= C_ATAPI; 1514 1.1.2.2 mjf xfer->c_cmd = sc_xfer; 1515 1.1.2.2 mjf xfer->c_databuf = sc_xfer->data; 1516 1.1.2.2 mjf xfer->c_bcount = sc_xfer->datalen; 1517 1.1.2.2 mjf xfer->c_start = siisata_atapi_start; 1518 1.1.2.2 mjf xfer->c_intr = siisata_atapi_complete; 1519 1.1.2.2 mjf xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1520 1.1.2.2 mjf xfer->c_dscpoll = 0; 1521 1.1.2.2 mjf s = splbio(); 1522 1.1.2.2 mjf ata_exec_xfer(atac->atac_channels[channel], xfer); 1523 1.1.2.2 mjf #ifdef DIAGNOSTIC 1524 1.1.2.2 mjf if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1525 1.1.2.2 mjf (sc_xfer->xs_status & XS_STS_DONE) == 0) 1526 1.1.2.2 mjf panic("%s: polled command not done", __func__); 1527 1.1.2.2 mjf #endif 1528 1.1.2.2 mjf splx(s); 1529 1.1.2.2 mjf return; 1530 1.1.2.2 mjf 1531 1.1.2.2 mjf default: 1532 1.1.2.2 mjf /* Not supported, nothing to do. */ 1533 1.1.2.2 mjf ; 1534 1.1.2.2 mjf } 1535 1.1.2.2 mjf } 1536 1.1.2.2 mjf 1537 1.1.2.2 mjf void 1538 1.1.2.2 mjf siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1539 1.1.2.2 mjf { 1540 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1541 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 1542 1.1.2.2 mjf struct siisata_prb *prbp; 1543 1.1.2.2 mjf struct atac_softc *atac = chp->ch_atac; 1544 1.1.2.2 mjf 1545 1.1.2.2 mjf struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1546 1.1.2.2 mjf struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1547 1.1.2.2 mjf 1548 1.1.2.2 mjf int slot = SIISATA_NON_NCQ_SLOT; 1549 1.1.2.2 mjf int i; 1550 1.1.2.2 mjf uint8_t *fis; 1551 1.1.2.2 mjf 1552 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s:%d:%d, scsi flags 0x%x \n", __func__, 1553 1.1.2.2 mjf device_xname(atac->atac_dev), chp->ch_channel, drvp->drive, 1554 1.1.2.2 mjf sc_xfer->xs_control), DEBUG_XFERS); 1555 1.1.2.2 mjf 1556 1.1.2.2 mjf #ifdef DIAGNOSTIC 1557 1.1.2.2 mjf if (__predict_false(schp->sch_active_slots & __BIT(slot))) { 1558 1.1.2.2 mjf panic("%s %s trying to use already active slot %d", 1559 1.1.2.2 mjf SIISATANAME(sc), __func__, slot); 1560 1.1.2.2 mjf } 1561 1.1.2.2 mjf #endif 1562 1.1.2.2 mjf 1563 1.1.2.2 mjf prbp = schp->sch_prb[slot]; 1564 1.1.2.2 mjf memset(prbp, 0, sizeof(struct siisata_prb)); 1565 1.1.2.2 mjf fis = prbp->prb_fis; 1566 1.1.2.2 mjf 1567 1.1.2.2 mjf /* fill in direction for ATAPI command */ 1568 1.1.2.2 mjf if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1569 1.1.2.2 mjf prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1570 1.1.2.2 mjf if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1571 1.1.2.2 mjf prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1572 1.1.2.2 mjf 1573 1.1.2.2 mjf /* XXX probably needs to be some common FIS-related code */ 1574 1.1.2.2 mjf fis[0] = 0x27; /* host to device */ 1575 1.1.2.2 mjf fis[1] = 0x80; /* command FIS (and PMP) */ 1576 1.1.2.2 mjf fis[2] = ATAPI_PKT_CMD; 1577 1.1.2.2 mjf fis[3] = (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0; 1578 1.1.2.2 mjf fis[7] = WDSD_IBM; 1579 1.1.2.2 mjf fis[15] = WDCTL_4BIT; 1580 1.1.2.2 mjf 1581 1.1.2.2 mjf /* copy over ATAPI command */ 1582 1.1.2.2 mjf memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1583 1.1.2.2 mjf 1584 1.1.2.2 mjf if (siisata_dma_setup(chp, slot, 1585 1.1.2.2 mjf (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1586 1.1.2.2 mjf xfer->c_databuf : NULL, 1587 1.1.2.2 mjf xfer->c_bcount, 1588 1.1.2.2 mjf (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1589 1.1.2.2 mjf BUS_DMA_READ : BUS_DMA_WRITE) 1590 1.1.2.2 mjf ) 1591 1.1.2.2 mjf panic("%s", __func__); 1592 1.1.2.2 mjf 1593 1.1.2.2 mjf if (xfer->c_flags & C_POLL) { 1594 1.1.2.2 mjf /* polled command, disable interrupts */ 1595 1.1.2.2 mjf GRWRITE(sc, GR_GC, 1596 1.1.2.2 mjf GRREAD(sc, GR_GC) & ~(GR_GC_PXIE(chp->ch_channel))); 1597 1.1.2.2 mjf } 1598 1.1.2.2 mjf 1599 1.1.2.2 mjf SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1600 1.1.2.2 mjf siisata_activate_prb(sc, chp->ch_channel, slot, 1601 1.1.2.2 mjf schp->sch_bus_prb[slot]); 1602 1.1.2.2 mjf schp->sch_active_slots |= __BIT(slot); 1603 1.1.2.2 mjf 1604 1.1.2.2 mjf if ((xfer->c_flags & C_POLL) == 0) { 1605 1.1.2.2 mjf chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1606 1.1.2.2 mjf callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1607 1.1.2.2 mjf siisata_timeout, chp); 1608 1.1.2.2 mjf goto out; 1609 1.1.2.2 mjf } 1610 1.1.2.2 mjf /* 1611 1.1.2.2 mjf * polled command 1612 1.1.2.2 mjf */ 1613 1.1.2.2 mjf for (i = 0; i < ATA_DELAY / 10; i++) { 1614 1.1.2.2 mjf if (sc_xfer->xs_status & XS_STS_DONE) 1615 1.1.2.2 mjf break; 1616 1.1.2.2 mjf siisata_intr_port(sc, schp); 1617 1.1.2.2 mjf DELAY(10000); 1618 1.1.2.2 mjf } 1619 1.1.2.2 mjf if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1620 1.1.2.2 mjf sc_xfer->error = XS_TIMEOUT; 1621 1.1.2.2 mjf siisata_atapi_complete(chp, xfer, slot); 1622 1.1.2.2 mjf } 1623 1.1.2.2 mjf /* reenable interrupts */ 1624 1.1.2.2 mjf GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1625 1.1.2.2 mjf out: 1626 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 1627 1.1.2.2 mjf ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1628 1.1.2.2 mjf return; 1629 1.1.2.2 mjf } 1630 1.1.2.2 mjf 1631 1.1.2.2 mjf int 1632 1.1.2.2 mjf siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1633 1.1.2.2 mjf int slot) 1634 1.1.2.2 mjf { 1635 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1636 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 1637 1.1.2.2 mjf struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1638 1.1.2.2 mjf uint8_t fis[4]; 1639 1.1.2.2 mjf uint32_t *prbfis = (void *)fis; 1640 1.1.2.2 mjf uint32_t pss, pis; 1641 1.1.2.2 mjf 1642 1.1.2.2 mjf SIISATA_DEBUG_PRINT( 1643 1.1.2.2 mjf ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1644 1.1.2.2 mjf 1645 1.1.2.2 mjf if ((xfer->c_flags & C_TIMEOU) != 0) { 1646 1.1.2.2 mjf sc_xfer->error = XS_TIMEOUT; 1647 1.1.2.2 mjf siisata_atapi_reset(chp, xfer); 1648 1.1.2.2 mjf return 1; 1649 1.1.2.2 mjf } 1650 1.1.2.2 mjf 1651 1.1.2.2 mjf pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 1652 1.1.2.2 mjf 1653 1.1.2.2 mjf if (pis & PR_PIS_CMDCMPL) { 1654 1.1.2.2 mjf /* get slot status, clearing completion interrupt */ 1655 1.1.2.2 mjf pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 1656 1.1.2.2 mjf /* is this expected? */ 1657 1.1.2.2 mjf if ((schp->sch_active_slots & __BIT(slot)) == 0) { 1658 1.1.2.2 mjf log(LOG_WARNING, "%s: unexpected command " 1659 1.1.2.2 mjf "completion on port %d slot %d\n", 1660 1.1.2.2 mjf SIISATANAME(sc), chp->ch_channel, slot); 1661 1.1.2.2 mjf return 0; 1662 1.1.2.2 mjf } 1663 1.1.2.2 mjf } 1664 1.1.2.2 mjf 1665 1.1.2.2 mjf if (pis & PR_PIS_CMDERRR) { 1666 1.1.2.2 mjf uint32_t ec; 1667 1.1.2.2 mjf 1668 1.1.2.2 mjf ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 1669 1.1.2.2 mjf if (ec <= PR_PCE_DATAFISERROR) { 1670 1.1.2.2 mjf if (ec != PR_PCE_DATAFISERROR) { 1671 1.1.2.2 mjf /* read in specific information about error */ 1672 1.1.2.2 mjf *prbfis = bus_space_read_stream_4( 1673 1.1.2.2 mjf sc->sc_prt, sc->sc_prh, 1674 1.1.2.2 mjf PRSX(chp->ch_channel, slot, PRSO_FIS)); 1675 1.1.2.2 mjf if (ec == PR_PCE_DEVICEERROR) { 1676 1.1.2.2 mjf /* error code 1 implies * 1677 1.1.2.2 mjf * WDCS_ERR in fis[2] */ 1678 1.1.2.2 mjf sc_xfer->error = XS_SHORTSENSE; 1679 1.1.2.2 mjf sc_xfer->sense.atapi_sense = fis[3]; 1680 1.1.2.2 mjf } 1681 1.1.2.2 mjf siisata_reinit_port(sc, chp); 1682 1.1.2.2 mjf } else 1683 1.1.2.2 mjf siisata_reinit_port(sc, chp); 1684 1.1.2.2 mjf } else { 1685 1.1.2.2 mjf /* okay, we have a "Fatal Error" */ 1686 1.1.2.2 mjf siisata_device_reset(sc, chp); 1687 1.1.2.2 mjf } 1688 1.1.2.2 mjf } 1689 1.1.2.2 mjf 1690 1.1.2.2 mjf chp->ch_flags &= ~ATACH_IRQ_WAIT; 1691 1.1.2.2 mjf siisata_atapi_done(chp, xfer, slot); 1692 1.1.2.2 mjf return 1; 1693 1.1.2.2 mjf } 1694 1.1.2.2 mjf 1695 1.1.2.2 mjf void 1696 1.1.2.2 mjf siisata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1697 1.1.2.2 mjf { 1698 1.1.2.2 mjf struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1699 1.1.2.2 mjf struct siisata_channel *schp = (struct siisata_channel *)chp; 1700 1.1.2.2 mjf struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1701 1.1.2.2 mjf struct atac_softc *atac = chp->ch_atac; 1702 1.1.2.2 mjf 1703 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: %s:%d:%d: flags 0x%x\n", __func__, 1704 1.1.2.2 mjf device_xname(atac->atac_dev), 1705 1.1.2.2 mjf chp->ch_channel, xfer->c_drive, 1706 1.1.2.2 mjf (unsigned int)xfer->c_flags), DEBUG_XFERS); 1707 1.1.2.2 mjf 1708 1.1.2.2 mjf /* this comamnd is not active any more */ 1709 1.1.2.2 mjf schp->sch_active_slots &= ~__BIT(slot); 1710 1.1.2.2 mjf 1711 1.1.2.2 mjf if (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 1712 1.1.2.2 mjf bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1713 1.1.2.2 mjf schp->sch_datad[slot]->dm_mapsize, 1714 1.1.2.2 mjf (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1715 1.1.2.2 mjf BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1716 1.1.2.2 mjf bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1717 1.1.2.2 mjf } 1718 1.1.2.2 mjf 1719 1.1.2.2 mjf xfer->c_bcount -= sc_xfer->datalen; 1720 1.1.2.2 mjf sc_xfer->resid = xfer->c_bcount; 1721 1.1.2.2 mjf 1722 1.1.2.2 mjf if (xfer->c_bcount != 0) { 1723 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: bcount value is " 1724 1.1.2.2 mjf "%d after io\n", __func__, xfer->c_bcount), DEBUG_XFERS); 1725 1.1.2.2 mjf } 1726 1.1.2.2 mjf #ifdef DIAGNOSTIC 1727 1.1.2.2 mjf if (xfer->c_bcount < 0) { 1728 1.1.2.2 mjf log(LOG_WARNING, "%s(): bcount value " 1729 1.1.2.2 mjf "is %d after io\n", __func__, xfer->c_bcount); 1730 1.1.2.2 mjf } 1731 1.1.2.2 mjf #endif 1732 1.1.2.2 mjf 1733 1.1.2.2 mjf 1734 1.1.2.2 mjf if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1735 1.1.2.2 mjf siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); 1736 1.1.2.2 mjf chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1737 1.1.2.2 mjf wakeup(&chp->ch_queue->active_xfer); 1738 1.1.2.2 mjf return; 1739 1.1.2.2 mjf } 1740 1.1.2.2 mjf 1741 1.1.2.2 mjf /* vvv is this in the right order? ^^^ */ 1742 1.1.2.2 mjf 1743 1.1.2.2 mjf callout_stop(&chp->ch_callout); 1744 1.1.2.2 mjf chp->ch_queue->active_xfer = NULL; 1745 1.1.2.2 mjf ata_free_xfer(chp, xfer); 1746 1.1.2.2 mjf 1747 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("%s: scsipi_done\n", __func__), DEBUG_XFERS); 1748 1.1.2.2 mjf scsipi_done(sc_xfer); 1749 1.1.2.2 mjf SIISATA_DEBUG_PRINT(("atastart from %s, flags 0x%x\n", __func__, 1750 1.1.2.2 mjf chp->ch_flags), DEBUG_XFERS); 1751 1.1.2.2 mjf atastart(chp); 1752 1.1.2.2 mjf return; 1753 1.1.2.2 mjf } 1754 1.1.2.2 mjf 1755 1.1.2.2 mjf void 1756 1.1.2.2 mjf siisata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 1757 1.1.2.2 mjf { 1758 1.1.2.2 mjf struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1759 1.1.2.2 mjf drvp->state = 0; 1760 1.1.2.2 mjf chp->ch_flags &= ~ATACH_IRQ_WAIT; 1761 1.1.2.2 mjf siisata_atapi_done(chp, xfer, SIISATA_NON_NCQ_SLOT); 1762 1.1.2.2 mjf return; 1763 1.1.2.2 mjf } 1764 1.1.2.2 mjf #endif /* NATAPIBUS */ 1765
Indexes created Tue Oct 21 15:09:54 GMT 2025