siisata.c revision 1.1
1 /* $NetBSD: siisata.c,v 1.1 2008/05/23 21:11:40 jnemeth Exp $ */ 2 /* Id: siisata.c,v 1.28 2008/05/21 15:51:36 jakllsch Exp */ 3 4 /* from ahcisata_core.c */ 5 6 /* 7 * Copyright (c) 2006 Manuel Bouyer. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Manuel Bouyer. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 /* from atapi_wdc.c */ 37 38 /* 39 * Copyright (c) 1998, 2001 Manuel Bouyer. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by Manuel Bouyer. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /*- 68 * Copyright (c) 2007, 2008 Jonathan A. Kollasch. 69 * All rights reserved. 70 * 71 * Redistribution and use in source and binary forms, with or without 72 * modification, are permitted provided that the following conditions 73 * are met: 74 * 1. Redistributions of source code must retain the above copyright 75 * notice, this list of conditions and the following disclaimer. 76 * 2. Redistributions in binary form must reproduce the above copyright 77 * notice, this list of conditions and the following disclaimer in the 78 * documentation and/or other materials provided with the distribution. 79 * 80 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 81 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 82 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 83 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 84 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 85 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 86 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 87 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 88 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 89 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 90 * 91 */ 92 93 #include <sys/types.h> 94 #include <sys/malloc.h> 95 #include <sys/param.h> 96 #include <sys/kernel.h> 97 #include <sys/systm.h> 98 #include <sys/syslog.h> 99 #include <sys/disklabel.h> 100 #include <sys/buf.h> 101 102 #include <uvm/uvm_extern.h> 103 104 #include <dev/ic/wdcreg.h> 105 #include <dev/ata/atareg.h> 106 #include <dev/ata/satavar.h> 107 #include <dev/ata/satareg.h> 108 #include <dev/ic/siisatavar.h> 109 110 #include "atapibus.h" 111 112 #ifdef SIISATA_DEBUG 113 #if 0 114 int siisata_debug_mask = 0xffff; 115 #else 116 int siisata_debug_mask = 0; 117 #endif 118 #endif 119 120 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 121 122 static void siisata_attach_port(struct siisata_softc *, int); 123 static void siisata_intr_port(struct siisata_softc *, 124 struct siisata_channel *); 125 126 void siisata_probe_drive(struct ata_channel *); 127 void siisata_setup_channel(struct ata_channel *); 128 129 int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); 130 void siisata_reset_drive(struct ata_drive_datas *, int); 131 void siisata_reset_channel(struct ata_channel *, int); 132 int siisata_ata_addref(struct ata_drive_datas *); 133 void siisata_ata_delref(struct ata_drive_datas *); 134 void siisata_killpending(struct ata_drive_datas *); 135 136 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 137 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 138 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 139 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 140 141 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 142 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 143 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 144 int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); 145 146 void siisata_timeout(void *); 147 148 static void siisata_reinit_port(struct siisata_softc *, struct ata_channel *); 149 static void siisata_device_reset(struct siisata_softc *, struct ata_channel *); 150 static inline void siisata_activate_prb(struct siisata_softc *, 151 int, int, bus_addr_t); 152 static int siisata_dma_setup(struct ata_channel *chp, int slot, 153 void *data, size_t, int); 154 155 #if NATAPIBUS > 0 156 void siisata_atapibus_attach(struct atabus_softc *); 157 void siisata_atapi_probe_device(struct atapibus_softc *, int); 158 void siisata_atapi_minphys(struct buf *); 159 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 160 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int slot); 161 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 162 void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 163 void siisata_atapi_reset(struct ata_channel *, struct ata_xfer *); 164 void siisata_atapi_scsipi_request(struct scsipi_channel *, 165 scsipi_adapter_req_t, void *); 166 void siisata_atapi_kill_pending(struct scsipi_periph *); 167 #endif /* NATAPIBUS */ 168 169 const struct ata_bustype siisata_ata_bustype = { 170 SCSIPI_BUSTYPE_ATA, 171 siisata_ata_bio, 172 siisata_reset_drive, 173 siisata_reset_channel, 174 siisata_exec_command, 175 ata_get_params, 176 siisata_ata_addref, 177 siisata_ata_delref, 178 siisata_killpending 179 }; 180 181 #if NATAPIBUS > 0 182 static const struct scsipi_bustype siisata_atapi_bustype = { 183 SCSIPI_BUSTYPE_ATAPI, 184 atapi_scsipi_cmd, 185 atapi_interpret_sense, 186 atapi_print_addr, 187 siisata_atapi_kill_pending 188 }; 189 #endif /* NATAPIBUS */ 190 191 192 void 193 siisata_attach(struct siisata_softc *sc) 194 { 195 int i; 196 197 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 198 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 199 200 /* come out of reset state */ 201 GRWRITE(sc, GR_GC, 0); 202 203 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 204 sc->sc_atac.atac_pio_cap = 4; 205 sc->sc_atac.atac_dma_cap = 2; 206 sc->sc_atac.atac_udma_cap = 6; 207 sc->sc_atac.atac_channels = sc->sc_chanarray; 208 sc->sc_atac.atac_probe = siisata_probe_drive; 209 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 210 sc->sc_atac.atac_set_modes = siisata_setup_channel; 211 #if NATAPIBUS > 0 212 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 213 #endif 214 215 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 216 siisata_attach_port(sc, i); 217 } 218 219 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 220 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 221 DEBUG_FUNCS); 222 return; 223 } 224 225 static void 226 siisata_init_port(struct siisata_softc *sc, int port) 227 { 228 struct siisata_channel *schp; 229 struct ata_channel *chp; 230 231 schp = &sc->sc_channels[port]; 232 chp = (struct ata_channel *)schp; 233 234 /* come out of reset, 64-bit activation */ 235 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 236 PR_PC_32BA | PR_PC_PORT_RESET); 237 /* initialize port */ 238 siisata_reinit_port(sc, chp); 239 /* clear any interrupts */ 240 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 241 /* enable CmdErrr+CmdCmpl interrupting */ 242 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 243 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 244 /* enable port interrupt */ 245 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 246 } 247 248 static void 249 siisata_attach_port(struct siisata_softc *sc, int port) 250 { 251 int j; 252 bus_dma_segment_t seg; 253 int dmasize; 254 int error; 255 int rseg; 256 void *prbp; 257 struct siisata_channel *schp; 258 struct ata_channel *chp; 259 260 schp = &sc->sc_channels[port]; 261 chp = (struct ata_channel *)schp; 262 sc->sc_chanarray[port] = chp; 263 chp->ch_channel = port; 264 chp->ch_atac = &sc->sc_atac; 265 chp->ch_queue = malloc(sizeof(struct ata_queue), 266 M_DEVBUF, M_NOWAIT); 267 if (chp->ch_queue == NULL) { 268 aprint_error_dev(sc->sc_atac.atac_dev, 269 "port %d: can't allocate memory " 270 "for command queue", chp->ch_channel); 271 goto error_out; 272 } 273 274 275 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 276 277 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 278 __func__, dmasize), DEBUG_FUNCS); 279 280 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 281 &seg, 1, &rseg, BUS_DMA_NOWAIT); 282 if (error) { 283 aprint_error_dev(sc->sc_atac.atac_dev, 284 "unable to allocate PRB table memory, " 285 "error=%d\n", error); 286 goto error_out; 287 } 288 289 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 290 &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 291 if (error) { 292 aprint_error_dev(sc->sc_atac.atac_dev, 293 "unable to map PRB table memory, " 294 "error=%d\n", error); 295 goto error_out; 296 } 297 298 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 299 BUS_DMA_NOWAIT, &schp->sch_prbd); 300 if (error) { 301 aprint_error_dev(sc->sc_atac.atac_dev, 302 "unable to create PRB table map, " 303 "error=%d\n", error); 304 goto error_out; 305 } 306 307 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 308 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 309 if (error) { 310 aprint_error_dev(sc->sc_atac.atac_dev, 311 "unable to load PRB table map, " 312 "error=%d\n", error); 313 goto error_out; 314 } 315 316 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 317 schp->sch_prb[j] = (struct siisata_prb *) 318 ((char *)prbp + SIISATA_CMD_SIZE * j); 319 schp->sch_bus_prb[j] = 320 schp->sch_prbd->dm_segs[0].ds_addr + 321 SIISATA_CMD_SIZE * j; 322 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 323 SIISATA_NSGE, MAXPHYS, 0, 324 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 325 &schp->sch_datad[j]); 326 if (error) { 327 aprint_error_dev(sc->sc_atac.atac_dev, 328 "couldn't create xfer DMA map, error=%d\n", 329 error); 330 goto error_out; 331 } 332 } 333 334 chp->ch_ndrive = 1; 335 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 336 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 337 aprint_error_dev(sc->sc_atac.atac_dev, 338 "couldn't map port %d SStatus regs\n", 339 chp->ch_channel); 340 goto error_out; 341 } 342 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 343 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 344 aprint_error_dev(sc->sc_atac.atac_dev, 345 "couldn't map port %d SControl regs\n", 346 chp->ch_channel); 347 goto error_out; 348 } 349 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 350 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 351 aprint_error_dev(sc->sc_atac.atac_dev, 352 "couldn't map port %d SError regs\n", 353 chp->ch_channel); 354 goto error_out; 355 } 356 357 siisata_init_port(sc, port); 358 359 ata_channel_attach(chp); 360 error_out: 361 return; 362 } 363 364 void 365 siisata_resume(struct siisata_softc *sc) 366 { 367 int i; 368 369 /* come out of reset state */ 370 GRWRITE(sc, GR_GC, 0); 371 372 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 373 siisata_init_port(sc, i); 374 } 375 376 } 377 378 int 379 siisata_intr(void *v) 380 { 381 struct siisata_softc *sc = v; 382 uint32_t is; 383 int i, r = 0; 384 while ((is = GRREAD(sc, GR_GIS))) { 385 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 386 SIISATANAME(sc), __func__, is), DEBUG_INTR); 387 r = 1; 388 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 389 if (is & GR_GIS_PXIS(i)) 390 siisata_intr_port(sc, &sc->sc_channels[i]); 391 } 392 return r; 393 } 394 395 static void 396 siisata_intr_port(struct siisata_softc *sc, struct siisata_channel *schp) 397 { 398 struct ata_channel *chp = &schp->ata_channel; 399 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 400 int slot = SIISATA_NON_NCQ_SLOT; 401 402 SIISATA_DEBUG_PRINT(("%s: %s port %d\n", 403 SIISATANAME(sc), __func__, chp->ch_channel), DEBUG_INTR); 404 405 if ((xfer != NULL) && (xfer->c_intr != NULL)) 406 xfer->c_intr(chp, xfer, slot); 407 #ifdef DIAGNOSTIC 408 else 409 log(LOG_WARNING, "%s: unable to handle interrupt\n", __func__); 410 #endif 411 412 /* clear some (ok, all) ints */ 413 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 414 415 return; 416 } 417 418 void 419 siisata_reset_drive(struct ata_drive_datas *drvp, int flags) 420 { 421 struct ata_channel *chp = drvp->chnl_softc; 422 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 423 struct siisata_channel *schp = (struct siisata_channel *)chp; 424 struct siisata_prb *prb; 425 int slot = SIISATA_NON_NCQ_SLOT; 426 427 /* wait for ready */ 428 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 429 DELAY(10); 430 431 prb = schp->sch_prb[slot]; 432 memset(prb, 0, sizeof(struct siisata_prb)); 433 prb->prb_control = 434 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 435 436 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 437 siisata_activate_prb(sc, chp->ch_channel, 438 slot, schp->sch_bus_prb[slot]); 439 440 /* wait for completion */ 441 while (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & PR_PXSS(slot)) 442 DELAY(10); 443 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 444 445 log(LOG_DEBUG, "%s: ch_status %x ch_error %x\n", 446 __func__, chp->ch_status, chp->ch_error); 447 448 #if 1 449 /* attempt to downgrade signaling in event of CRC error */ 450 /* XXX should be part of the MI (S)ATA subsystem */ 451 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 452 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 453 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 454 DELAY(10); 455 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 456 SControl_IPM_NONE | SControl_SPD_G1); 457 DELAY(10); 458 for (;;) { 459 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 460 & SStatus_DET_mask) == SStatus_DET_DEV) 461 break; 462 DELAY(10); 463 } 464 } 465 #endif 466 467 #if 1 468 chp->ch_status = 0; 469 chp->ch_error = 0; 470 #endif 471 return; 472 } 473 474 void 475 siisata_reset_channel(struct ata_channel *chp, int flags) 476 { 477 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 478 struct siisata_channel *schp = (struct siisata_channel *)chp; 479 480 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 481 DEBUG_FUNCS); 482 483 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 484 schp->sch_sstatus) != SStatus_DET_DEV) { 485 log(LOG_CRIT, "%s port %d: reset failed\n", 486 SIISATANAME(sc), chp->ch_channel); 487 /* XXX and then ? */ 488 } 489 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 490 DELAY(10); 491 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 492 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 493 if (chp->ch_queue->active_xfer) { 494 chp->ch_queue->active_xfer->c_kill_xfer(chp, 495 chp->ch_queue->active_xfer, KILL_RESET); 496 } 497 498 return; 499 } 500 501 int 502 siisata_ata_addref(struct ata_drive_datas *drvp) 503 { 504 return 0; 505 } 506 507 void 508 siisata_ata_delref(struct ata_drive_datas *drvp) 509 { 510 return; 511 } 512 513 void 514 siisata_killpending(struct ata_drive_datas *drvp) 515 { 516 return; 517 } 518 519 void 520 siisata_probe_drive(struct ata_channel *chp) 521 { 522 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 523 struct siisata_channel *schp = (struct siisata_channel *)chp; 524 int i; 525 int s; 526 uint32_t sig; 527 int slot = SIISATA_NON_NCQ_SLOT; 528 struct siisata_prb *prb; 529 530 DELAY(chp->ch_channel * 2048 + 1023); /* XXX */ 531 532 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 533 __func__, chp->ch_channel), DEBUG_FUNCS); 534 535 /* XXX This should be done by other code. */ 536 for (i = 0; i < chp->ch_ndrive; i++) { 537 chp->ch_drive[i].chnl_softc = chp; 538 chp->ch_drive[i].drive = i; 539 } 540 541 switch (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 542 schp->sch_sstatus)) { 543 case SStatus_DET_DEV: 544 /* wait for ready */ 545 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) 546 & PR_PS_PORT_READY)) 547 DELAY(10); 548 549 prb = schp->sch_prb[slot]; 550 memset(prb, 0, sizeof(struct siisata_prb)); 551 prb->prb_control = 552 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 553 554 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 555 siisata_activate_prb(sc, chp->ch_channel, 556 slot, schp->sch_bus_prb[slot]); 557 558 /* wait for completion */ 559 while (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) 560 & PR_PXSS(slot)) 561 DELAY(10); 562 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 563 564 /* read the signature out of the FIS */ 565 sig = 0; 566 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 567 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 568 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 569 PRSO_FIS+0xc)) & 0xff; 570 571 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 572 __func__, sig), DEBUG_PROBE); 573 574 /* some ATAPI devices have bogus lower two bytes, sigh */ 575 if ((sig & 0xffff0000) == 0xeb140000) { 576 sig &= 0xffff0000; 577 sig |= 0x00000101; 578 } 579 580 s = splbio(); 581 switch (sig) { 582 case 0xeb140101: 583 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 584 break; 585 case 0x00000101: 586 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 587 break; 588 default: 589 aprint_error_dev(sc->sc_atac.atac_dev, 590 "%s: unknown device signature 0x%08x\n", 591 __func__, sig); 592 } 593 splx(s); 594 break; 595 default: 596 break; 597 } 598 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 599 __func__, chp->ch_channel), DEBUG_PROBE); 600 return; 601 } 602 603 void 604 siisata_setup_channel(struct ata_channel *chp) 605 { 606 return; 607 } 608 609 int 610 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 611 { 612 struct ata_channel *chp = drvp->chnl_softc; 613 struct ata_xfer *xfer; 614 int ret; 615 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 616 int s; 617 618 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 619 SIISATANAME(sc), __func__), DEBUG_FUNCS); 620 621 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? 622 ATAXF_CANSLEEP : ATAXF_NOSLEEP); 623 if (xfer == NULL) 624 return ATACMD_TRY_AGAIN; 625 if (ata_c->flags & AT_POLL) 626 xfer->c_flags |= C_POLL; 627 if (ata_c->flags & AT_WAIT) 628 xfer->c_flags |= C_WAIT; 629 xfer->c_drive = drvp->drive; 630 xfer->c_databuf = ata_c->data; 631 xfer->c_bcount = ata_c->bcount; 632 xfer->c_cmd = ata_c; 633 xfer->c_start = siisata_cmd_start; 634 xfer->c_intr = siisata_cmd_complete; 635 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 636 s = splbio(); 637 ata_exec_xfer(chp, xfer); 638 #ifdef DIAGNOSTIC 639 if ((ata_c->flags & AT_POLL) != 0 && 640 (ata_c->flags & AT_DONE) == 0) 641 panic("%s: polled command not done", __func__); 642 #endif 643 if (ata_c->flags & AT_DONE) { 644 ret = ATACMD_COMPLETE; 645 } else { 646 if (ata_c->flags & AT_WAIT) { 647 while ((ata_c->flags & AT_DONE) == 0) { 648 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 649 SIISATANAME(sc), __func__), DEBUG_FUNCS); 650 tsleep(ata_c, PRIBIO, "siicmd", 0); 651 } 652 ret = ATACMD_COMPLETE; 653 } else { 654 ret = ATACMD_QUEUED; 655 } 656 } 657 splx(s); 658 SIISATA_DEBUG_PRINT( 659 ("%s: %s ends\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 660 return ret; 661 } 662 663 void 664 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 665 { 666 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 667 struct siisata_channel *schp = (struct siisata_channel *)chp; 668 struct ata_command *ata_c = xfer->c_cmd; 669 int slot = SIISATA_NON_NCQ_SLOT; 670 struct siisata_prb *prb; 671 uint8_t *fis; 672 int i; 673 674 SIISATA_DEBUG_PRINT( 675 ("%s: %s port %d, slot %d\n", 676 SIISATANAME(sc), __func__, chp->ch_channel, slot), 677 DEBUG_FUNCS); 678 679 #ifdef DIAGNOSTIC 680 if (__predict_false(schp->sch_active_slots & __BIT(slot))) { 681 panic("%s %s trying to use already active slot %d", 682 SIISATANAME(sc), __func__, slot); 683 } 684 #endif 685 686 prb = schp->sch_prb[slot]; 687 memset(prb, 0, sizeof(struct siisata_prb)); 688 fis = prb->prb_fis; 689 690 /* XXX probably needs to be some common FIS-related code */ 691 fis[0] = 0x27; /* host to device */ 692 fis[1] = 0x80; /* command FIS (also, PMP) */ 693 fis[2] = ata_c->r_command; 694 fis[3] = ata_c->r_features; 695 fis[4] = ata_c->r_sector; 696 fis[5] = ata_c->r_cyl & 0xff; 697 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 698 fis[7] = ata_c->r_head & 0x0f; 699 fis[12] = ata_c->r_count; 700 fis[15] = WDCTL_4BIT; 701 702 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 703 704 if (siisata_dma_setup(chp, slot, 705 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 706 ata_c->bcount, 707 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 708 ata_c->flags |= AT_DF; 709 siisata_cmd_complete(chp, xfer, slot); 710 return; 711 } 712 713 if (xfer->c_flags & C_POLL) { 714 /* polled command, disable interrupts */ 715 GRWRITE(sc, GR_GC, 716 GRREAD(sc, GR_GC) & ~(GR_GC_PXIE(chp->ch_channel))); 717 } 718 719 /* go for it */ 720 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 721 siisata_activate_prb(sc, chp->ch_channel, 722 slot, schp->sch_bus_prb[slot]); 723 724 /* keep track of what's going on */ 725 schp->sch_active_slots |= __BIT(slot); 726 727 if ((ata_c->flags & AT_POLL) == 0) { 728 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 729 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 730 siisata_timeout, chp); 731 goto out; 732 } 733 734 for (i = 0; i < ata_c->timeout / 10; i++) { 735 if (ata_c->flags & AT_DONE) 736 break; 737 siisata_intr_port(sc, schp); 738 if (ata_c->flags & AT_WAIT) 739 tsleep(&xfer, PRIBIO, "siipl", mstohz(10)); 740 else 741 DELAY(10000); 742 } 743 744 if ((ata_c->flags & AT_DONE) == 0) { 745 ata_c->flags |= AT_TIMEOU; 746 siisata_cmd_complete(chp, xfer, slot); 747 } 748 749 /* reenable interrupts */ 750 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 751 out: 752 SIISATA_DEBUG_PRINT( 753 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 754 return; 755 } 756 757 void 758 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 759 int reason) 760 { 761 int slot = SIISATA_NON_NCQ_SLOT; 762 763 struct ata_command *ata_c = xfer->c_cmd; 764 switch (reason) { 765 case KILL_GONE: 766 ata_c->flags |= AT_GONE; 767 break; 768 case KILL_RESET: 769 ata_c->flags |= AT_RESET; 770 break; 771 default: 772 panic("%s: port %d: unknown reason %d", 773 __func__, chp->ch_channel, reason); 774 } 775 siisata_cmd_done(chp, xfer, slot); 776 } 777 778 int 779 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 780 { 781 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 782 struct siisata_channel *schp = (struct siisata_channel *)chp; 783 struct ata_command *ata_c = xfer->c_cmd; 784 uint32_t pss, pis; 785 uint8_t fis[4]; 786 uint32_t *prbfis = (void *)fis; 787 788 SIISATA_DEBUG_PRINT( 789 ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 790 791 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 792 793 if ((xfer->c_flags & C_TIMEOU) != 0) 794 goto command_done; 795 796 if (pis & PR_PIS_CMDCMPL) { 797 /* get slot status, clearing completion interrupt */ 798 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 799 /* is this expected? */ 800 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 801 log(LOG_WARNING, "%s: unexpected command " 802 "completion on port %d slot %d\n", 803 SIISATANAME(sc), chp->ch_channel, slot); 804 return 0; 805 } else 806 goto command_done; 807 } 808 809 if (pis & PR_PIS_CMDERRR) { 810 uint32_t ec; 811 812 /* emulate a CRC error by default */ 813 chp->ch_status = WDCS_ERR; 814 chp->ch_error = WDCE_CRC; 815 816 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 817 if (ec <= PR_PCE_DATAFISERROR) { 818 if (ec != PR_PCE_DATAFISERROR) { 819 /* read in specific information about error */ 820 *prbfis = bus_space_read_stream_4( 821 sc->sc_prt, sc->sc_prh, 822 PRSX(chp->ch_channel, slot, PRSO_FIS)); 823 chp->ch_status = fis[2]; 824 chp->ch_error = fis[3]; 825 } 826 siisata_reinit_port(sc, chp); 827 } else { 828 /* okay, we have a "Fatal Error" */ 829 siisata_device_reset(sc, chp); 830 } 831 goto command_done; 832 } 833 return 0; 834 835 command_done: 836 chp->ch_flags &= ~ATACH_IRQ_WAIT; 837 if (xfer->c_flags & C_TIMEOU) 838 ata_c->flags |= AT_TIMEOU; 839 else 840 callout_stop(&chp->ch_callout); 841 842 843 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 844 siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); 845 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 846 wakeup(&chp->ch_queue->active_xfer); 847 return 0; 848 } 849 850 chp->ch_queue->active_xfer = NULL; 851 852 if (pis) { 853 ata_c->r_head = 0; 854 ata_c->r_count = 0; 855 ata_c->r_sector = 0; 856 ata_c->r_cyl = 0; 857 if (chp->ch_status & WDCS_BSY) { 858 ata_c->flags |= AT_TIMEOU; 859 } else if (chp->ch_status & WDCS_ERR) { 860 ata_c->r_error = chp->ch_error; 861 ata_c->flags |= AT_ERROR; 862 } 863 } 864 siisata_cmd_done(chp, xfer, slot); 865 return 0; 866 } 867 868 void 869 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 870 { 871 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 872 struct siisata_channel *schp = (struct siisata_channel *)chp; 873 struct ata_command *ata_c = xfer->c_cmd; 874 int i; 875 uint16_t *idwordbuf; 876 877 SIISATA_DEBUG_PRINT( 878 ("%s: %s.\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 879 880 /* this comamnd is not active any more */ 881 schp->sch_active_slots &= ~__BIT(slot); 882 883 /* we're done with the prb */ 884 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 885 886 if (ata_c->flags & (AT_READ | AT_WRITE)) { 887 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 888 schp->sch_datad[slot]->dm_mapsize, 889 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 890 BUS_DMASYNC_POSTWRITE); 891 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 892 } 893 894 idwordbuf = xfer->c_databuf; 895 896 /* correct the endianess of IDENTIFY data */ 897 if (ata_c->r_command == WDCC_IDENTIFY || 898 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 899 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 900 idwordbuf[i] = le16toh(idwordbuf[i]); 901 } 902 } 903 904 ata_c->flags |= AT_DONE; 905 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 906 ata_c->flags |= AT_XFDONE; 907 908 ata_free_xfer(chp, xfer); 909 if (ata_c->flags & AT_WAIT) 910 wakeup(ata_c); 911 else if (ata_c->callback) 912 ata_c->callback(ata_c->callback_arg); 913 atastart(chp); 914 return; 915 } 916 917 int 918 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 919 { 920 struct ata_channel *chp = drvp->chnl_softc; 921 struct ata_xfer *xfer; 922 923 #if 1 924 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 925 SIISATA_DEBUG_PRINT( 926 ("%s: %s.\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 927 #endif 928 929 xfer = ata_get_xfer(ATAXF_NOSLEEP); 930 if (xfer == NULL) 931 return ATACMD_TRY_AGAIN; 932 if (ata_bio->flags & ATA_POLL) 933 xfer->c_flags |= C_POLL; 934 xfer->c_drive = drvp->drive; 935 xfer->c_cmd = ata_bio; 936 xfer->c_databuf = ata_bio->databuf; 937 xfer->c_bcount = ata_bio->bcount; 938 xfer->c_start = siisata_bio_start; 939 xfer->c_intr = siisata_bio_complete; 940 xfer->c_kill_xfer = siisata_bio_kill_xfer; 941 ata_exec_xfer(chp, xfer); 942 return (ata_bio->flags & ATA_ITSDONE) ? 943 ATACMD_COMPLETE : ATACMD_QUEUED; 944 } 945 946 void 947 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 948 { 949 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 950 struct siisata_channel *schp = (struct siisata_channel *)chp; 951 struct siisata_prb *prb; 952 struct ata_bio *ata_bio = xfer->c_cmd; 953 int slot = SIISATA_NON_NCQ_SLOT; 954 int nblks, i; 955 uint8_t *fis; 956 957 SIISATA_DEBUG_PRINT( 958 ("%s: %s port %d, slot %d\n", 959 SIISATANAME(sc), __func__, chp->ch_channel, slot), 960 DEBUG_FUNCS); 961 962 #ifdef DIAGNOSTIC 963 if (__predict_false(schp->sch_active_slots & __BIT(slot))) { 964 panic("%s %s trying to use already active slot %d", 965 SIISATANAME(sc), __func__, slot); 966 } 967 #endif 968 969 prb = schp->sch_prb[slot]; 970 memset(prb, 0, sizeof(struct siisata_prb)); 971 fis = prb->prb_fis; 972 973 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 974 975 /* XXX probably needs to be some common FIS-related code */ 976 fis[0] = 0x27; /* host to device */ 977 fis[1] = 0x80; /* command FIS (also, PMP) */ 978 if (ata_bio->flags & ATA_LBA48) { 979 fis[2] = (ata_bio->flags & ATA_READ) ? 980 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 981 } else { 982 fis[2] = 983 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 984 } 985 fis[4] = ata_bio->blkno & 0xff; 986 fis[5] = (ata_bio->blkno >> 8) & 0xff; 987 fis[6] = (ata_bio->blkno >> 16) & 0xff; 988 if (ata_bio->flags & ATA_LBA48) { 989 fis[7] = WDSD_LBA; 990 fis[8] = (ata_bio->blkno >> 24) & 0xff; 991 fis[9] = (ata_bio->blkno >> 32) & 0xff; 992 fis[10] = (ata_bio->blkno >> 40) & 0xff; 993 } else { 994 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 995 } 996 fis[12] = nblks & 0xff; 997 fis[13] = (ata_bio->flags & ATA_LBA48) ? 998 ((nblks >> 8) & 0xff) : 0; 999 fis[15] = WDCTL_4BIT; 1000 1001 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 1002 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1003 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1004 ata_bio->error = ERR_DMA; 1005 ata_bio->r_error = 0; 1006 siisata_bio_complete(chp, xfer, slot); 1007 return; 1008 } 1009 1010 if (xfer->c_flags & C_POLL) { 1011 /* polled command, disable interrupts */ 1012 GRWRITE(sc, GR_GC, 1013 GRREAD(sc, GR_GC) & ~(GR_GC_PXIE(chp->ch_channel))); 1014 } 1015 1016 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1017 siisata_activate_prb(sc, chp->ch_channel, 1018 slot, schp->sch_bus_prb[slot]); 1019 1020 /* keep track of what's going on */ 1021 schp->sch_active_slots |= __BIT(slot); 1022 1023 if ((xfer->c_flags & C_POLL) == 0) { 1024 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1025 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1026 siisata_timeout, chp); 1027 goto out; 1028 } 1029 1030 for (i = 0; i < ATA_DELAY / 10; i++) { 1031 if (ata_bio->flags & ATA_ITSDONE) 1032 break; 1033 siisata_intr_port(sc, schp); 1034 if (ata_bio->flags & ATA_NOSLEEP) 1035 DELAY(10000); 1036 else 1037 tsleep(&xfer, PRIBIO, "siipl", mstohz(10)); 1038 } 1039 1040 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1041 out: 1042 SIISATA_DEBUG_PRINT( 1043 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1044 return; 1045 } 1046 1047 void 1048 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1049 int reason) 1050 { 1051 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1052 struct siisata_channel *schp = (struct siisata_channel *)chp; 1053 struct ata_bio *ata_bio = xfer->c_cmd; 1054 int drive = xfer->c_drive; 1055 int slot = SIISATA_NON_NCQ_SLOT; 1056 1057 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", SIISATANAME(sc), 1058 __func__, chp->ch_channel), DEBUG_FUNCS); 1059 1060 /* mark slot inactive */ 1061 schp->sch_active_slots &= ~__BIT(slot); 1062 /* we're done with the prb */ 1063 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1064 1065 ata_free_xfer(chp, xfer); 1066 ata_bio->flags |= ATA_ITSDONE; 1067 switch (reason) { 1068 case KILL_GONE: 1069 ata_bio->error = ERR_NODEV; 1070 break; 1071 case KILL_RESET: 1072 ata_bio->error = ERR_RESET; 1073 break; 1074 default: 1075 panic("%s: port %d: unknown reason %d", 1076 __func__, chp->ch_channel, reason); 1077 } 1078 ata_bio->r_error = WDCE_ABRT; 1079 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1080 } 1081 1082 int 1083 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1084 { 1085 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1086 struct siisata_channel *schp = (struct siisata_channel *)chp; 1087 struct ata_bio *ata_bio = xfer->c_cmd; 1088 int drive = xfer->c_drive; 1089 uint32_t pss, pis; 1090 uint8_t fis[4]; 1091 uint32_t *prbfis = (void *)fis; 1092 1093 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 1094 1095 if (pis & PR_PIS_CMDCMPL) { 1096 /* get slot status, clearing completion interrupt */ 1097 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 1098 /* is this expected? */ 1099 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 1100 log(LOG_WARNING, "%s: unexpected command " 1101 "completion on port %d slot %d\n", 1102 SIISATANAME(sc), chp->ch_channel, slot); 1103 return 0; 1104 } else { 1105 if (ata_bio->flags & ATA_READ) 1106 ata_bio->bcount -= PRREAD(sc, 1107 PRSX(chp->ch_channel, slot, PRSO_RTC)); 1108 else 1109 ata_bio->bcount = 0; 1110 1111 /* XXX is reseting these right? */ 1112 chp->ch_status = 0; 1113 chp->ch_error = 0; 1114 ata_bio->error = 0; 1115 goto command_done; 1116 } 1117 } 1118 1119 if (pis & PR_PIS_CMDERRR) { 1120 uint32_t ec; 1121 1122 /* emulate a CRC error by default */ 1123 chp->ch_status = WDCS_ERR; 1124 chp->ch_error = WDCE_CRC; 1125 1126 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 1127 if (ec <= PR_PCE_DATAFISERROR) { 1128 if (ec != PR_PCE_DATAFISERROR) { 1129 /* read in specific information about error */ 1130 *prbfis = bus_space_read_stream_4( 1131 sc->sc_prt, sc->sc_prh, 1132 PRSX(chp->ch_channel, slot, PRSO_FIS)); 1133 chp->ch_status = fis[2]; 1134 chp->ch_error = fis[3]; 1135 } 1136 siisata_reinit_port(sc, chp); 1137 } else { 1138 /* okay, we have a "Fatal Error" */ 1139 siisata_device_reset(sc, chp); 1140 } 1141 goto command_done; 1142 } 1143 return 0; 1144 1145 command_done: 1146 schp->sch_active_slots &= ~__BIT(slot); 1147 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1148 callout_stop(&chp->ch_callout); 1149 1150 chp->ch_queue->active_xfer = NULL; 1151 1152 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1153 schp->sch_datad[slot]->dm_mapsize, 1154 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1155 BUS_DMASYNC_POSTWRITE); 1156 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1157 1158 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1159 siisata_bio_kill_xfer(chp, xfer, KILL_GONE); 1160 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1161 wakeup(&chp->ch_queue->active_xfer); 1162 return 0; 1163 } 1164 ata_free_xfer(chp, xfer); 1165 ata_bio->flags |= ATA_ITSDONE; 1166 if (chp->ch_status & WDCS_DWF) { 1167 ata_bio->error = ERR_DF; 1168 } else if (chp->ch_status & WDCS_ERR) { 1169 ata_bio->error = ERROR; 1170 ata_bio->r_error = chp->ch_error; 1171 } else if (chp->ch_status & WDCS_CORR) 1172 ata_bio->flags |= ATA_CORR; 1173 1174 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld\n", SIISATANAME(sc), 1175 __func__, ata_bio->bcount), DEBUG_XFERS); 1176 1177 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1178 1179 atastart(chp); 1180 return 0; 1181 } 1182 1183 void 1184 siisata_timeout(void *v) 1185 { 1186 struct ata_channel *chp = (struct ata_channel *)v; 1187 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1188 int slot = SIISATA_NON_NCQ_SLOT; 1189 int s = splbio(); 1190 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1191 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1192 xfer->c_flags |= C_TIMEOU; 1193 xfer->c_intr(chp, xfer, slot); 1194 } 1195 splx(s); 1196 } 1197 1198 static int 1199 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1200 size_t count, int op) 1201 { 1202 1203 int error, seg; 1204 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1205 struct siisata_channel *schp = (struct siisata_channel *)chp; 1206 1207 struct siisata_prb *prbp; 1208 1209 prbp = schp->sch_prb[slot]; 1210 1211 if (data == NULL) { 1212 goto end; 1213 } 1214 1215 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1216 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1217 if (error) { 1218 log(LOG_ERR, "%s port %d: " 1219 "failed to load xfer in slot %d: error %d\n", 1220 SIISATANAME(sc), chp->ch_channel, slot, error); 1221 return error; 1222 } 1223 1224 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1225 schp->sch_datad[slot]->dm_mapsize, 1226 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1227 1228 /* make sure it's clean */ 1229 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1230 1231 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1232 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1233 DEBUG_FUNCS | DEBUG_DEBUG); 1234 1235 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1236 prbp->prb_sge[seg].sge_da = 1237 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1238 prbp->prb_sge[seg].sge_dc = 1239 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1240 prbp->prb_sge[seg].sge_flags = htole32(0); 1241 } 1242 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1243 end: 1244 return 0; 1245 } 1246 1247 static inline void 1248 siisata_activate_prb(struct siisata_softc *sc, int p, int s, bus_addr_t v) 1249 { 1250 bus_size_t o = PRO_CARX(p, s); 1251 PRWRITE(sc, o, v); 1252 o += 4; 1253 #if 0 1254 if (sizeof(bus_addr_t) == 8) 1255 PRWRITE(sc, o, (v >> 32)); 1256 else 1257 #endif 1258 PRWRITE(sc, o, 0); 1259 } 1260 1261 static void 1262 siisata_reinit_port(struct siisata_softc *sc, struct ata_channel *chp) 1263 { 1264 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 1265 PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) | PR_PC_PORT_INITIALIZE); 1266 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 1267 DELAY(10); 1268 } 1269 1270 static void 1271 siisata_device_reset(struct siisata_softc *sc, struct ata_channel *chp) 1272 { 1273 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 1274 PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) | PR_PC_DEVICE_RESET); 1275 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 1276 DELAY(10); 1277 } 1278 1279 1280 #if NATAPIBUS > 0 1281 void 1282 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1283 { 1284 struct ata_channel *chp = ata_sc->sc_chan; 1285 struct atac_softc *atac = chp->ch_atac; 1286 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1287 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1288 1289 /* 1290 * Fill in the scsipi_adapter. 1291 */ 1292 adapt->adapt_dev = atac->atac_dev; 1293 adapt->adapt_nchannels = atac->atac_nchannels; 1294 adapt->adapt_request = siisata_atapi_scsipi_request; 1295 adapt->adapt_minphys = siisata_atapi_minphys; 1296 atac->atac_atapi_adapter.atapi_probe_device = 1297 siisata_atapi_probe_device; 1298 1299 /* 1300 * Fill in the scsipi_channel. 1301 */ 1302 memset(chan, 0, sizeof(*chan)); 1303 chan->chan_adapter = adapt; 1304 chan->chan_bustype = &siisata_atapi_bustype; 1305 chan->chan_channel = chp->ch_channel; 1306 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1307 chan->chan_openings = 1; 1308 chan->chan_max_periph = 1; 1309 chan->chan_ntargets = 1; 1310 chan->chan_nluns = 1; 1311 1312 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1313 atapiprint); 1314 } 1315 1316 void 1317 siisata_atapi_minphys(struct buf *bp) 1318 { 1319 if (bp->b_bcount > MAXPHYS) 1320 bp->b_bcount = MAXPHYS; 1321 minphys(bp); 1322 } 1323 1324 /* 1325 * Kill off all pending xfers for a periph. 1326 * 1327 * Must be called at splbio(). 1328 */ 1329 void 1330 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1331 { 1332 struct atac_softc *atac = 1333 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1334 struct ata_channel *chp = 1335 atac->atac_channels[periph->periph_channel->chan_channel]; 1336 1337 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1338 } 1339 1340 void 1341 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1342 int reason) 1343 { 1344 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1345 1346 /* remove this command from xfer queue */ 1347 switch (reason) { 1348 case KILL_GONE: 1349 sc_xfer->error = XS_DRIVER_STUFFUP; 1350 break; 1351 case KILL_RESET: 1352 sc_xfer->error = XS_RESET; 1353 break; 1354 default: 1355 panic("%s: port %d: unknown reason %d", 1356 __func__, chp->ch_channel, reason); 1357 } 1358 ata_free_xfer(chp, xfer); 1359 scsipi_done(sc_xfer); 1360 } 1361 1362 void 1363 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1364 { 1365 struct scsipi_channel *chan = sc->sc_channel; 1366 struct scsipi_periph *periph; 1367 struct ataparams ids; 1368 struct ataparams *id = &ids; 1369 struct siisata_softc *siic = 1370 device_private(chan->chan_adapter->adapt_dev); 1371 struct atac_softc *atac = &siic->sc_atac; 1372 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1373 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1374 struct scsipibus_attach_args sa; 1375 char serial_number[21], model[41], firmware_revision[9]; 1376 int s; 1377 1378 /* skip if already attached */ 1379 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1380 return; 1381 1382 /* if no ATAPI device detected at attach time, skip */ 1383 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1384 SIISATA_DEBUG_PRINT(("%s: drive %d " 1385 "not present\n", __func__, target), DEBUG_PROBE); 1386 return; 1387 } 1388 1389 /* Some ATAPI devices need a bit more time after software reset. */ 1390 delay(5000); 1391 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1392 #ifdef ATAPI_DEBUG_PROBE 1393 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1394 device_xname(sc->sc_dev), target, 1395 id->atap_config & ATAPI_CFG_CMD_MASK, 1396 id->atap_config & ATAPI_CFG_DRQ_MASK); 1397 #endif 1398 periph = scsipi_alloc_periph(M_NOWAIT); 1399 if (periph == NULL) { 1400 aprint_error_dev(sc->sc_dev, 1401 "%s: unable to allocate periph for " 1402 "channel %d drive %d", __func__, 1403 chp->ch_channel, target); 1404 return; 1405 } 1406 periph->periph_dev = NULL; 1407 periph->periph_channel = chan; 1408 periph->periph_switch = &atapi_probe_periphsw; 1409 periph->periph_target = target; 1410 periph->periph_lun = 0; 1411 periph->periph_quirks = PQUIRK_ONLYBIG; 1412 1413 #ifdef SCSIPI_DEBUG 1414 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1415 SCSIPI_DEBUG_TARGET == target) 1416 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1417 #endif 1418 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1419 if (id->atap_config & ATAPI_CFG_REMOV) 1420 periph->periph_flags |= PERIPH_REMOVABLE; 1421 if (periph->periph_type == T_SEQUENTIAL) { 1422 s = splbio(); 1423 drvp->drive_flags |= DRIVE_ATAPIST; 1424 splx(s); 1425 } 1426 1427 sa.sa_periph = periph; 1428 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1429 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1430 T_REMOV : T_FIXED; 1431 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1432 scsipi_strvis((u_char *)serial_number, 20, 1433 id->atap_serial, 20); 1434 scsipi_strvis((u_char *)firmware_revision, 8, 1435 id->atap_revision, 8); 1436 sa.sa_inqbuf.vendor = model; 1437 sa.sa_inqbuf.product = serial_number; 1438 sa.sa_inqbuf.revision = firmware_revision; 1439 1440 /* 1441 * Determine the operating mode capabilities of the device. 1442 */ 1443 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1444 == ATAPI_CFG_CMD_16) { 1445 periph->periph_cap |= PERIPH_CAP_CMD16; 1446 1447 /* configure port for packet length */ 1448 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1449 PRREAD(siic, PRX(chp->ch_channel, PRO_PCS)) | 1450 PR_PC_PACKET_LENGTH); 1451 } 1452 /* XXX This is gross. */ 1453 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1454 1455 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1456 1457 if (drvp->drv_softc) 1458 ata_probe_caps(drvp); 1459 else { 1460 s = splbio(); 1461 drvp->drive_flags &= ~DRIVE_ATAPI; 1462 splx(s); 1463 } 1464 } else { 1465 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1466 "failed for drive %s:%d:%d: error 0x%x\n", 1467 __func__, SIISATANAME(siic), chp->ch_channel, target, 1468 chp->ch_error), DEBUG_PROBE); 1469 s = splbio(); 1470 drvp->drive_flags &= ~DRIVE_ATAPI; 1471 splx(s); 1472 } 1473 } 1474 1475 void 1476 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1477 scsipi_adapter_req_t req, void *arg) 1478 { 1479 struct scsipi_adapter *adapt = chan->chan_adapter; 1480 struct scsipi_periph *periph; 1481 struct scsipi_xfer *sc_xfer; 1482 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1483 struct atac_softc *atac = &sc->sc_atac; 1484 struct ata_xfer *xfer; 1485 int channel = chan->chan_channel; 1486 int drive, s; 1487 1488 switch (req) { 1489 case ADAPTER_REQ_RUN_XFER: 1490 sc_xfer = arg; 1491 periph = sc_xfer->xs_periph; 1492 drive = periph->periph_target; 1493 1494 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1495 device_xname(atac->atac_dev), channel, drive), 1496 DEBUG_XFERS); 1497 1498 if (!device_is_active(atac->atac_dev)) { 1499 sc_xfer->error = XS_DRIVER_STUFFUP; 1500 scsipi_done(sc_xfer); 1501 return; 1502 } 1503 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1504 if (xfer == NULL) { 1505 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1506 scsipi_done(sc_xfer); 1507 return; 1508 } 1509 1510 if (sc_xfer->xs_control & XS_CTL_POLL) 1511 xfer->c_flags |= C_POLL; 1512 xfer->c_drive = drive; 1513 xfer->c_flags |= C_ATAPI; 1514 xfer->c_cmd = sc_xfer; 1515 xfer->c_databuf = sc_xfer->data; 1516 xfer->c_bcount = sc_xfer->datalen; 1517 xfer->c_start = siisata_atapi_start; 1518 xfer->c_intr = siisata_atapi_complete; 1519 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1520 xfer->c_dscpoll = 0; 1521 s = splbio(); 1522 ata_exec_xfer(atac->atac_channels[channel], xfer); 1523 #ifdef DIAGNOSTIC 1524 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1525 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1526 panic("%s: polled command not done", __func__); 1527 #endif 1528 splx(s); 1529 return; 1530 1531 default: 1532 /* Not supported, nothing to do. */ 1533 ; 1534 } 1535 } 1536 1537 void 1538 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1539 { 1540 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1541 struct siisata_channel *schp = (struct siisata_channel *)chp; 1542 struct siisata_prb *prbp; 1543 struct atac_softc *atac = chp->ch_atac; 1544 1545 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1546 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1547 1548 int slot = SIISATA_NON_NCQ_SLOT; 1549 int i; 1550 uint8_t *fis; 1551 1552 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d, scsi flags 0x%x \n", __func__, 1553 device_xname(atac->atac_dev), chp->ch_channel, drvp->drive, 1554 sc_xfer->xs_control), DEBUG_XFERS); 1555 1556 #ifdef DIAGNOSTIC 1557 if (__predict_false(schp->sch_active_slots & __BIT(slot))) { 1558 panic("%s %s trying to use already active slot %d", 1559 SIISATANAME(sc), __func__, slot); 1560 } 1561 #endif 1562 1563 prbp = schp->sch_prb[slot]; 1564 memset(prbp, 0, sizeof(struct siisata_prb)); 1565 fis = prbp->prb_fis; 1566 1567 /* fill in direction for ATAPI command */ 1568 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1569 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1570 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1571 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1572 1573 /* XXX probably needs to be some common FIS-related code */ 1574 fis[0] = 0x27; /* host to device */ 1575 fis[1] = 0x80; /* command FIS (and PMP) */ 1576 fis[2] = ATAPI_PKT_CMD; 1577 fis[3] = (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0; 1578 fis[7] = WDSD_IBM; 1579 fis[15] = WDCTL_4BIT; 1580 1581 /* copy over ATAPI command */ 1582 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1583 1584 if (siisata_dma_setup(chp, slot, 1585 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1586 xfer->c_databuf : NULL, 1587 xfer->c_bcount, 1588 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1589 BUS_DMA_READ : BUS_DMA_WRITE) 1590 ) 1591 panic("%s", __func__); 1592 1593 if (xfer->c_flags & C_POLL) { 1594 /* polled command, disable interrupts */ 1595 GRWRITE(sc, GR_GC, 1596 GRREAD(sc, GR_GC) & ~(GR_GC_PXIE(chp->ch_channel))); 1597 } 1598 1599 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1600 siisata_activate_prb(sc, chp->ch_channel, slot, 1601 schp->sch_bus_prb[slot]); 1602 schp->sch_active_slots |= __BIT(slot); 1603 1604 if ((xfer->c_flags & C_POLL) == 0) { 1605 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1606 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1607 siisata_timeout, chp); 1608 goto out; 1609 } 1610 /* 1611 * polled command 1612 */ 1613 for (i = 0; i < ATA_DELAY / 10; i++) { 1614 if (sc_xfer->xs_status & XS_STS_DONE) 1615 break; 1616 siisata_intr_port(sc, schp); 1617 DELAY(10000); 1618 } 1619 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1620 sc_xfer->error = XS_TIMEOUT; 1621 siisata_atapi_complete(chp, xfer, slot); 1622 } 1623 /* reenable interrupts */ 1624 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1625 out: 1626 SIISATA_DEBUG_PRINT( 1627 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1628 return; 1629 } 1630 1631 int 1632 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1633 int slot) 1634 { 1635 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1636 struct siisata_channel *schp = (struct siisata_channel *)chp; 1637 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1638 uint8_t fis[4]; 1639 uint32_t *prbfis = (void *)fis; 1640 uint32_t pss, pis; 1641 1642 SIISATA_DEBUG_PRINT( 1643 ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1644 1645 if ((xfer->c_flags & C_TIMEOU) != 0) { 1646 sc_xfer->error = XS_TIMEOUT; 1647 siisata_atapi_reset(chp, xfer); 1648 return 1; 1649 } 1650 1651 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 1652 1653 if (pis & PR_PIS_CMDCMPL) { 1654 /* get slot status, clearing completion interrupt */ 1655 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 1656 /* is this expected? */ 1657 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 1658 log(LOG_WARNING, "%s: unexpected command " 1659 "completion on port %d slot %d\n", 1660 SIISATANAME(sc), chp->ch_channel, slot); 1661 return 0; 1662 } 1663 } 1664 1665 if (pis & PR_PIS_CMDERRR) { 1666 uint32_t ec; 1667 1668 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 1669 if (ec <= PR_PCE_DATAFISERROR) { 1670 if (ec != PR_PCE_DATAFISERROR) { 1671 /* read in specific information about error */ 1672 *prbfis = bus_space_read_stream_4( 1673 sc->sc_prt, sc->sc_prh, 1674 PRSX(chp->ch_channel, slot, PRSO_FIS)); 1675 if (ec == PR_PCE_DEVICEERROR) { 1676 /* error code 1 implies * 1677 * WDCS_ERR in fis[2] */ 1678 sc_xfer->error = XS_SHORTSENSE; 1679 sc_xfer->sense.atapi_sense = fis[3]; 1680 } 1681 siisata_reinit_port(sc, chp); 1682 } else 1683 siisata_reinit_port(sc, chp); 1684 } else { 1685 /* okay, we have a "Fatal Error" */ 1686 siisata_device_reset(sc, chp); 1687 } 1688 } 1689 1690 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1691 siisata_atapi_done(chp, xfer, slot); 1692 return 1; 1693 } 1694 1695 void 1696 siisata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1697 { 1698 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1699 struct siisata_channel *schp = (struct siisata_channel *)chp; 1700 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1701 struct atac_softc *atac = chp->ch_atac; 1702 1703 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d: flags 0x%x\n", __func__, 1704 device_xname(atac->atac_dev), 1705 chp->ch_channel, xfer->c_drive, 1706 (unsigned int)xfer->c_flags), DEBUG_XFERS); 1707 1708 /* this comamnd is not active any more */ 1709 schp->sch_active_slots &= ~__BIT(slot); 1710 1711 if (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 1712 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1713 schp->sch_datad[slot]->dm_mapsize, 1714 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1715 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1716 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1717 } 1718 1719 xfer->c_bcount -= sc_xfer->datalen; 1720 sc_xfer->resid = xfer->c_bcount; 1721 1722 if (xfer->c_bcount != 0) { 1723 SIISATA_DEBUG_PRINT(("%s: bcount value is " 1724 "%d after io\n", __func__, xfer->c_bcount), DEBUG_XFERS); 1725 } 1726 #ifdef DIAGNOSTIC 1727 if (xfer->c_bcount < 0) { 1728 log(LOG_WARNING, "%s(): bcount value " 1729 "is %d after io\n", __func__, xfer->c_bcount); 1730 } 1731 #endif 1732 1733 1734 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1735 siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); 1736 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1737 wakeup(&chp->ch_queue->active_xfer); 1738 return; 1739 } 1740 1741 /* vvv is this in the right order? ^^^ */ 1742 1743 callout_stop(&chp->ch_callout); 1744 chp->ch_queue->active_xfer = NULL; 1745 ata_free_xfer(chp, xfer); 1746 1747 SIISATA_DEBUG_PRINT(("%s: scsipi_done\n", __func__), DEBUG_XFERS); 1748 scsipi_done(sc_xfer); 1749 SIISATA_DEBUG_PRINT(("atastart from %s, flags 0x%x\n", __func__, 1750 chp->ch_flags), DEBUG_XFERS); 1751 atastart(chp); 1752 return; 1753 } 1754 1755 void 1756 siisata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 1757 { 1758 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1759 drvp->state = 0; 1760 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1761 siisata_atapi_done(chp, xfer, SIISATA_NON_NCQ_SLOT); 1762 return; 1763 } 1764 #endif /* NATAPIBUS */ 1765
Indexes created Fri Sep 26 20:09:58 GMT 2025