siisata.c revision 1.2
1 /* $NetBSD: siisata.c,v 1.2 2008/09/14 21:53:49 jakllsch Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* from atapi_wdc.c */ 36 37 /* 38 * Copyright (c) 1998, 2001 Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Manuel Bouyer. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 2007, 2008 Jonathan A. Kollasch. 68 * All rights reserved. 69 * 70 * Redistribution and use in source and binary forms, with or without 71 * modification, are permitted provided that the following conditions 72 * are met: 73 * 1. Redistributions of source code must retain the above copyright 74 * notice, this list of conditions and the following disclaimer. 75 * 2. Redistributions in binary form must reproduce the above copyright 76 * notice, this list of conditions and the following disclaimer in the 77 * documentation and/or other materials provided with the distribution. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 80 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 81 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 82 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 83 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 84 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 85 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 86 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 87 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 88 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 89 * 90 */ 91 92 #include <sys/types.h> 93 #include <sys/malloc.h> 94 #include <sys/param.h> 95 #include <sys/kernel.h> 96 #include <sys/systm.h> 97 #include <sys/syslog.h> 98 #include <sys/disklabel.h> 99 #include <sys/buf.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <dev/ic/wdcreg.h> 104 #include <dev/ata/atareg.h> 105 #include <dev/ata/satavar.h> 106 #include <dev/ata/satareg.h> 107 #include <dev/ic/siisatavar.h> 108 109 #include "atapibus.h" 110 111 #ifdef SIISATA_DEBUG 112 #if 0 113 int siisata_debug_mask = 0xffff; 114 #else 115 int siisata_debug_mask = 0; 116 #endif 117 #endif 118 119 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 120 121 static void siisata_attach_port(struct siisata_softc *, int); 122 static void siisata_intr_port(struct siisata_softc *, 123 struct siisata_channel *); 124 125 void siisata_probe_drive(struct ata_channel *); 126 void siisata_setup_channel(struct ata_channel *); 127 128 int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); 129 void siisata_reset_drive(struct ata_drive_datas *, int); 130 void siisata_reset_channel(struct ata_channel *, int); 131 int siisata_ata_addref(struct ata_drive_datas *); 132 void siisata_ata_delref(struct ata_drive_datas *); 133 void siisata_killpending(struct ata_drive_datas *); 134 135 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 136 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 137 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 138 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 139 140 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 141 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 142 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 143 int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); 144 145 void siisata_timeout(void *); 146 147 static void siisata_reinit_port(struct ata_channel *); 148 static void siisata_device_reset(struct ata_channel *); 149 static void siisata_activate_prb(struct siisata_channel *, int); 150 static void siisata_deactivate_prb(struct siisata_channel *, int); 151 static int siisata_dma_setup(struct ata_channel *chp, int slot, 152 void *data, size_t, int); 153 154 #if NATAPIBUS > 0 155 void siisata_atapibus_attach(struct atabus_softc *); 156 void siisata_atapi_probe_device(struct atapibus_softc *, int); 157 void siisata_atapi_minphys(struct buf *); 158 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 159 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 160 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 161 void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 162 void siisata_atapi_reset(struct ata_channel *, struct ata_xfer *); 163 void siisata_atapi_scsipi_request(struct scsipi_channel *, 164 scsipi_adapter_req_t, void *); 165 void siisata_atapi_kill_pending(struct scsipi_periph *); 166 #endif /* NATAPIBUS */ 167 168 const struct ata_bustype siisata_ata_bustype = { 169 SCSIPI_BUSTYPE_ATA, 170 siisata_ata_bio, 171 siisata_reset_drive, 172 siisata_reset_channel, 173 siisata_exec_command, 174 ata_get_params, 175 siisata_ata_addref, 176 siisata_ata_delref, 177 siisata_killpending 178 }; 179 180 #if NATAPIBUS > 0 181 static const struct scsipi_bustype siisata_atapi_bustype = { 182 SCSIPI_BUSTYPE_ATAPI, 183 atapi_scsipi_cmd, 184 atapi_interpret_sense, 185 atapi_print_addr, 186 siisata_atapi_kill_pending 187 }; 188 #endif /* NATAPIBUS */ 189 190 191 void 192 siisata_attach(struct siisata_softc *sc) 193 { 194 int i; 195 196 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 197 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 198 199 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 200 sc->sc_atac.atac_pio_cap = 4; 201 sc->sc_atac.atac_dma_cap = 2; 202 sc->sc_atac.atac_udma_cap = 6; 203 sc->sc_atac.atac_channels = sc->sc_chanarray; 204 sc->sc_atac.atac_probe = siisata_probe_drive; 205 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 206 sc->sc_atac.atac_set_modes = siisata_setup_channel; 207 #if NATAPIBUS > 0 208 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 209 #endif 210 211 /* come out of reset state */ 212 GRWRITE(sc, GR_GC, 0); 213 214 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 215 siisata_attach_port(sc, i); 216 } 217 218 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 219 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 220 DEBUG_FUNCS); 221 return; 222 } 223 224 static void 225 siisata_init_port(struct siisata_softc *sc, int port) 226 { 227 struct siisata_channel *schp; 228 struct ata_channel *chp; 229 230 schp = &sc->sc_channels[port]; 231 chp = (struct ata_channel *)schp; 232 233 /* come out of reset, 64-bit activation */ 234 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 235 PR_PC_32BA | PR_PC_PORT_RESET); 236 /* initialize port */ 237 siisata_reinit_port(chp); 238 /* clear any interrupts */ 239 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 240 /* enable CmdErrr+CmdCmpl interrupting */ 241 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 242 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 243 /* enable port interrupt */ 244 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 245 } 246 247 static void 248 siisata_attach_port(struct siisata_softc *sc, int port) 249 { 250 int j; 251 bus_dma_segment_t seg; 252 int dmasize; 253 int error; 254 int rseg; 255 void *prbp; 256 struct siisata_channel *schp; 257 struct ata_channel *chp; 258 259 schp = &sc->sc_channels[port]; 260 chp = (struct ata_channel *)schp; 261 sc->sc_chanarray[port] = chp; 262 chp->ch_channel = port; 263 chp->ch_atac = &sc->sc_atac; 264 chp->ch_queue = malloc(sizeof(struct ata_queue), 265 M_DEVBUF, M_NOWAIT); 266 if (chp->ch_queue == NULL) { 267 aprint_error_dev(sc->sc_atac.atac_dev, 268 "port %d: can't allocate memory " 269 "for command queue", chp->ch_channel); 270 return; 271 } 272 273 274 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 275 276 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 277 __func__, dmasize), DEBUG_FUNCS); 278 279 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 280 &seg, 1, &rseg, BUS_DMA_NOWAIT); 281 if (error) { 282 aprint_error_dev(sc->sc_atac.atac_dev, 283 "unable to allocate PRB table memory, " 284 "error=%d\n", error); 285 return; 286 } 287 288 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 289 &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 290 if (error) { 291 aprint_error_dev(sc->sc_atac.atac_dev, 292 "unable to map PRB table memory, " 293 "error=%d\n", error); 294 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 295 return; 296 } 297 298 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 299 BUS_DMA_NOWAIT, &schp->sch_prbd); 300 if (error) { 301 aprint_error_dev(sc->sc_atac.atac_dev, 302 "unable to create PRB table map, " 303 "error=%d\n", error); 304 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 305 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 306 return; 307 } 308 309 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 310 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 311 if (error) { 312 aprint_error_dev(sc->sc_atac.atac_dev, 313 "unable to load PRB table map, " 314 "error=%d\n", error); 315 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 316 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 317 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 318 return; 319 } 320 321 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 322 schp->sch_prb[j] = (struct siisata_prb *) 323 ((char *)prbp + SIISATA_CMD_SIZE * j); 324 schp->sch_bus_prb[j] = 325 schp->sch_prbd->dm_segs[0].ds_addr + 326 SIISATA_CMD_SIZE * j; 327 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 328 SIISATA_NSGE, MAXPHYS, 0, 329 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 330 &schp->sch_datad[j]); 331 if (error) { 332 aprint_error_dev(sc->sc_atac.atac_dev, 333 "couldn't create xfer DMA map, error=%d\n", 334 error); 335 return; 336 } 337 } 338 339 chp->ch_ndrive = 1; 340 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 341 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "couldn't map port %d SStatus regs\n", 344 chp->ch_channel); 345 return; 346 } 347 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 348 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 349 aprint_error_dev(sc->sc_atac.atac_dev, 350 "couldn't map port %d SControl regs\n", 351 chp->ch_channel); 352 return; 353 } 354 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 355 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 356 aprint_error_dev(sc->sc_atac.atac_dev, 357 "couldn't map port %d SError regs\n", 358 chp->ch_channel); 359 return; 360 } 361 362 siisata_init_port(sc, port); 363 364 ata_channel_attach(chp); 365 366 return; 367 } 368 369 void 370 siisata_resume(struct siisata_softc *sc) 371 { 372 int i; 373 374 /* come out of reset state */ 375 GRWRITE(sc, GR_GC, 0); 376 377 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 378 siisata_init_port(sc, i); 379 } 380 381 } 382 383 int 384 siisata_intr(void *v) 385 { 386 struct siisata_softc *sc = v; 387 uint32_t is; 388 int i, r = 0; 389 while ((is = GRREAD(sc, GR_GIS))) { 390 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 391 SIISATANAME(sc), __func__, is), DEBUG_INTR); 392 r = 1; 393 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 394 if (is & GR_GIS_PXIS(i)) 395 siisata_intr_port(sc, &sc->sc_channels[i]); 396 } 397 return r; 398 } 399 400 static void 401 siisata_intr_port(struct siisata_softc *sc, struct siisata_channel *schp) 402 { 403 struct ata_channel *chp = &schp->ata_channel; 404 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 405 int slot = SIISATA_NON_NCQ_SLOT; 406 407 SIISATA_DEBUG_PRINT(("%s: %s port %d\n", 408 SIISATANAME(sc), __func__, chp->ch_channel), DEBUG_INTR); 409 410 if ((xfer != NULL) && (xfer->c_intr != NULL)) 411 xfer->c_intr(chp, xfer, slot); 412 #ifdef DIAGNOSTIC 413 else 414 log(LOG_WARNING, "%s: unable to handle interrupt\n", __func__); 415 #endif 416 417 /* clear some (ok, all) ints */ 418 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 419 420 return; 421 } 422 423 void 424 siisata_reset_drive(struct ata_drive_datas *drvp, int flags) 425 { 426 struct ata_channel *chp = drvp->chnl_softc; 427 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 428 struct siisata_channel *schp = (struct siisata_channel *)chp; 429 struct siisata_prb *prb; 430 int slot = SIISATA_NON_NCQ_SLOT; 431 432 /* wait for ready */ 433 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 434 DELAY(10); 435 436 prb = schp->sch_prb[slot]; 437 memset(prb, 0, sizeof(struct siisata_prb)); 438 prb->prb_control = 439 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 440 441 siisata_activate_prb(schp, slot); 442 443 /* wait for completion */ 444 while (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & PR_PXSS(slot)) 445 DELAY(10); 446 447 siisata_deactivate_prb(schp, slot); 448 449 log(LOG_DEBUG, "%s: ch_status %x ch_error %x\n", 450 __func__, chp->ch_status, chp->ch_error); 451 452 #if 1 453 /* attempt to downgrade signaling in event of CRC error */ 454 /* XXX should be part of the MI (S)ATA subsystem */ 455 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 456 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 457 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 458 DELAY(10); 459 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 460 SControl_IPM_NONE | SControl_SPD_G1); 461 DELAY(10); 462 for (;;) { 463 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 464 & SStatus_DET_mask) == SStatus_DET_DEV) 465 break; 466 DELAY(10); 467 } 468 } 469 #endif 470 471 #if 1 472 chp->ch_status = 0; 473 chp->ch_error = 0; 474 #endif 475 return; 476 } 477 478 void 479 siisata_reset_channel(struct ata_channel *chp, int flags) 480 { 481 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 482 struct siisata_channel *schp = (struct siisata_channel *)chp; 483 484 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 485 DEBUG_FUNCS); 486 487 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 488 schp->sch_sstatus) != SStatus_DET_DEV) { 489 log(LOG_CRIT, "%s port %d: reset failed\n", 490 SIISATANAME(sc), chp->ch_channel); 491 /* XXX and then ? */ 492 } 493 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 494 DELAY(10); 495 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 496 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 497 if (chp->ch_queue->active_xfer) { 498 chp->ch_queue->active_xfer->c_kill_xfer(chp, 499 chp->ch_queue->active_xfer, KILL_RESET); 500 } 501 502 return; 503 } 504 505 int 506 siisata_ata_addref(struct ata_drive_datas *drvp) 507 { 508 return 0; 509 } 510 511 void 512 siisata_ata_delref(struct ata_drive_datas *drvp) 513 { 514 return; 515 } 516 517 void 518 siisata_killpending(struct ata_drive_datas *drvp) 519 { 520 return; 521 } 522 523 void 524 siisata_probe_drive(struct ata_channel *chp) 525 { 526 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 527 struct siisata_channel *schp = (struct siisata_channel *)chp; 528 int i; 529 int s; 530 uint32_t sig; 531 int slot = SIISATA_NON_NCQ_SLOT; 532 struct siisata_prb *prb; 533 534 DELAY(chp->ch_channel * 2048 + 1023); /* XXX */ 535 536 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 537 __func__, chp->ch_channel), DEBUG_FUNCS); 538 539 /* XXX This should be done by other code. */ 540 for (i = 0; i < chp->ch_ndrive; i++) { 541 chp->ch_drive[i].chnl_softc = chp; 542 chp->ch_drive[i].drive = i; 543 } 544 545 switch (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 546 schp->sch_sstatus)) { 547 case SStatus_DET_DEV: 548 /* wait for ready */ 549 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) 550 & PR_PS_PORT_READY)) 551 DELAY(10); 552 553 prb = schp->sch_prb[slot]; 554 memset(prb, 0, sizeof(struct siisata_prb)); 555 prb->prb_control = 556 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 557 558 siisata_activate_prb(schp, slot); 559 560 /* wait for completion */ 561 while (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) 562 & PR_PXSS(slot)) 563 DELAY(10); 564 565 siisata_deactivate_prb(schp, slot); 566 567 /* read the signature out of the FIS */ 568 sig = 0; 569 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 570 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 571 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 572 PRSO_FIS+0xc)) & 0xff; 573 574 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 575 __func__, sig), DEBUG_PROBE); 576 577 /* some ATAPI devices have bogus lower two bytes, sigh */ 578 if ((sig & 0xffff0000) == 0xeb140000) { 579 sig &= 0xffff0000; 580 sig |= 0x00000101; 581 } 582 583 s = splbio(); 584 switch (sig) { 585 case 0xeb140101: 586 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 587 break; 588 case 0x00000101: 589 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 590 break; 591 default: 592 aprint_error_dev(sc->sc_atac.atac_dev, 593 "%s: unknown device signature 0x%08x\n", 594 __func__, sig); 595 } 596 splx(s); 597 break; 598 default: 599 break; 600 } 601 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 602 __func__, chp->ch_channel), DEBUG_PROBE); 603 return; 604 } 605 606 void 607 siisata_setup_channel(struct ata_channel *chp) 608 { 609 return; 610 } 611 612 int 613 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 614 { 615 struct ata_channel *chp = drvp->chnl_softc; 616 struct ata_xfer *xfer; 617 int ret; 618 int s; 619 620 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 621 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 622 DEBUG_FUNCS); 623 624 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? 625 ATAXF_CANSLEEP : ATAXF_NOSLEEP); 626 if (xfer == NULL) 627 return ATACMD_TRY_AGAIN; 628 if (ata_c->flags & AT_POLL) 629 xfer->c_flags |= C_POLL; 630 if (ata_c->flags & AT_WAIT) 631 xfer->c_flags |= C_WAIT; 632 xfer->c_drive = drvp->drive; 633 xfer->c_databuf = ata_c->data; 634 xfer->c_bcount = ata_c->bcount; 635 xfer->c_cmd = ata_c; 636 xfer->c_start = siisata_cmd_start; 637 xfer->c_intr = siisata_cmd_complete; 638 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 639 s = splbio(); 640 ata_exec_xfer(chp, xfer); 641 #ifdef DIAGNOSTIC 642 if ((ata_c->flags & AT_POLL) != 0 && 643 (ata_c->flags & AT_DONE) == 0) 644 panic("%s: polled command not done", __func__); 645 #endif 646 if (ata_c->flags & AT_DONE) { 647 ret = ATACMD_COMPLETE; 648 } else { 649 if (ata_c->flags & AT_WAIT) { 650 while ((ata_c->flags & AT_DONE) == 0) { 651 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 652 SIISATANAME( 653 (struct siisata_softc *)chp->ch_atac), 654 __func__), DEBUG_FUNCS); 655 tsleep(ata_c, PRIBIO, "siicmd", 0); 656 } 657 ret = ATACMD_COMPLETE; 658 } else { 659 ret = ATACMD_QUEUED; 660 } 661 } 662 splx(s); 663 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 664 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 665 DEBUG_FUNCS); 666 return ret; 667 } 668 669 void 670 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 671 { 672 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 673 struct siisata_channel *schp = (struct siisata_channel *)chp; 674 struct ata_command *ata_c = xfer->c_cmd; 675 int slot = SIISATA_NON_NCQ_SLOT; 676 struct siisata_prb *prb; 677 uint8_t *fis; 678 int i; 679 680 SIISATA_DEBUG_PRINT(("%s: %s port %d, slot %d\n", 681 SIISATANAME(sc), __func__, chp->ch_channel, slot), DEBUG_FUNCS); 682 683 prb = schp->sch_prb[slot]; 684 memset(prb, 0, sizeof(struct siisata_prb)); 685 fis = prb->prb_fis; 686 687 /* XXX probably needs to be some common FIS-related code */ 688 fis[0] = 0x27; /* host to device */ 689 fis[1] = 0x80; /* command FIS (also, PMP) */ 690 fis[2] = ata_c->r_command; 691 fis[3] = ata_c->r_features; 692 fis[4] = ata_c->r_sector; 693 fis[5] = ata_c->r_cyl & 0xff; 694 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 695 fis[7] = ata_c->r_head & 0x0f; 696 fis[12] = ata_c->r_count; 697 fis[15] = WDCTL_4BIT; 698 699 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 700 701 if (siisata_dma_setup(chp, slot, 702 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 703 ata_c->bcount, 704 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 705 ata_c->flags |= AT_DF; 706 siisata_cmd_complete(chp, xfer, slot); 707 return; 708 } 709 710 if (xfer->c_flags & C_POLL) { 711 /* polled command, disable interrupts */ 712 GRWRITE(sc, GR_GC, 713 GRREAD(sc, GR_GC) & ~(GR_GC_PXIE(chp->ch_channel))); 714 } 715 716 /* go for it */ 717 siisata_activate_prb(schp, slot); 718 719 if ((ata_c->flags & AT_POLL) == 0) { 720 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 721 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 722 siisata_timeout, chp); 723 goto out; 724 } 725 726 for (i = 0; i < ata_c->timeout / 10; i++) { 727 if (ata_c->flags & AT_DONE) 728 break; 729 siisata_intr_port(sc, schp); 730 if (ata_c->flags & AT_WAIT) 731 tsleep(&xfer, PRIBIO, "siipl", mstohz(10)); 732 else 733 DELAY(10000); 734 } 735 736 if ((ata_c->flags & AT_DONE) == 0) { 737 ata_c->flags |= AT_TIMEOU; 738 siisata_cmd_complete(chp, xfer, slot); 739 } 740 741 /* reenable interrupts */ 742 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 743 out: 744 SIISATA_DEBUG_PRINT( 745 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 746 return; 747 } 748 749 void 750 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 751 int reason) 752 { 753 int slot = SIISATA_NON_NCQ_SLOT; 754 755 struct ata_command *ata_c = xfer->c_cmd; 756 switch (reason) { 757 case KILL_GONE: 758 ata_c->flags |= AT_GONE; 759 break; 760 case KILL_RESET: 761 ata_c->flags |= AT_RESET; 762 break; 763 default: 764 panic("%s: port %d: unknown reason %d", 765 __func__, chp->ch_channel, reason); 766 } 767 siisata_cmd_done(chp, xfer, slot); 768 } 769 770 int 771 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 772 { 773 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 774 struct siisata_channel *schp = (struct siisata_channel *)chp; 775 struct ata_command *ata_c = xfer->c_cmd; 776 uint32_t pss, pis; 777 uint8_t fis[4]; 778 uint32_t *prbfis = (void *)fis; 779 780 SIISATA_DEBUG_PRINT( 781 ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 782 783 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 784 785 if ((xfer->c_flags & C_TIMEOU) != 0) 786 goto command_done; 787 788 if (pis & PR_PIS_CMDCMPL) { 789 /* get slot status, clearing completion interrupt */ 790 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 791 /* is this expected? */ 792 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 793 log(LOG_WARNING, "%s: unexpected command " 794 "completion on port %d slot %d\n", 795 SIISATANAME(sc), chp->ch_channel, slot); 796 return 0; 797 } else 798 goto command_done; 799 } 800 801 if (pis & PR_PIS_CMDERRR) { 802 uint32_t ec; 803 804 /* emulate a CRC error by default */ 805 chp->ch_status = WDCS_ERR; 806 chp->ch_error = WDCE_CRC; 807 808 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 809 if (ec <= PR_PCE_DATAFISERROR) { 810 if (ec != PR_PCE_DATAFISERROR) { 811 /* read in specific information about error */ 812 *prbfis = bus_space_read_stream_4( 813 sc->sc_prt, sc->sc_prh, 814 PRSX(chp->ch_channel, slot, PRSO_FIS)); 815 chp->ch_status = fis[2]; 816 chp->ch_error = fis[3]; 817 } 818 siisata_reinit_port(chp); 819 } else { 820 /* okay, we have a "Fatal Error" */ 821 siisata_device_reset(chp); 822 } 823 goto command_done; 824 } 825 return 0; 826 827 command_done: 828 chp->ch_flags &= ~ATACH_IRQ_WAIT; 829 if (xfer->c_flags & C_TIMEOU) 830 ata_c->flags |= AT_TIMEOU; 831 else 832 callout_stop(&chp->ch_callout); 833 834 835 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 836 siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); 837 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 838 wakeup(&chp->ch_queue->active_xfer); 839 return 0; 840 } 841 842 chp->ch_queue->active_xfer = NULL; 843 844 if (pis) { 845 ata_c->r_head = 0; 846 ata_c->r_count = 0; 847 ata_c->r_sector = 0; 848 ata_c->r_cyl = 0; 849 if (chp->ch_status & WDCS_BSY) { 850 ata_c->flags |= AT_TIMEOU; 851 } else if (chp->ch_status & WDCS_ERR) { 852 ata_c->r_error = chp->ch_error; 853 ata_c->flags |= AT_ERROR; 854 } 855 } 856 siisata_cmd_done(chp, xfer, slot); 857 return 0; 858 } 859 860 void 861 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 862 { 863 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 864 struct siisata_channel *schp = (struct siisata_channel *)chp; 865 struct ata_command *ata_c = xfer->c_cmd; 866 int i; 867 uint16_t *idwordbuf; 868 869 SIISATA_DEBUG_PRINT( 870 ("%s: %s.\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 871 872 siisata_deactivate_prb(schp, slot); 873 874 if (ata_c->flags & (AT_READ | AT_WRITE)) { 875 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 876 schp->sch_datad[slot]->dm_mapsize, 877 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 878 BUS_DMASYNC_POSTWRITE); 879 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 880 } 881 882 idwordbuf = xfer->c_databuf; 883 884 /* correct the endianess of IDENTIFY data */ 885 if (ata_c->r_command == WDCC_IDENTIFY || 886 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 887 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 888 idwordbuf[i] = le16toh(idwordbuf[i]); 889 } 890 } 891 892 ata_c->flags |= AT_DONE; 893 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 894 ata_c->flags |= AT_XFDONE; 895 896 ata_free_xfer(chp, xfer); 897 if (ata_c->flags & AT_WAIT) 898 wakeup(ata_c); 899 else if (ata_c->callback) 900 ata_c->callback(ata_c->callback_arg); 901 atastart(chp); 902 return; 903 } 904 905 int 906 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 907 { 908 struct ata_channel *chp = drvp->chnl_softc; 909 struct ata_xfer *xfer; 910 911 SIISATA_DEBUG_PRINT( ("%s: %s.\n", 912 SIISATANAME((struct siisata_softc *)chp->ch_atac), 913 __func__), DEBUG_FUNCS); 914 915 xfer = ata_get_xfer(ATAXF_NOSLEEP); 916 if (xfer == NULL) 917 return ATACMD_TRY_AGAIN; 918 if (ata_bio->flags & ATA_POLL) 919 xfer->c_flags |= C_POLL; 920 xfer->c_drive = drvp->drive; 921 xfer->c_cmd = ata_bio; 922 xfer->c_databuf = ata_bio->databuf; 923 xfer->c_bcount = ata_bio->bcount; 924 xfer->c_start = siisata_bio_start; 925 xfer->c_intr = siisata_bio_complete; 926 xfer->c_kill_xfer = siisata_bio_kill_xfer; 927 ata_exec_xfer(chp, xfer); 928 return (ata_bio->flags & ATA_ITSDONE) ? 929 ATACMD_COMPLETE : ATACMD_QUEUED; 930 } 931 932 void 933 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 934 { 935 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 936 struct siisata_channel *schp = (struct siisata_channel *)chp; 937 struct siisata_prb *prb; 938 struct ata_bio *ata_bio = xfer->c_cmd; 939 int slot = SIISATA_NON_NCQ_SLOT; 940 int nblks, i; 941 uint8_t *fis; 942 943 SIISATA_DEBUG_PRINT( 944 ("%s: %s port %d, slot %d\n", 945 SIISATANAME(sc), __func__, chp->ch_channel, slot), 946 DEBUG_FUNCS); 947 948 prb = schp->sch_prb[slot]; 949 memset(prb, 0, sizeof(struct siisata_prb)); 950 fis = prb->prb_fis; 951 952 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 953 954 /* XXX probably needs to be some common FIS-related code */ 955 fis[0] = 0x27; /* host to device */ 956 fis[1] = 0x80; /* command FIS (also, PMP) */ 957 if (ata_bio->flags & ATA_LBA48) { 958 fis[2] = (ata_bio->flags & ATA_READ) ? 959 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 960 } else { 961 fis[2] = 962 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 963 } 964 fis[4] = ata_bio->blkno & 0xff; 965 fis[5] = (ata_bio->blkno >> 8) & 0xff; 966 fis[6] = (ata_bio->blkno >> 16) & 0xff; 967 if (ata_bio->flags & ATA_LBA48) { 968 fis[7] = WDSD_LBA; 969 fis[8] = (ata_bio->blkno >> 24) & 0xff; 970 fis[9] = (ata_bio->blkno >> 32) & 0xff; 971 fis[10] = (ata_bio->blkno >> 40) & 0xff; 972 } else { 973 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 974 } 975 fis[12] = nblks & 0xff; 976 fis[13] = (ata_bio->flags & ATA_LBA48) ? 977 ((nblks >> 8) & 0xff) : 0; 978 fis[15] = WDCTL_4BIT; 979 980 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 981 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 982 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 983 ata_bio->error = ERR_DMA; 984 ata_bio->r_error = 0; 985 siisata_bio_complete(chp, xfer, slot); 986 return; 987 } 988 989 if (xfer->c_flags & C_POLL) { 990 /* polled command, disable interrupts */ 991 GRWRITE(sc, GR_GC, 992 GRREAD(sc, GR_GC) & ~(GR_GC_PXIE(chp->ch_channel))); 993 } 994 995 siisata_activate_prb(schp, slot); 996 997 if ((xfer->c_flags & C_POLL) == 0) { 998 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 999 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1000 siisata_timeout, chp); 1001 goto out; 1002 } 1003 1004 for (i = 0; i < ATA_DELAY / 10; i++) { 1005 if (ata_bio->flags & ATA_ITSDONE) 1006 break; 1007 siisata_intr_port(sc, schp); 1008 if (ata_bio->flags & ATA_NOSLEEP) 1009 DELAY(10000); 1010 else 1011 tsleep(&xfer, PRIBIO, "siipl", mstohz(10)); 1012 } 1013 1014 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1015 out: 1016 SIISATA_DEBUG_PRINT( 1017 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1018 return; 1019 } 1020 1021 void 1022 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1023 int reason) 1024 { 1025 struct siisata_channel *schp = (struct siisata_channel *)chp; 1026 struct ata_bio *ata_bio = xfer->c_cmd; 1027 int drive = xfer->c_drive; 1028 int slot = SIISATA_NON_NCQ_SLOT; 1029 1030 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1031 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1032 __func__, chp->ch_channel), DEBUG_FUNCS); 1033 1034 siisata_deactivate_prb(schp, slot); 1035 1036 ata_free_xfer(chp, xfer); 1037 ata_bio->flags |= ATA_ITSDONE; 1038 switch (reason) { 1039 case KILL_GONE: 1040 ata_bio->error = ERR_NODEV; 1041 break; 1042 case KILL_RESET: 1043 ata_bio->error = ERR_RESET; 1044 break; 1045 default: 1046 panic("%s: port %d: unknown reason %d", 1047 __func__, chp->ch_channel, reason); 1048 } 1049 ata_bio->r_error = WDCE_ABRT; 1050 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1051 } 1052 1053 int 1054 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1055 { 1056 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1057 struct siisata_channel *schp = (struct siisata_channel *)chp; 1058 struct ata_bio *ata_bio = xfer->c_cmd; 1059 int drive = xfer->c_drive; 1060 uint32_t pss, pis; 1061 uint8_t fis[4]; 1062 uint32_t *prbfis = (void *)fis; 1063 1064 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 1065 1066 if (pis & PR_PIS_CMDCMPL) { 1067 /* get slot status, clearing completion interrupt */ 1068 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 1069 /* is this expected? */ 1070 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 1071 log(LOG_WARNING, "%s: unexpected command " 1072 "completion on port %d slot %d\n", 1073 SIISATANAME(sc), chp->ch_channel, slot); 1074 return 0; 1075 } else { 1076 if (ata_bio->flags & ATA_READ) 1077 ata_bio->bcount -= PRREAD(sc, 1078 PRSX(chp->ch_channel, slot, PRSO_RTC)); 1079 else 1080 ata_bio->bcount = 0; 1081 1082 /* XXX is reseting these right? */ 1083 chp->ch_status = 0; 1084 chp->ch_error = 0; 1085 ata_bio->error = 0; 1086 goto command_done; 1087 } 1088 } 1089 1090 if (pis & PR_PIS_CMDERRR) { 1091 uint32_t ec; 1092 1093 /* emulate a CRC error by default */ 1094 chp->ch_status = WDCS_ERR; 1095 chp->ch_error = WDCE_CRC; 1096 1097 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 1098 if (ec <= PR_PCE_DATAFISERROR) { 1099 if (ec != PR_PCE_DATAFISERROR) { 1100 /* read in specific information about error */ 1101 *prbfis = bus_space_read_stream_4( 1102 sc->sc_prt, sc->sc_prh, 1103 PRSX(chp->ch_channel, slot, PRSO_FIS)); 1104 chp->ch_status = fis[2]; 1105 chp->ch_error = fis[3]; 1106 } 1107 siisata_reinit_port(chp); 1108 } else { 1109 /* okay, we have a "Fatal Error" */ 1110 siisata_device_reset(chp); 1111 } 1112 goto command_done; 1113 } 1114 return 0; 1115 1116 command_done: 1117 schp->sch_active_slots &= ~__BIT(slot); 1118 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1119 callout_stop(&chp->ch_callout); 1120 1121 chp->ch_queue->active_xfer = NULL; 1122 1123 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1124 schp->sch_datad[slot]->dm_mapsize, 1125 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1126 BUS_DMASYNC_POSTWRITE); 1127 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1128 1129 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1130 siisata_bio_kill_xfer(chp, xfer, KILL_GONE); 1131 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1132 wakeup(&chp->ch_queue->active_xfer); 1133 return 0; 1134 } 1135 ata_free_xfer(chp, xfer); 1136 ata_bio->flags |= ATA_ITSDONE; 1137 if (chp->ch_status & WDCS_DWF) { 1138 ata_bio->error = ERR_DF; 1139 } else if (chp->ch_status & WDCS_ERR) { 1140 ata_bio->error = ERROR; 1141 ata_bio->r_error = chp->ch_error; 1142 } else if (chp->ch_status & WDCS_CORR) 1143 ata_bio->flags |= ATA_CORR; 1144 1145 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld\n", SIISATANAME(sc), 1146 __func__, ata_bio->bcount), DEBUG_XFERS); 1147 1148 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1149 1150 atastart(chp); 1151 return 0; 1152 } 1153 1154 void 1155 siisata_timeout(void *v) 1156 { 1157 struct ata_channel *chp = (struct ata_channel *)v; 1158 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1159 int slot = SIISATA_NON_NCQ_SLOT; 1160 int s = splbio(); 1161 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1162 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1163 xfer->c_flags |= C_TIMEOU; 1164 xfer->c_intr(chp, xfer, slot); 1165 } 1166 splx(s); 1167 } 1168 1169 static int 1170 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1171 size_t count, int op) 1172 { 1173 1174 int error, seg; 1175 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1176 struct siisata_channel *schp = (struct siisata_channel *)chp; 1177 1178 struct siisata_prb *prbp; 1179 1180 prbp = schp->sch_prb[slot]; 1181 1182 if (data == NULL) { 1183 goto end; 1184 } 1185 1186 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1187 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1188 if (error) { 1189 log(LOG_ERR, "%s port %d: " 1190 "failed to load xfer in slot %d: error %d\n", 1191 SIISATANAME(sc), chp->ch_channel, slot, error); 1192 return error; 1193 } 1194 1195 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1196 schp->sch_datad[slot]->dm_mapsize, 1197 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1198 1199 /* make sure it's clean */ 1200 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1201 1202 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1203 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1204 DEBUG_FUNCS | DEBUG_DEBUG); 1205 1206 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1207 prbp->prb_sge[seg].sge_da = 1208 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1209 prbp->prb_sge[seg].sge_dc = 1210 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1211 prbp->prb_sge[seg].sge_flags = htole32(0); 1212 } 1213 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1214 end: 1215 return 0; 1216 } 1217 1218 static void 1219 siisata_activate_prb(struct siisata_channel *schp, int slot) 1220 { 1221 struct siisata_softc *sc; 1222 bus_size_t offset; 1223 bus_addr_t pprb; 1224 int port; 1225 1226 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1227 1228 KASSERTMSG(((schp->sch_active_slots & __BIT(slot)) == __BIT(slot)), 1229 ("%s: trying to activate active slot %d", SIISATANAME(sc), slot)); 1230 1231 port = schp->ata_channel.ch_channel; 1232 1233 offset = PRO_CARX(port, slot); 1234 1235 pprb = schp->sch_bus_prb[slot]; 1236 1237 1238 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1239 /* keep track of what's going on */ 1240 schp->sch_active_slots |= __BIT(slot); 1241 1242 1243 PRWRITE(sc, offset, pprb); 1244 offset += 4; 1245 #if 0 1246 if (sizeof(bus_addr_t) == 8) 1247 PRWRITE(sc, offset, (pprb >> 32)); 1248 else 1249 #endif 1250 PRWRITE(sc, offset, 0); 1251 } 1252 1253 static void 1254 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1255 { 1256 struct siisata_softc *sc; 1257 1258 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1259 1260 KASSERTMSG(((schp->sch_active_slots & __BIT(slot)) == 0), 1261 ("%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1262 slot)); 1263 1264 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1265 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1266 } 1267 1268 static void 1269 siisata_reinit_port(struct ata_channel *chp) 1270 { 1271 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1272 1273 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 1274 PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) | PR_PC_PORT_INITIALIZE); 1275 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 1276 DELAY(10); 1277 } 1278 1279 static void 1280 siisata_device_reset(struct ata_channel *chp) 1281 { 1282 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1283 1284 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 1285 PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) | PR_PC_DEVICE_RESET); 1286 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 1287 DELAY(10); 1288 } 1289 1290 1291 #if NATAPIBUS > 0 1292 void 1293 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1294 { 1295 struct ata_channel *chp = ata_sc->sc_chan; 1296 struct atac_softc *atac = chp->ch_atac; 1297 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1298 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1299 1300 /* 1301 * Fill in the scsipi_adapter. 1302 */ 1303 adapt->adapt_dev = atac->atac_dev; 1304 adapt->adapt_nchannels = atac->atac_nchannels; 1305 adapt->adapt_request = siisata_atapi_scsipi_request; 1306 adapt->adapt_minphys = siisata_atapi_minphys; 1307 atac->atac_atapi_adapter.atapi_probe_device = 1308 siisata_atapi_probe_device; 1309 1310 /* 1311 * Fill in the scsipi_channel. 1312 */ 1313 memset(chan, 0, sizeof(*chan)); 1314 chan->chan_adapter = adapt; 1315 chan->chan_bustype = &siisata_atapi_bustype; 1316 chan->chan_channel = chp->ch_channel; 1317 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1318 chan->chan_openings = 1; 1319 chan->chan_max_periph = 1; 1320 chan->chan_ntargets = 1; 1321 chan->chan_nluns = 1; 1322 1323 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1324 atapiprint); 1325 } 1326 1327 void 1328 siisata_atapi_minphys(struct buf *bp) 1329 { 1330 if (bp->b_bcount > MAXPHYS) 1331 bp->b_bcount = MAXPHYS; 1332 minphys(bp); 1333 } 1334 1335 /* 1336 * Kill off all pending xfers for a periph. 1337 * 1338 * Must be called at splbio(). 1339 */ 1340 void 1341 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1342 { 1343 struct atac_softc *atac = 1344 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1345 struct ata_channel *chp = 1346 atac->atac_channels[periph->periph_channel->chan_channel]; 1347 1348 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1349 } 1350 1351 void 1352 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1353 int reason) 1354 { 1355 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1356 1357 /* remove this command from xfer queue */ 1358 switch (reason) { 1359 case KILL_GONE: 1360 sc_xfer->error = XS_DRIVER_STUFFUP; 1361 break; 1362 case KILL_RESET: 1363 sc_xfer->error = XS_RESET; 1364 break; 1365 default: 1366 panic("%s: port %d: unknown reason %d", 1367 __func__, chp->ch_channel, reason); 1368 } 1369 ata_free_xfer(chp, xfer); 1370 scsipi_done(sc_xfer); 1371 } 1372 1373 void 1374 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1375 { 1376 struct scsipi_channel *chan = sc->sc_channel; 1377 struct scsipi_periph *periph; 1378 struct ataparams ids; 1379 struct ataparams *id = &ids; 1380 struct siisata_softc *siic = 1381 device_private(chan->chan_adapter->adapt_dev); 1382 struct atac_softc *atac = &siic->sc_atac; 1383 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1384 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1385 struct scsipibus_attach_args sa; 1386 char serial_number[21], model[41], firmware_revision[9]; 1387 int s; 1388 1389 /* skip if already attached */ 1390 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1391 return; 1392 1393 /* if no ATAPI device detected at attach time, skip */ 1394 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1395 SIISATA_DEBUG_PRINT(("%s: drive %d " 1396 "not present\n", __func__, target), DEBUG_PROBE); 1397 return; 1398 } 1399 1400 /* Some ATAPI devices need a bit more time after software reset. */ 1401 delay(5000); 1402 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1403 #ifdef ATAPI_DEBUG_PROBE 1404 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1405 device_xname(sc->sc_dev), target, 1406 id->atap_config & ATAPI_CFG_CMD_MASK, 1407 id->atap_config & ATAPI_CFG_DRQ_MASK); 1408 #endif 1409 periph = scsipi_alloc_periph(M_NOWAIT); 1410 if (periph == NULL) { 1411 aprint_error_dev(sc->sc_dev, 1412 "%s: unable to allocate periph for " 1413 "channel %d drive %d", __func__, 1414 chp->ch_channel, target); 1415 return; 1416 } 1417 periph->periph_dev = NULL; 1418 periph->periph_channel = chan; 1419 periph->periph_switch = &atapi_probe_periphsw; 1420 periph->periph_target = target; 1421 periph->periph_lun = 0; 1422 periph->periph_quirks = PQUIRK_ONLYBIG; 1423 1424 #ifdef SCSIPI_DEBUG 1425 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1426 SCSIPI_DEBUG_TARGET == target) 1427 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1428 #endif 1429 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1430 if (id->atap_config & ATAPI_CFG_REMOV) 1431 periph->periph_flags |= PERIPH_REMOVABLE; 1432 if (periph->periph_type == T_SEQUENTIAL) { 1433 s = splbio(); 1434 drvp->drive_flags |= DRIVE_ATAPIST; 1435 splx(s); 1436 } 1437 1438 sa.sa_periph = periph; 1439 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1440 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1441 T_REMOV : T_FIXED; 1442 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1443 scsipi_strvis((u_char *)serial_number, 20, 1444 id->atap_serial, 20); 1445 scsipi_strvis((u_char *)firmware_revision, 8, 1446 id->atap_revision, 8); 1447 sa.sa_inqbuf.vendor = model; 1448 sa.sa_inqbuf.product = serial_number; 1449 sa.sa_inqbuf.revision = firmware_revision; 1450 1451 /* 1452 * Determine the operating mode capabilities of the device. 1453 */ 1454 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1455 == ATAPI_CFG_CMD_16) { 1456 periph->periph_cap |= PERIPH_CAP_CMD16; 1457 1458 /* configure port for packet length */ 1459 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1460 PRREAD(siic, PRX(chp->ch_channel, PRO_PCS)) | 1461 PR_PC_PACKET_LENGTH); 1462 } 1463 /* XXX This is gross. */ 1464 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1465 1466 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1467 1468 if (drvp->drv_softc) 1469 ata_probe_caps(drvp); 1470 else { 1471 s = splbio(); 1472 drvp->drive_flags &= ~DRIVE_ATAPI; 1473 splx(s); 1474 } 1475 } else { 1476 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1477 "failed for drive %s:%d:%d: error 0x%x\n", 1478 __func__, SIISATANAME(siic), chp->ch_channel, target, 1479 chp->ch_error), DEBUG_PROBE); 1480 s = splbio(); 1481 drvp->drive_flags &= ~DRIVE_ATAPI; 1482 splx(s); 1483 } 1484 } 1485 1486 void 1487 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1488 scsipi_adapter_req_t req, void *arg) 1489 { 1490 struct scsipi_adapter *adapt = chan->chan_adapter; 1491 struct scsipi_periph *periph; 1492 struct scsipi_xfer *sc_xfer; 1493 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1494 struct atac_softc *atac = &sc->sc_atac; 1495 struct ata_xfer *xfer; 1496 int channel = chan->chan_channel; 1497 int drive, s; 1498 1499 switch (req) { 1500 case ADAPTER_REQ_RUN_XFER: 1501 sc_xfer = arg; 1502 periph = sc_xfer->xs_periph; 1503 drive = periph->periph_target; 1504 1505 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1506 device_xname(atac->atac_dev), channel, drive), 1507 DEBUG_XFERS); 1508 1509 if (!device_is_active(atac->atac_dev)) { 1510 sc_xfer->error = XS_DRIVER_STUFFUP; 1511 scsipi_done(sc_xfer); 1512 return; 1513 } 1514 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1515 if (xfer == NULL) { 1516 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1517 scsipi_done(sc_xfer); 1518 return; 1519 } 1520 1521 if (sc_xfer->xs_control & XS_CTL_POLL) 1522 xfer->c_flags |= C_POLL; 1523 xfer->c_drive = drive; 1524 xfer->c_flags |= C_ATAPI; 1525 xfer->c_cmd = sc_xfer; 1526 xfer->c_databuf = sc_xfer->data; 1527 xfer->c_bcount = sc_xfer->datalen; 1528 xfer->c_start = siisata_atapi_start; 1529 xfer->c_intr = siisata_atapi_complete; 1530 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1531 xfer->c_dscpoll = 0; 1532 s = splbio(); 1533 ata_exec_xfer(atac->atac_channels[channel], xfer); 1534 #ifdef DIAGNOSTIC 1535 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1536 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1537 panic("%s: polled command not done", __func__); 1538 #endif 1539 splx(s); 1540 return; 1541 1542 default: 1543 /* Not supported, nothing to do. */ 1544 ; 1545 } 1546 } 1547 1548 void 1549 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1550 { 1551 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1552 struct siisata_channel *schp = (struct siisata_channel *)chp; 1553 struct siisata_prb *prbp; 1554 1555 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1556 1557 int slot = SIISATA_NON_NCQ_SLOT; 1558 int i; 1559 uint8_t *fis; 1560 1561 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1562 SIISATANAME(sc), chp->ch_channel, 1563 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1564 DEBUG_XFERS); 1565 1566 prbp = schp->sch_prb[slot]; 1567 memset(prbp, 0, sizeof(struct siisata_prb)); 1568 fis = prbp->prb_fis; 1569 1570 /* fill in direction for ATAPI command */ 1571 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1572 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1573 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1574 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1575 1576 /* XXX probably needs to be some common FIS-related code */ 1577 fis[0] = 0x27; /* host to device */ 1578 fis[1] = 0x80; /* command FIS (and PMP) */ 1579 fis[2] = ATAPI_PKT_CMD; 1580 fis[3] = (xfer->c_flags & C_DMA) ? ATAPI_PKT_CMD_FTRE_DMA : 0; 1581 fis[7] = WDSD_IBM; 1582 fis[15] = WDCTL_4BIT; 1583 1584 /* copy over ATAPI command */ 1585 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1586 1587 if (siisata_dma_setup(chp, slot, 1588 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1589 xfer->c_databuf : NULL, 1590 xfer->c_bcount, 1591 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1592 BUS_DMA_READ : BUS_DMA_WRITE) 1593 ) 1594 panic("%s", __func__); 1595 1596 if (xfer->c_flags & C_POLL) { 1597 /* polled command, disable interrupts */ 1598 GRWRITE(sc, GR_GC, 1599 GRREAD(sc, GR_GC) & ~(GR_GC_PXIE(chp->ch_channel))); 1600 } 1601 1602 siisata_activate_prb(schp, slot); 1603 1604 if ((xfer->c_flags & C_POLL) == 0) { 1605 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1606 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1607 siisata_timeout, chp); 1608 goto out; 1609 } 1610 /* 1611 * polled command 1612 */ 1613 for (i = 0; i < ATA_DELAY / 10; i++) { 1614 if (sc_xfer->xs_status & XS_STS_DONE) 1615 break; 1616 siisata_intr_port(sc, schp); 1617 DELAY(10000); 1618 } 1619 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1620 sc_xfer->error = XS_TIMEOUT; 1621 siisata_atapi_complete(chp, xfer, slot); 1622 } 1623 /* reenable interrupts */ 1624 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1625 out: 1626 SIISATA_DEBUG_PRINT( 1627 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1628 return; 1629 } 1630 1631 int 1632 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1633 int slot) 1634 { 1635 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1636 struct siisata_channel *schp = (struct siisata_channel *)chp; 1637 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1638 uint8_t fis[4]; 1639 uint32_t *prbfis = (void *)fis; 1640 uint32_t pss, pis; 1641 1642 SIISATA_DEBUG_PRINT( 1643 ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1644 1645 if ((xfer->c_flags & C_TIMEOU) != 0) { 1646 sc_xfer->error = XS_TIMEOUT; 1647 siisata_atapi_reset(chp, xfer); 1648 return 1; 1649 } 1650 1651 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 1652 1653 if (pis & PR_PIS_CMDCMPL) { 1654 /* get slot status, clearing completion interrupt */ 1655 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 1656 /* is this expected? */ 1657 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 1658 log(LOG_WARNING, "%s: unexpected command " 1659 "completion on port %d slot %d\n", 1660 SIISATANAME(sc), chp->ch_channel, slot); 1661 return 0; 1662 } 1663 } 1664 1665 if (pis & PR_PIS_CMDERRR) { 1666 uint32_t ec; 1667 1668 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 1669 if (ec <= PR_PCE_DATAFISERROR) { 1670 if (ec != PR_PCE_DATAFISERROR) { 1671 /* read in specific information about error */ 1672 *prbfis = bus_space_read_stream_4( 1673 sc->sc_prt, sc->sc_prh, 1674 PRSX(chp->ch_channel, slot, PRSO_FIS)); 1675 if (ec == PR_PCE_DEVICEERROR) { 1676 /* error code 1 implies * 1677 * WDCS_ERR in fis[2] */ 1678 sc_xfer->error = XS_SHORTSENSE; 1679 sc_xfer->sense.atapi_sense = fis[3]; 1680 } 1681 } 1682 siisata_reinit_port(chp); 1683 } else { 1684 /* okay, we have a "Fatal Error" */ 1685 siisata_device_reset(chp); 1686 } 1687 } 1688 1689 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1690 siisata_atapi_done(chp, xfer, slot); 1691 return 1; 1692 } 1693 1694 void 1695 siisata_atapi_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1696 { 1697 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1698 struct siisata_channel *schp = (struct siisata_channel *)chp; 1699 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1700 1701 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d: flags 0x%x\n", __func__, 1702 device_xname(chp->ch_atac->atac_dev), 1703 chp->ch_channel, xfer->c_drive, 1704 (unsigned int)xfer->c_flags), DEBUG_XFERS); 1705 1706 /* this comamnd is not active any more */ 1707 schp->sch_active_slots &= ~__BIT(slot); 1708 1709 if (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 1710 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1711 schp->sch_datad[slot]->dm_mapsize, 1712 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1713 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1714 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1715 } 1716 1717 xfer->c_bcount -= sc_xfer->datalen; 1718 sc_xfer->resid = xfer->c_bcount; 1719 1720 if (xfer->c_bcount != 0) { 1721 SIISATA_DEBUG_PRINT(("%s: bcount value is " 1722 "%d after io\n", __func__, xfer->c_bcount), DEBUG_XFERS); 1723 } 1724 #ifdef DIAGNOSTIC 1725 if (xfer->c_bcount < 0) { 1726 log(LOG_WARNING, "%s(): bcount value " 1727 "is %d after io\n", __func__, xfer->c_bcount); 1728 } 1729 #endif 1730 1731 1732 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1733 siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); 1734 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1735 wakeup(&chp->ch_queue->active_xfer); 1736 return; 1737 } 1738 1739 /* vvv is this in the right order? ^^^ */ 1740 1741 callout_stop(&chp->ch_callout); 1742 chp->ch_queue->active_xfer = NULL; 1743 ata_free_xfer(chp, xfer); 1744 1745 SIISATA_DEBUG_PRINT(("%s: scsipi_done\n", __func__), DEBUG_XFERS); 1746 scsipi_done(sc_xfer); 1747 SIISATA_DEBUG_PRINT(("atastart from %s, flags 0x%x\n", __func__, 1748 chp->ch_flags), DEBUG_XFERS); 1749 atastart(chp); 1750 return; 1751 } 1752 1753 void 1754 siisata_atapi_reset(struct ata_channel *chp, struct ata_xfer *xfer) 1755 { 1756 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->c_drive]; 1757 drvp->state = 0; 1758 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1759 siisata_atapi_done(chp, xfer, SIISATA_NON_NCQ_SLOT); 1760 return; 1761 } 1762 #endif /* NATAPIBUS */ 1763
Indexes created Sun Sep 28 16:09:52 GMT 2025