siisata.c revision 1.22
1 /* $NetBSD: siisata.c,v 1.22 2012/07/31 15:50:34 bouyer Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.22 2012/07/31 15:50:34 bouyer Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/malloc.h> 86 #include <sys/param.h> 87 #include <sys/kernel.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 113 static void siisata_attach_port(struct siisata_softc *, int); 114 static void siisata_intr_port(struct siisata_channel *); 115 116 void siisata_probe_drive(struct ata_channel *); 117 void siisata_setup_channel(struct ata_channel *); 118 119 int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); 120 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 121 void siisata_reset_channel(struct ata_channel *, int); 122 int siisata_ata_addref(struct ata_drive_datas *); 123 void siisata_ata_delref(struct ata_drive_datas *); 124 void siisata_killpending(struct ata_drive_datas *); 125 126 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 127 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 128 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 129 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 130 131 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 132 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 133 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 134 int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); 135 136 void siisata_timeout(void *); 137 138 static void siisata_reinit_port(struct ata_channel *); 139 static void siisata_device_reset(struct ata_channel *); 140 static void siisata_activate_prb(struct siisata_channel *, int); 141 static void siisata_deactivate_prb(struct siisata_channel *, int); 142 static int siisata_dma_setup(struct ata_channel *chp, int slot, 143 void *data, size_t, int); 144 145 #if NATAPIBUS > 0 146 void siisata_atapibus_attach(struct atabus_softc *); 147 void siisata_atapi_probe_device(struct atapibus_softc *, int); 148 void siisata_atapi_minphys(struct buf *); 149 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 150 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 151 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 153 void siisata_atapi_scsipi_request(struct scsipi_channel *, 154 scsipi_adapter_req_t, void *); 155 void siisata_atapi_kill_pending(struct scsipi_periph *); 156 #endif /* NATAPIBUS */ 157 158 const struct ata_bustype siisata_ata_bustype = { 159 SCSIPI_BUSTYPE_ATA, 160 siisata_ata_bio, 161 siisata_reset_drive, 162 siisata_reset_channel, 163 siisata_exec_command, 164 ata_get_params, 165 siisata_ata_addref, 166 siisata_ata_delref, 167 siisata_killpending 168 }; 169 170 #if NATAPIBUS > 0 171 static const struct scsipi_bustype siisata_atapi_bustype = { 172 SCSIPI_BUSTYPE_ATAPI, 173 atapi_scsipi_cmd, 174 atapi_interpret_sense, 175 atapi_print_addr, 176 siisata_atapi_kill_pending, 177 NULL, 178 }; 179 #endif /* NATAPIBUS */ 180 181 182 void 183 siisata_attach(struct siisata_softc *sc) 184 { 185 int i; 186 187 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 188 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 189 190 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 191 sc->sc_atac.atac_pio_cap = 4; 192 sc->sc_atac.atac_dma_cap = 2; 193 sc->sc_atac.atac_udma_cap = 6; 194 sc->sc_atac.atac_channels = sc->sc_chanarray; 195 sc->sc_atac.atac_probe = siisata_probe_drive; 196 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 197 sc->sc_atac.atac_set_modes = siisata_setup_channel; 198 #if NATAPIBUS > 0 199 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 200 #endif 201 202 /* come out of reset state */ 203 GRWRITE(sc, GR_GC, 0); 204 205 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 206 siisata_attach_port(sc, i); 207 } 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 211 DEBUG_FUNCS); 212 return; 213 } 214 215 static void 216 siisata_disable_port_interrupt(struct ata_channel *chp) 217 { 218 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 219 220 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 221 } 222 223 static void 224 siisata_enable_port_interrupt(struct ata_channel *chp) 225 { 226 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 227 228 /* clear any interrupts */ 229 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 230 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 231 /* and enable CmdErrr+CmdCmpl interrupting */ 232 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 233 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 234 } 235 236 static void 237 siisata_init_port(struct siisata_softc *sc, int port) 238 { 239 struct siisata_channel *schp; 240 struct ata_channel *chp; 241 242 schp = &sc->sc_channels[port]; 243 chp = (struct ata_channel *)schp; 244 245 /* come out of reset, 64-bit activation */ 246 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 247 PR_PC_32BA | PR_PC_PORT_RESET); 248 /* initialize port */ 249 siisata_reinit_port(chp); 250 /* enable CmdErrr+CmdCmpl interrupting */ 251 siisata_enable_port_interrupt(chp); 252 /* enable port interrupt */ 253 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 254 } 255 256 static void 257 siisata_attach_port(struct siisata_softc *sc, int port) 258 { 259 int j; 260 int dmasize; 261 int error; 262 void *prbp; 263 struct siisata_channel *schp; 264 struct ata_channel *chp; 265 266 schp = &sc->sc_channels[port]; 267 chp = (struct ata_channel *)schp; 268 sc->sc_chanarray[port] = chp; 269 chp->ch_channel = port; 270 chp->ch_atac = &sc->sc_atac; 271 chp->ch_queue = malloc(sizeof(struct ata_queue), 272 M_DEVBUF, M_NOWAIT); 273 if (chp->ch_queue == NULL) { 274 aprint_error_dev(sc->sc_atac.atac_dev, 275 "port %d: can't allocate memory " 276 "for command queue\n", chp->ch_channel); 277 return; 278 } 279 280 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 281 282 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 283 __func__, dmasize), DEBUG_FUNCS); 284 285 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 286 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 287 if (error) { 288 aprint_error_dev(sc->sc_atac.atac_dev, 289 "unable to allocate PRB table memory, " 290 "error=%d\n", error); 291 return; 292 } 293 294 error = bus_dmamem_map(sc->sc_dmat, 295 &schp->sch_prb_seg, schp->sch_prb_nseg, 296 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 297 if (error) { 298 aprint_error_dev(sc->sc_atac.atac_dev, 299 "unable to map PRB table memory, " 300 "error=%d\n", error); 301 bus_dmamem_free(sc->sc_dmat, 302 &schp->sch_prb_seg, schp->sch_prb_nseg); 303 return; 304 } 305 306 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 307 BUS_DMA_NOWAIT, &schp->sch_prbd); 308 if (error) { 309 aprint_error_dev(sc->sc_atac.atac_dev, 310 "unable to create PRB table map, " 311 "error=%d\n", error); 312 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 313 bus_dmamem_free(sc->sc_dmat, 314 &schp->sch_prb_seg, schp->sch_prb_nseg); 315 return; 316 } 317 318 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 319 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 320 if (error) { 321 aprint_error_dev(sc->sc_atac.atac_dev, 322 "unable to load PRB table map, " 323 "error=%d\n", error); 324 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 325 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 326 bus_dmamem_free(sc->sc_dmat, 327 &schp->sch_prb_seg, schp->sch_prb_nseg); 328 return; 329 } 330 331 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 332 schp->sch_prb[j] = (struct siisata_prb *) 333 ((char *)prbp + SIISATA_CMD_SIZE * j); 334 schp->sch_bus_prb[j] = 335 schp->sch_prbd->dm_segs[0].ds_addr + 336 SIISATA_CMD_SIZE * j; 337 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 338 SIISATA_NSGE, MAXPHYS, 0, 339 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 340 &schp->sch_datad[j]); 341 if (error) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "couldn't create xfer DMA map, error=%d\n", 344 error); 345 return; 346 } 347 } 348 349 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 350 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 351 aprint_error_dev(sc->sc_atac.atac_dev, 352 "couldn't map port %d SStatus regs\n", 353 chp->ch_channel); 354 return; 355 } 356 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 357 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 358 aprint_error_dev(sc->sc_atac.atac_dev, 359 "couldn't map port %d SControl regs\n", 360 chp->ch_channel); 361 return; 362 } 363 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 364 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 365 aprint_error_dev(sc->sc_atac.atac_dev, 366 "couldn't map port %d SError regs\n", 367 chp->ch_channel); 368 return; 369 } 370 371 siisata_init_port(sc, port); 372 373 ata_channel_attach(chp); 374 375 return; 376 } 377 378 int 379 siisata_detach(struct siisata_softc *sc, int flags) 380 { 381 struct atac_softc *atac = &sc->sc_atac; 382 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 383 struct siisata_channel *schp; 384 struct ata_channel *chp; 385 int i, j, error; 386 387 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 388 schp = &sc->sc_channels[i]; 389 chp = sc->sc_chanarray[i]; 390 391 if (chp->atabus == NULL) 392 continue; 393 if ((error = config_detach(chp->atabus, flags)) != 0) 394 return error; 395 396 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 397 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 398 399 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 400 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 401 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 402 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 403 bus_dmamem_free(sc->sc_dmat, 404 &schp->sch_prb_seg, schp->sch_prb_nseg); 405 406 free(chp->ch_queue, M_DEVBUF); 407 chp->atabus = NULL; 408 } 409 410 if (adapt->adapt_refcnt != 0) 411 return EBUSY; 412 413 /* leave the chip in reset */ 414 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 415 416 return 0; 417 } 418 419 void 420 siisata_resume(struct siisata_softc *sc) 421 { 422 int i; 423 424 /* come out of reset state */ 425 GRWRITE(sc, GR_GC, 0); 426 427 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 428 siisata_init_port(sc, i); 429 } 430 431 } 432 433 int 434 siisata_intr(void *v) 435 { 436 struct siisata_softc *sc = v; 437 uint32_t is; 438 int i, r = 0; 439 while ((is = GRREAD(sc, GR_GIS))) { 440 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 441 SIISATANAME(sc), __func__, is), DEBUG_INTR); 442 r = 1; 443 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 444 if (is & GR_GIS_PXIS(i)) 445 siisata_intr_port(&sc->sc_channels[i]); 446 } 447 return r; 448 } 449 450 static void 451 siisata_intr_port(struct siisata_channel *schp) 452 { 453 struct siisata_softc *sc; 454 struct ata_channel *chp; 455 struct ata_xfer *xfer; 456 int slot; 457 uint32_t pss, pis; 458 uint32_t prbfis; 459 460 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 461 chp = &schp->ata_channel; 462 xfer = chp->ch_queue->active_xfer; 463 slot = SIISATA_NON_NCQ_SLOT; 464 465 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 466 467 SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x ", 468 SIISATANAME(sc), __func__, chp->ch_channel, pis), DEBUG_INTR); 469 470 if (pis & PR_PIS_CMDCMPL) { 471 /* get slot status, clearing completion interrupt */ 472 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 473 SIISATA_DEBUG_PRINT(("pss 0x%x\n", pss), DEBUG_INTR); 474 /* is this expected? */ 475 /* XXX improve */ 476 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 477 aprint_error( "%s: unexpected command " 478 "completion on port %d\n", 479 SIISATANAME(sc), chp->ch_channel); 480 return; 481 } 482 if ((~pss & __BIT(slot)) == 0) { 483 aprint_error( "%s: unknown slot " 484 "completion on port %d, pss 0x%x\n", 485 SIISATANAME(sc), chp->ch_channel, pss); 486 return; 487 } 488 } else if (pis & PR_PIS_CMDERRR) { 489 uint32_t ec; 490 491 /* emulate a CRC error by default */ 492 chp->ch_status = WDCS_ERR; 493 chp->ch_error = WDCE_CRC; 494 495 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 496 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 497 if (ec <= PR_PCE_DATAFISERROR) { 498 if (ec == PR_PCE_DEVICEERROR && xfer != NULL) { 499 /* read in specific information about error */ 500 prbfis = bus_space_read_stream_4( 501 sc->sc_prt, sc->sc_prh, 502 PRSX(chp->ch_channel, slot, PRSO_FIS)); 503 /* set ch_status and ch_error */ 504 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 505 } 506 siisata_reinit_port(chp); 507 } else { 508 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 509 " on channel %d (ctx 0x%x), resetting\n", 510 ec, chp->ch_channel, 511 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 512 /* okay, we have a "Fatal Error" */ 513 siisata_device_reset(chp); 514 } 515 } 516 517 /* clear some (ok, all) ints */ 518 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 519 if (xfer && xfer->c_intr) 520 xfer->c_intr(chp, xfer, slot); 521 522 return; 523 } 524 525 void 526 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 527 { 528 struct ata_channel *chp = drvp->chnl_softc; 529 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 530 struct siisata_channel *schp = (struct siisata_channel *)chp; 531 struct siisata_prb *prb; 532 int slot = SIISATA_NON_NCQ_SLOT; 533 int i; 534 535 /* wait for ready */ 536 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 537 DELAY(10); 538 539 prb = schp->sch_prb[slot]; 540 memset(prb, 0, sizeof(struct siisata_prb)); 541 prb->prb_control = 542 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 543 KASSERT(drvp->drive <= PMP_PORT_CTL); 544 prb->prb_fis[rhd_c] = drvp->drive; 545 546 siisata_activate_prb(schp, slot); 547 548 for(i = 0; i < 3100; i++) { 549 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 550 PR_PXSS(slot)) == 0) 551 break; 552 if (flags & AT_WAIT) 553 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 554 else 555 DELAY(10000); 556 } 557 558 siisata_deactivate_prb(schp, slot); 559 if (i == 3100) { 560 /* timeout */ 561 siisata_device_reset(chp); 562 if (sigp) 563 *sigp = 0xffffffff; 564 } else { 565 /* read the signature out of the FIS */ 566 if (sigp) { 567 *sigp = 0; 568 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 569 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 570 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, slot, 571 PRSO_FIS+0xc)) & 0xff; 572 } 573 } 574 575 #if 1 576 /* attempt to downgrade signaling in event of CRC error */ 577 /* XXX should be part of the MI (S)ATA subsystem */ 578 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 579 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 580 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 581 DELAY(10); 582 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 583 SControl_IPM_NONE | SControl_SPD_G1); 584 DELAY(10); 585 for (;;) { 586 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 587 & SStatus_DET_mask) == SStatus_DET_DEV) 588 break; 589 DELAY(10); 590 } 591 } 592 #endif 593 594 #if 1 595 chp->ch_status = 0; 596 chp->ch_error = 0; 597 #endif 598 return; 599 } 600 601 void 602 siisata_reset_channel(struct ata_channel *chp, int flags) 603 { 604 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 605 struct siisata_channel *schp = (struct siisata_channel *)chp; 606 607 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 608 DEBUG_FUNCS); 609 610 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 611 schp->sch_sstatus) != SStatus_DET_DEV) { 612 aprint_error("%s port %d: reset failed\n", 613 SIISATANAME(sc), chp->ch_channel); 614 /* XXX and then ? */ 615 } 616 /* wait for ready */ 617 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 618 DELAY(10); 619 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 620 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 621 if (chp->ch_queue->active_xfer) { 622 chp->ch_queue->active_xfer->c_kill_xfer(chp, 623 chp->ch_queue->active_xfer, KILL_RESET); 624 } 625 626 return; 627 } 628 629 int 630 siisata_ata_addref(struct ata_drive_datas *drvp) 631 { 632 return 0; 633 } 634 635 void 636 siisata_ata_delref(struct ata_drive_datas *drvp) 637 { 638 return; 639 } 640 641 void 642 siisata_killpending(struct ata_drive_datas *drvp) 643 { 644 return; 645 } 646 647 void 648 siisata_probe_drive(struct ata_channel *chp) 649 { 650 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 651 struct siisata_channel *schp = (struct siisata_channel *)chp; 652 int i; 653 uint32_t sig; 654 int slot = SIISATA_NON_NCQ_SLOT; 655 struct siisata_prb *prb; 656 bool timed_out; 657 658 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 659 __func__, chp->ch_channel), DEBUG_FUNCS); 660 661 /* 662 * disable port interrupt as we're polling for PHY up and 663 * prb completion 664 */ 665 siisata_disable_port_interrupt(chp); 666 667 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 668 schp->sch_sstatus)) { 669 case SStatus_DET_DEV: 670 /* clear any interrupts */ 671 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 672 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 673 /* wait for ready */ 674 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 675 & PR_PS_PORT_READY)) 676 DELAY(10); 677 prb = schp->sch_prb[slot]; 678 memset(prb, 0, sizeof(struct siisata_prb)); 679 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 680 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 681 682 siisata_activate_prb(schp, slot); 683 684 timed_out = 1; 685 for(i = 0; i < 3100; i++) { 686 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 687 PR_PXSS(slot)) == 0) { 688 /* prb completed */ 689 timed_out = 0; 690 break; 691 } 692 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 693 (PR_PIS_CMDERRR << 16)) { 694 /* we got an error; handle as timeout */ 695 break; 696 } 697 698 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 699 } 700 701 siisata_deactivate_prb(schp, slot); 702 if (timed_out) { 703 aprint_error_dev(sc->sc_atac.atac_dev, 704 "SOFT_RESET failed on port %d (error %d PSS 0x%x), " 705 "disabling\n", chp->ch_channel, 706 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 707 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); 708 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 709 PR_PC_PORT_RESET); 710 break; 711 } 712 713 /* read the signature out of the FIS */ 714 sig = 0; 715 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 716 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 717 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 718 PRSO_FIS+0xc)) & 0xff; 719 720 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 721 __func__, sig), DEBUG_PROBE); 722 723 if (sig == 0x96690101) 724 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 725 PR_PC_PMP_ENABLE); 726 sata_interpret_sig(chp, 0, sig); 727 break; 728 default: 729 break; 730 } 731 732 siisata_enable_port_interrupt(chp); 733 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 734 __func__, chp->ch_channel), DEBUG_PROBE); 735 return; 736 } 737 738 void 739 siisata_setup_channel(struct ata_channel *chp) 740 { 741 return; 742 } 743 744 int 745 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 746 { 747 struct ata_channel *chp = drvp->chnl_softc; 748 struct ata_xfer *xfer; 749 int ret; 750 int s; 751 752 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 753 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 754 DEBUG_FUNCS); 755 756 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? 757 ATAXF_CANSLEEP : ATAXF_NOSLEEP); 758 if (xfer == NULL) 759 return ATACMD_TRY_AGAIN; 760 if (ata_c->flags & AT_POLL) 761 xfer->c_flags |= C_POLL; 762 if (ata_c->flags & AT_WAIT) 763 xfer->c_flags |= C_WAIT; 764 xfer->c_drive = drvp->drive; 765 xfer->c_databuf = ata_c->data; 766 xfer->c_bcount = ata_c->bcount; 767 xfer->c_cmd = ata_c; 768 xfer->c_start = siisata_cmd_start; 769 xfer->c_intr = siisata_cmd_complete; 770 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 771 s = splbio(); 772 ata_exec_xfer(chp, xfer); 773 #ifdef DIAGNOSTIC 774 if ((ata_c->flags & AT_POLL) != 0 && 775 (ata_c->flags & AT_DONE) == 0) 776 panic("%s: polled command not done", __func__); 777 #endif 778 if (ata_c->flags & AT_DONE) { 779 ret = ATACMD_COMPLETE; 780 } else { 781 if (ata_c->flags & AT_WAIT) { 782 while ((ata_c->flags & AT_DONE) == 0) { 783 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 784 SIISATANAME( 785 (struct siisata_softc *)chp->ch_atac), 786 __func__), DEBUG_FUNCS); 787 tsleep(ata_c, PRIBIO, "siicmd", 0); 788 } 789 ret = ATACMD_COMPLETE; 790 } else { 791 ret = ATACMD_QUEUED; 792 } 793 } 794 splx(s); 795 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 796 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 797 DEBUG_FUNCS); 798 return ret; 799 } 800 801 void 802 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 803 { 804 struct siisata_channel *schp = (struct siisata_channel *)chp; 805 struct ata_command *ata_c = xfer->c_cmd; 806 int slot = SIISATA_NON_NCQ_SLOT; 807 struct siisata_prb *prb; 808 int i; 809 810 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 811 SIISATANAME((struct siisata_softc *)chp->ch_atac), 812 __func__, chp->ch_channel, xfer->c_drive, 813 ata_c->r_command, slot), 814 DEBUG_FUNCS|DEBUG_XFERS); 815 816 chp->ch_status = 0; 817 chp->ch_error = 0; 818 819 prb = schp->sch_prb[slot]; 820 memset(prb, 0, sizeof(struct siisata_prb)); 821 822 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 823 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 824 prb->prb_fis[rhd_c] |= xfer->c_drive; 825 826 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 827 828 if (siisata_dma_setup(chp, slot, 829 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 830 ata_c->bcount, 831 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 832 ata_c->flags |= AT_DF; 833 siisata_cmd_complete(chp, xfer, slot); 834 return; 835 } 836 837 if (xfer->c_flags & C_POLL) { 838 /* polled command, disable interrupts */ 839 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 840 siisata_disable_port_interrupt(chp); 841 } 842 843 /* go for it */ 844 siisata_activate_prb(schp, slot); 845 846 if ((ata_c->flags & AT_POLL) == 0) { 847 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 848 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 849 siisata_timeout, chp); 850 goto out; 851 } 852 853 /* 854 * polled command 855 */ 856 for (i = 0; i < ata_c->timeout / 10; i++) { 857 if (ata_c->flags & AT_DONE) 858 break; 859 siisata_intr_port(schp); 860 DELAY(1000); 861 } 862 863 if ((ata_c->flags & AT_DONE) == 0) { 864 siisata_timeout(chp); 865 } 866 867 /* reenable interrupts */ 868 siisata_enable_port_interrupt(chp); 869 out: 870 SIISATA_DEBUG_PRINT( 871 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 872 return; 873 } 874 875 void 876 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 877 int reason) 878 { 879 int slot = SIISATA_NON_NCQ_SLOT; 880 881 struct ata_command *ata_c = xfer->c_cmd; 882 switch (reason) { 883 case KILL_GONE: 884 ata_c->flags |= AT_GONE; 885 break; 886 case KILL_RESET: 887 ata_c->flags |= AT_RESET; 888 break; 889 default: 890 panic("%s: port %d: unknown reason %d", 891 __func__, chp->ch_channel, reason); 892 } 893 siisata_cmd_done(chp, xfer, slot); 894 } 895 896 int 897 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 898 { 899 struct ata_command *ata_c = xfer->c_cmd; 900 #ifdef SIISATA_DEBUG 901 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 902 #endif 903 904 SIISATA_DEBUG_PRINT( 905 ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS|DEBUG_XFERS); 906 907 chp->ch_flags &= ~ATACH_IRQ_WAIT; 908 if (xfer->c_flags & C_TIMEOU) 909 ata_c->flags |= AT_TIMEOU; 910 else 911 callout_stop(&chp->ch_callout); 912 913 if (chp->ch_status & WDCS_BSY) { 914 ata_c->flags |= AT_TIMEOU; 915 } else if (chp->ch_status & WDCS_ERR) { 916 ata_c->r_error = chp->ch_error; 917 ata_c->flags |= AT_ERROR; 918 } 919 920 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 921 siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); 922 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 923 wakeup(&chp->ch_queue->active_xfer); 924 return 0; 925 } else 926 siisata_cmd_done(chp, xfer, slot); 927 928 return 0; 929 } 930 931 void 932 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 933 { 934 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 935 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 936 struct siisata_channel *schp = (struct siisata_channel *)chp; 937 struct ata_command *ata_c = xfer->c_cmd; 938 uint16_t *idwordbuf; 939 int i; 940 941 SIISATA_DEBUG_PRINT( 942 ("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), __func__, 943 ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 944 945 siisata_deactivate_prb(schp, slot); 946 947 if (ata_c->flags & (AT_READ | AT_WRITE)) { 948 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 949 schp->sch_datad[slot]->dm_mapsize, 950 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 951 BUS_DMASYNC_POSTWRITE); 952 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 953 } 954 955 if (ata_c->flags & AT_READREG) { 956 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 957 PRSX(chp->ch_channel, slot, PRSO_FIS), 958 fis, __arraycount(fis)); 959 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 960 } 961 962 /* correct the endianess of IDENTIFY data */ 963 if (ata_c->r_command == WDCC_IDENTIFY || 964 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 965 idwordbuf = xfer->c_databuf; 966 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 967 idwordbuf[i] = le16toh(idwordbuf[i]); 968 } 969 } 970 971 ata_c->flags |= AT_DONE; 972 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 973 ata_c->flags |= AT_XFDONE; 974 975 chp->ch_queue->active_xfer = NULL; 976 ata_free_xfer(chp, xfer); 977 if (ata_c->flags & AT_WAIT) 978 wakeup(ata_c); 979 else if (ata_c->callback) 980 ata_c->callback(ata_c->callback_arg); 981 atastart(chp); 982 return; 983 } 984 985 int 986 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 987 { 988 struct ata_channel *chp = drvp->chnl_softc; 989 struct ata_xfer *xfer; 990 991 SIISATA_DEBUG_PRINT( ("%s: %s.\n", 992 SIISATANAME((struct siisata_softc *)chp->ch_atac), 993 __func__), DEBUG_FUNCS); 994 995 xfer = ata_get_xfer(ATAXF_NOSLEEP); 996 if (xfer == NULL) 997 return ATACMD_TRY_AGAIN; 998 if (ata_bio->flags & ATA_POLL) 999 xfer->c_flags |= C_POLL; 1000 xfer->c_drive = drvp->drive; 1001 xfer->c_cmd = ata_bio; 1002 xfer->c_databuf = ata_bio->databuf; 1003 xfer->c_bcount = ata_bio->bcount; 1004 xfer->c_start = siisata_bio_start; 1005 xfer->c_intr = siisata_bio_complete; 1006 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1007 ata_exec_xfer(chp, xfer); 1008 return (ata_bio->flags & ATA_ITSDONE) ? 1009 ATACMD_COMPLETE : ATACMD_QUEUED; 1010 } 1011 1012 void 1013 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1014 { 1015 struct siisata_channel *schp = (struct siisata_channel *)chp; 1016 struct siisata_prb *prb; 1017 struct ata_bio *ata_bio = xfer->c_cmd; 1018 int slot = SIISATA_NON_NCQ_SLOT; 1019 int i; 1020 1021 SIISATA_DEBUG_PRINT( 1022 ("%s: %s port %d, slot %d\n", 1023 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, chp->ch_channel, slot), 1024 DEBUG_FUNCS); 1025 1026 chp->ch_status = 0; 1027 chp->ch_error = 0; 1028 1029 prb = schp->sch_prb[slot]; 1030 memset(prb, 0, sizeof(struct siisata_prb)); 1031 1032 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1033 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1034 prb->prb_fis[rhd_c] |= xfer->c_drive; 1035 1036 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 1037 1038 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1039 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1040 ata_bio->error = ERR_DMA; 1041 ata_bio->r_error = 0; 1042 siisata_bio_complete(chp, xfer, slot); 1043 return; 1044 } 1045 1046 if (xfer->c_flags & C_POLL) { 1047 /* polled command, disable interrupts */ 1048 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1049 siisata_disable_port_interrupt(chp); 1050 } 1051 1052 siisata_activate_prb(schp, slot); 1053 1054 if ((ata_bio->flags & ATA_POLL) == 0) { 1055 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1056 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1057 siisata_timeout, chp); 1058 goto out; 1059 } 1060 1061 /* 1062 * polled command 1063 */ 1064 for (i = 0; i < ATA_DELAY / 10; i++) { 1065 if (ata_bio->flags & ATA_ITSDONE) 1066 break; 1067 siisata_intr_port(schp); 1068 DELAY(1000); 1069 } 1070 1071 siisata_enable_port_interrupt(chp); 1072 out: 1073 SIISATA_DEBUG_PRINT( 1074 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 1075 return; 1076 } 1077 1078 void 1079 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1080 int reason) 1081 { 1082 struct siisata_channel *schp = (struct siisata_channel *)chp; 1083 struct ata_bio *ata_bio = xfer->c_cmd; 1084 int drive = xfer->c_drive; 1085 int slot = SIISATA_NON_NCQ_SLOT; 1086 1087 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1088 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1089 __func__, chp->ch_channel), DEBUG_FUNCS); 1090 1091 siisata_deactivate_prb(schp, slot); 1092 1093 ata_free_xfer(chp, xfer); 1094 ata_bio->flags |= ATA_ITSDONE; 1095 switch (reason) { 1096 case KILL_GONE: 1097 ata_bio->error = ERR_NODEV; 1098 break; 1099 case KILL_RESET: 1100 ata_bio->error = ERR_RESET; 1101 break; 1102 default: 1103 panic("%s: port %d: unknown reason %d", 1104 __func__, chp->ch_channel, reason); 1105 } 1106 ata_bio->r_error = WDCE_ABRT; 1107 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1108 } 1109 1110 int 1111 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1112 { 1113 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1114 struct siisata_channel *schp = (struct siisata_channel *)chp; 1115 struct ata_bio *ata_bio = xfer->c_cmd; 1116 int drive = xfer->c_drive; 1117 1118 schp->sch_active_slots &= ~__BIT(slot); 1119 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1120 if (xfer->c_flags & C_TIMEOU) { 1121 ata_bio->error = TIMEOUT; 1122 } else { 1123 callout_stop(&chp->ch_callout); 1124 ata_bio->error = NOERROR; 1125 } 1126 1127 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1128 schp->sch_datad[slot]->dm_mapsize, 1129 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1130 BUS_DMASYNC_POSTWRITE); 1131 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1132 1133 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1134 siisata_bio_kill_xfer(chp, xfer, KILL_GONE); 1135 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1136 wakeup(&chp->ch_queue->active_xfer); 1137 return 0; 1138 } 1139 1140 chp->ch_queue->active_xfer = NULL; 1141 ata_free_xfer(chp, xfer); 1142 ata_bio->flags |= ATA_ITSDONE; 1143 if (chp->ch_status & WDCS_DWF) { 1144 ata_bio->error = ERR_DF; 1145 } else if (chp->ch_status & WDCS_ERR) { 1146 ata_bio->error = ERROR; 1147 ata_bio->r_error = chp->ch_error; 1148 } else if (chp->ch_status & WDCS_CORR) 1149 ata_bio->flags |= ATA_CORR; 1150 1151 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), 1152 __func__, ata_bio->bcount), DEBUG_XFERS); 1153 if (ata_bio->error == NOERROR) { 1154 if (ata_bio->flags & ATA_READ) 1155 ata_bio->bcount -= 1156 PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1157 else 1158 ata_bio->bcount = 0; 1159 } 1160 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1161 if (ata_bio->flags & ATA_POLL) 1162 return 1; 1163 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1164 atastart(chp); 1165 return 0; 1166 } 1167 1168 void 1169 siisata_timeout(void *v) 1170 { 1171 struct ata_channel *chp = (struct ata_channel *)v; 1172 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1173 int slot = SIISATA_NON_NCQ_SLOT; 1174 int s = splbio(); 1175 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1176 siisata_device_reset(chp); 1177 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1178 xfer->c_flags |= C_TIMEOU; 1179 xfer->c_intr(chp, xfer, slot); 1180 } 1181 splx(s); 1182 } 1183 1184 static int 1185 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1186 size_t count, int op) 1187 { 1188 1189 int error, seg; 1190 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1191 struct siisata_channel *schp = (struct siisata_channel *)chp; 1192 1193 struct siisata_prb *prbp; 1194 1195 prbp = schp->sch_prb[slot]; 1196 1197 if (data == NULL) { 1198 goto end; 1199 } 1200 1201 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1202 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1203 if (error) { 1204 aprint_error("%s port %d: " 1205 "failed to load xfer in slot %d: error %d\n", 1206 SIISATANAME(sc), chp->ch_channel, slot, error); 1207 return error; 1208 } 1209 1210 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1211 schp->sch_datad[slot]->dm_mapsize, 1212 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1213 1214 /* make sure it's clean */ 1215 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1216 1217 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1218 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1219 DEBUG_FUNCS | DEBUG_DEBUG); 1220 1221 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1222 prbp->prb_sge[seg].sge_da = 1223 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1224 prbp->prb_sge[seg].sge_dc = 1225 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1226 prbp->prb_sge[seg].sge_flags = htole32(0); 1227 } 1228 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1229 end: 1230 return 0; 1231 } 1232 1233 static void 1234 siisata_activate_prb(struct siisata_channel *schp, int slot) 1235 { 1236 struct siisata_softc *sc; 1237 bus_size_t offset; 1238 uint64_t pprb; 1239 1240 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1241 1242 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != __BIT(slot), 1243 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1244 1245 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1246 /* keep track of what's going on */ 1247 schp->sch_active_slots |= __BIT(slot); 1248 1249 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1250 1251 pprb = schp->sch_bus_prb[slot]; 1252 1253 PRWRITE(sc, offset + 0, pprb >> 0); 1254 PRWRITE(sc, offset + 4, pprb >> 32); 1255 } 1256 1257 static void 1258 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1259 { 1260 struct siisata_softc *sc; 1261 1262 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1263 1264 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1265 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1266 slot); 1267 1268 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1269 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1270 } 1271 1272 static void 1273 siisata_reinit_port(struct ata_channel *chp) 1274 { 1275 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1276 1277 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1278 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1279 DELAY(10); 1280 if (chp->ch_ndrives > 1) 1281 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1282 } 1283 1284 static void 1285 siisata_device_reset(struct ata_channel *chp) 1286 { 1287 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1288 1289 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1290 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1291 DELAY(10); 1292 } 1293 1294 1295 #if NATAPIBUS > 0 1296 void 1297 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1298 { 1299 struct ata_channel *chp = ata_sc->sc_chan; 1300 struct atac_softc *atac = chp->ch_atac; 1301 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1302 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1303 1304 /* 1305 * Fill in the scsipi_adapter. 1306 */ 1307 adapt->adapt_dev = atac->atac_dev; 1308 adapt->adapt_nchannels = atac->atac_nchannels; 1309 adapt->adapt_request = siisata_atapi_scsipi_request; 1310 adapt->adapt_minphys = siisata_atapi_minphys; 1311 atac->atac_atapi_adapter.atapi_probe_device = 1312 siisata_atapi_probe_device; 1313 1314 /* 1315 * Fill in the scsipi_channel. 1316 */ 1317 memset(chan, 0, sizeof(*chan)); 1318 chan->chan_adapter = adapt; 1319 chan->chan_bustype = &siisata_atapi_bustype; 1320 chan->chan_channel = chp->ch_channel; 1321 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1322 chan->chan_openings = 1; 1323 chan->chan_max_periph = 1; 1324 chan->chan_ntargets = 1; 1325 chan->chan_nluns = 1; 1326 1327 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1328 atapiprint); 1329 } 1330 1331 void 1332 siisata_atapi_minphys(struct buf *bp) 1333 { 1334 if (bp->b_bcount > MAXPHYS) 1335 bp->b_bcount = MAXPHYS; 1336 minphys(bp); 1337 } 1338 1339 /* 1340 * Kill off all pending xfers for a periph. 1341 * 1342 * Must be called at splbio(). 1343 */ 1344 void 1345 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1346 { 1347 struct atac_softc *atac = 1348 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1349 struct ata_channel *chp = 1350 atac->atac_channels[periph->periph_channel->chan_channel]; 1351 1352 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1353 } 1354 1355 void 1356 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1357 int reason) 1358 { 1359 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1360 1361 /* remove this command from xfer queue */ 1362 switch (reason) { 1363 case KILL_GONE: 1364 sc_xfer->error = XS_DRIVER_STUFFUP; 1365 break; 1366 case KILL_RESET: 1367 sc_xfer->error = XS_RESET; 1368 break; 1369 default: 1370 panic("%s: port %d: unknown reason %d", 1371 __func__, chp->ch_channel, reason); 1372 } 1373 ata_free_xfer(chp, xfer); 1374 scsipi_done(sc_xfer); 1375 } 1376 1377 void 1378 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1379 { 1380 struct scsipi_channel *chan = sc->sc_channel; 1381 struct scsipi_periph *periph; 1382 struct ataparams ids; 1383 struct ataparams *id = &ids; 1384 struct siisata_softc *siic = 1385 device_private(chan->chan_adapter->adapt_dev); 1386 struct atac_softc *atac = &siic->sc_atac; 1387 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1388 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1389 struct scsipibus_attach_args sa; 1390 char serial_number[21], model[41], firmware_revision[9]; 1391 int s; 1392 1393 /* skip if already attached */ 1394 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1395 return; 1396 1397 /* if no ATAPI device detected at attach time, skip */ 1398 if (drvp->drive_type == ATA_DRIVET_ATAPI) { 1399 SIISATA_DEBUG_PRINT(("%s: drive %d " 1400 "not present\n", __func__, target), DEBUG_PROBE); 1401 return; 1402 } 1403 1404 /* Some ATAPI devices need a bit more time after software reset. */ 1405 DELAY(5000); 1406 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1407 #ifdef ATAPI_DEBUG_PROBE 1408 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1409 device_xname(sc->sc_dev), target, 1410 id->atap_config & ATAPI_CFG_CMD_MASK, 1411 id->atap_config & ATAPI_CFG_DRQ_MASK); 1412 #endif 1413 periph = scsipi_alloc_periph(M_NOWAIT); 1414 if (periph == NULL) { 1415 aprint_error_dev(sc->sc_dev, 1416 "%s: unable to allocate periph for " 1417 "channel %d drive %d\n", __func__, 1418 chp->ch_channel, target); 1419 return; 1420 } 1421 periph->periph_dev = NULL; 1422 periph->periph_channel = chan; 1423 periph->periph_switch = &atapi_probe_periphsw; 1424 periph->periph_target = target; 1425 periph->periph_lun = 0; 1426 periph->periph_quirks = PQUIRK_ONLYBIG; 1427 1428 #ifdef SCSIPI_DEBUG 1429 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1430 SCSIPI_DEBUG_TARGET == target) 1431 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1432 #endif 1433 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1434 if (id->atap_config & ATAPI_CFG_REMOV) 1435 periph->periph_flags |= PERIPH_REMOVABLE; 1436 sa.sa_periph = periph; 1437 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1438 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1439 T_REMOV : T_FIXED; 1440 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1441 scsipi_strvis((u_char *)serial_number, 20, 1442 id->atap_serial, 20); 1443 scsipi_strvis((u_char *)firmware_revision, 8, 1444 id->atap_revision, 8); 1445 sa.sa_inqbuf.vendor = model; 1446 sa.sa_inqbuf.product = serial_number; 1447 sa.sa_inqbuf.revision = firmware_revision; 1448 1449 /* 1450 * Determine the operating mode capabilities of the device. 1451 */ 1452 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1453 == ATAPI_CFG_CMD_16) { 1454 periph->periph_cap |= PERIPH_CAP_CMD16; 1455 1456 /* configure port for packet length */ 1457 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1458 PR_PC_PACKET_LENGTH); 1459 } else { 1460 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1461 PR_PC_PACKET_LENGTH); 1462 } 1463 1464 /* XXX This is gross. */ 1465 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1466 1467 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1468 1469 if (drvp->drv_softc) 1470 ata_probe_caps(drvp); 1471 else { 1472 s = splbio(); 1473 drvp->drive_type &= ATA_DRIVET_NONE; 1474 splx(s); 1475 } 1476 } else { 1477 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1478 "failed for drive %s:%d:%d: error 0x%x\n", 1479 __func__, SIISATANAME(siic), chp->ch_channel, target, 1480 chp->ch_error), DEBUG_PROBE); 1481 s = splbio(); 1482 drvp->drive_type &= ATA_DRIVET_NONE; 1483 splx(s); 1484 } 1485 } 1486 1487 void 1488 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1489 scsipi_adapter_req_t req, void *arg) 1490 { 1491 struct scsipi_adapter *adapt = chan->chan_adapter; 1492 struct scsipi_periph *periph; 1493 struct scsipi_xfer *sc_xfer; 1494 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1495 struct atac_softc *atac = &sc->sc_atac; 1496 struct ata_xfer *xfer; 1497 int channel = chan->chan_channel; 1498 int drive, s; 1499 1500 switch (req) { 1501 case ADAPTER_REQ_RUN_XFER: 1502 sc_xfer = arg; 1503 periph = sc_xfer->xs_periph; 1504 drive = periph->periph_target; 1505 1506 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1507 device_xname(atac->atac_dev), channel, drive), 1508 DEBUG_XFERS); 1509 1510 if (!device_is_active(atac->atac_dev)) { 1511 sc_xfer->error = XS_DRIVER_STUFFUP; 1512 scsipi_done(sc_xfer); 1513 return; 1514 } 1515 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1516 if (xfer == NULL) { 1517 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1518 scsipi_done(sc_xfer); 1519 return; 1520 } 1521 1522 if (sc_xfer->xs_control & XS_CTL_POLL) 1523 xfer->c_flags |= C_POLL; 1524 xfer->c_drive = drive; 1525 xfer->c_flags |= C_ATAPI; 1526 xfer->c_cmd = sc_xfer; 1527 xfer->c_databuf = sc_xfer->data; 1528 xfer->c_bcount = sc_xfer->datalen; 1529 xfer->c_start = siisata_atapi_start; 1530 xfer->c_intr = siisata_atapi_complete; 1531 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1532 xfer->c_dscpoll = 0; 1533 s = splbio(); 1534 ata_exec_xfer(atac->atac_channels[channel], xfer); 1535 #ifdef DIAGNOSTIC 1536 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1537 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1538 panic("%s: polled command not done", __func__); 1539 #endif 1540 splx(s); 1541 return; 1542 1543 default: 1544 /* Not supported, nothing to do. */ 1545 ; 1546 } 1547 } 1548 1549 void 1550 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1551 { 1552 struct siisata_channel *schp = (struct siisata_channel *)chp; 1553 struct siisata_prb *prbp; 1554 1555 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1556 1557 int slot = SIISATA_NON_NCQ_SLOT; 1558 int i; 1559 1560 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1561 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1562 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1563 DEBUG_XFERS); 1564 1565 chp->ch_status = 0; 1566 chp->ch_error = 0; 1567 1568 prbp = schp->sch_prb[slot]; 1569 memset(prbp, 0, sizeof(struct siisata_prb)); 1570 1571 1572 /* fill in direction for ATAPI command */ 1573 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1574 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1575 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1576 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1577 1578 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1579 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1580 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1581 1582 /* copy over ATAPI command */ 1583 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1584 1585 if (siisata_dma_setup(chp, slot, 1586 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1587 xfer->c_databuf : NULL, 1588 xfer->c_bcount, 1589 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1590 BUS_DMA_READ : BUS_DMA_WRITE) 1591 ) 1592 panic("%s", __func__); 1593 1594 if (xfer->c_flags & C_POLL) { 1595 /* polled command, disable interrupts */ 1596 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1597 siisata_disable_port_interrupt(chp); 1598 } 1599 1600 siisata_activate_prb(schp, slot); 1601 1602 if ((xfer->c_flags & C_POLL) == 0) { 1603 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1604 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1605 siisata_timeout, chp); 1606 goto out; 1607 } 1608 1609 /* 1610 * polled command 1611 */ 1612 for (i = 0; i < ATA_DELAY / 10; i++) { 1613 if (sc_xfer->xs_status & XS_STS_DONE) 1614 break; 1615 siisata_intr_port(schp); 1616 DELAY(1000); 1617 } 1618 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1619 siisata_timeout(chp); 1620 } 1621 /* reenable interrupts */ 1622 siisata_enable_port_interrupt(chp); 1623 out: 1624 SIISATA_DEBUG_PRINT( 1625 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 1626 return; 1627 } 1628 1629 int 1630 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1631 int slot) 1632 { 1633 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1634 struct siisata_channel *schp = (struct siisata_channel *)chp; 1635 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1636 1637 SIISATA_DEBUG_PRINT( 1638 ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1639 1640 /* this comamnd is not active any more */ 1641 schp->sch_active_slots &= ~__BIT(slot); 1642 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1643 if (xfer->c_flags & C_TIMEOU) { 1644 sc_xfer->error = XS_TIMEOUT; 1645 } else { 1646 callout_stop(&chp->ch_callout); 1647 sc_xfer->error = XS_NOERROR; 1648 } 1649 1650 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1651 schp->sch_datad[slot]->dm_mapsize, 1652 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1653 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1654 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1655 1656 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1657 siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); 1658 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1659 wakeup(&chp->ch_queue->active_xfer); 1660 return 0; /* XXX verify */ 1661 } 1662 1663 chp->ch_queue->active_xfer = NULL; 1664 ata_free_xfer(chp, xfer); 1665 sc_xfer->resid = sc_xfer->datalen; 1666 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1667 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1668 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1669 if ((chp->ch_status & WDCS_ERR) && 1670 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1671 sc_xfer->resid == sc_xfer->datalen)) { 1672 sc_xfer->error = XS_SHORTSENSE; 1673 sc_xfer->sense.atapi_sense = chp->ch_error; 1674 if ((sc_xfer->xs_periph->periph_quirks & 1675 PQUIRK_NOSENSE) == 0) { 1676 /* request sense */ 1677 sc_xfer->error = XS_BUSY; 1678 sc_xfer->status = SCSI_CHECK; 1679 } 1680 } 1681 scsipi_done(sc_xfer); 1682 atastart(chp); 1683 return 0; /* XXX verify */ 1684 } 1685 1686 #endif /* NATAPIBUS */ 1687
Indexes created Fri Sep 26 20:09:58 GMT 2025