siisata.c revision 1.27.6.3
1 /* $NetBSD: siisata.c,v 1.27.6.3 2017/02/05 13:40:28 skrll Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.27.6.3 2017/02/05 13:40:28 skrll Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/malloc.h> 86 #include <sys/param.h> 87 #include <sys/kernel.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 113 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 114 #if _BYTE_ORDER == _LITTLE_ENDIAN 115 #define bus_space_read_stream_4 bus_space_read_4 116 #define bus_space_read_region_stream_4 bus_space_read_region_4 117 #else 118 static inline uint32_t 119 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 120 { 121 return htole32(bus_space_read_4(t, h, o)); 122 } 123 124 static inline void 125 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint32_t *p, bus_size_t c) 126 { 127 bus_space_read_region_4(t, h, o, p, c); 128 for (bus_size_t i = 0; i < c; i++) { 129 p[i] = htole32(p[i]); 130 } 131 } 132 #endif 133 #endif 134 135 static void siisata_attach_port(struct siisata_softc *, int); 136 static void siisata_intr_port(struct siisata_channel *); 137 138 void siisata_probe_drive(struct ata_channel *); 139 void siisata_setup_channel(struct ata_channel *); 140 141 int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); 142 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 143 void siisata_reset_channel(struct ata_channel *, int); 144 int siisata_ata_addref(struct ata_drive_datas *); 145 void siisata_ata_delref(struct ata_drive_datas *); 146 void siisata_killpending(struct ata_drive_datas *); 147 148 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 149 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 150 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 151 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 152 153 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 154 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 155 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 156 int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); 157 158 void siisata_timeout(void *); 159 160 static void siisata_reinit_port(struct ata_channel *); 161 static void siisata_device_reset(struct ata_channel *); 162 static void siisata_activate_prb(struct siisata_channel *, int); 163 static void siisata_deactivate_prb(struct siisata_channel *, int); 164 static int siisata_dma_setup(struct ata_channel *chp, int slot, 165 void *data, size_t, int); 166 167 #if NATAPIBUS > 0 168 void siisata_atapibus_attach(struct atabus_softc *); 169 void siisata_atapi_probe_device(struct atapibus_softc *, int); 170 void siisata_atapi_minphys(struct buf *); 171 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 172 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 173 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 174 void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 175 void siisata_atapi_scsipi_request(struct scsipi_channel *, 176 scsipi_adapter_req_t, void *); 177 void siisata_atapi_kill_pending(struct scsipi_periph *); 178 #endif /* NATAPIBUS */ 179 180 const struct ata_bustype siisata_ata_bustype = { 181 SCSIPI_BUSTYPE_ATA, 182 siisata_ata_bio, 183 siisata_reset_drive, 184 siisata_reset_channel, 185 siisata_exec_command, 186 ata_get_params, 187 siisata_ata_addref, 188 siisata_ata_delref, 189 siisata_killpending 190 }; 191 192 #if NATAPIBUS > 0 193 static const struct scsipi_bustype siisata_atapi_bustype = { 194 SCSIPI_BUSTYPE_ATAPI, 195 atapi_scsipi_cmd, 196 atapi_interpret_sense, 197 atapi_print_addr, 198 siisata_atapi_kill_pending, 199 NULL, 200 }; 201 #endif /* NATAPIBUS */ 202 203 204 void 205 siisata_attach(struct siisata_softc *sc) 206 { 207 int i; 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 211 212 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 213 sc->sc_atac.atac_pio_cap = 4; 214 sc->sc_atac.atac_dma_cap = 2; 215 sc->sc_atac.atac_udma_cap = 6; 216 sc->sc_atac.atac_channels = sc->sc_chanarray; 217 sc->sc_atac.atac_probe = siisata_probe_drive; 218 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 219 sc->sc_atac.atac_set_modes = siisata_setup_channel; 220 #if NATAPIBUS > 0 221 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 222 #endif 223 224 /* come out of reset state */ 225 GRWRITE(sc, GR_GC, 0); 226 227 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 228 siisata_attach_port(sc, i); 229 } 230 231 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 232 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 233 DEBUG_FUNCS); 234 return; 235 } 236 237 static void 238 siisata_disable_port_interrupt(struct ata_channel *chp) 239 { 240 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 241 242 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 243 } 244 245 static void 246 siisata_enable_port_interrupt(struct ata_channel *chp) 247 { 248 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 249 250 /* clear any interrupts */ 251 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 252 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 253 /* and enable CmdErrr+CmdCmpl interrupting */ 254 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 255 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 256 } 257 258 static void 259 siisata_init_port(struct siisata_softc *sc, int port) 260 { 261 struct siisata_channel *schp; 262 struct ata_channel *chp; 263 264 schp = &sc->sc_channels[port]; 265 chp = (struct ata_channel *)schp; 266 267 /* come out of reset, 64-bit activation */ 268 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 269 PR_PC_32BA | PR_PC_PORT_RESET); 270 /* initialize port */ 271 siisata_reinit_port(chp); 272 /* enable CmdErrr+CmdCmpl interrupting */ 273 siisata_enable_port_interrupt(chp); 274 /* enable port interrupt */ 275 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 276 } 277 278 static void 279 siisata_attach_port(struct siisata_softc *sc, int port) 280 { 281 int j; 282 int dmasize; 283 int error; 284 void *prbp; 285 struct siisata_channel *schp; 286 struct ata_channel *chp; 287 288 schp = &sc->sc_channels[port]; 289 chp = (struct ata_channel *)schp; 290 sc->sc_chanarray[port] = chp; 291 chp->ch_channel = port; 292 chp->ch_atac = &sc->sc_atac; 293 chp->ch_queue = malloc(sizeof(struct ata_queue), 294 M_DEVBUF, M_NOWAIT|M_ZERO); 295 if (chp->ch_queue == NULL) { 296 aprint_error_dev(sc->sc_atac.atac_dev, 297 "port %d: can't allocate memory " 298 "for command queue\n", chp->ch_channel); 299 return; 300 } 301 302 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 303 304 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 305 __func__, dmasize), DEBUG_FUNCS); 306 307 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 308 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 309 if (error) { 310 aprint_error_dev(sc->sc_atac.atac_dev, 311 "unable to allocate PRB table memory, " 312 "error=%d\n", error); 313 return; 314 } 315 316 error = bus_dmamem_map(sc->sc_dmat, 317 &schp->sch_prb_seg, schp->sch_prb_nseg, 318 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 319 if (error) { 320 aprint_error_dev(sc->sc_atac.atac_dev, 321 "unable to map PRB table memory, " 322 "error=%d\n", error); 323 bus_dmamem_free(sc->sc_dmat, 324 &schp->sch_prb_seg, schp->sch_prb_nseg); 325 return; 326 } 327 328 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 329 BUS_DMA_NOWAIT, &schp->sch_prbd); 330 if (error) { 331 aprint_error_dev(sc->sc_atac.atac_dev, 332 "unable to create PRB table map, " 333 "error=%d\n", error); 334 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 335 bus_dmamem_free(sc->sc_dmat, 336 &schp->sch_prb_seg, schp->sch_prb_nseg); 337 return; 338 } 339 340 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 341 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 342 if (error) { 343 aprint_error_dev(sc->sc_atac.atac_dev, 344 "unable to load PRB table map, " 345 "error=%d\n", error); 346 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 347 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 348 bus_dmamem_free(sc->sc_dmat, 349 &schp->sch_prb_seg, schp->sch_prb_nseg); 350 return; 351 } 352 353 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 354 schp->sch_prb[j] = (struct siisata_prb *) 355 ((char *)prbp + SIISATA_CMD_SIZE * j); 356 schp->sch_bus_prb[j] = 357 schp->sch_prbd->dm_segs[0].ds_addr + 358 SIISATA_CMD_SIZE * j; 359 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 360 SIISATA_NSGE, MAXPHYS, 0, 361 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 362 &schp->sch_datad[j]); 363 if (error) { 364 aprint_error_dev(sc->sc_atac.atac_dev, 365 "couldn't create xfer DMA map, error=%d\n", 366 error); 367 return; 368 } 369 } 370 371 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 372 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 373 aprint_error_dev(sc->sc_atac.atac_dev, 374 "couldn't map port %d SStatus regs\n", 375 chp->ch_channel); 376 return; 377 } 378 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 379 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 380 aprint_error_dev(sc->sc_atac.atac_dev, 381 "couldn't map port %d SControl regs\n", 382 chp->ch_channel); 383 return; 384 } 385 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 386 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 387 aprint_error_dev(sc->sc_atac.atac_dev, 388 "couldn't map port %d SError regs\n", 389 chp->ch_channel); 390 return; 391 } 392 393 siisata_init_port(sc, port); 394 395 ata_channel_attach(chp); 396 397 return; 398 } 399 400 int 401 siisata_detach(struct siisata_softc *sc, int flags) 402 { 403 struct atac_softc *atac = &sc->sc_atac; 404 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 405 struct siisata_channel *schp; 406 struct ata_channel *chp; 407 int i, j, error; 408 409 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 410 schp = &sc->sc_channels[i]; 411 chp = sc->sc_chanarray[i]; 412 413 if (chp->atabus == NULL) 414 continue; 415 if ((error = config_detach(chp->atabus, flags)) != 0) 416 return error; 417 418 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 419 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 420 421 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 422 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 423 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 424 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 425 bus_dmamem_free(sc->sc_dmat, 426 &schp->sch_prb_seg, schp->sch_prb_nseg); 427 428 free(chp->ch_queue, M_DEVBUF); 429 chp->atabus = NULL; 430 } 431 432 if (adapt->adapt_refcnt != 0) 433 return EBUSY; 434 435 /* leave the chip in reset */ 436 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 437 438 return 0; 439 } 440 441 void 442 siisata_resume(struct siisata_softc *sc) 443 { 444 int i; 445 446 /* come out of reset state */ 447 GRWRITE(sc, GR_GC, 0); 448 449 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 450 siisata_init_port(sc, i); 451 } 452 453 } 454 455 int 456 siisata_intr(void *v) 457 { 458 struct siisata_softc *sc = v; 459 uint32_t is; 460 int i, r = 0; 461 while ((is = GRREAD(sc, GR_GIS))) { 462 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 463 SIISATANAME(sc), __func__, is), DEBUG_INTR); 464 r = 1; 465 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 466 if (is & GR_GIS_PXIS(i)) 467 siisata_intr_port(&sc->sc_channels[i]); 468 } 469 return r; 470 } 471 472 static void 473 siisata_intr_port(struct siisata_channel *schp) 474 { 475 struct siisata_softc *sc; 476 struct ata_channel *chp; 477 struct ata_xfer *xfer; 478 int slot; 479 uint32_t pss, pis; 480 uint32_t prbfis; 481 482 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 483 chp = &schp->ata_channel; 484 xfer = chp->ch_queue->active_xfer; 485 slot = SIISATA_NON_NCQ_SLOT; 486 487 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 488 489 SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x ", 490 SIISATANAME(sc), __func__, chp->ch_channel, pis), DEBUG_INTR); 491 492 if (pis & PR_PIS_CMDCMPL) { 493 /* get slot status, clearing completion interrupt */ 494 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 495 SIISATA_DEBUG_PRINT(("pss 0x%x\n", pss), DEBUG_INTR); 496 /* is this expected? */ 497 /* XXX improve */ 498 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 499 aprint_error( "%s: unexpected command " 500 "completion on port %d\n", 501 SIISATANAME(sc), chp->ch_channel); 502 return; 503 } 504 if ((~pss & __BIT(slot)) == 0) { 505 aprint_error( "%s: unknown slot " 506 "completion on port %d, pss 0x%x\n", 507 SIISATANAME(sc), chp->ch_channel, pss); 508 return; 509 } 510 } else if (pis & PR_PIS_CMDERRR) { 511 uint32_t ec; 512 513 /* emulate a CRC error by default */ 514 chp->ch_status = WDCS_ERR; 515 chp->ch_error = WDCE_CRC; 516 517 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 518 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 519 if (ec <= PR_PCE_DATAFISERROR) { 520 if (ec == PR_PCE_DEVICEERROR && xfer != NULL) { 521 /* read in specific information about error */ 522 prbfis = bus_space_read_stream_4( 523 sc->sc_prt, sc->sc_prh, 524 PRSX(chp->ch_channel, slot, PRSO_FIS)); 525 /* set ch_status and ch_error */ 526 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 527 } 528 siisata_reinit_port(chp); 529 } else { 530 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 531 " on channel %d (ctx 0x%x), resetting\n", 532 ec, chp->ch_channel, 533 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 534 /* okay, we have a "Fatal Error" */ 535 siisata_device_reset(chp); 536 } 537 } 538 539 /* clear some (ok, all) ints */ 540 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 541 if (xfer && xfer->c_intr) 542 xfer->c_intr(chp, xfer, slot); 543 544 return; 545 } 546 547 void 548 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 549 { 550 struct ata_channel *chp = drvp->chnl_softc; 551 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 552 struct siisata_channel *schp = (struct siisata_channel *)chp; 553 struct siisata_prb *prb; 554 int slot = SIISATA_NON_NCQ_SLOT; 555 int i; 556 557 /* wait for ready */ 558 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 559 DELAY(10); 560 561 prb = schp->sch_prb[slot]; 562 memset(prb, 0, sizeof(struct siisata_prb)); 563 prb->prb_control = 564 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 565 KASSERT(drvp->drive <= PMP_PORT_CTL); 566 prb->prb_fis[rhd_c] = drvp->drive; 567 568 siisata_activate_prb(schp, slot); 569 570 for(i = 0; i < 3100; i++) { 571 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 572 PR_PXSS(slot)) == 0) 573 break; 574 if (flags & AT_WAIT) 575 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 576 else 577 DELAY(10000); 578 } 579 580 siisata_deactivate_prb(schp, slot); 581 if (i == 3100) { 582 /* timeout */ 583 siisata_device_reset(chp); 584 if (sigp) 585 *sigp = 0xffffffff; 586 } else { 587 /* read the signature out of the FIS */ 588 if (sigp) { 589 *sigp = 0; 590 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 591 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 592 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, slot, 593 PRSO_FIS+0xc)) & 0xff; 594 } 595 } 596 597 #if 1 598 /* attempt to downgrade signaling in event of CRC error */ 599 /* XXX should be part of the MI (S)ATA subsystem */ 600 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 601 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 602 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 603 DELAY(10); 604 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 605 SControl_IPM_NONE | SControl_SPD_G1); 606 DELAY(10); 607 for (;;) { 608 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 609 & SStatus_DET_mask) == SStatus_DET_DEV) 610 break; 611 DELAY(10); 612 } 613 } 614 #endif 615 616 #if 1 617 chp->ch_status = 0; 618 chp->ch_error = 0; 619 #endif 620 return; 621 } 622 623 void 624 siisata_reset_channel(struct ata_channel *chp, int flags) 625 { 626 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 627 struct siisata_channel *schp = (struct siisata_channel *)chp; 628 629 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 630 DEBUG_FUNCS); 631 632 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 633 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 634 aprint_error("%s port %d: reset failed\n", 635 SIISATANAME(sc), chp->ch_channel); 636 /* XXX and then ? */ 637 } 638 /* wait for ready */ 639 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 640 DELAY(10); 641 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 642 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 643 if (chp->ch_queue->active_xfer) { 644 chp->ch_queue->active_xfer->c_kill_xfer(chp, 645 chp->ch_queue->active_xfer, KILL_RESET); 646 } 647 648 return; 649 } 650 651 int 652 siisata_ata_addref(struct ata_drive_datas *drvp) 653 { 654 return 0; 655 } 656 657 void 658 siisata_ata_delref(struct ata_drive_datas *drvp) 659 { 660 return; 661 } 662 663 void 664 siisata_killpending(struct ata_drive_datas *drvp) 665 { 666 return; 667 } 668 669 void 670 siisata_probe_drive(struct ata_channel *chp) 671 { 672 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 673 struct siisata_channel *schp = (struct siisata_channel *)chp; 674 int i; 675 uint32_t sig; 676 int slot = SIISATA_NON_NCQ_SLOT; 677 struct siisata_prb *prb; 678 bool timed_out; 679 680 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 681 __func__, chp->ch_channel), DEBUG_FUNCS); 682 683 /* 684 * disable port interrupt as we're polling for PHY up and 685 * prb completion 686 */ 687 siisata_disable_port_interrupt(chp); 688 689 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 690 schp->sch_sstatus, AT_WAIT)) { 691 case SStatus_DET_DEV: 692 /* clear any interrupts */ 693 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 694 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 695 /* wait for ready */ 696 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 697 & PR_PS_PORT_READY)) 698 DELAY(10); 699 prb = schp->sch_prb[slot]; 700 memset(prb, 0, sizeof(struct siisata_prb)); 701 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 702 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 703 704 siisata_activate_prb(schp, slot); 705 706 timed_out = 1; 707 for(i = 0; i < 3100; i++) { 708 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 709 PR_PXSS(slot)) == 0) { 710 /* prb completed */ 711 timed_out = 0; 712 break; 713 } 714 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 715 (PR_PIS_CMDERRR << 16)) { 716 /* we got an error; handle as timeout */ 717 break; 718 } 719 720 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 721 } 722 723 siisata_deactivate_prb(schp, slot); 724 if (timed_out) { 725 aprint_error_dev(sc->sc_atac.atac_dev, 726 "SOFT_RESET failed on port %d (error %d PSS 0x%x), " 727 "resetting\n", chp->ch_channel, 728 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 729 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); 730 siisata_reinit_port(chp); 731 break; 732 } 733 734 /* read the signature out of the FIS */ 735 sig = 0; 736 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 737 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 738 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 739 PRSO_FIS+0xc)) & 0xff; 740 741 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 742 __func__, sig), DEBUG_PROBE); 743 744 if (sig == 0x96690101) 745 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 746 PR_PC_PMP_ENABLE); 747 sata_interpret_sig(chp, 0, sig); 748 break; 749 default: 750 break; 751 } 752 753 siisata_enable_port_interrupt(chp); 754 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 755 __func__, chp->ch_channel), DEBUG_PROBE); 756 return; 757 } 758 759 void 760 siisata_setup_channel(struct ata_channel *chp) 761 { 762 return; 763 } 764 765 int 766 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 767 { 768 struct ata_channel *chp = drvp->chnl_softc; 769 struct ata_xfer *xfer; 770 int ret; 771 int s; 772 773 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 774 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 775 DEBUG_FUNCS); 776 777 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? 778 ATAXF_CANSLEEP : ATAXF_NOSLEEP); 779 if (xfer == NULL) 780 return ATACMD_TRY_AGAIN; 781 if (ata_c->flags & AT_POLL) 782 xfer->c_flags |= C_POLL; 783 if (ata_c->flags & AT_WAIT) 784 xfer->c_flags |= C_WAIT; 785 xfer->c_drive = drvp->drive; 786 xfer->c_databuf = ata_c->data; 787 xfer->c_bcount = ata_c->bcount; 788 xfer->c_cmd = ata_c; 789 xfer->c_start = siisata_cmd_start; 790 xfer->c_intr = siisata_cmd_complete; 791 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 792 s = splbio(); 793 ata_exec_xfer(chp, xfer); 794 #ifdef DIAGNOSTIC 795 if ((ata_c->flags & AT_POLL) != 0 && 796 (ata_c->flags & AT_DONE) == 0) 797 panic("%s: polled command not done", __func__); 798 #endif 799 if (ata_c->flags & AT_DONE) { 800 ret = ATACMD_COMPLETE; 801 } else { 802 if (ata_c->flags & AT_WAIT) { 803 while ((ata_c->flags & AT_DONE) == 0) { 804 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 805 SIISATANAME( 806 (struct siisata_softc *)chp->ch_atac), 807 __func__), DEBUG_FUNCS); 808 tsleep(ata_c, PRIBIO, "siicmd", 0); 809 } 810 ret = ATACMD_COMPLETE; 811 } else { 812 ret = ATACMD_QUEUED; 813 } 814 } 815 splx(s); 816 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 817 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 818 DEBUG_FUNCS); 819 return ret; 820 } 821 822 void 823 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 824 { 825 struct siisata_channel *schp = (struct siisata_channel *)chp; 826 struct ata_command *ata_c = xfer->c_cmd; 827 int slot = SIISATA_NON_NCQ_SLOT; 828 struct siisata_prb *prb; 829 int i; 830 831 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 832 SIISATANAME((struct siisata_softc *)chp->ch_atac), 833 __func__, chp->ch_channel, xfer->c_drive, 834 ata_c->r_command, slot), 835 DEBUG_FUNCS|DEBUG_XFERS); 836 837 chp->ch_status = 0; 838 chp->ch_error = 0; 839 840 prb = schp->sch_prb[slot]; 841 memset(prb, 0, sizeof(struct siisata_prb)); 842 843 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 844 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 845 prb->prb_fis[rhd_c] |= xfer->c_drive; 846 847 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 848 849 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 850 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 851 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 852 } 853 854 if (siisata_dma_setup(chp, slot, 855 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 856 ata_c->bcount, 857 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 858 ata_c->flags |= AT_DF; 859 siisata_cmd_complete(chp, xfer, slot); 860 return; 861 } 862 863 if (xfer->c_flags & C_POLL) { 864 /* polled command, disable interrupts */ 865 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 866 siisata_disable_port_interrupt(chp); 867 } 868 869 /* go for it */ 870 siisata_activate_prb(schp, slot); 871 872 if ((ata_c->flags & AT_POLL) == 0) { 873 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 874 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 875 siisata_timeout, chp); 876 goto out; 877 } 878 879 /* 880 * polled command 881 */ 882 for (i = 0; i < ata_c->timeout / 10; i++) { 883 if (ata_c->flags & AT_DONE) 884 break; 885 siisata_intr_port(schp); 886 DELAY(1000); 887 } 888 889 if ((ata_c->flags & AT_DONE) == 0) { 890 siisata_timeout(chp); 891 } 892 893 /* reenable interrupts */ 894 siisata_enable_port_interrupt(chp); 895 out: 896 SIISATA_DEBUG_PRINT( 897 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 898 return; 899 } 900 901 void 902 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 903 int reason) 904 { 905 int slot = SIISATA_NON_NCQ_SLOT; 906 907 struct ata_command *ata_c = xfer->c_cmd; 908 switch (reason) { 909 case KILL_GONE: 910 ata_c->flags |= AT_GONE; 911 break; 912 case KILL_RESET: 913 ata_c->flags |= AT_RESET; 914 break; 915 default: 916 panic("%s: port %d: unknown reason %d", 917 __func__, chp->ch_channel, reason); 918 } 919 siisata_cmd_done(chp, xfer, slot); 920 } 921 922 int 923 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 924 { 925 struct ata_command *ata_c = xfer->c_cmd; 926 #ifdef SIISATA_DEBUG 927 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 928 #endif 929 930 SIISATA_DEBUG_PRINT( 931 ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS|DEBUG_XFERS); 932 933 chp->ch_flags &= ~ATACH_IRQ_WAIT; 934 if (xfer->c_flags & C_TIMEOU) 935 ata_c->flags |= AT_TIMEOU; 936 else 937 callout_stop(&chp->ch_callout); 938 939 if (chp->ch_status & WDCS_BSY) { 940 ata_c->flags |= AT_TIMEOU; 941 } else if (chp->ch_status & WDCS_ERR) { 942 ata_c->r_error = chp->ch_error; 943 ata_c->flags |= AT_ERROR; 944 } 945 946 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 947 siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); 948 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 949 wakeup(&chp->ch_queue->active_xfer); 950 return 0; 951 } else 952 siisata_cmd_done(chp, xfer, slot); 953 954 return 0; 955 } 956 957 void 958 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 959 { 960 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 961 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 962 struct siisata_channel *schp = (struct siisata_channel *)chp; 963 struct ata_command *ata_c = xfer->c_cmd; 964 uint16_t *idwordbuf; 965 int i; 966 967 SIISATA_DEBUG_PRINT( 968 ("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), __func__, 969 ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 970 971 siisata_deactivate_prb(schp, slot); 972 973 if (ata_c->flags & (AT_READ | AT_WRITE)) { 974 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 975 schp->sch_datad[slot]->dm_mapsize, 976 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 977 BUS_DMASYNC_POSTWRITE); 978 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 979 } 980 981 if (ata_c->flags & AT_READREG) { 982 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 983 PRSX(chp->ch_channel, slot, PRSO_FIS), 984 fis, __arraycount(fis)); 985 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 986 } 987 988 /* correct the endianess of IDENTIFY data */ 989 if (ata_c->r_command == WDCC_IDENTIFY || 990 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 991 idwordbuf = xfer->c_databuf; 992 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 993 idwordbuf[i] = le16toh(idwordbuf[i]); 994 } 995 } 996 997 ata_c->flags |= AT_DONE; 998 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 999 ata_c->flags |= AT_XFDONE; 1000 1001 chp->ch_queue->active_xfer = NULL; 1002 ata_free_xfer(chp, xfer); 1003 if (ata_c->flags & AT_WAIT) 1004 wakeup(ata_c); 1005 else if (ata_c->callback) 1006 ata_c->callback(ata_c->callback_arg); 1007 atastart(chp); 1008 return; 1009 } 1010 1011 int 1012 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1013 { 1014 struct ata_channel *chp = drvp->chnl_softc; 1015 struct ata_xfer *xfer; 1016 1017 SIISATA_DEBUG_PRINT( ("%s: %s.\n", 1018 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1019 __func__), DEBUG_FUNCS); 1020 1021 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1022 if (xfer == NULL) 1023 return ATACMD_TRY_AGAIN; 1024 if (ata_bio->flags & ATA_POLL) 1025 xfer->c_flags |= C_POLL; 1026 xfer->c_drive = drvp->drive; 1027 xfer->c_cmd = ata_bio; 1028 xfer->c_databuf = ata_bio->databuf; 1029 xfer->c_bcount = ata_bio->bcount; 1030 xfer->c_start = siisata_bio_start; 1031 xfer->c_intr = siisata_bio_complete; 1032 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1033 ata_exec_xfer(chp, xfer); 1034 return (ata_bio->flags & ATA_ITSDONE) ? 1035 ATACMD_COMPLETE : ATACMD_QUEUED; 1036 } 1037 1038 void 1039 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1040 { 1041 struct siisata_channel *schp = (struct siisata_channel *)chp; 1042 struct siisata_prb *prb; 1043 struct ata_bio *ata_bio = xfer->c_cmd; 1044 int slot = SIISATA_NON_NCQ_SLOT; 1045 int i; 1046 1047 SIISATA_DEBUG_PRINT( 1048 ("%s: %s port %d, slot %d\n", 1049 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, chp->ch_channel, slot), 1050 DEBUG_FUNCS); 1051 1052 chp->ch_status = 0; 1053 chp->ch_error = 0; 1054 1055 prb = schp->sch_prb[slot]; 1056 memset(prb, 0, sizeof(struct siisata_prb)); 1057 1058 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1059 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1060 prb->prb_fis[rhd_c] |= xfer->c_drive; 1061 1062 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 1063 1064 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1065 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1066 ata_bio->error = ERR_DMA; 1067 ata_bio->r_error = 0; 1068 siisata_bio_complete(chp, xfer, slot); 1069 return; 1070 } 1071 1072 if (xfer->c_flags & C_POLL) { 1073 /* polled command, disable interrupts */ 1074 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1075 siisata_disable_port_interrupt(chp); 1076 } 1077 1078 siisata_activate_prb(schp, slot); 1079 1080 if ((ata_bio->flags & ATA_POLL) == 0) { 1081 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1082 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1083 siisata_timeout, chp); 1084 goto out; 1085 } 1086 1087 /* 1088 * polled command 1089 */ 1090 for (i = 0; i < ATA_DELAY / 10; i++) { 1091 if (ata_bio->flags & ATA_ITSDONE) 1092 break; 1093 siisata_intr_port(schp); 1094 DELAY(1000); 1095 } 1096 1097 siisata_enable_port_interrupt(chp); 1098 out: 1099 SIISATA_DEBUG_PRINT( 1100 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 1101 return; 1102 } 1103 1104 void 1105 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1106 int reason) 1107 { 1108 struct siisata_channel *schp = (struct siisata_channel *)chp; 1109 struct ata_bio *ata_bio = xfer->c_cmd; 1110 int drive = xfer->c_drive; 1111 int slot = SIISATA_NON_NCQ_SLOT; 1112 1113 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1114 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1115 __func__, chp->ch_channel), DEBUG_FUNCS); 1116 1117 siisata_deactivate_prb(schp, slot); 1118 1119 ata_free_xfer(chp, xfer); 1120 ata_bio->flags |= ATA_ITSDONE; 1121 switch (reason) { 1122 case KILL_GONE: 1123 ata_bio->error = ERR_NODEV; 1124 break; 1125 case KILL_RESET: 1126 ata_bio->error = ERR_RESET; 1127 break; 1128 default: 1129 panic("%s: port %d: unknown reason %d", 1130 __func__, chp->ch_channel, reason); 1131 } 1132 ata_bio->r_error = WDCE_ABRT; 1133 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1134 } 1135 1136 int 1137 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1138 { 1139 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1140 struct siisata_channel *schp = (struct siisata_channel *)chp; 1141 struct ata_bio *ata_bio = xfer->c_cmd; 1142 int drive = xfer->c_drive; 1143 1144 schp->sch_active_slots &= ~__BIT(slot); 1145 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1146 if (xfer->c_flags & C_TIMEOU) { 1147 ata_bio->error = TIMEOUT; 1148 } else { 1149 callout_stop(&chp->ch_callout); 1150 ata_bio->error = NOERROR; 1151 } 1152 1153 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1154 schp->sch_datad[slot]->dm_mapsize, 1155 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1156 BUS_DMASYNC_POSTWRITE); 1157 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1158 1159 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1160 siisata_bio_kill_xfer(chp, xfer, KILL_GONE); 1161 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1162 wakeup(&chp->ch_queue->active_xfer); 1163 return 0; 1164 } 1165 1166 chp->ch_queue->active_xfer = NULL; 1167 ata_free_xfer(chp, xfer); 1168 ata_bio->flags |= ATA_ITSDONE; 1169 if (chp->ch_status & WDCS_DWF) { 1170 ata_bio->error = ERR_DF; 1171 } else if (chp->ch_status & WDCS_ERR) { 1172 ata_bio->error = ERROR; 1173 ata_bio->r_error = chp->ch_error; 1174 } else if (chp->ch_status & WDCS_CORR) 1175 ata_bio->flags |= ATA_CORR; 1176 1177 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), 1178 __func__, ata_bio->bcount), DEBUG_XFERS); 1179 if (ata_bio->error == NOERROR) { 1180 if (ata_bio->flags & ATA_READ) 1181 ata_bio->bcount -= 1182 PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1183 else 1184 ata_bio->bcount = 0; 1185 } 1186 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1187 if (ata_bio->flags & ATA_POLL) 1188 return 1; 1189 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1190 atastart(chp); 1191 return 0; 1192 } 1193 1194 void 1195 siisata_timeout(void *v) 1196 { 1197 struct ata_channel *chp = (struct ata_channel *)v; 1198 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1199 int slot = SIISATA_NON_NCQ_SLOT; 1200 int s = splbio(); 1201 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1202 siisata_device_reset(chp); 1203 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1204 xfer->c_flags |= C_TIMEOU; 1205 xfer->c_intr(chp, xfer, slot); 1206 } 1207 splx(s); 1208 } 1209 1210 static int 1211 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1212 size_t count, int op) 1213 { 1214 1215 int error, seg; 1216 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1217 struct siisata_channel *schp = (struct siisata_channel *)chp; 1218 1219 struct siisata_prb *prbp; 1220 1221 prbp = schp->sch_prb[slot]; 1222 1223 if (data == NULL) { 1224 goto end; 1225 } 1226 1227 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1228 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1229 if (error) { 1230 aprint_error("%s port %d: " 1231 "failed to load xfer in slot %d: error %d\n", 1232 SIISATANAME(sc), chp->ch_channel, slot, error); 1233 return error; 1234 } 1235 1236 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1237 schp->sch_datad[slot]->dm_mapsize, 1238 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1239 1240 /* make sure it's clean */ 1241 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1242 1243 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1244 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1245 DEBUG_FUNCS | DEBUG_DEBUG); 1246 1247 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1248 prbp->prb_sge[seg].sge_da = 1249 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1250 prbp->prb_sge[seg].sge_dc = 1251 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1252 prbp->prb_sge[seg].sge_flags = htole32(0); 1253 } 1254 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1255 end: 1256 return 0; 1257 } 1258 1259 static void 1260 siisata_activate_prb(struct siisata_channel *schp, int slot) 1261 { 1262 struct siisata_softc *sc; 1263 bus_size_t offset; 1264 uint64_t pprb; 1265 1266 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1267 1268 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != __BIT(slot), 1269 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1270 1271 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1272 /* keep track of what's going on */ 1273 schp->sch_active_slots |= __BIT(slot); 1274 1275 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1276 1277 pprb = schp->sch_bus_prb[slot]; 1278 1279 PRWRITE(sc, offset + 0, pprb >> 0); 1280 PRWRITE(sc, offset + 4, pprb >> 32); 1281 } 1282 1283 static void 1284 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1285 { 1286 struct siisata_softc *sc; 1287 1288 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1289 1290 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1291 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1292 slot); 1293 1294 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1295 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1296 } 1297 1298 static void 1299 siisata_reinit_port(struct ata_channel *chp) 1300 { 1301 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1302 1303 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1304 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1305 DELAY(10); 1306 if (chp->ch_ndrives > 1) 1307 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1308 } 1309 1310 static void 1311 siisata_device_reset(struct ata_channel *chp) 1312 { 1313 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1314 1315 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1316 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1317 DELAY(10); 1318 } 1319 1320 1321 #if NATAPIBUS > 0 1322 void 1323 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1324 { 1325 struct ata_channel *chp = ata_sc->sc_chan; 1326 struct atac_softc *atac = chp->ch_atac; 1327 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1328 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1329 1330 /* 1331 * Fill in the scsipi_adapter. 1332 */ 1333 adapt->adapt_dev = atac->atac_dev; 1334 adapt->adapt_nchannels = atac->atac_nchannels; 1335 adapt->adapt_request = siisata_atapi_scsipi_request; 1336 adapt->adapt_minphys = siisata_atapi_minphys; 1337 atac->atac_atapi_adapter.atapi_probe_device = 1338 siisata_atapi_probe_device; 1339 1340 /* 1341 * Fill in the scsipi_channel. 1342 */ 1343 memset(chan, 0, sizeof(*chan)); 1344 chan->chan_adapter = adapt; 1345 chan->chan_bustype = &siisata_atapi_bustype; 1346 chan->chan_channel = chp->ch_channel; 1347 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1348 chan->chan_openings = 1; 1349 chan->chan_max_periph = 1; 1350 chan->chan_ntargets = 1; 1351 chan->chan_nluns = 1; 1352 1353 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1354 atapiprint); 1355 } 1356 1357 void 1358 siisata_atapi_minphys(struct buf *bp) 1359 { 1360 if (bp->b_bcount > MAXPHYS) 1361 bp->b_bcount = MAXPHYS; 1362 minphys(bp); 1363 } 1364 1365 /* 1366 * Kill off all pending xfers for a periph. 1367 * 1368 * Must be called at splbio(). 1369 */ 1370 void 1371 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1372 { 1373 struct atac_softc *atac = 1374 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1375 struct ata_channel *chp = 1376 atac->atac_channels[periph->periph_channel->chan_channel]; 1377 1378 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1379 } 1380 1381 void 1382 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1383 int reason) 1384 { 1385 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1386 1387 /* remove this command from xfer queue */ 1388 switch (reason) { 1389 case KILL_GONE: 1390 sc_xfer->error = XS_DRIVER_STUFFUP; 1391 break; 1392 case KILL_RESET: 1393 sc_xfer->error = XS_RESET; 1394 break; 1395 default: 1396 panic("%s: port %d: unknown reason %d", 1397 __func__, chp->ch_channel, reason); 1398 } 1399 ata_free_xfer(chp, xfer); 1400 scsipi_done(sc_xfer); 1401 } 1402 1403 void 1404 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1405 { 1406 struct scsipi_channel *chan = sc->sc_channel; 1407 struct scsipi_periph *periph; 1408 struct ataparams ids; 1409 struct ataparams *id = &ids; 1410 struct siisata_softc *siic = 1411 device_private(chan->chan_adapter->adapt_dev); 1412 struct atac_softc *atac = &siic->sc_atac; 1413 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1414 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1415 struct scsipibus_attach_args sa; 1416 char serial_number[21], model[41], firmware_revision[9]; 1417 int s; 1418 1419 /* skip if already attached */ 1420 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1421 return; 1422 1423 /* if no ATAPI device detected at attach time, skip */ 1424 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1425 SIISATA_DEBUG_PRINT(("%s: drive %d " 1426 "not present\n", __func__, target), DEBUG_PROBE); 1427 return; 1428 } 1429 1430 /* Some ATAPI devices need a bit more time after software reset. */ 1431 DELAY(5000); 1432 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1433 #ifdef ATAPI_DEBUG_PROBE 1434 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1435 device_xname(sc->sc_dev), target, 1436 id->atap_config & ATAPI_CFG_CMD_MASK, 1437 id->atap_config & ATAPI_CFG_DRQ_MASK); 1438 #endif 1439 periph = scsipi_alloc_periph(M_NOWAIT); 1440 if (periph == NULL) { 1441 aprint_error_dev(sc->sc_dev, 1442 "%s: unable to allocate periph for " 1443 "channel %d drive %d\n", __func__, 1444 chp->ch_channel, target); 1445 return; 1446 } 1447 periph->periph_dev = NULL; 1448 periph->periph_channel = chan; 1449 periph->periph_switch = &atapi_probe_periphsw; 1450 periph->periph_target = target; 1451 periph->periph_lun = 0; 1452 periph->periph_quirks = PQUIRK_ONLYBIG; 1453 1454 #ifdef SCSIPI_DEBUG 1455 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1456 SCSIPI_DEBUG_TARGET == target) 1457 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1458 #endif 1459 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1460 if (id->atap_config & ATAPI_CFG_REMOV) 1461 periph->periph_flags |= PERIPH_REMOVABLE; 1462 sa.sa_periph = periph; 1463 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1464 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1465 T_REMOV : T_FIXED; 1466 strnvisx(model, sizeof(model), id->atap_model, 40, 1467 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1468 strnvisx(serial_number, sizeof(serial_number), 1469 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1470 strnvisx(firmware_revision, sizeof(firmware_revision), 1471 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1472 sa.sa_inqbuf.vendor = model; 1473 sa.sa_inqbuf.product = serial_number; 1474 sa.sa_inqbuf.revision = firmware_revision; 1475 1476 /* 1477 * Determine the operating mode capabilities of the device. 1478 */ 1479 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1480 == ATAPI_CFG_CMD_16) { 1481 periph->periph_cap |= PERIPH_CAP_CMD16; 1482 1483 /* configure port for packet length */ 1484 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1485 PR_PC_PACKET_LENGTH); 1486 } else { 1487 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1488 PR_PC_PACKET_LENGTH); 1489 } 1490 1491 /* XXX This is gross. */ 1492 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1493 1494 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1495 1496 if (drvp->drv_softc) 1497 ata_probe_caps(drvp); 1498 else { 1499 s = splbio(); 1500 drvp->drive_type &= ATA_DRIVET_NONE; 1501 splx(s); 1502 } 1503 } else { 1504 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1505 "failed for drive %s:%d:%d: error 0x%x\n", 1506 __func__, SIISATANAME(siic), chp->ch_channel, target, 1507 chp->ch_error), DEBUG_PROBE); 1508 s = splbio(); 1509 drvp->drive_type &= ATA_DRIVET_NONE; 1510 splx(s); 1511 } 1512 } 1513 1514 void 1515 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1516 scsipi_adapter_req_t req, void *arg) 1517 { 1518 struct scsipi_adapter *adapt = chan->chan_adapter; 1519 struct scsipi_periph *periph; 1520 struct scsipi_xfer *sc_xfer; 1521 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1522 struct atac_softc *atac = &sc->sc_atac; 1523 struct ata_xfer *xfer; 1524 int channel = chan->chan_channel; 1525 int drive, s; 1526 1527 switch (req) { 1528 case ADAPTER_REQ_RUN_XFER: 1529 sc_xfer = arg; 1530 periph = sc_xfer->xs_periph; 1531 drive = periph->periph_target; 1532 1533 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1534 device_xname(atac->atac_dev), channel, drive), 1535 DEBUG_XFERS); 1536 1537 if (!device_is_active(atac->atac_dev)) { 1538 sc_xfer->error = XS_DRIVER_STUFFUP; 1539 scsipi_done(sc_xfer); 1540 return; 1541 } 1542 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1543 if (xfer == NULL) { 1544 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1545 scsipi_done(sc_xfer); 1546 return; 1547 } 1548 1549 if (sc_xfer->xs_control & XS_CTL_POLL) 1550 xfer->c_flags |= C_POLL; 1551 xfer->c_drive = drive; 1552 xfer->c_flags |= C_ATAPI; 1553 xfer->c_cmd = sc_xfer; 1554 xfer->c_databuf = sc_xfer->data; 1555 xfer->c_bcount = sc_xfer->datalen; 1556 xfer->c_start = siisata_atapi_start; 1557 xfer->c_intr = siisata_atapi_complete; 1558 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1559 xfer->c_dscpoll = 0; 1560 s = splbio(); 1561 ata_exec_xfer(atac->atac_channels[channel], xfer); 1562 #ifdef DIAGNOSTIC 1563 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1564 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1565 panic("%s: polled command not done", __func__); 1566 #endif 1567 splx(s); 1568 return; 1569 1570 default: 1571 /* Not supported, nothing to do. */ 1572 ; 1573 } 1574 } 1575 1576 void 1577 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1578 { 1579 struct siisata_channel *schp = (struct siisata_channel *)chp; 1580 struct siisata_prb *prbp; 1581 1582 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1583 1584 int slot = SIISATA_NON_NCQ_SLOT; 1585 int i; 1586 1587 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1588 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1589 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1590 DEBUG_XFERS); 1591 1592 chp->ch_status = 0; 1593 chp->ch_error = 0; 1594 1595 prbp = schp->sch_prb[slot]; 1596 memset(prbp, 0, sizeof(struct siisata_prb)); 1597 1598 1599 /* fill in direction for ATAPI command */ 1600 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1601 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1602 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1603 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1604 1605 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1606 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1607 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1608 1609 /* copy over ATAPI command */ 1610 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1611 1612 if (siisata_dma_setup(chp, slot, 1613 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1614 xfer->c_databuf : NULL, 1615 xfer->c_bcount, 1616 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1617 BUS_DMA_READ : BUS_DMA_WRITE) 1618 ) 1619 panic("%s", __func__); 1620 1621 if (xfer->c_flags & C_POLL) { 1622 /* polled command, disable interrupts */ 1623 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1624 siisata_disable_port_interrupt(chp); 1625 } 1626 1627 siisata_activate_prb(schp, slot); 1628 1629 if ((xfer->c_flags & C_POLL) == 0) { 1630 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1631 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1632 siisata_timeout, chp); 1633 goto out; 1634 } 1635 1636 /* 1637 * polled command 1638 */ 1639 for (i = 0; i < ATA_DELAY / 10; i++) { 1640 if (sc_xfer->xs_status & XS_STS_DONE) 1641 break; 1642 siisata_intr_port(schp); 1643 DELAY(1000); 1644 } 1645 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1646 siisata_timeout(chp); 1647 } 1648 /* reenable interrupts */ 1649 siisata_enable_port_interrupt(chp); 1650 out: 1651 SIISATA_DEBUG_PRINT( 1652 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 1653 return; 1654 } 1655 1656 int 1657 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1658 int slot) 1659 { 1660 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1661 struct siisata_channel *schp = (struct siisata_channel *)chp; 1662 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1663 1664 SIISATA_DEBUG_PRINT( 1665 ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1666 1667 /* this comamnd is not active any more */ 1668 schp->sch_active_slots &= ~__BIT(slot); 1669 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1670 if (xfer->c_flags & C_TIMEOU) { 1671 sc_xfer->error = XS_TIMEOUT; 1672 } else { 1673 callout_stop(&chp->ch_callout); 1674 sc_xfer->error = XS_NOERROR; 1675 } 1676 1677 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1678 schp->sch_datad[slot]->dm_mapsize, 1679 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1680 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1681 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1682 1683 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1684 siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); 1685 chp->ch_drive[xfer->c_drive].drive_flags &= ~ATA_DRIVE_WAITDRAIN; 1686 wakeup(&chp->ch_queue->active_xfer); 1687 return 0; /* XXX verify */ 1688 } 1689 1690 chp->ch_queue->active_xfer = NULL; 1691 ata_free_xfer(chp, xfer); 1692 sc_xfer->resid = sc_xfer->datalen; 1693 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1694 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1695 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1696 if ((chp->ch_status & WDCS_ERR) && 1697 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1698 sc_xfer->resid == sc_xfer->datalen)) { 1699 sc_xfer->error = XS_SHORTSENSE; 1700 sc_xfer->sense.atapi_sense = chp->ch_error; 1701 if ((sc_xfer->xs_periph->periph_quirks & 1702 PQUIRK_NOSENSE) == 0) { 1703 /* request sense */ 1704 sc_xfer->error = XS_BUSY; 1705 sc_xfer->status = SCSI_CHECK; 1706 } 1707 } 1708 scsipi_done(sc_xfer); 1709 atastart(chp); 1710 return 0; /* XXX verify */ 1711 } 1712 1713 #endif /* NATAPIBUS */ 1714
Indexes created Mon Oct 20 10:10:01 GMT 2025