siisata.c revision 1.3
1 /* $NetBSD: siisata.c,v 1.3 2009/06/17 04:37:57 jakllsch Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Manuel Bouyer. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* from atapi_wdc.c */ 36 37 /* 38 * Copyright (c) 1998, 2001 Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Manuel Bouyer. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /*- 67 * Copyright (c) 2007, 2008 Jonathan A. Kollasch. 68 * All rights reserved. 69 * 70 * Redistribution and use in source and binary forms, with or without 71 * modification, are permitted provided that the following conditions 72 * are met: 73 * 1. Redistributions of source code must retain the above copyright 74 * notice, this list of conditions and the following disclaimer. 75 * 2. Redistributions in binary form must reproduce the above copyright 76 * notice, this list of conditions and the following disclaimer in the 77 * documentation and/or other materials provided with the distribution. 78 * 79 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 80 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 81 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 82 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 83 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 84 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 85 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 86 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 87 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 88 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 89 * 90 */ 91 92 #include <sys/types.h> 93 #include <sys/malloc.h> 94 #include <sys/param.h> 95 #include <sys/kernel.h> 96 #include <sys/systm.h> 97 #include <sys/syslog.h> 98 #include <sys/disklabel.h> 99 #include <sys/buf.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <dev/ata/atareg.h> 104 #include <dev/ata/satavar.h> 105 #include <dev/ata/satareg.h> 106 #include <dev/ata/satafisvar.h> 107 #include <dev/ic/siisatavar.h> 108 #include <dev/ic/wdcreg.h> 109 110 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 111 112 #include "atapibus.h" 113 114 #ifdef SIISATA_DEBUG 115 #if 0 116 int siisata_debug_mask = 0xffff; 117 #else 118 int siisata_debug_mask = 0; 119 #endif 120 #endif 121 122 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 123 124 static void siisata_attach_port(struct siisata_softc *, int); 125 static void siisata_intr_port(struct siisata_channel *); 126 127 void siisata_probe_drive(struct ata_channel *); 128 void siisata_setup_channel(struct ata_channel *); 129 130 int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); 131 void siisata_reset_drive(struct ata_drive_datas *, int); 132 void siisata_reset_channel(struct ata_channel *, int); 133 int siisata_ata_addref(struct ata_drive_datas *); 134 void siisata_ata_delref(struct ata_drive_datas *); 135 void siisata_killpending(struct ata_drive_datas *); 136 137 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 138 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 139 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 140 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 141 142 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 143 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 144 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 145 int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); 146 147 void siisata_timeout(void *); 148 149 static void siisata_reinit_port(struct ata_channel *); 150 static void siisata_device_reset(struct ata_channel *); 151 static void siisata_activate_prb(struct siisata_channel *, int); 152 static void siisata_deactivate_prb(struct siisata_channel *, int); 153 static int siisata_dma_setup(struct ata_channel *chp, int slot, 154 void *data, size_t, int); 155 156 #if NATAPIBUS > 0 157 void siisata_atapibus_attach(struct atabus_softc *); 158 void siisata_atapi_probe_device(struct atapibus_softc *, int); 159 void siisata_atapi_minphys(struct buf *); 160 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 161 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 162 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 163 void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 164 void siisata_atapi_scsipi_request(struct scsipi_channel *, 165 scsipi_adapter_req_t, void *); 166 void siisata_atapi_kill_pending(struct scsipi_periph *); 167 #endif /* NATAPIBUS */ 168 169 const struct ata_bustype siisata_ata_bustype = { 170 SCSIPI_BUSTYPE_ATA, 171 siisata_ata_bio, 172 siisata_reset_drive, 173 siisata_reset_channel, 174 siisata_exec_command, 175 ata_get_params, 176 siisata_ata_addref, 177 siisata_ata_delref, 178 siisata_killpending 179 }; 180 181 #if NATAPIBUS > 0 182 static const struct scsipi_bustype siisata_atapi_bustype = { 183 SCSIPI_BUSTYPE_ATAPI, 184 atapi_scsipi_cmd, 185 atapi_interpret_sense, 186 atapi_print_addr, 187 siisata_atapi_kill_pending 188 }; 189 #endif /* NATAPIBUS */ 190 191 192 void 193 siisata_attach(struct siisata_softc *sc) 194 { 195 int i; 196 197 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 198 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 199 200 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 201 sc->sc_atac.atac_pio_cap = 4; 202 sc->sc_atac.atac_dma_cap = 2; 203 sc->sc_atac.atac_udma_cap = 6; 204 sc->sc_atac.atac_channels = sc->sc_chanarray; 205 sc->sc_atac.atac_probe = siisata_probe_drive; 206 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 207 sc->sc_atac.atac_set_modes = siisata_setup_channel; 208 #if NATAPIBUS > 0 209 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 210 #endif 211 212 /* come out of reset state */ 213 GRWRITE(sc, GR_GC, 0); 214 215 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 216 siisata_attach_port(sc, i); 217 } 218 219 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 220 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 221 DEBUG_FUNCS); 222 return; 223 } 224 225 static void 226 siisata_init_port(struct siisata_softc *sc, int port) 227 { 228 struct siisata_channel *schp; 229 struct ata_channel *chp; 230 231 schp = &sc->sc_channels[port]; 232 chp = (struct ata_channel *)schp; 233 234 /* come out of reset, 64-bit activation */ 235 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 236 PR_PC_32BA | PR_PC_PORT_RESET); 237 /* initialize port */ 238 siisata_reinit_port(chp); 239 /* clear any interrupts */ 240 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 241 /* enable CmdErrr+CmdCmpl interrupting */ 242 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 243 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 244 /* enable port interrupt */ 245 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 246 } 247 248 static void 249 siisata_attach_port(struct siisata_softc *sc, int port) 250 { 251 int j; 252 bus_dma_segment_t seg; 253 int dmasize; 254 int error; 255 int rseg; 256 void *prbp; 257 struct siisata_channel *schp; 258 struct ata_channel *chp; 259 260 schp = &sc->sc_channels[port]; 261 chp = (struct ata_channel *)schp; 262 sc->sc_chanarray[port] = chp; 263 chp->ch_channel = port; 264 chp->ch_atac = &sc->sc_atac; 265 chp->ch_queue = malloc(sizeof(struct ata_queue), 266 M_DEVBUF, M_NOWAIT); 267 if (chp->ch_queue == NULL) { 268 aprint_error_dev(sc->sc_atac.atac_dev, 269 "port %d: can't allocate memory " 270 "for command queue\n", chp->ch_channel); 271 return; 272 } 273 274 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 275 276 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 277 __func__, dmasize), DEBUG_FUNCS); 278 279 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 280 &seg, 1, &rseg, BUS_DMA_NOWAIT); 281 if (error) { 282 aprint_error_dev(sc->sc_atac.atac_dev, 283 "unable to allocate PRB table memory, " 284 "error=%d\n", error); 285 return; 286 } 287 288 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 289 &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 290 if (error) { 291 aprint_error_dev(sc->sc_atac.atac_dev, 292 "unable to map PRB table memory, " 293 "error=%d\n", error); 294 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 295 return; 296 } 297 298 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 299 BUS_DMA_NOWAIT, &schp->sch_prbd); 300 if (error) { 301 aprint_error_dev(sc->sc_atac.atac_dev, 302 "unable to create PRB table map, " 303 "error=%d\n", error); 304 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 305 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 306 return; 307 } 308 309 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 310 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 311 if (error) { 312 aprint_error_dev(sc->sc_atac.atac_dev, 313 "unable to load PRB table map, " 314 "error=%d\n", error); 315 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 316 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 317 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 318 return; 319 } 320 321 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 322 schp->sch_prb[j] = (struct siisata_prb *) 323 ((char *)prbp + SIISATA_CMD_SIZE * j); 324 schp->sch_bus_prb[j] = 325 schp->sch_prbd->dm_segs[0].ds_addr + 326 SIISATA_CMD_SIZE * j; 327 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 328 SIISATA_NSGE, MAXPHYS, 0, 329 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 330 &schp->sch_datad[j]); 331 if (error) { 332 aprint_error_dev(sc->sc_atac.atac_dev, 333 "couldn't create xfer DMA map, error=%d\n", 334 error); 335 return; 336 } 337 } 338 339 chp->ch_ndrive = 1; 340 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 341 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "couldn't map port %d SStatus regs\n", 344 chp->ch_channel); 345 return; 346 } 347 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 348 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 349 aprint_error_dev(sc->sc_atac.atac_dev, 350 "couldn't map port %d SControl regs\n", 351 chp->ch_channel); 352 return; 353 } 354 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 355 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 356 aprint_error_dev(sc->sc_atac.atac_dev, 357 "couldn't map port %d SError regs\n", 358 chp->ch_channel); 359 return; 360 } 361 362 siisata_init_port(sc, port); 363 364 ata_channel_attach(chp); 365 366 return; 367 } 368 369 int 370 siisata_detach(struct siisata_softc *sc, int flags) 371 { 372 struct atac_softc *atac = &sc->sc_atac; 373 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 374 struct siisata_channel *schp; 375 struct ata_channel *chp; 376 bus_dmamap_t dmam; 377 int i, j, error; 378 379 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 380 schp = &sc->sc_channels[i]; 381 chp = sc->sc_chanarray[i]; 382 383 if (chp->atabus == NULL) 384 continue; 385 if ((error = config_detach(chp->atabus, flags)) != 0) 386 return error; 387 388 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 389 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 390 391 dmam = schp->sch_prbd; 392 bus_dmamap_unload(sc->sc_dmat, dmam); 393 bus_dmamap_destroy(sc->sc_dmat, dmam); 394 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 395 dmam->dm_mapsize); 396 bus_dmamem_free(sc->sc_dmat, dmam->dm_segs, dmam->dm_nsegs); 397 398 free(chp->ch_queue, M_DEVBUF); 399 chp->atabus = NULL; 400 } 401 402 if (adapt->adapt_refcnt != 0) 403 return EBUSY; 404 405 /* leave the chip in reset */ 406 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 407 408 return 0; 409 } 410 411 void 412 siisata_resume(struct siisata_softc *sc) 413 { 414 int i; 415 416 /* come out of reset state */ 417 GRWRITE(sc, GR_GC, 0); 418 419 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 420 siisata_init_port(sc, i); 421 } 422 423 } 424 425 int 426 siisata_intr(void *v) 427 { 428 struct siisata_softc *sc = v; 429 uint32_t is; 430 int i, r = 0; 431 while ((is = GRREAD(sc, GR_GIS))) { 432 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 433 SIISATANAME(sc), __func__, is), DEBUG_INTR); 434 r = 1; 435 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 436 if (is & GR_GIS_PXIS(i)) 437 siisata_intr_port(&sc->sc_channels[i]); 438 } 439 return r; 440 } 441 442 static void 443 siisata_intr_port(struct siisata_channel *schp) 444 { 445 struct siisata_softc *sc; 446 struct ata_channel *chp; 447 struct ata_xfer *xfer; 448 int slot; 449 uint32_t pss, pis; 450 uint32_t prbfis; 451 452 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 453 chp = &schp->ata_channel; 454 xfer = chp->ch_queue->active_xfer; 455 slot = SIISATA_NON_NCQ_SLOT; 456 457 SIISATA_DEBUG_PRINT(("%s: %s port %d\n", 458 SIISATANAME(sc), __func__, chp->ch_channel), DEBUG_INTR); 459 460 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 461 462 if (pis & PR_PIS_CMDCMPL) { 463 /* get slot status, clearing completion interrupt */ 464 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 465 /* is this expected? */ 466 /* XXX improve */ 467 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 468 log(LOG_WARNING, "%s: unexpected command " 469 "completion on port %d\n", 470 SIISATANAME(sc), chp->ch_channel); 471 return; 472 } 473 } else if (pis & PR_PIS_CMDERRR) { 474 uint32_t ec; 475 476 /* emulate a CRC error by default */ 477 chp->ch_status = WDCS_ERR; 478 chp->ch_error = WDCE_CRC; 479 480 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 481 if (ec <= PR_PCE_DATAFISERROR) { 482 if (ec != PR_PCE_DATAFISERROR) { 483 /* read in specific information about error */ 484 prbfis = bus_space_read_stream_4( 485 sc->sc_prt, sc->sc_prh, 486 PRSX(chp->ch_channel, slot, PRSO_FIS)); 487 /* set ch_status and ch_error */ 488 satafis_sdb_parse(chp, (uint8_t *)&prbfis); 489 } 490 siisata_reinit_port(chp); 491 } else { 492 /* okay, we have a "Fatal Error" */ 493 siisata_device_reset(chp); 494 } 495 } 496 497 KASSERT(xfer != NULL); 498 KASSERT(xfer->c_intr != NULL); 499 xfer->c_intr(chp, xfer, slot); 500 501 /* clear some (ok, all) ints */ 502 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 503 504 return; 505 } 506 507 void 508 siisata_reset_drive(struct ata_drive_datas *drvp, int flags) 509 { 510 struct ata_channel *chp = drvp->chnl_softc; 511 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 512 struct siisata_channel *schp = (struct siisata_channel *)chp; 513 struct siisata_prb *prb; 514 kmutex_t mtx; 515 kcondvar_t cv; 516 int slot = SIISATA_NON_NCQ_SLOT; 517 int i; 518 int wait; 519 520 mutex_init(&mtx, MUTEX_DEFAULT, IPL_NONE); 521 cv_init(&cv, "siipd"); 522 523 wait = mstohz(10); 524 wait = wait ? wait : 1; 525 526 /* wait for ready */ 527 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 528 DELAY(10); 529 530 prb = schp->sch_prb[slot]; 531 memset(prb, 0, sizeof(struct siisata_prb)); 532 prb->prb_control = 533 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 534 535 siisata_activate_prb(schp, slot); 536 537 for(i = 0; i < (31000/(1000/(wait*hz))); i++) { 538 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 539 PR_PXSS(slot)) 540 break; 541 else 542 cv_timedwait(&cv, &mtx, wait); 543 } 544 545 siisata_deactivate_prb(schp, slot); 546 547 log(LOG_DEBUG, "%s: ch_status %x ch_error %x\n", 548 __func__, chp->ch_status, chp->ch_error); 549 550 #if 1 551 /* attempt to downgrade signaling in event of CRC error */ 552 /* XXX should be part of the MI (S)ATA subsystem */ 553 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 554 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 555 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 556 DELAY(10); 557 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 558 SControl_IPM_NONE | SControl_SPD_G1); 559 DELAY(10); 560 for (;;) { 561 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 562 & SStatus_DET_mask) == SStatus_DET_DEV) 563 break; 564 DELAY(10); 565 } 566 } 567 #endif 568 569 #if 1 570 chp->ch_status = 0; 571 chp->ch_error = 0; 572 #endif 573 574 cv_destroy(&cv); 575 mutex_destroy(&mtx); 576 577 return; 578 } 579 580 void 581 siisata_reset_channel(struct ata_channel *chp, int flags) 582 { 583 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 584 struct siisata_channel *schp = (struct siisata_channel *)chp; 585 586 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 587 DEBUG_FUNCS); 588 589 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 590 schp->sch_sstatus) != SStatus_DET_DEV) { 591 log(LOG_CRIT, "%s port %d: reset failed\n", 592 SIISATANAME(sc), chp->ch_channel); 593 /* XXX and then ? */ 594 } 595 /* wait for ready */ 596 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 597 DELAY(10); 598 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 599 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 600 if (chp->ch_queue->active_xfer) { 601 chp->ch_queue->active_xfer->c_kill_xfer(chp, 602 chp->ch_queue->active_xfer, KILL_RESET); 603 } 604 605 return; 606 } 607 608 int 609 siisata_ata_addref(struct ata_drive_datas *drvp) 610 { 611 return 0; 612 } 613 614 void 615 siisata_ata_delref(struct ata_drive_datas *drvp) 616 { 617 return; 618 } 619 620 void 621 siisata_killpending(struct ata_drive_datas *drvp) 622 { 623 return; 624 } 625 626 void 627 siisata_probe_drive(struct ata_channel *chp) 628 { 629 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 630 struct siisata_channel *schp = (struct siisata_channel *)chp; 631 int i; 632 int s; 633 uint32_t sig; 634 int slot = SIISATA_NON_NCQ_SLOT; 635 struct siisata_prb *prb; 636 kmutex_t mtx; 637 kcondvar_t cv; 638 int wait; 639 640 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 641 __func__, chp->ch_channel), DEBUG_FUNCS); 642 643 /* XXX This should be done by other code. */ 644 for (i = 0; i < chp->ch_ndrive; i++) { 645 chp->ch_drive[i].chnl_softc = chp; 646 chp->ch_drive[i].drive = i; 647 } 648 649 mutex_init(&mtx, MUTEX_DEFAULT, IPL_NONE); 650 cv_init(&cv, "siipd"); 651 652 wait = mstohz(10); 653 wait = wait ? wait : 1; 654 655 switch (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 656 schp->sch_sstatus)) { 657 case SStatus_DET_DEV: 658 /* wait for ready */ 659 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) 660 & PR_PS_PORT_READY)) 661 DELAY(10); 662 663 prb = schp->sch_prb[slot]; 664 memset(prb, 0, sizeof(struct siisata_prb)); 665 prb->prb_control = 666 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 667 668 siisata_activate_prb(schp, slot); 669 670 for(i = 0; i < (31000/(1000/(wait*hz))); i++) { 671 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 672 PR_PXSS(slot)) 673 break; 674 else 675 cv_timedwait(&cv, &mtx, wait); 676 } 677 678 siisata_deactivate_prb(schp, slot); 679 680 /* read the signature out of the FIS */ 681 sig = 0; 682 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 683 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 684 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 685 PRSO_FIS+0xc)) & 0xff; 686 687 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 688 __func__, sig), DEBUG_PROBE); 689 690 /* some ATAPI devices have bogus lower two bytes, sigh */ 691 if ((sig & 0xffff0000) == 0xeb140000) { 692 sig &= 0xffff0000; 693 sig |= 0x00000101; 694 } 695 696 s = splbio(); 697 switch (sig) { 698 case 0xeb140101: 699 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 700 break; 701 case 0x00000101: 702 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 703 break; 704 default: 705 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 706 aprint_verbose_dev(sc->sc_atac.atac_dev, 707 "Unrecognized signature 0x%08x on port %d. " 708 "Assuming it's a disk.\n", sig, chp->ch_channel); 709 break; 710 } 711 splx(s); 712 break; 713 default: 714 break; 715 } 716 717 cv_destroy(&cv); 718 mutex_destroy(&mtx); 719 720 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 721 __func__, chp->ch_channel), DEBUG_PROBE); 722 return; 723 } 724 725 void 726 siisata_setup_channel(struct ata_channel *chp) 727 { 728 return; 729 } 730 731 int 732 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 733 { 734 struct ata_channel *chp = drvp->chnl_softc; 735 struct ata_xfer *xfer; 736 int ret; 737 int s; 738 739 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 740 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 741 DEBUG_FUNCS); 742 743 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? 744 ATAXF_CANSLEEP : ATAXF_NOSLEEP); 745 if (xfer == NULL) 746 return ATACMD_TRY_AGAIN; 747 if (ata_c->flags & AT_POLL) 748 xfer->c_flags |= C_POLL; 749 if (ata_c->flags & AT_WAIT) 750 xfer->c_flags |= C_WAIT; 751 xfer->c_drive = drvp->drive; 752 xfer->c_databuf = ata_c->data; 753 xfer->c_bcount = ata_c->bcount; 754 xfer->c_cmd = ata_c; 755 xfer->c_start = siisata_cmd_start; 756 xfer->c_intr = siisata_cmd_complete; 757 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 758 s = splbio(); 759 ata_exec_xfer(chp, xfer); 760 #ifdef DIAGNOSTIC 761 if ((ata_c->flags & AT_POLL) != 0 && 762 (ata_c->flags & AT_DONE) == 0) 763 panic("%s: polled command not done", __func__); 764 #endif 765 if (ata_c->flags & AT_DONE) { 766 ret = ATACMD_COMPLETE; 767 } else { 768 if (ata_c->flags & AT_WAIT) { 769 while ((ata_c->flags & AT_DONE) == 0) { 770 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 771 SIISATANAME( 772 (struct siisata_softc *)chp->ch_atac), 773 __func__), DEBUG_FUNCS); 774 tsleep(ata_c, PRIBIO, "siicmd", 0); 775 } 776 ret = ATACMD_COMPLETE; 777 } else { 778 ret = ATACMD_QUEUED; 779 } 780 } 781 splx(s); 782 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 783 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 784 DEBUG_FUNCS); 785 return ret; 786 } 787 788 void 789 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 790 { 791 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 792 struct siisata_channel *schp = (struct siisata_channel *)chp; 793 struct ata_command *ata_c = xfer->c_cmd; 794 int slot = SIISATA_NON_NCQ_SLOT; 795 struct siisata_prb *prb; 796 int i; 797 798 SIISATA_DEBUG_PRINT(("%s: %s port %d, slot %d\n", 799 SIISATANAME(sc), __func__, chp->ch_channel, slot), DEBUG_FUNCS); 800 801 prb = schp->sch_prb[slot]; 802 memset(prb, 0, sizeof(struct siisata_prb)); 803 804 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 805 806 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 807 808 if (siisata_dma_setup(chp, slot, 809 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 810 ata_c->bcount, 811 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 812 ata_c->flags |= AT_DF; 813 siisata_cmd_complete(chp, xfer, slot); 814 return; 815 } 816 817 if (xfer->c_flags & C_POLL) { 818 /* polled command, disable interrupts */ 819 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 820 } 821 822 /* go for it */ 823 siisata_activate_prb(schp, slot); 824 825 if ((ata_c->flags & AT_POLL) == 0) { 826 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 827 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 828 siisata_timeout, chp); 829 goto out; 830 } 831 832 /* 833 * polled command 834 */ 835 for (i = 0; i < ata_c->timeout / 10; i++) { 836 if (ata_c->flags & AT_DONE) 837 break; 838 siisata_intr_port(schp); 839 DELAY(10000); 840 } 841 842 if ((ata_c->flags & AT_DONE) == 0) { 843 ata_c->flags |= AT_TIMEOU; 844 siisata_cmd_complete(chp, xfer, slot); 845 } 846 847 /* reenable interrupts */ 848 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 849 out: 850 SIISATA_DEBUG_PRINT( 851 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 852 return; 853 } 854 855 void 856 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 857 int reason) 858 { 859 int slot = SIISATA_NON_NCQ_SLOT; 860 861 struct ata_command *ata_c = xfer->c_cmd; 862 switch (reason) { 863 case KILL_GONE: 864 ata_c->flags |= AT_GONE; 865 break; 866 case KILL_RESET: 867 ata_c->flags |= AT_RESET; 868 break; 869 default: 870 panic("%s: port %d: unknown reason %d", 871 __func__, chp->ch_channel, reason); 872 } 873 siisata_cmd_done(chp, xfer, slot); 874 } 875 876 int 877 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 878 { 879 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 880 struct ata_command *ata_c = xfer->c_cmd; 881 882 SIISATA_DEBUG_PRINT( 883 ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 884 885 chp->ch_flags &= ~ATACH_IRQ_WAIT; 886 if (xfer->c_flags & C_TIMEOU) 887 ata_c->flags |= AT_TIMEOU; 888 else 889 callout_stop(&chp->ch_callout); 890 891 892 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 893 siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); 894 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 895 wakeup(&chp->ch_queue->active_xfer); 896 return 0; 897 } 898 899 chp->ch_queue->active_xfer = NULL; 900 901 { 902 ata_c->r_head = 0; 903 ata_c->r_count = 0; 904 ata_c->r_sector = 0; 905 ata_c->r_cyl = 0; 906 if (chp->ch_status & WDCS_BSY) { 907 ata_c->flags |= AT_TIMEOU; 908 } else if (chp->ch_status & WDCS_ERR) { 909 ata_c->r_error = chp->ch_error; 910 ata_c->flags |= AT_ERROR; 911 } 912 } 913 siisata_cmd_done(chp, xfer, slot); 914 return 0; 915 } 916 917 void 918 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 919 { 920 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 921 struct siisata_channel *schp = (struct siisata_channel *)chp; 922 struct ata_command *ata_c = xfer->c_cmd; 923 int i; 924 uint16_t *idwordbuf; 925 926 SIISATA_DEBUG_PRINT( 927 ("%s: %s.\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 928 929 siisata_deactivate_prb(schp, slot); 930 931 if (ata_c->flags & (AT_READ | AT_WRITE)) { 932 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 933 schp->sch_datad[slot]->dm_mapsize, 934 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 935 BUS_DMASYNC_POSTWRITE); 936 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 937 } 938 939 idwordbuf = xfer->c_databuf; 940 941 /* correct the endianess of IDENTIFY data */ 942 if (ata_c->r_command == WDCC_IDENTIFY || 943 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 944 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 945 idwordbuf[i] = le16toh(idwordbuf[i]); 946 } 947 } 948 949 ata_c->flags |= AT_DONE; 950 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 951 ata_c->flags |= AT_XFDONE; 952 953 ata_free_xfer(chp, xfer); 954 if (ata_c->flags & AT_WAIT) 955 wakeup(ata_c); 956 else if (ata_c->callback) 957 ata_c->callback(ata_c->callback_arg); 958 atastart(chp); 959 return; 960 } 961 962 int 963 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 964 { 965 struct ata_channel *chp = drvp->chnl_softc; 966 struct ata_xfer *xfer; 967 968 SIISATA_DEBUG_PRINT( ("%s: %s.\n", 969 SIISATANAME((struct siisata_softc *)chp->ch_atac), 970 __func__), DEBUG_FUNCS); 971 972 xfer = ata_get_xfer(ATAXF_NOSLEEP); 973 if (xfer == NULL) 974 return ATACMD_TRY_AGAIN; 975 if (ata_bio->flags & ATA_POLL) 976 xfer->c_flags |= C_POLL; 977 xfer->c_drive = drvp->drive; 978 xfer->c_cmd = ata_bio; 979 xfer->c_databuf = ata_bio->databuf; 980 xfer->c_bcount = ata_bio->bcount; 981 xfer->c_start = siisata_bio_start; 982 xfer->c_intr = siisata_bio_complete; 983 xfer->c_kill_xfer = siisata_bio_kill_xfer; 984 ata_exec_xfer(chp, xfer); 985 return (ata_bio->flags & ATA_ITSDONE) ? 986 ATACMD_COMPLETE : ATACMD_QUEUED; 987 } 988 989 void 990 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 991 { 992 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 993 struct siisata_channel *schp = (struct siisata_channel *)chp; 994 struct siisata_prb *prb; 995 struct ata_bio *ata_bio = xfer->c_cmd; 996 int slot = SIISATA_NON_NCQ_SLOT; 997 int i; 998 999 SIISATA_DEBUG_PRINT( 1000 ("%s: %s port %d, slot %d\n", 1001 SIISATANAME(sc), __func__, chp->ch_channel, slot), 1002 DEBUG_FUNCS); 1003 1004 prb = schp->sch_prb[slot]; 1005 memset(prb, 0, sizeof(struct siisata_prb)); 1006 1007 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1008 1009 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 1010 1011 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1012 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1013 ata_bio->error = ERR_DMA; 1014 ata_bio->r_error = 0; 1015 siisata_bio_complete(chp, xfer, slot); 1016 return; 1017 } 1018 1019 if (xfer->c_flags & C_POLL) { 1020 /* polled command, disable interrupts */ 1021 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1022 } 1023 1024 siisata_activate_prb(schp, slot); 1025 1026 if ((ata_bio->flags & ATA_POLL) == 0) { 1027 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1028 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1029 siisata_timeout, chp); 1030 goto out; 1031 } 1032 1033 /* 1034 * polled command 1035 */ 1036 for (i = 0; i < ATA_DELAY / 10; i++) { 1037 if (ata_bio->flags & ATA_ITSDONE) 1038 break; 1039 siisata_intr_port(schp); 1040 DELAY(10000); 1041 } 1042 1043 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1044 out: 1045 SIISATA_DEBUG_PRINT( 1046 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1047 return; 1048 } 1049 1050 void 1051 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1052 int reason) 1053 { 1054 struct siisata_channel *schp = (struct siisata_channel *)chp; 1055 struct ata_bio *ata_bio = xfer->c_cmd; 1056 int drive = xfer->c_drive; 1057 int slot = SIISATA_NON_NCQ_SLOT; 1058 1059 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1060 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1061 __func__, chp->ch_channel), DEBUG_FUNCS); 1062 1063 siisata_deactivate_prb(schp, slot); 1064 1065 ata_free_xfer(chp, xfer); 1066 ata_bio->flags |= ATA_ITSDONE; 1067 switch (reason) { 1068 case KILL_GONE: 1069 ata_bio->error = ERR_NODEV; 1070 break; 1071 case KILL_RESET: 1072 ata_bio->error = ERR_RESET; 1073 break; 1074 default: 1075 panic("%s: port %d: unknown reason %d", 1076 __func__, chp->ch_channel, reason); 1077 } 1078 ata_bio->r_error = WDCE_ABRT; 1079 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1080 } 1081 1082 int 1083 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1084 { 1085 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1086 struct siisata_channel *schp = (struct siisata_channel *)chp; 1087 struct ata_bio *ata_bio = xfer->c_cmd; 1088 int drive = xfer->c_drive; 1089 1090 schp->sch_active_slots &= ~__BIT(slot); 1091 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1092 if (xfer->c_flags & C_TIMEOU) { 1093 ata_bio->error = TIMEOUT; 1094 } else { 1095 callout_stop(&chp->ch_callout); 1096 ata_bio->error = NOERROR; 1097 } 1098 1099 chp->ch_queue->active_xfer = NULL; 1100 1101 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1102 schp->sch_datad[slot]->dm_mapsize, 1103 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1104 BUS_DMASYNC_POSTWRITE); 1105 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1106 1107 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1108 siisata_bio_kill_xfer(chp, xfer, KILL_GONE); 1109 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1110 wakeup(&chp->ch_queue->active_xfer); 1111 return 0; 1112 } 1113 ata_free_xfer(chp, xfer); 1114 ata_bio->flags |= ATA_ITSDONE; 1115 if (chp->ch_status & WDCS_DWF) { 1116 ata_bio->error = ERR_DF; 1117 } else if (chp->ch_status & WDCS_ERR) { 1118 ata_bio->error = ERROR; 1119 ata_bio->r_error = chp->ch_error; 1120 } else if (chp->ch_status & WDCS_CORR) 1121 ata_bio->flags |= ATA_CORR; 1122 1123 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), 1124 __func__, ata_bio->bcount), DEBUG_XFERS); 1125 if ((ata_bio->flags & ATA_READ) || (ata_bio->error == NOERROR)) 1126 ata_bio->bcount -= PRREAD(sc, 1127 PRSX(chp->ch_channel, slot, PRSO_RTC)); 1128 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1129 if (ata_bio->flags & ATA_POLL) 1130 return 1; 1131 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1132 atastart(chp); 1133 return 0; 1134 } 1135 1136 void 1137 siisata_timeout(void *v) 1138 { 1139 struct ata_channel *chp = (struct ata_channel *)v; 1140 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1141 int slot = SIISATA_NON_NCQ_SLOT; 1142 int s = splbio(); 1143 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1144 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1145 xfer->c_flags |= C_TIMEOU; 1146 xfer->c_intr(chp, xfer, slot); 1147 } 1148 splx(s); 1149 } 1150 1151 static int 1152 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1153 size_t count, int op) 1154 { 1155 1156 int error, seg; 1157 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1158 struct siisata_channel *schp = (struct siisata_channel *)chp; 1159 1160 struct siisata_prb *prbp; 1161 1162 prbp = schp->sch_prb[slot]; 1163 1164 if (data == NULL) { 1165 goto end; 1166 } 1167 1168 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1169 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1170 if (error) { 1171 log(LOG_ERR, "%s port %d: " 1172 "failed to load xfer in slot %d: error %d\n", 1173 SIISATANAME(sc), chp->ch_channel, slot, error); 1174 return error; 1175 } 1176 1177 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1178 schp->sch_datad[slot]->dm_mapsize, 1179 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1180 1181 /* make sure it's clean */ 1182 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1183 1184 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1185 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1186 DEBUG_FUNCS | DEBUG_DEBUG); 1187 1188 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1189 prbp->prb_sge[seg].sge_da = 1190 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1191 prbp->prb_sge[seg].sge_dc = 1192 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1193 prbp->prb_sge[seg].sge_flags = htole32(0); 1194 } 1195 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1196 end: 1197 return 0; 1198 } 1199 1200 static void 1201 siisata_activate_prb(struct siisata_channel *schp, int slot) 1202 { 1203 struct siisata_softc *sc; 1204 bus_size_t offset; 1205 bus_addr_t pprb; 1206 int port; 1207 1208 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1209 1210 KASSERTMSG(((schp->sch_active_slots & __BIT(slot)) == __BIT(slot)), 1211 ("%s: trying to activate active slot %d", SIISATANAME(sc), slot)); 1212 1213 port = schp->ata_channel.ch_channel; 1214 1215 offset = PRO_CARX(port, slot); 1216 1217 pprb = schp->sch_bus_prb[slot]; 1218 1219 1220 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1221 /* keep track of what's going on */ 1222 schp->sch_active_slots |= __BIT(slot); 1223 1224 1225 PRWRITE(sc, offset, pprb); 1226 offset += 4; 1227 #if 0 1228 if (sizeof(bus_addr_t) == 8) 1229 PRWRITE(sc, offset, (pprb >> 32)); 1230 else 1231 #endif 1232 PRWRITE(sc, offset, 0); 1233 } 1234 1235 static void 1236 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1237 { 1238 struct siisata_softc *sc; 1239 1240 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1241 1242 KASSERTMSG(((schp->sch_active_slots & __BIT(slot)) == 0), 1243 ("%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1244 slot)); 1245 1246 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1247 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1248 } 1249 1250 static void 1251 siisata_reinit_port(struct ata_channel *chp) 1252 { 1253 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1254 1255 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 1256 PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) | PR_PC_PORT_INITIALIZE); 1257 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 1258 DELAY(10); 1259 } 1260 1261 static void 1262 siisata_device_reset(struct ata_channel *chp) 1263 { 1264 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1265 1266 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 1267 PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) | PR_PC_DEVICE_RESET); 1268 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PCS)) & PR_PS_PORT_READY)) 1269 DELAY(10); 1270 } 1271 1272 1273 #if NATAPIBUS > 0 1274 void 1275 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1276 { 1277 struct ata_channel *chp = ata_sc->sc_chan; 1278 struct atac_softc *atac = chp->ch_atac; 1279 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1280 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1281 1282 /* 1283 * Fill in the scsipi_adapter. 1284 */ 1285 adapt->adapt_dev = atac->atac_dev; 1286 adapt->adapt_nchannels = atac->atac_nchannels; 1287 adapt->adapt_request = siisata_atapi_scsipi_request; 1288 adapt->adapt_minphys = siisata_atapi_minphys; 1289 atac->atac_atapi_adapter.atapi_probe_device = 1290 siisata_atapi_probe_device; 1291 1292 /* 1293 * Fill in the scsipi_channel. 1294 */ 1295 memset(chan, 0, sizeof(*chan)); 1296 chan->chan_adapter = adapt; 1297 chan->chan_bustype = &siisata_atapi_bustype; 1298 chan->chan_channel = chp->ch_channel; 1299 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1300 chan->chan_openings = 1; 1301 chan->chan_max_periph = 1; 1302 chan->chan_ntargets = 1; 1303 chan->chan_nluns = 1; 1304 1305 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1306 atapiprint); 1307 } 1308 1309 void 1310 siisata_atapi_minphys(struct buf *bp) 1311 { 1312 if (bp->b_bcount > MAXPHYS) 1313 bp->b_bcount = MAXPHYS; 1314 minphys(bp); 1315 } 1316 1317 /* 1318 * Kill off all pending xfers for a periph. 1319 * 1320 * Must be called at splbio(). 1321 */ 1322 void 1323 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1324 { 1325 struct atac_softc *atac = 1326 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1327 struct ata_channel *chp = 1328 atac->atac_channels[periph->periph_channel->chan_channel]; 1329 1330 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1331 } 1332 1333 void 1334 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1335 int reason) 1336 { 1337 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1338 1339 /* remove this command from xfer queue */ 1340 switch (reason) { 1341 case KILL_GONE: 1342 sc_xfer->error = XS_DRIVER_STUFFUP; 1343 break; 1344 case KILL_RESET: 1345 sc_xfer->error = XS_RESET; 1346 break; 1347 default: 1348 panic("%s: port %d: unknown reason %d", 1349 __func__, chp->ch_channel, reason); 1350 } 1351 ata_free_xfer(chp, xfer); 1352 scsipi_done(sc_xfer); 1353 } 1354 1355 void 1356 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1357 { 1358 struct scsipi_channel *chan = sc->sc_channel; 1359 struct scsipi_periph *periph; 1360 struct ataparams ids; 1361 struct ataparams *id = &ids; 1362 struct siisata_softc *siic = 1363 device_private(chan->chan_adapter->adapt_dev); 1364 struct atac_softc *atac = &siic->sc_atac; 1365 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1366 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1367 struct scsipibus_attach_args sa; 1368 char serial_number[21], model[41], firmware_revision[9]; 1369 int s; 1370 1371 /* skip if already attached */ 1372 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1373 return; 1374 1375 /* if no ATAPI device detected at attach time, skip */ 1376 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1377 SIISATA_DEBUG_PRINT(("%s: drive %d " 1378 "not present\n", __func__, target), DEBUG_PROBE); 1379 return; 1380 } 1381 1382 /* Some ATAPI devices need a bit more time after software reset. */ 1383 delay(5000); 1384 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1385 #ifdef ATAPI_DEBUG_PROBE 1386 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1387 device_xname(sc->sc_dev), target, 1388 id->atap_config & ATAPI_CFG_CMD_MASK, 1389 id->atap_config & ATAPI_CFG_DRQ_MASK); 1390 #endif 1391 periph = scsipi_alloc_periph(M_NOWAIT); 1392 if (periph == NULL) { 1393 aprint_error_dev(sc->sc_dev, 1394 "%s: unable to allocate periph for " 1395 "channel %d drive %d\n", __func__, 1396 chp->ch_channel, target); 1397 return; 1398 } 1399 periph->periph_dev = NULL; 1400 periph->periph_channel = chan; 1401 periph->periph_switch = &atapi_probe_periphsw; 1402 periph->periph_target = target; 1403 periph->periph_lun = 0; 1404 periph->periph_quirks = PQUIRK_ONLYBIG; 1405 1406 #ifdef SCSIPI_DEBUG 1407 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1408 SCSIPI_DEBUG_TARGET == target) 1409 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1410 #endif 1411 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1412 if (id->atap_config & ATAPI_CFG_REMOV) 1413 periph->periph_flags |= PERIPH_REMOVABLE; 1414 if (periph->periph_type == T_SEQUENTIAL) { 1415 s = splbio(); 1416 drvp->drive_flags |= DRIVE_ATAPIST; 1417 splx(s); 1418 } 1419 1420 sa.sa_periph = periph; 1421 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1422 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1423 T_REMOV : T_FIXED; 1424 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1425 scsipi_strvis((u_char *)serial_number, 20, 1426 id->atap_serial, 20); 1427 scsipi_strvis((u_char *)firmware_revision, 8, 1428 id->atap_revision, 8); 1429 sa.sa_inqbuf.vendor = model; 1430 sa.sa_inqbuf.product = serial_number; 1431 sa.sa_inqbuf.revision = firmware_revision; 1432 1433 /* 1434 * Determine the operating mode capabilities of the device. 1435 */ 1436 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1437 == ATAPI_CFG_CMD_16) { 1438 periph->periph_cap |= PERIPH_CAP_CMD16; 1439 1440 /* configure port for packet length */ 1441 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1442 PRREAD(siic, PRX(chp->ch_channel, PRO_PCS)) | 1443 PR_PC_PACKET_LENGTH); 1444 } 1445 /* XXX This is gross. */ 1446 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1447 1448 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1449 1450 if (drvp->drv_softc) 1451 ata_probe_caps(drvp); 1452 else { 1453 s = splbio(); 1454 drvp->drive_flags &= ~DRIVE_ATAPI; 1455 splx(s); 1456 } 1457 } else { 1458 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1459 "failed for drive %s:%d:%d: error 0x%x\n", 1460 __func__, SIISATANAME(siic), chp->ch_channel, target, 1461 chp->ch_error), DEBUG_PROBE); 1462 s = splbio(); 1463 drvp->drive_flags &= ~DRIVE_ATAPI; 1464 splx(s); 1465 } 1466 } 1467 1468 void 1469 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1470 scsipi_adapter_req_t req, void *arg) 1471 { 1472 struct scsipi_adapter *adapt = chan->chan_adapter; 1473 struct scsipi_periph *periph; 1474 struct scsipi_xfer *sc_xfer; 1475 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1476 struct atac_softc *atac = &sc->sc_atac; 1477 struct ata_xfer *xfer; 1478 int channel = chan->chan_channel; 1479 int drive, s; 1480 1481 switch (req) { 1482 case ADAPTER_REQ_RUN_XFER: 1483 sc_xfer = arg; 1484 periph = sc_xfer->xs_periph; 1485 drive = periph->periph_target; 1486 1487 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1488 device_xname(atac->atac_dev), channel, drive), 1489 DEBUG_XFERS); 1490 1491 if (!device_is_active(atac->atac_dev)) { 1492 sc_xfer->error = XS_DRIVER_STUFFUP; 1493 scsipi_done(sc_xfer); 1494 return; 1495 } 1496 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1497 if (xfer == NULL) { 1498 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1499 scsipi_done(sc_xfer); 1500 return; 1501 } 1502 1503 if (sc_xfer->xs_control & XS_CTL_POLL) 1504 xfer->c_flags |= C_POLL; 1505 xfer->c_drive = drive; 1506 xfer->c_flags |= C_ATAPI; 1507 xfer->c_cmd = sc_xfer; 1508 xfer->c_databuf = sc_xfer->data; 1509 xfer->c_bcount = sc_xfer->datalen; 1510 xfer->c_start = siisata_atapi_start; 1511 xfer->c_intr = siisata_atapi_complete; 1512 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1513 xfer->c_dscpoll = 0; 1514 s = splbio(); 1515 ata_exec_xfer(atac->atac_channels[channel], xfer); 1516 #ifdef DIAGNOSTIC 1517 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1518 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1519 panic("%s: polled command not done", __func__); 1520 #endif 1521 splx(s); 1522 return; 1523 1524 default: 1525 /* Not supported, nothing to do. */ 1526 ; 1527 } 1528 } 1529 1530 void 1531 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1532 { 1533 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1534 struct siisata_channel *schp = (struct siisata_channel *)chp; 1535 struct siisata_prb *prbp; 1536 1537 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1538 1539 int slot = SIISATA_NON_NCQ_SLOT; 1540 int i; 1541 1542 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1543 SIISATANAME(sc), chp->ch_channel, 1544 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1545 DEBUG_XFERS); 1546 1547 prbp = schp->sch_prb[slot]; 1548 memset(prbp, 0, sizeof(struct siisata_prb)); 1549 1550 1551 /* fill in direction for ATAPI command */ 1552 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1553 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1554 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1555 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1556 1557 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1558 1559 /* copy over ATAPI command */ 1560 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1561 1562 if (siisata_dma_setup(chp, slot, 1563 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1564 xfer->c_databuf : NULL, 1565 xfer->c_bcount, 1566 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1567 BUS_DMA_READ : BUS_DMA_WRITE) 1568 ) 1569 panic("%s", __func__); 1570 1571 if (xfer->c_flags & C_POLL) { 1572 /* polled command, disable interrupts */ 1573 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1574 } 1575 1576 siisata_activate_prb(schp, slot); 1577 1578 if ((xfer->c_flags & C_POLL) == 0) { 1579 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1580 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1581 siisata_timeout, chp); 1582 goto out; 1583 } 1584 1585 /* 1586 * polled command 1587 */ 1588 for (i = 0; i < ATA_DELAY / 10; i++) { 1589 if (sc_xfer->xs_status & XS_STS_DONE) 1590 break; 1591 siisata_intr_port(schp); 1592 DELAY(10000); 1593 } 1594 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1595 sc_xfer->error = XS_TIMEOUT; 1596 siisata_atapi_complete(chp, xfer, slot); 1597 } 1598 /* reenable interrupts */ 1599 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1600 out: 1601 SIISATA_DEBUG_PRINT( 1602 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1603 return; 1604 } 1605 1606 int 1607 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1608 int slot) 1609 { 1610 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1611 struct siisata_channel *schp = (struct siisata_channel *)chp; 1612 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1613 1614 SIISATA_DEBUG_PRINT( 1615 ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1616 1617 /* this comamnd is not active any more */ 1618 schp->sch_active_slots &= ~__BIT(slot); 1619 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1620 if (xfer->c_flags & C_TIMEOU) { 1621 sc_xfer->error = XS_TIMEOUT; 1622 } else { 1623 callout_stop(&chp->ch_callout); 1624 sc_xfer->error = XS_NOERROR; 1625 } 1626 1627 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1628 schp->sch_datad[slot]->dm_mapsize, 1629 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1630 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1631 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1632 1633 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1634 siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); 1635 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1636 wakeup(&chp->ch_queue->active_xfer); 1637 return 0; /* XXX verify */ 1638 } 1639 1640 chp->ch_queue->active_xfer = NULL; 1641 ata_free_xfer(chp, xfer); 1642 1643 sc_xfer->resid = sc_xfer->datalen; 1644 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1645 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1646 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1647 if ((chp->ch_status & WDCS_ERR) && 1648 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1649 sc_xfer->resid == sc_xfer->datalen)) { 1650 sc_xfer->error = XS_SHORTSENSE; 1651 sc_xfer->sense.atapi_sense = chp->ch_error; 1652 if ((sc_xfer->xs_periph->periph_quirks & 1653 PQUIRK_NOSENSE) == 0) { 1654 /* request sense */ 1655 sc_xfer->error = XS_BUSY; 1656 sc_xfer->status = SCSI_CHECK; 1657 } 1658 } 1659 scsipi_done(sc_xfer); 1660 atastart(chp); 1661 return 0; /* XXX verify */ 1662 } 1663 1664 #endif /* NATAPIBUS */ 1665
Indexes created Tue Sep 30 10:09:55 GMT 2025