siisata.c revision 1.30.4.11
1 /* $NetBSD: siisata.c,v 1.30.4.11 2017/04/23 14:33:28 jakllsch Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.30.4.11 2017/04/23 14:33:28 jakllsch Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 113 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 114 #if _BYTE_ORDER == _LITTLE_ENDIAN 115 #define bus_space_read_stream_4 bus_space_read_4 116 #define bus_space_read_region_stream_4 bus_space_read_region_4 117 #else 118 static inline uint32_t 119 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 120 { 121 return htole32(bus_space_read_4(t, h, o)); 122 } 123 124 static inline void 125 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint32_t *p, bus_size_t c) 126 { 127 bus_space_read_region_4(t, h, o, p, c); 128 for (bus_size_t i = 0; i < c; i++) { 129 p[i] = htole32(p[i]); 130 } 131 } 132 #endif 133 #endif 134 135 static void siisata_attach_port(struct siisata_softc *, int); 136 static void siisata_intr_port(struct siisata_channel *); 137 138 void siisata_probe_drive(struct ata_channel *); 139 void siisata_setup_channel(struct ata_channel *); 140 141 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 142 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 143 void siisata_reset_channel(struct ata_channel *, int); 144 int siisata_ata_addref(struct ata_drive_datas *); 145 void siisata_ata_delref(struct ata_drive_datas *); 146 void siisata_killpending(struct ata_drive_datas *); 147 148 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 149 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 150 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 151 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 152 153 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 154 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 155 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 156 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 157 158 void siisata_timeout(void *); 159 160 static void siisata_reinit_port(struct ata_channel *); 161 static void siisata_device_reset(struct ata_channel *); 162 static void siisata_activate_prb(struct siisata_channel *, int); 163 static void siisata_deactivate_prb(struct siisata_channel *, int); 164 static int siisata_dma_setup(struct ata_channel *chp, int slot, 165 void *data, size_t, int); 166 167 #if NATAPIBUS > 0 168 void siisata_atapibus_attach(struct atabus_softc *); 169 void siisata_atapi_probe_device(struct atapibus_softc *, int); 170 void siisata_atapi_minphys(struct buf *); 171 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 172 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 173 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 174 void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 175 void siisata_atapi_scsipi_request(struct scsipi_channel *, 176 scsipi_adapter_req_t, void *); 177 void siisata_atapi_kill_pending(struct scsipi_periph *); 178 #endif /* NATAPIBUS */ 179 180 const struct ata_bustype siisata_ata_bustype = { 181 SCSIPI_BUSTYPE_ATA, 182 siisata_ata_bio, 183 siisata_reset_drive, 184 siisata_reset_channel, 185 siisata_exec_command, 186 ata_get_params, 187 siisata_ata_addref, 188 siisata_ata_delref, 189 siisata_killpending 190 }; 191 192 #if NATAPIBUS > 0 193 static const struct scsipi_bustype siisata_atapi_bustype = { 194 SCSIPI_BUSTYPE_ATAPI, 195 atapi_scsipi_cmd, 196 atapi_interpret_sense, 197 atapi_print_addr, 198 siisata_atapi_kill_pending, 199 NULL, 200 }; 201 #endif /* NATAPIBUS */ 202 203 204 void 205 siisata_attach(struct siisata_softc *sc) 206 { 207 int i; 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 211 212 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 213 sc->sc_atac.atac_pio_cap = 4; 214 sc->sc_atac.atac_dma_cap = 2; 215 sc->sc_atac.atac_udma_cap = 6; 216 sc->sc_atac.atac_channels = sc->sc_chanarray; 217 sc->sc_atac.atac_probe = siisata_probe_drive; 218 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 219 sc->sc_atac.atac_set_modes = siisata_setup_channel; 220 #if NATAPIBUS > 0 221 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 222 #endif 223 224 /* come out of reset state */ 225 GRWRITE(sc, GR_GC, 0); 226 227 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 228 siisata_attach_port(sc, i); 229 } 230 231 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 232 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 233 DEBUG_FUNCS); 234 return; 235 } 236 237 static void 238 siisata_disable_port_interrupt(struct ata_channel *chp) 239 { 240 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 241 242 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 243 } 244 245 static void 246 siisata_enable_port_interrupt(struct ata_channel *chp) 247 { 248 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 249 250 /* clear any interrupts */ 251 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 252 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 253 /* and enable CmdErrr+CmdCmpl interrupting */ 254 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 255 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 256 } 257 258 static void 259 siisata_init_port(struct siisata_softc *sc, int port) 260 { 261 struct siisata_channel *schp; 262 struct ata_channel *chp; 263 264 schp = &sc->sc_channels[port]; 265 chp = (struct ata_channel *)schp; 266 267 /* come out of reset, 64-bit activation */ 268 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 269 PR_PC_32BA | PR_PC_PORT_RESET); 270 /* initialize port */ 271 siisata_reinit_port(chp); 272 /* enable CmdErrr+CmdCmpl interrupting */ 273 siisata_enable_port_interrupt(chp); 274 /* enable port interrupt */ 275 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 276 } 277 278 static void 279 siisata_attach_port(struct siisata_softc *sc, int port) 280 { 281 int j; 282 int dmasize; 283 int error; 284 void *prbp; 285 struct siisata_channel *schp; 286 struct ata_channel *chp; 287 288 schp = &sc->sc_channels[port]; 289 chp = (struct ata_channel *)schp; 290 sc->sc_chanarray[port] = chp; 291 chp->ch_channel = port; 292 chp->ch_atac = &sc->sc_atac; 293 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 294 if (chp->ch_queue == NULL) { 295 aprint_error_dev(sc->sc_atac.atac_dev, 296 "port %d: can't allocate memory " 297 "for command queue\n", chp->ch_channel); 298 return; 299 } 300 301 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 302 303 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 304 __func__, dmasize), DEBUG_FUNCS); 305 306 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 307 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 308 if (error) { 309 aprint_error_dev(sc->sc_atac.atac_dev, 310 "unable to allocate PRB table memory, " 311 "error=%d\n", error); 312 return; 313 } 314 315 error = bus_dmamem_map(sc->sc_dmat, 316 &schp->sch_prb_seg, schp->sch_prb_nseg, 317 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 318 if (error) { 319 aprint_error_dev(sc->sc_atac.atac_dev, 320 "unable to map PRB table memory, " 321 "error=%d\n", error); 322 bus_dmamem_free(sc->sc_dmat, 323 &schp->sch_prb_seg, schp->sch_prb_nseg); 324 return; 325 } 326 327 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 328 BUS_DMA_NOWAIT, &schp->sch_prbd); 329 if (error) { 330 aprint_error_dev(sc->sc_atac.atac_dev, 331 "unable to create PRB table map, " 332 "error=%d\n", error); 333 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 334 bus_dmamem_free(sc->sc_dmat, 335 &schp->sch_prb_seg, schp->sch_prb_nseg); 336 return; 337 } 338 339 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 340 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 341 if (error) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "unable to load PRB table map, " 344 "error=%d\n", error); 345 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 346 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 347 bus_dmamem_free(sc->sc_dmat, 348 &schp->sch_prb_seg, schp->sch_prb_nseg); 349 return; 350 } 351 352 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 353 schp->sch_prb[j] = (struct siisata_prb *) 354 ((char *)prbp + SIISATA_CMD_SIZE * j); 355 schp->sch_bus_prb[j] = 356 schp->sch_prbd->dm_segs[0].ds_addr + 357 SIISATA_CMD_SIZE * j; 358 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 359 SIISATA_NSGE, MAXPHYS, 0, 360 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 361 &schp->sch_datad[j]); 362 if (error) { 363 aprint_error_dev(sc->sc_atac.atac_dev, 364 "couldn't create xfer DMA map, error=%d\n", 365 error); 366 return; 367 } 368 } 369 370 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 371 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 372 aprint_error_dev(sc->sc_atac.atac_dev, 373 "couldn't map port %d SStatus regs\n", 374 chp->ch_channel); 375 return; 376 } 377 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 378 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 379 aprint_error_dev(sc->sc_atac.atac_dev, 380 "couldn't map port %d SControl regs\n", 381 chp->ch_channel); 382 return; 383 } 384 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 385 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 386 aprint_error_dev(sc->sc_atac.atac_dev, 387 "couldn't map port %d SError regs\n", 388 chp->ch_channel); 389 return; 390 } 391 392 siisata_init_port(sc, port); 393 394 ata_channel_attach(chp); 395 396 return; 397 } 398 399 int 400 siisata_detach(struct siisata_softc *sc, int flags) 401 { 402 struct atac_softc *atac = &sc->sc_atac; 403 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 404 struct siisata_channel *schp; 405 struct ata_channel *chp; 406 int i, j, error; 407 408 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 409 schp = &sc->sc_channels[i]; 410 chp = sc->sc_chanarray[i]; 411 412 if (chp->atabus == NULL) 413 continue; 414 if ((error = config_detach(chp->atabus, flags)) != 0) 415 return error; 416 417 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 418 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 419 420 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 421 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 422 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 423 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 424 bus_dmamem_free(sc->sc_dmat, 425 &schp->sch_prb_seg, schp->sch_prb_nseg); 426 427 free(chp->ch_queue, M_DEVBUF); 428 chp->atabus = NULL; 429 } 430 431 if (adapt->adapt_refcnt != 0) 432 return EBUSY; 433 434 /* leave the chip in reset */ 435 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 436 437 return 0; 438 } 439 440 void 441 siisata_resume(struct siisata_softc *sc) 442 { 443 int i; 444 445 /* come out of reset state */ 446 GRWRITE(sc, GR_GC, 0); 447 448 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 449 siisata_init_port(sc, i); 450 } 451 452 } 453 454 int 455 siisata_intr(void *v) 456 { 457 struct siisata_softc *sc = v; 458 uint32_t is; 459 int i, r = 0; 460 while ((is = GRREAD(sc, GR_GIS))) { 461 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 462 SIISATANAME(sc), __func__, is), DEBUG_INTR); 463 r = 1; 464 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 465 if (is & GR_GIS_PXIS(i)) 466 siisata_intr_port(&sc->sc_channels[i]); 467 } 468 return r; 469 } 470 471 static void 472 siisata_intr_port(struct siisata_channel *schp) 473 { 474 struct siisata_softc *sc; 475 struct ata_channel *chp; 476 struct ata_xfer *xfer; 477 int slot; 478 uint32_t pss, pis; 479 uint32_t prbfis; 480 481 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 482 chp = &schp->ata_channel; 483 xfer = ata_queue_hwslot_to_xfer(chp->ch_queue, 0); /* XXX slot */ 484 slot = SIISATA_NON_NCQ_SLOT; 485 486 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 487 488 SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x ", 489 SIISATANAME(sc), __func__, chp->ch_channel, pis), DEBUG_INTR); 490 491 if (pis & PR_PIS_CMDCMPL) { 492 /* get slot status, clearing completion interrupt */ 493 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 494 SIISATA_DEBUG_PRINT(("pss 0x%x\n", pss), DEBUG_INTR); 495 /* is this expected? */ 496 /* XXX improve */ 497 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 498 aprint_error( "%s: unexpected command " 499 "completion on port %d\n", 500 SIISATANAME(sc), chp->ch_channel); 501 return; 502 } 503 if ((~pss & __BIT(slot)) == 0) { 504 aprint_error( "%s: unknown slot " 505 "completion on port %d, pss 0x%x\n", 506 SIISATANAME(sc), chp->ch_channel, pss); 507 return; 508 } 509 } else if (pis & PR_PIS_CMDERRR) { 510 uint32_t ec; 511 512 /* emulate a CRC error by default */ 513 chp->ch_status = WDCS_ERR; 514 chp->ch_error = WDCE_CRC; 515 516 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 517 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 518 if (ec <= PR_PCE_DATAFISERROR) { 519 if (ec == PR_PCE_DEVICEERROR && xfer != NULL) { 520 /* read in specific information about error */ 521 prbfis = bus_space_read_stream_4( 522 sc->sc_prt, sc->sc_prh, 523 PRSX(chp->ch_channel, slot, PRSO_FIS)); 524 /* set ch_status and ch_error */ 525 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 526 } 527 siisata_reinit_port(chp); 528 } else { 529 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 530 " on channel %d (ctx 0x%x), resetting\n", 531 ec, chp->ch_channel, 532 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 533 /* okay, we have a "Fatal Error" */ 534 siisata_device_reset(chp); 535 } 536 } 537 538 /* clear some (ok, all) ints */ 539 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 540 if (xfer && xfer->c_intr) 541 xfer->c_intr(chp, xfer, 0); 542 543 return; 544 } 545 546 void 547 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 548 { 549 struct ata_channel *chp = drvp->chnl_softc; 550 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 551 struct siisata_channel *schp = (struct siisata_channel *)chp; 552 struct siisata_prb *prb; 553 int slot = SIISATA_NON_NCQ_SLOT; 554 int i; 555 556 /* wait for ready */ 557 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 558 DELAY(10); 559 560 prb = schp->sch_prb[slot]; 561 memset(prb, 0, sizeof(struct siisata_prb)); 562 prb->prb_control = 563 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 564 KASSERT(drvp->drive <= PMP_PORT_CTL); 565 prb->prb_fis[rhd_c] = drvp->drive; 566 567 siisata_activate_prb(schp, slot); 568 569 for(i = 0; i < 3100; i++) { 570 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 571 PR_PXSS(slot)) == 0) 572 break; 573 if (flags & AT_WAIT) 574 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 575 else 576 DELAY(10000); 577 } 578 579 siisata_deactivate_prb(schp, slot); 580 if (i == 3100) { 581 /* timeout */ 582 siisata_device_reset(chp); 583 if (sigp) 584 *sigp = 0xffffffff; 585 } else { 586 /* read the signature out of the FIS */ 587 if (sigp) { 588 *sigp = 0; 589 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 590 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 591 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, slot, 592 PRSO_FIS+0xc)) & 0xff; 593 } 594 } 595 596 #if 1 597 /* attempt to downgrade signaling in event of CRC error */ 598 /* XXX should be part of the MI (S)ATA subsystem */ 599 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 600 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 601 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 602 DELAY(10); 603 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 604 SControl_IPM_NONE | SControl_SPD_G1); 605 DELAY(10); 606 for (;;) { 607 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 608 & SStatus_DET_mask) == SStatus_DET_DEV) 609 break; 610 DELAY(10); 611 } 612 } 613 #endif 614 615 #if 1 616 chp->ch_status = 0; 617 chp->ch_error = 0; 618 #endif 619 return; 620 } 621 622 void 623 siisata_reset_channel(struct ata_channel *chp, int flags) 624 { 625 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 626 struct siisata_channel *schp = (struct siisata_channel *)chp; 627 628 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 629 DEBUG_FUNCS); 630 631 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 632 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 633 aprint_error("%s port %d: reset failed\n", 634 SIISATANAME(sc), chp->ch_channel); 635 /* XXX and then ? */ 636 } 637 /* wait for ready */ 638 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 639 DELAY(10); 640 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 641 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 642 ata_kill_active(chp, KILL_RESET); 643 644 return; 645 } 646 647 int 648 siisata_ata_addref(struct ata_drive_datas *drvp) 649 { 650 return 0; 651 } 652 653 void 654 siisata_ata_delref(struct ata_drive_datas *drvp) 655 { 656 return; 657 } 658 659 void 660 siisata_killpending(struct ata_drive_datas *drvp) 661 { 662 return; 663 } 664 665 void 666 siisata_probe_drive(struct ata_channel *chp) 667 { 668 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 669 struct siisata_channel *schp = (struct siisata_channel *)chp; 670 int i; 671 uint32_t sig; 672 int slot = SIISATA_NON_NCQ_SLOT; 673 struct siisata_prb *prb; 674 bool timed_out; 675 676 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 677 __func__, chp->ch_channel), DEBUG_FUNCS); 678 679 /* 680 * disable port interrupt as we're polling for PHY up and 681 * prb completion 682 */ 683 siisata_disable_port_interrupt(chp); 684 685 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 686 schp->sch_sstatus, AT_WAIT)) { 687 case SStatus_DET_DEV: 688 /* clear any interrupts */ 689 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 690 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 691 /* wait for ready */ 692 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 693 & PR_PS_PORT_READY)) 694 DELAY(10); 695 prb = schp->sch_prb[slot]; 696 memset(prb, 0, sizeof(struct siisata_prb)); 697 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 698 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 699 700 siisata_activate_prb(schp, slot); 701 702 timed_out = 1; 703 for(i = 0; i < 3100; i++) { 704 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 705 PR_PXSS(slot)) == 0) { 706 /* prb completed */ 707 timed_out = 0; 708 break; 709 } 710 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 711 (PR_PIS_CMDERRR << 16)) { 712 /* we got an error; handle as timeout */ 713 break; 714 } 715 716 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 717 } 718 719 siisata_deactivate_prb(schp, slot); 720 if (timed_out) { 721 aprint_error_dev(sc->sc_atac.atac_dev, 722 "SOFT_RESET failed on port %d (error %d PSS 0x%x), " 723 "resetting\n", chp->ch_channel, 724 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 725 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); 726 siisata_reinit_port(chp); 727 break; 728 } 729 730 /* read the signature out of the FIS */ 731 sig = 0; 732 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 733 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 734 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 735 PRSO_FIS+0xc)) & 0xff; 736 737 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 738 __func__, sig), DEBUG_PROBE); 739 740 if (sig == 0x96690101) 741 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 742 PR_PC_PMP_ENABLE); 743 sata_interpret_sig(chp, 0, sig); 744 break; 745 default: 746 break; 747 } 748 749 siisata_enable_port_interrupt(chp); 750 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 751 __func__, chp->ch_channel), DEBUG_PROBE); 752 return; 753 } 754 755 void 756 siisata_setup_channel(struct ata_channel *chp) 757 { 758 return; 759 } 760 761 int 762 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 763 { 764 struct ata_channel *chp = drvp->chnl_softc; 765 struct ata_command *ata_c = &xfer->c_ata_c; 766 int ret; 767 int s; 768 769 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 770 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 771 DEBUG_FUNCS); 772 773 if (ata_c->flags & AT_POLL) 774 xfer->c_flags |= C_POLL; 775 if (ata_c->flags & AT_WAIT) 776 xfer->c_flags |= C_WAIT; 777 xfer->c_drive = drvp->drive; 778 xfer->c_databuf = ata_c->data; 779 xfer->c_bcount = ata_c->bcount; 780 xfer->c_start = siisata_cmd_start; 781 xfer->c_intr = siisata_cmd_complete; 782 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 783 s = splbio(); 784 ata_exec_xfer(chp, xfer); 785 #ifdef DIAGNOSTIC 786 if ((ata_c->flags & AT_POLL) != 0 && 787 (ata_c->flags & AT_DONE) == 0) 788 panic("%s: polled command not done", __func__); 789 #endif 790 if (ata_c->flags & AT_DONE) { 791 ret = ATACMD_COMPLETE; 792 } else { 793 if (ata_c->flags & AT_WAIT) { 794 while ((ata_c->flags & AT_DONE) == 0) { 795 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 796 SIISATANAME( 797 (struct siisata_softc *)chp->ch_atac), 798 __func__), DEBUG_FUNCS); 799 tsleep(ata_c, PRIBIO, "siicmd", 0); 800 } 801 ret = ATACMD_COMPLETE; 802 } else { 803 ret = ATACMD_QUEUED; 804 } 805 } 806 splx(s); 807 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 808 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 809 DEBUG_FUNCS); 810 return ret; 811 } 812 813 void 814 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 815 { 816 struct siisata_channel *schp = (struct siisata_channel *)chp; 817 struct ata_command *ata_c = &xfer->c_ata_c; 818 int slot = SIISATA_NON_NCQ_SLOT; 819 struct siisata_prb *prb; 820 int i; 821 822 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 823 SIISATANAME((struct siisata_softc *)chp->ch_atac), 824 __func__, chp->ch_channel, xfer->c_drive, 825 ata_c->r_command, slot), 826 DEBUG_FUNCS|DEBUG_XFERS); 827 828 chp->ch_status = 0; 829 chp->ch_error = 0; 830 831 prb = schp->sch_prb[slot]; 832 memset(prb, 0, sizeof(struct siisata_prb)); 833 834 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 835 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 836 prb->prb_fis[rhd_c] |= xfer->c_drive; 837 838 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 839 840 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 841 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 842 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 843 } 844 845 if (siisata_dma_setup(chp, slot, 846 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 847 ata_c->bcount, 848 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 849 ata_c->flags |= AT_DF; 850 siisata_cmd_complete(chp, xfer, 0); 851 return; 852 } 853 854 if (xfer->c_flags & C_POLL) { 855 /* polled command, disable interrupts */ 856 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 857 siisata_disable_port_interrupt(chp); 858 } 859 860 /* go for it */ 861 siisata_activate_prb(schp, slot); 862 863 if ((ata_c->flags & AT_POLL) == 0) { 864 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 865 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 866 siisata_timeout, xfer); 867 goto out; 868 } 869 870 /* 871 * polled command 872 */ 873 for (i = 0; i < ata_c->timeout / 10; i++) { 874 if (ata_c->flags & AT_DONE) 875 break; 876 siisata_intr_port(schp); 877 DELAY(1000); 878 } 879 880 if ((ata_c->flags & AT_DONE) == 0) { 881 siisata_timeout(xfer); 882 } 883 884 /* reenable interrupts */ 885 siisata_enable_port_interrupt(chp); 886 out: 887 SIISATA_DEBUG_PRINT( 888 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 889 return; 890 } 891 892 void 893 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 894 int reason) 895 { 896 int slot = SIISATA_NON_NCQ_SLOT; 897 898 struct ata_command *ata_c = &xfer->c_ata_c; 899 switch (reason) { 900 case KILL_GONE: 901 ata_c->flags |= AT_GONE; 902 break; 903 case KILL_RESET: 904 ata_c->flags |= AT_RESET; 905 break; 906 default: 907 panic("%s: port %d: unknown reason %d", 908 __func__, chp->ch_channel, reason); 909 } 910 siisata_cmd_done(chp, xfer, slot); 911 } 912 913 int 914 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 915 { 916 struct ata_command *ata_c = &xfer->c_ata_c; 917 #ifdef SIISATA_DEBUG 918 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 919 #endif 920 int slot = SIISATA_NON_NCQ_SLOT; 921 922 SIISATA_DEBUG_PRINT( 923 ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS|DEBUG_XFERS); 924 925 chp->ch_flags &= ~ATACH_IRQ_WAIT; 926 if (xfer->c_flags & C_TIMEOU) 927 ata_c->flags |= AT_TIMEOU; 928 else 929 callout_stop(&xfer->c_timo_callout); 930 931 if (chp->ch_status & WDCS_BSY) { 932 ata_c->flags |= AT_TIMEOU; 933 } else if (chp->ch_status & WDCS_ERR) { 934 ata_c->r_error = chp->ch_error; 935 ata_c->flags |= AT_ERROR; 936 } 937 938 ata_deactivate_xfer(chp, xfer); 939 940 if (!ata_waitdrain_xfer_check(chp, xfer)) { 941 siisata_cmd_done(chp, xfer, slot); 942 } 943 944 return 0; 945 } 946 947 void 948 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 949 { 950 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 951 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 952 struct siisata_channel *schp = (struct siisata_channel *)chp; 953 struct ata_command *ata_c = &xfer->c_ata_c; 954 uint16_t *idwordbuf; 955 int i; 956 957 SIISATA_DEBUG_PRINT( 958 ("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), __func__, 959 ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 960 961 siisata_deactivate_prb(schp, slot); 962 963 if (ata_c->flags & (AT_READ | AT_WRITE)) { 964 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 965 schp->sch_datad[slot]->dm_mapsize, 966 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 967 BUS_DMASYNC_POSTWRITE); 968 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 969 } 970 971 if (ata_c->flags & AT_READREG) { 972 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 973 PRSX(chp->ch_channel, slot, PRSO_FIS), 974 fis, __arraycount(fis)); 975 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 976 } 977 978 /* correct the endianess of IDENTIFY data */ 979 if (ata_c->r_command == WDCC_IDENTIFY || 980 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 981 idwordbuf = xfer->c_databuf; 982 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 983 idwordbuf[i] = le16toh(idwordbuf[i]); 984 } 985 } 986 987 ata_c->flags |= AT_DONE; 988 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 989 ata_c->flags |= AT_XFDONE; 990 991 if (ata_c->flags & AT_WAIT) 992 wakeup(ata_c); 993 else if (ata_c->callback) 994 ata_c->callback(ata_c->callback_arg); 995 atastart(chp); 996 return; 997 } 998 999 int 1000 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1001 { 1002 struct ata_channel *chp = drvp->chnl_softc; 1003 struct ata_bio *ata_bio = &xfer->c_bio; 1004 1005 SIISATA_DEBUG_PRINT( ("%s: %s.\n", 1006 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1007 __func__), DEBUG_FUNCS); 1008 1009 if (xfer == NULL) 1010 return ATACMD_TRY_AGAIN; 1011 if (ata_bio->flags & ATA_POLL) 1012 xfer->c_flags |= C_POLL; 1013 xfer->c_drive = drvp->drive; 1014 xfer->c_databuf = ata_bio->databuf; 1015 xfer->c_bcount = ata_bio->bcount; 1016 xfer->c_start = siisata_bio_start; 1017 xfer->c_intr = siisata_bio_complete; 1018 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1019 ata_exec_xfer(chp, xfer); 1020 return (ata_bio->flags & ATA_ITSDONE) ? 1021 ATACMD_COMPLETE : ATACMD_QUEUED; 1022 } 1023 1024 void 1025 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1026 { 1027 struct siisata_channel *schp = (struct siisata_channel *)chp; 1028 struct siisata_prb *prb; 1029 struct ata_bio *ata_bio = &xfer->c_bio; 1030 int slot = SIISATA_NON_NCQ_SLOT; 1031 int i; 1032 1033 SIISATA_DEBUG_PRINT( 1034 ("%s: %s port %d, slot %d\n", 1035 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, chp->ch_channel, slot), 1036 DEBUG_FUNCS); 1037 1038 chp->ch_status = 0; 1039 chp->ch_error = 0; 1040 1041 prb = schp->sch_prb[slot]; 1042 memset(prb, 0, sizeof(struct siisata_prb)); 1043 1044 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1045 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1046 prb->prb_fis[rhd_c] |= xfer->c_drive; 1047 1048 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 1049 1050 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1051 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1052 ata_bio->error = ERR_DMA; 1053 ata_bio->r_error = 0; 1054 siisata_bio_complete(chp, xfer, 0); 1055 return; 1056 } 1057 1058 if (xfer->c_flags & C_POLL) { 1059 /* polled command, disable interrupts */ 1060 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1061 siisata_disable_port_interrupt(chp); 1062 } 1063 1064 siisata_activate_prb(schp, slot); 1065 1066 if ((ata_bio->flags & ATA_POLL) == 0) { 1067 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1068 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1069 siisata_timeout, xfer); 1070 goto out; 1071 } 1072 1073 /* 1074 * polled command 1075 */ 1076 for (i = 0; i < ATA_DELAY / 10; i++) { 1077 if (ata_bio->flags & ATA_ITSDONE) 1078 break; 1079 siisata_intr_port(schp); 1080 DELAY(1000); 1081 } 1082 1083 siisata_enable_port_interrupt(chp); 1084 out: 1085 SIISATA_DEBUG_PRINT( 1086 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 1087 return; 1088 } 1089 1090 void 1091 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1092 int reason) 1093 { 1094 struct siisata_channel *schp = (struct siisata_channel *)chp; 1095 struct ata_bio *ata_bio = &xfer->c_bio; 1096 int drive = xfer->c_drive; 1097 int slot = SIISATA_NON_NCQ_SLOT; 1098 1099 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1100 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1101 __func__, chp->ch_channel), DEBUG_FUNCS); 1102 1103 siisata_deactivate_prb(schp, slot); 1104 1105 ata_bio->flags |= ATA_ITSDONE; 1106 switch (reason) { 1107 case KILL_GONE: 1108 ata_bio->error = ERR_NODEV; 1109 break; 1110 case KILL_RESET: 1111 ata_bio->error = ERR_RESET; 1112 break; 1113 default: 1114 panic("%s: port %d: unknown reason %d", 1115 __func__, chp->ch_channel, reason); 1116 } 1117 ata_bio->r_error = WDCE_ABRT; 1118 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1119 } 1120 1121 int 1122 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1123 { 1124 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1125 struct siisata_channel *schp = (struct siisata_channel *)chp; 1126 struct ata_bio *ata_bio = &xfer->c_bio; 1127 int drive = xfer->c_drive; 1128 int slot = SIISATA_NON_NCQ_SLOT; 1129 1130 schp->sch_active_slots &= ~__BIT(slot); 1131 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1132 if (xfer->c_flags & C_TIMEOU) { 1133 ata_bio->error = TIMEOUT; 1134 } else { 1135 callout_stop(&xfer->c_timo_callout); 1136 ata_bio->error = NOERROR; 1137 } 1138 1139 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1140 schp->sch_datad[slot]->dm_mapsize, 1141 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1142 BUS_DMASYNC_POSTWRITE); 1143 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1144 1145 ata_deactivate_xfer(chp, xfer); 1146 1147 if (ata_waitdrain_xfer_check(chp, xfer)) { 1148 return 0; 1149 } 1150 1151 ata_bio->flags |= ATA_ITSDONE; 1152 if (chp->ch_status & WDCS_DWF) { 1153 ata_bio->error = ERR_DF; 1154 } else if (chp->ch_status & WDCS_ERR) { 1155 ata_bio->error = ERROR; 1156 ata_bio->r_error = chp->ch_error; 1157 } else if (chp->ch_status & WDCS_CORR) 1158 ata_bio->flags |= ATA_CORR; 1159 1160 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), 1161 __func__, ata_bio->bcount), DEBUG_XFERS); 1162 if (ata_bio->error == NOERROR) { 1163 if (ata_bio->flags & ATA_READ) 1164 ata_bio->bcount -= 1165 PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1166 else 1167 ata_bio->bcount = 0; 1168 } 1169 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1170 if (ata_bio->flags & ATA_POLL) 1171 return 1; 1172 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1173 atastart(chp); 1174 return 0; 1175 } 1176 1177 void 1178 siisata_timeout(void *v) 1179 { 1180 struct ata_xfer *xfer = v; 1181 struct ata_channel *chp = xfer->c_chp; 1182 int s = splbio(); 1183 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1184 siisata_device_reset(chp); 1185 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1186 xfer->c_flags |= C_TIMEOU; 1187 xfer->c_intr(chp, xfer, 0); 1188 } 1189 splx(s); 1190 } 1191 1192 static int 1193 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1194 size_t count, int op) 1195 { 1196 1197 int error, seg; 1198 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1199 struct siisata_channel *schp = (struct siisata_channel *)chp; 1200 1201 struct siisata_prb *prbp; 1202 1203 prbp = schp->sch_prb[slot]; 1204 1205 if (data == NULL) { 1206 goto end; 1207 } 1208 1209 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1210 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1211 if (error) { 1212 aprint_error("%s port %d: " 1213 "failed to load xfer in slot %d: error %d\n", 1214 SIISATANAME(sc), chp->ch_channel, slot, error); 1215 return error; 1216 } 1217 1218 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1219 schp->sch_datad[slot]->dm_mapsize, 1220 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1221 1222 /* make sure it's clean */ 1223 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1224 1225 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1226 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1227 DEBUG_FUNCS | DEBUG_DEBUG); 1228 1229 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1230 prbp->prb_sge[seg].sge_da = 1231 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1232 prbp->prb_sge[seg].sge_dc = 1233 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1234 prbp->prb_sge[seg].sge_flags = htole32(0); 1235 } 1236 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1237 end: 1238 return 0; 1239 } 1240 1241 static void 1242 siisata_activate_prb(struct siisata_channel *schp, int slot) 1243 { 1244 struct siisata_softc *sc; 1245 bus_size_t offset; 1246 uint64_t pprb; 1247 1248 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1249 1250 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != __BIT(slot), 1251 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1252 1253 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1254 /* keep track of what's going on */ 1255 schp->sch_active_slots |= __BIT(slot); 1256 1257 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1258 1259 pprb = schp->sch_bus_prb[slot]; 1260 1261 PRWRITE(sc, offset + 0, pprb >> 0); 1262 PRWRITE(sc, offset + 4, pprb >> 32); 1263 } 1264 1265 static void 1266 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1267 { 1268 struct siisata_softc *sc; 1269 1270 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1271 1272 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1273 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1274 slot); 1275 1276 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1277 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1278 } 1279 1280 static void 1281 siisata_reinit_port(struct ata_channel *chp) 1282 { 1283 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1284 1285 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1286 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1287 DELAY(10); 1288 if (chp->ch_ndrives > 1) 1289 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1290 } 1291 1292 static void 1293 siisata_device_reset(struct ata_channel *chp) 1294 { 1295 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1296 1297 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1298 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1299 DELAY(10); 1300 } 1301 1302 1303 #if NATAPIBUS > 0 1304 void 1305 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1306 { 1307 struct ata_channel *chp = ata_sc->sc_chan; 1308 struct atac_softc *atac = chp->ch_atac; 1309 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1310 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1311 1312 /* 1313 * Fill in the scsipi_adapter. 1314 */ 1315 adapt->adapt_dev = atac->atac_dev; 1316 adapt->adapt_nchannels = atac->atac_nchannels; 1317 adapt->adapt_request = siisata_atapi_scsipi_request; 1318 adapt->adapt_minphys = siisata_atapi_minphys; 1319 atac->atac_atapi_adapter.atapi_probe_device = 1320 siisata_atapi_probe_device; 1321 1322 /* 1323 * Fill in the scsipi_channel. 1324 */ 1325 memset(chan, 0, sizeof(*chan)); 1326 chan->chan_adapter = adapt; 1327 chan->chan_bustype = &siisata_atapi_bustype; 1328 chan->chan_channel = chp->ch_channel; 1329 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1330 chan->chan_openings = 1; 1331 chan->chan_max_periph = 1; 1332 chan->chan_ntargets = 1; 1333 chan->chan_nluns = 1; 1334 1335 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1336 atapiprint); 1337 } 1338 1339 void 1340 siisata_atapi_minphys(struct buf *bp) 1341 { 1342 if (bp->b_bcount > MAXPHYS) 1343 bp->b_bcount = MAXPHYS; 1344 minphys(bp); 1345 } 1346 1347 /* 1348 * Kill off all pending xfers for a periph. 1349 * 1350 * Must be called at splbio(). 1351 */ 1352 void 1353 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1354 { 1355 struct atac_softc *atac = 1356 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1357 struct ata_channel *chp = 1358 atac->atac_channels[periph->periph_channel->chan_channel]; 1359 1360 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1361 } 1362 1363 void 1364 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1365 int reason) 1366 { 1367 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1368 1369 /* remove this command from xfer queue */ 1370 switch (reason) { 1371 case KILL_GONE: 1372 sc_xfer->error = XS_DRIVER_STUFFUP; 1373 break; 1374 case KILL_RESET: 1375 sc_xfer->error = XS_RESET; 1376 break; 1377 default: 1378 panic("%s: port %d: unknown reason %d", 1379 __func__, chp->ch_channel, reason); 1380 } 1381 ata_free_xfer(chp, xfer); 1382 scsipi_done(sc_xfer); 1383 } 1384 1385 void 1386 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1387 { 1388 struct scsipi_channel *chan = sc->sc_channel; 1389 struct scsipi_periph *periph; 1390 struct ataparams ids; 1391 struct ataparams *id = &ids; 1392 struct siisata_softc *siic = 1393 device_private(chan->chan_adapter->adapt_dev); 1394 struct atac_softc *atac = &siic->sc_atac; 1395 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1396 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1397 struct scsipibus_attach_args sa; 1398 char serial_number[21], model[41], firmware_revision[9]; 1399 int s; 1400 1401 /* skip if already attached */ 1402 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1403 return; 1404 1405 /* if no ATAPI device detected at attach time, skip */ 1406 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1407 SIISATA_DEBUG_PRINT(("%s: drive %d " 1408 "not present\n", __func__, target), DEBUG_PROBE); 1409 return; 1410 } 1411 1412 /* Some ATAPI devices need a bit more time after software reset. */ 1413 DELAY(5000); 1414 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1415 #ifdef ATAPI_DEBUG_PROBE 1416 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1417 device_xname(sc->sc_dev), target, 1418 id->atap_config & ATAPI_CFG_CMD_MASK, 1419 id->atap_config & ATAPI_CFG_DRQ_MASK); 1420 #endif 1421 periph = scsipi_alloc_periph(M_NOWAIT); 1422 if (periph == NULL) { 1423 aprint_error_dev(sc->sc_dev, 1424 "%s: unable to allocate periph for " 1425 "channel %d drive %d\n", __func__, 1426 chp->ch_channel, target); 1427 return; 1428 } 1429 periph->periph_dev = NULL; 1430 periph->periph_channel = chan; 1431 periph->periph_switch = &atapi_probe_periphsw; 1432 periph->periph_target = target; 1433 periph->periph_lun = 0; 1434 periph->periph_quirks = PQUIRK_ONLYBIG; 1435 1436 #ifdef SCSIPI_DEBUG 1437 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1438 SCSIPI_DEBUG_TARGET == target) 1439 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1440 #endif 1441 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1442 if (id->atap_config & ATAPI_CFG_REMOV) 1443 periph->periph_flags |= PERIPH_REMOVABLE; 1444 sa.sa_periph = periph; 1445 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1446 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1447 T_REMOV : T_FIXED; 1448 strnvisx(model, sizeof(model), id->atap_model, 40, 1449 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1450 strnvisx(serial_number, sizeof(serial_number), 1451 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1452 strnvisx(firmware_revision, sizeof(firmware_revision), 1453 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1454 sa.sa_inqbuf.vendor = model; 1455 sa.sa_inqbuf.product = serial_number; 1456 sa.sa_inqbuf.revision = firmware_revision; 1457 1458 /* 1459 * Determine the operating mode capabilities of the device. 1460 */ 1461 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1462 == ATAPI_CFG_CMD_16) { 1463 periph->periph_cap |= PERIPH_CAP_CMD16; 1464 1465 /* configure port for packet length */ 1466 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1467 PR_PC_PACKET_LENGTH); 1468 } else { 1469 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1470 PR_PC_PACKET_LENGTH); 1471 } 1472 1473 /* XXX This is gross. */ 1474 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1475 1476 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1477 1478 if (drvp->drv_softc) 1479 ata_probe_caps(drvp); 1480 else { 1481 s = splbio(); 1482 drvp->drive_type &= ATA_DRIVET_NONE; 1483 splx(s); 1484 } 1485 } else { 1486 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1487 "failed for drive %s:%d:%d: error 0x%x\n", 1488 __func__, SIISATANAME(siic), chp->ch_channel, target, 1489 chp->ch_error), DEBUG_PROBE); 1490 s = splbio(); 1491 drvp->drive_type &= ATA_DRIVET_NONE; 1492 splx(s); 1493 } 1494 } 1495 1496 void 1497 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1498 scsipi_adapter_req_t req, void *arg) 1499 { 1500 struct scsipi_adapter *adapt = chan->chan_adapter; 1501 struct scsipi_periph *periph; 1502 struct scsipi_xfer *sc_xfer; 1503 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1504 struct atac_softc *atac = &sc->sc_atac; 1505 struct ata_xfer *xfer; 1506 int channel = chan->chan_channel; 1507 int drive, s; 1508 1509 switch (req) { 1510 case ADAPTER_REQ_RUN_XFER: 1511 sc_xfer = arg; 1512 periph = sc_xfer->xs_periph; 1513 drive = periph->periph_target; 1514 1515 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1516 device_xname(atac->atac_dev), channel, drive), 1517 DEBUG_XFERS); 1518 1519 if (!device_is_active(atac->atac_dev)) { 1520 sc_xfer->error = XS_DRIVER_STUFFUP; 1521 scsipi_done(sc_xfer); 1522 return; 1523 } 1524 xfer = ata_get_xfer(atac->atac_channels[channel]); 1525 if (xfer == NULL) { 1526 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1527 scsipi_done(sc_xfer); 1528 return; 1529 } 1530 1531 if (sc_xfer->xs_control & XS_CTL_POLL) 1532 xfer->c_flags |= C_POLL; 1533 xfer->c_drive = drive; 1534 xfer->c_flags |= C_ATAPI; 1535 xfer->c_scsipi = sc_xfer; 1536 xfer->c_databuf = sc_xfer->data; 1537 xfer->c_bcount = sc_xfer->datalen; 1538 xfer->c_start = siisata_atapi_start; 1539 xfer->c_intr = siisata_atapi_complete; 1540 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1541 xfer->c_dscpoll = 0; 1542 s = splbio(); 1543 ata_exec_xfer(atac->atac_channels[channel], xfer); 1544 #ifdef DIAGNOSTIC 1545 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1546 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1547 panic("%s: polled command not done", __func__); 1548 #endif 1549 splx(s); 1550 return; 1551 1552 default: 1553 /* Not supported, nothing to do. */ 1554 ; 1555 } 1556 } 1557 1558 void 1559 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1560 { 1561 struct siisata_channel *schp = (struct siisata_channel *)chp; 1562 struct siisata_prb *prbp; 1563 1564 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1565 1566 int slot = SIISATA_NON_NCQ_SLOT; 1567 int i; 1568 1569 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1570 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1571 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1572 DEBUG_XFERS); 1573 1574 chp->ch_status = 0; 1575 chp->ch_error = 0; 1576 1577 prbp = schp->sch_prb[slot]; 1578 memset(prbp, 0, sizeof(struct siisata_prb)); 1579 1580 1581 /* fill in direction for ATAPI command */ 1582 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1583 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1584 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1585 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1586 1587 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1588 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1589 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1590 1591 /* copy over ATAPI command */ 1592 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1593 1594 if (siisata_dma_setup(chp, slot, 1595 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1596 xfer->c_databuf : NULL, 1597 xfer->c_bcount, 1598 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1599 BUS_DMA_READ : BUS_DMA_WRITE) 1600 ) 1601 panic("%s", __func__); 1602 1603 if (xfer->c_flags & C_POLL) { 1604 /* polled command, disable interrupts */ 1605 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1606 siisata_disable_port_interrupt(chp); 1607 } 1608 1609 siisata_activate_prb(schp, slot); 1610 1611 if ((xfer->c_flags & C_POLL) == 0) { 1612 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1613 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1614 siisata_timeout, xfer); 1615 goto out; 1616 } 1617 1618 /* 1619 * polled command 1620 */ 1621 for (i = 0; i < ATA_DELAY / 10; i++) { 1622 if (sc_xfer->xs_status & XS_STS_DONE) 1623 break; 1624 siisata_intr_port(schp); 1625 DELAY(1000); 1626 } 1627 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1628 siisata_timeout(xfer); 1629 } 1630 /* reenable interrupts */ 1631 siisata_enable_port_interrupt(chp); 1632 out: 1633 SIISATA_DEBUG_PRINT( 1634 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 1635 return; 1636 } 1637 1638 int 1639 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1640 int is) 1641 { 1642 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1643 struct siisata_channel *schp = (struct siisata_channel *)chp; 1644 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1645 int slot = SIISATA_NON_NCQ_SLOT; 1646 1647 SIISATA_DEBUG_PRINT( 1648 ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1649 1650 /* this comamnd is not active any more */ 1651 schp->sch_active_slots &= ~__BIT(slot); 1652 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1653 if (xfer->c_flags & C_TIMEOU) { 1654 sc_xfer->error = XS_TIMEOUT; 1655 } else { 1656 callout_stop(&xfer->c_timo_callout); 1657 sc_xfer->error = XS_NOERROR; 1658 } 1659 1660 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1661 schp->sch_datad[slot]->dm_mapsize, 1662 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1663 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1664 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1665 1666 ata_deactivate_xfer(chp, xfer); 1667 1668 if (ata_waitdrain_xfer_check(chp, xfer)) { 1669 sc_xfer->error = XS_DRIVER_STUFFUP; 1670 return 0; /* XXX verify */ 1671 } 1672 1673 ata_free_xfer(chp, xfer); 1674 sc_xfer->resid = sc_xfer->datalen; 1675 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1676 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1677 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1678 if ((chp->ch_status & WDCS_ERR) && 1679 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1680 sc_xfer->resid == sc_xfer->datalen)) { 1681 sc_xfer->error = XS_SHORTSENSE; 1682 sc_xfer->sense.atapi_sense = chp->ch_error; 1683 if ((sc_xfer->xs_periph->periph_quirks & 1684 PQUIRK_NOSENSE) == 0) { 1685 /* request sense */ 1686 sc_xfer->error = XS_BUSY; 1687 sc_xfer->status = SCSI_CHECK; 1688 } 1689 } 1690 scsipi_done(sc_xfer); 1691 atastart(chp); 1692 return 0; /* XXX verify */ 1693 } 1694 1695 #endif /* NATAPIBUS */ 1696
Indexes created Mon Oct 20 20:10:13 GMT 2025