siisata.c revision 1.30.4.14
1 /* $NetBSD: siisata.c,v 1.30.4.14 2017/04/24 21:19:21 jakllsch Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.30.4.14 2017/04/24 21:19:21 jakllsch Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 113 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 114 #if _BYTE_ORDER == _LITTLE_ENDIAN 115 #define bus_space_read_stream_4 bus_space_read_4 116 #define bus_space_read_region_stream_4 bus_space_read_region_4 117 #else 118 static inline uint32_t 119 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 120 { 121 return htole32(bus_space_read_4(t, h, o)); 122 } 123 124 static inline void 125 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 126 bus_size_t o, uint32_t *p, bus_size_t c) 127 { 128 bus_space_read_region_4(t, h, o, p, c); 129 for (bus_size_t i = 0; i < c; i++) { 130 p[i] = htole32(p[i]); 131 } 132 } 133 #endif 134 #endif 135 136 static void siisata_attach_port(struct siisata_softc *, int); 137 static void siisata_intr_port(struct siisata_channel *); 138 139 void siisata_probe_drive(struct ata_channel *); 140 void siisata_setup_channel(struct ata_channel *); 141 142 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 143 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 144 void siisata_reset_channel(struct ata_channel *, int); 145 int siisata_ata_addref(struct ata_drive_datas *); 146 void siisata_ata_delref(struct ata_drive_datas *); 147 void siisata_killpending(struct ata_drive_datas *); 148 149 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 150 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 151 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 153 154 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 155 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 156 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 158 159 void siisata_timeout(void *); 160 161 static void siisata_reinit_port(struct ata_channel *); 162 static void siisata_device_reset(struct ata_channel *); 163 static void siisata_activate_prb(struct siisata_channel *, int); 164 static void siisata_deactivate_prb(struct siisata_channel *, int); 165 static int siisata_dma_setup(struct ata_channel *chp, int, void *, 166 size_t, int); 167 168 #if NATAPIBUS > 0 169 void siisata_atapibus_attach(struct atabus_softc *); 170 void siisata_atapi_probe_device(struct atapibus_softc *, int); 171 void siisata_atapi_minphys(struct buf *); 172 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 173 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 174 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 175 void siisata_atapi_scsipi_request(struct scsipi_channel *, 176 scsipi_adapter_req_t, void *); 177 void siisata_atapi_kill_pending(struct scsipi_periph *); 178 #endif /* NATAPIBUS */ 179 180 const struct ata_bustype siisata_ata_bustype = { 181 SCSIPI_BUSTYPE_ATA, 182 siisata_ata_bio, 183 siisata_reset_drive, 184 siisata_reset_channel, 185 siisata_exec_command, 186 ata_get_params, 187 siisata_ata_addref, 188 siisata_ata_delref, 189 siisata_killpending 190 }; 191 192 #if NATAPIBUS > 0 193 static const struct scsipi_bustype siisata_atapi_bustype = { 194 SCSIPI_BUSTYPE_ATAPI, 195 atapi_scsipi_cmd, 196 atapi_interpret_sense, 197 atapi_print_addr, 198 siisata_atapi_kill_pending, 199 NULL, 200 }; 201 #endif /* NATAPIBUS */ 202 203 204 void 205 siisata_attach(struct siisata_softc *sc) 206 { 207 int i; 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 211 212 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 213 sc->sc_atac.atac_pio_cap = 4; 214 sc->sc_atac.atac_dma_cap = 2; 215 sc->sc_atac.atac_udma_cap = 6; 216 sc->sc_atac.atac_channels = sc->sc_chanarray; 217 sc->sc_atac.atac_probe = siisata_probe_drive; 218 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 219 sc->sc_atac.atac_set_modes = siisata_setup_channel; 220 #if NATAPIBUS > 0 221 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 222 #endif 223 224 /* come out of reset state */ 225 GRWRITE(sc, GR_GC, 0); 226 227 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 228 siisata_attach_port(sc, i); 229 } 230 231 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 232 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 233 return; 234 } 235 236 static void 237 siisata_disable_port_interrupt(struct ata_channel *chp) 238 { 239 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 240 241 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 242 } 243 244 static void 245 siisata_enable_port_interrupt(struct ata_channel *chp) 246 { 247 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 248 249 /* clear any interrupts */ 250 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 251 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 252 /* and enable CmdErrr+CmdCmpl interrupting */ 253 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 254 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 255 } 256 257 static void 258 siisata_init_port(struct siisata_softc *sc, int port) 259 { 260 struct siisata_channel *schp; 261 struct ata_channel *chp; 262 263 schp = &sc->sc_channels[port]; 264 chp = (struct ata_channel *)schp; 265 266 /* come out of reset, 64-bit activation */ 267 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 268 PR_PC_32BA | PR_PC_PORT_RESET); 269 /* initialize port */ 270 siisata_reinit_port(chp); 271 /* enable CmdErrr+CmdCmpl interrupting */ 272 siisata_enable_port_interrupt(chp); 273 /* enable port interrupt */ 274 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 275 } 276 277 static void 278 siisata_attach_port(struct siisata_softc *sc, int port) 279 { 280 int j; 281 int dmasize; 282 int error; 283 void *prbp; 284 struct siisata_channel *schp; 285 struct ata_channel *chp; 286 287 schp = &sc->sc_channels[port]; 288 chp = (struct ata_channel *)schp; 289 sc->sc_chanarray[port] = chp; 290 chp->ch_channel = port; 291 chp->ch_atac = &sc->sc_atac; 292 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 293 if (chp->ch_queue == NULL) { 294 aprint_error_dev(sc->sc_atac.atac_dev, 295 "port %d: can't allocate memory " 296 "for command queue\n", chp->ch_channel); 297 return; 298 } 299 300 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 301 302 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 303 __func__, dmasize), DEBUG_FUNCS); 304 305 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 306 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 307 if (error) { 308 aprint_error_dev(sc->sc_atac.atac_dev, 309 "unable to allocate PRB table memory, " 310 "error=%d\n", error); 311 return; 312 } 313 314 error = bus_dmamem_map(sc->sc_dmat, 315 &schp->sch_prb_seg, schp->sch_prb_nseg, 316 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 317 if (error) { 318 aprint_error_dev(sc->sc_atac.atac_dev, 319 "unable to map PRB table memory, " 320 "error=%d\n", error); 321 bus_dmamem_free(sc->sc_dmat, 322 &schp->sch_prb_seg, schp->sch_prb_nseg); 323 return; 324 } 325 326 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 327 BUS_DMA_NOWAIT, &schp->sch_prbd); 328 if (error) { 329 aprint_error_dev(sc->sc_atac.atac_dev, 330 "unable to create PRB table map, " 331 "error=%d\n", error); 332 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 333 bus_dmamem_free(sc->sc_dmat, 334 &schp->sch_prb_seg, schp->sch_prb_nseg); 335 return; 336 } 337 338 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 339 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 340 if (error) { 341 aprint_error_dev(sc->sc_atac.atac_dev, 342 "unable to load PRB table map, " 343 "error=%d\n", error); 344 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 345 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 346 bus_dmamem_free(sc->sc_dmat, 347 &schp->sch_prb_seg, schp->sch_prb_nseg); 348 return; 349 } 350 351 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 352 schp->sch_prb[j] = (struct siisata_prb *) 353 ((char *)prbp + SIISATA_CMD_SIZE * j); 354 schp->sch_bus_prb[j] = 355 schp->sch_prbd->dm_segs[0].ds_addr + 356 SIISATA_CMD_SIZE * j; 357 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 358 SIISATA_NSGE, MAXPHYS, 0, 359 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 360 &schp->sch_datad[j]); 361 if (error) { 362 aprint_error_dev(sc->sc_atac.atac_dev, 363 "couldn't create xfer DMA map, error=%d\n", 364 error); 365 return; 366 } 367 } 368 369 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 370 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 371 aprint_error_dev(sc->sc_atac.atac_dev, 372 "couldn't map port %d SStatus regs\n", 373 chp->ch_channel); 374 return; 375 } 376 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 377 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 378 aprint_error_dev(sc->sc_atac.atac_dev, 379 "couldn't map port %d SControl regs\n", 380 chp->ch_channel); 381 return; 382 } 383 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 384 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 385 aprint_error_dev(sc->sc_atac.atac_dev, 386 "couldn't map port %d SError regs\n", 387 chp->ch_channel); 388 return; 389 } 390 391 siisata_init_port(sc, port); 392 393 ata_channel_attach(chp); 394 395 return; 396 } 397 398 int 399 siisata_detach(struct siisata_softc *sc, int flags) 400 { 401 struct atac_softc *atac = &sc->sc_atac; 402 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 403 struct siisata_channel *schp; 404 struct ata_channel *chp; 405 int i, j, error; 406 407 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 408 schp = &sc->sc_channels[i]; 409 chp = sc->sc_chanarray[i]; 410 411 if (chp->atabus == NULL) 412 continue; 413 if ((error = config_detach(chp->atabus, flags)) != 0) 414 return error; 415 416 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 417 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 418 419 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 420 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 421 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 422 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 423 bus_dmamem_free(sc->sc_dmat, 424 &schp->sch_prb_seg, schp->sch_prb_nseg); 425 426 free(chp->ch_queue, M_DEVBUF); 427 chp->atabus = NULL; 428 } 429 430 if (adapt->adapt_refcnt != 0) 431 return EBUSY; 432 433 /* leave the chip in reset */ 434 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 435 436 return 0; 437 } 438 439 void 440 siisata_resume(struct siisata_softc *sc) 441 { 442 int i; 443 444 /* come out of reset state */ 445 GRWRITE(sc, GR_GC, 0); 446 447 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 448 siisata_init_port(sc, i); 449 } 450 451 } 452 453 int 454 siisata_intr(void *v) 455 { 456 struct siisata_softc *sc = v; 457 uint32_t is; 458 int i, r = 0; 459 while ((is = GRREAD(sc, GR_GIS))) { 460 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 461 SIISATANAME(sc), __func__, is), DEBUG_INTR); 462 r = 1; 463 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 464 if (is & GR_GIS_PXIS(i)) 465 siisata_intr_port(&sc->sc_channels[i]); 466 } 467 return r; 468 } 469 470 static void 471 siisata_intr_port(struct siisata_channel *schp) 472 { 473 struct siisata_softc *sc; 474 struct ata_channel *chp; 475 struct ata_xfer *xfer; 476 int slot; 477 uint32_t pss, pis; 478 uint32_t prbfis; 479 480 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 481 chp = &schp->ata_channel; 482 xfer = ata_queue_hwslot_to_xfer(chp->ch_queue, 0); /* XXX slot */ 483 slot = SIISATA_NON_NCQ_SLOT; 484 485 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 486 487 SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x ", SIISATANAME(sc), 488 __func__, chp->ch_channel, pis), DEBUG_INTR); 489 490 if (pis & PR_PIS_CMDCMPL) { 491 /* get slot status, clearing completion interrupt */ 492 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 493 SIISATA_DEBUG_PRINT(("pss 0x%x\n", pss), DEBUG_INTR); 494 /* is this expected? */ 495 /* XXX improve */ 496 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 497 aprint_error( "%s: unexpected command " 498 "completion on port %d\n", 499 SIISATANAME(sc), chp->ch_channel); 500 return; 501 } 502 if ((~pss & __BIT(slot)) == 0) { 503 aprint_error( "%s: unknown slot " 504 "completion on port %d, pss 0x%x\n", 505 SIISATANAME(sc), chp->ch_channel, pss); 506 return; 507 } 508 } else if (pis & PR_PIS_CMDERRR) { 509 uint32_t ec; 510 511 /* emulate a CRC error by default */ 512 chp->ch_status = WDCS_ERR; 513 chp->ch_error = WDCE_CRC; 514 515 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 516 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 517 if (ec <= PR_PCE_DATAFISERROR) { 518 if (ec == PR_PCE_DEVICEERROR && xfer != NULL) { 519 /* read in specific information about error */ 520 prbfis = bus_space_read_stream_4( 521 sc->sc_prt, sc->sc_prh, 522 PRSX(chp->ch_channel, slot, PRSO_FIS)); 523 /* set ch_status and ch_error */ 524 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 525 } 526 siisata_reinit_port(chp); 527 } else { 528 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 529 " on channel %d (ctx 0x%x), resetting\n", 530 ec, chp->ch_channel, 531 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 532 /* okay, we have a "Fatal Error" */ 533 siisata_device_reset(chp); 534 } 535 } 536 537 /* clear some (ok, all) ints */ 538 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 539 if (xfer && xfer->c_intr) 540 xfer->c_intr(chp, xfer, 0); 541 542 return; 543 } 544 545 void 546 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 547 { 548 struct ata_channel *chp = drvp->chnl_softc; 549 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 550 struct siisata_channel *schp = (struct siisata_channel *)chp; 551 struct siisata_prb *prb; 552 int slot = SIISATA_NON_NCQ_SLOT; 553 int i; 554 555 /* wait for ready */ 556 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 557 DELAY(10); 558 559 prb = schp->sch_prb[slot]; 560 memset(prb, 0, SIISATA_CMD_SIZE); 561 prb->prb_control = 562 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 563 KASSERT(drvp->drive <= PMP_PORT_CTL); 564 prb->prb_fis[rhd_c] = drvp->drive; 565 566 siisata_activate_prb(schp, slot); 567 568 for(i = 0; i < 3100; i++) { 569 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 570 PR_PXSS(slot)) == 0) 571 break; 572 if (flags & AT_WAIT) 573 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 574 else 575 DELAY(10000); 576 } 577 578 siisata_deactivate_prb(schp, slot); 579 if (i == 3100) { 580 /* timeout */ 581 siisata_device_reset(chp); 582 if (sigp) 583 *sigp = 0xffffffff; 584 } else { 585 /* read the signature out of the FIS */ 586 if (sigp) { 587 *sigp = 0; 588 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 589 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 590 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, slot, 591 PRSO_FIS+0xc)) & 0xff; 592 } 593 } 594 595 #if 1 596 /* attempt to downgrade signaling in event of CRC error */ 597 /* XXX should be part of the MI (S)ATA subsystem */ 598 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 599 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 600 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 601 DELAY(10); 602 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 603 SControl_IPM_NONE | SControl_SPD_G1); 604 DELAY(10); 605 for (;;) { 606 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 607 & SStatus_DET_mask) == SStatus_DET_DEV) 608 break; 609 DELAY(10); 610 } 611 } 612 #endif 613 614 #if 1 615 chp->ch_status = 0; 616 chp->ch_error = 0; 617 #endif 618 return; 619 } 620 621 void 622 siisata_reset_channel(struct ata_channel *chp, int flags) 623 { 624 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 625 struct siisata_channel *schp = (struct siisata_channel *)chp; 626 627 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 628 DEBUG_FUNCS); 629 630 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 631 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 632 aprint_error("%s port %d: reset failed\n", 633 SIISATANAME(sc), chp->ch_channel); 634 /* XXX and then ? */ 635 } 636 /* wait for ready */ 637 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 638 DELAY(10); 639 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 640 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 641 ata_kill_active(chp, KILL_RESET); 642 643 return; 644 } 645 646 int 647 siisata_ata_addref(struct ata_drive_datas *drvp) 648 { 649 return 0; 650 } 651 652 void 653 siisata_ata_delref(struct ata_drive_datas *drvp) 654 { 655 return; 656 } 657 658 void 659 siisata_killpending(struct ata_drive_datas *drvp) 660 { 661 return; 662 } 663 664 void 665 siisata_probe_drive(struct ata_channel *chp) 666 { 667 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 668 struct siisata_channel *schp = (struct siisata_channel *)chp; 669 int i; 670 uint32_t sig; 671 int slot = SIISATA_NON_NCQ_SLOT; 672 struct siisata_prb *prb; 673 bool timed_out; 674 675 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 676 __func__, chp->ch_channel), DEBUG_FUNCS); 677 678 /* 679 * disable port interrupt as we're polling for PHY up and 680 * prb completion 681 */ 682 siisata_disable_port_interrupt(chp); 683 684 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 685 schp->sch_sstatus, AT_WAIT)) { 686 case SStatus_DET_DEV: 687 /* clear any interrupts */ 688 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 689 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 690 /* wait for ready */ 691 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 692 & PR_PS_PORT_READY)) 693 DELAY(10); 694 prb = schp->sch_prb[slot]; 695 memset(prb, 0, SIISATA_CMD_SIZE); 696 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 697 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 698 699 siisata_activate_prb(schp, slot); 700 701 timed_out = 1; 702 for(i = 0; i < 3100; i++) { 703 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 704 PR_PXSS(slot)) == 0) { 705 /* prb completed */ 706 timed_out = 0; 707 break; 708 } 709 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 710 (PR_PIS_CMDERRR << 16)) { 711 /* we got an error; handle as timeout */ 712 break; 713 } 714 715 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 716 } 717 718 siisata_deactivate_prb(schp, slot); 719 if (timed_out) { 720 aprint_error_dev(sc->sc_atac.atac_dev, 721 "SOFT_RESET failed on port %d (error %d PSS 0x%x), " 722 "resetting\n", chp->ch_channel, 723 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 724 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); 725 siisata_reinit_port(chp); 726 break; 727 } 728 729 /* read the signature out of the FIS */ 730 sig = 0; 731 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 732 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 733 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 734 PRSO_FIS+0xc)) & 0xff; 735 736 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 737 __func__, sig), DEBUG_PROBE); 738 739 if (sig == 0x96690101) 740 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 741 PR_PC_PMP_ENABLE); 742 sata_interpret_sig(chp, 0, sig); 743 break; 744 default: 745 break; 746 } 747 748 siisata_enable_port_interrupt(chp); 749 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 750 __func__, chp->ch_channel), DEBUG_PROBE); 751 return; 752 } 753 754 void 755 siisata_setup_channel(struct ata_channel *chp) 756 { 757 return; 758 } 759 760 int 761 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 762 { 763 struct ata_channel *chp = drvp->chnl_softc; 764 struct ata_command *ata_c = &xfer->c_ata_c; 765 int ret; 766 int s; 767 768 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 769 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 770 DEBUG_FUNCS); 771 772 if (ata_c->flags & AT_POLL) 773 xfer->c_flags |= C_POLL; 774 if (ata_c->flags & AT_WAIT) 775 xfer->c_flags |= C_WAIT; 776 xfer->c_drive = drvp->drive; 777 xfer->c_databuf = ata_c->data; 778 xfer->c_bcount = ata_c->bcount; 779 xfer->c_start = siisata_cmd_start; 780 xfer->c_intr = siisata_cmd_complete; 781 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 782 s = splbio(); 783 ata_exec_xfer(chp, xfer); 784 #ifdef DIAGNOSTIC 785 if ((ata_c->flags & AT_POLL) != 0 && 786 (ata_c->flags & AT_DONE) == 0) 787 panic("%s: polled command not done", __func__); 788 #endif 789 if (ata_c->flags & AT_DONE) { 790 ret = ATACMD_COMPLETE; 791 } else { 792 if (ata_c->flags & AT_WAIT) { 793 while ((ata_c->flags & AT_DONE) == 0) { 794 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 795 SIISATANAME( 796 (struct siisata_softc *)chp->ch_atac), 797 __func__), DEBUG_FUNCS); 798 tsleep(ata_c, PRIBIO, "siicmd", 0); 799 } 800 ret = ATACMD_COMPLETE; 801 } else { 802 ret = ATACMD_QUEUED; 803 } 804 } 805 splx(s); 806 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 807 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 808 DEBUG_FUNCS); 809 return ret; 810 } 811 812 void 813 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 814 { 815 struct siisata_channel *schp = (struct siisata_channel *)chp; 816 struct ata_command *ata_c = &xfer->c_ata_c; 817 int slot = SIISATA_NON_NCQ_SLOT; 818 struct siisata_prb *prb; 819 int i; 820 821 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 822 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 823 chp->ch_channel, xfer->c_drive, ata_c->r_command, slot), 824 DEBUG_FUNCS|DEBUG_XFERS); 825 826 chp->ch_status = 0; 827 chp->ch_error = 0; 828 829 prb = schp->sch_prb[slot]; 830 memset(prb, 0, SIISATA_CMD_SIZE); 831 832 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 833 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 834 prb->prb_fis[rhd_c] |= xfer->c_drive; 835 836 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 837 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 838 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 839 } 840 841 if (siisata_dma_setup(chp, slot, 842 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 843 ata_c->bcount, 844 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 845 ata_c->flags |= AT_DF; 846 siisata_cmd_complete(chp, xfer, 0); 847 return; 848 } 849 850 if (xfer->c_flags & C_POLL) { 851 /* polled command, disable interrupts */ 852 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 853 siisata_disable_port_interrupt(chp); 854 } 855 856 /* go for it */ 857 siisata_activate_prb(schp, slot); 858 859 if ((ata_c->flags & AT_POLL) == 0) { 860 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 861 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 862 siisata_timeout, xfer); 863 goto out; 864 } 865 866 /* 867 * polled command 868 */ 869 for (i = 0; i < ata_c->timeout / 10; i++) { 870 if (ata_c->flags & AT_DONE) 871 break; 872 siisata_intr_port(schp); 873 DELAY(1000); 874 } 875 876 if ((ata_c->flags & AT_DONE) == 0) { 877 siisata_timeout(xfer); 878 } 879 880 /* reenable interrupts */ 881 siisata_enable_port_interrupt(chp); 882 out: 883 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 884 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 885 DEBUG_FUNCS); 886 return; 887 } 888 889 void 890 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 891 int reason) 892 { 893 int slot = SIISATA_NON_NCQ_SLOT; 894 895 struct ata_command *ata_c = &xfer->c_ata_c; 896 switch (reason) { 897 case KILL_GONE: 898 ata_c->flags |= AT_GONE; 899 break; 900 case KILL_RESET: 901 ata_c->flags |= AT_RESET; 902 break; 903 default: 904 panic("%s: port %d: unknown reason %d", 905 __func__, chp->ch_channel, reason); 906 } 907 siisata_cmd_done(chp, xfer, slot); 908 } 909 910 int 911 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 912 { 913 struct ata_command *ata_c = &xfer->c_ata_c; 914 #ifdef SIISATA_DEBUG 915 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 916 #endif 917 int slot = SIISATA_NON_NCQ_SLOT; 918 919 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 920 DEBUG_FUNCS|DEBUG_XFERS); 921 922 chp->ch_flags &= ~ATACH_IRQ_WAIT; 923 if (xfer->c_flags & C_TIMEOU) 924 ata_c->flags |= AT_TIMEOU; 925 else 926 callout_stop(&xfer->c_timo_callout); 927 928 if (chp->ch_status & WDCS_BSY) { 929 ata_c->flags |= AT_TIMEOU; 930 } else if (chp->ch_status & WDCS_ERR) { 931 ata_c->r_error = chp->ch_error; 932 ata_c->flags |= AT_ERROR; 933 } 934 935 ata_deactivate_xfer(chp, xfer); 936 937 if (!ata_waitdrain_xfer_check(chp, xfer)) { 938 siisata_cmd_done(chp, xfer, slot); 939 } 940 941 return 0; 942 } 943 944 void 945 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 946 { 947 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 948 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 949 struct siisata_channel *schp = (struct siisata_channel *)chp; 950 struct ata_command *ata_c = &xfer->c_ata_c; 951 uint16_t *idwordbuf; 952 int i; 953 954 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 955 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 956 957 siisata_deactivate_prb(schp, slot); 958 959 if (ata_c->flags & (AT_READ | AT_WRITE)) { 960 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 961 schp->sch_datad[slot]->dm_mapsize, 962 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 963 BUS_DMASYNC_POSTWRITE); 964 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 965 } 966 967 if (ata_c->flags & AT_READREG) { 968 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 969 PRSX(chp->ch_channel, slot, PRSO_FIS), 970 fis, __arraycount(fis)); 971 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 972 } 973 974 /* correct the endianess of IDENTIFY data */ 975 if (ata_c->r_command == WDCC_IDENTIFY || 976 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 977 idwordbuf = xfer->c_databuf; 978 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 979 idwordbuf[i] = le16toh(idwordbuf[i]); 980 } 981 } 982 983 ata_c->flags |= AT_DONE; 984 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 985 ata_c->flags |= AT_XFDONE; 986 987 if (ata_c->flags & AT_WAIT) 988 wakeup(ata_c); 989 else if (ata_c->callback) 990 ata_c->callback(ata_c->callback_arg); 991 atastart(chp); 992 return; 993 } 994 995 int 996 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 997 { 998 struct ata_channel *chp = drvp->chnl_softc; 999 struct ata_bio *ata_bio = &xfer->c_bio; 1000 1001 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1002 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1003 DEBUG_FUNCS); 1004 1005 if (xfer == NULL) 1006 return ATACMD_TRY_AGAIN; 1007 if (ata_bio->flags & ATA_POLL) 1008 xfer->c_flags |= C_POLL; 1009 xfer->c_drive = drvp->drive; 1010 xfer->c_databuf = ata_bio->databuf; 1011 xfer->c_bcount = ata_bio->bcount; 1012 xfer->c_start = siisata_bio_start; 1013 xfer->c_intr = siisata_bio_complete; 1014 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1015 ata_exec_xfer(chp, xfer); 1016 return (ata_bio->flags & ATA_ITSDONE) ? 1017 ATACMD_COMPLETE : ATACMD_QUEUED; 1018 } 1019 1020 void 1021 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1022 { 1023 struct siisata_channel *schp = (struct siisata_channel *)chp; 1024 struct siisata_prb *prb; 1025 struct ata_bio *ata_bio = &xfer->c_bio; 1026 int slot = SIISATA_NON_NCQ_SLOT; 1027 int i; 1028 1029 SIISATA_DEBUG_PRINT(("%s: %s port %d, slot %d\n", 1030 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1031 chp->ch_channel, slot), DEBUG_FUNCS); 1032 1033 chp->ch_status = 0; 1034 chp->ch_error = 0; 1035 1036 prb = schp->sch_prb[slot]; 1037 memset(prb, 0, SIISATA_CMD_SIZE); 1038 1039 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1040 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1041 prb->prb_fis[rhd_c] |= xfer->c_drive; 1042 1043 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1044 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1045 ata_bio->error = ERR_DMA; 1046 ata_bio->r_error = 0; 1047 siisata_bio_complete(chp, xfer, 0); 1048 return; 1049 } 1050 1051 if (xfer->c_flags & C_POLL) { 1052 /* polled command, disable interrupts */ 1053 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1054 siisata_disable_port_interrupt(chp); 1055 } 1056 1057 siisata_activate_prb(schp, slot); 1058 1059 if ((ata_bio->flags & ATA_POLL) == 0) { 1060 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1061 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1062 siisata_timeout, xfer); 1063 goto out; 1064 } 1065 1066 /* 1067 * polled command 1068 */ 1069 for (i = 0; i < ATA_DELAY / 10; i++) { 1070 if (ata_bio->flags & ATA_ITSDONE) 1071 break; 1072 siisata_intr_port(schp); 1073 DELAY(1000); 1074 } 1075 1076 siisata_enable_port_interrupt(chp); 1077 out: 1078 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1079 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1080 DEBUG_FUNCS); 1081 return; 1082 } 1083 1084 void 1085 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1086 int reason) 1087 { 1088 struct siisata_channel *schp = (struct siisata_channel *)chp; 1089 struct ata_bio *ata_bio = &xfer->c_bio; 1090 int drive = xfer->c_drive; 1091 int slot = SIISATA_NON_NCQ_SLOT; 1092 1093 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1094 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1095 chp->ch_channel), DEBUG_FUNCS); 1096 1097 siisata_deactivate_prb(schp, slot); 1098 1099 ata_bio->flags |= ATA_ITSDONE; 1100 switch (reason) { 1101 case KILL_GONE: 1102 ata_bio->error = ERR_NODEV; 1103 break; 1104 case KILL_RESET: 1105 ata_bio->error = ERR_RESET; 1106 break; 1107 default: 1108 panic("%s: port %d: unknown reason %d", 1109 __func__, chp->ch_channel, reason); 1110 } 1111 ata_bio->r_error = WDCE_ABRT; 1112 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1113 } 1114 1115 int 1116 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1117 { 1118 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1119 struct siisata_channel *schp = (struct siisata_channel *)chp; 1120 struct ata_bio *ata_bio = &xfer->c_bio; 1121 int drive = xfer->c_drive; 1122 int slot = SIISATA_NON_NCQ_SLOT; 1123 1124 schp->sch_active_slots &= ~__BIT(slot); 1125 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1126 if (xfer->c_flags & C_TIMEOU) { 1127 ata_bio->error = TIMEOUT; 1128 } else { 1129 callout_stop(&xfer->c_timo_callout); 1130 ata_bio->error = NOERROR; 1131 } 1132 1133 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1134 schp->sch_datad[slot]->dm_mapsize, 1135 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1136 BUS_DMASYNC_POSTWRITE); 1137 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1138 1139 ata_deactivate_xfer(chp, xfer); 1140 1141 if (ata_waitdrain_xfer_check(chp, xfer)) { 1142 return 0; 1143 } 1144 1145 ata_bio->flags |= ATA_ITSDONE; 1146 if (chp->ch_status & WDCS_DWF) { 1147 ata_bio->error = ERR_DF; 1148 } else if (chp->ch_status & WDCS_ERR) { 1149 ata_bio->error = ERROR; 1150 ata_bio->r_error = chp->ch_error; 1151 } else if (chp->ch_status & WDCS_CORR) 1152 ata_bio->flags |= ATA_CORR; 1153 1154 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1155 ata_bio->bcount), DEBUG_XFERS); 1156 if (ata_bio->error == NOERROR) { 1157 if (ata_bio->flags & ATA_READ) 1158 ata_bio->bcount -= 1159 PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1160 else 1161 ata_bio->bcount = 0; 1162 } 1163 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1164 if (ata_bio->flags & ATA_POLL) 1165 return 1; 1166 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1167 atastart(chp); 1168 return 0; 1169 } 1170 1171 void 1172 siisata_timeout(void *v) 1173 { 1174 struct ata_xfer *xfer = v; 1175 struct ata_channel *chp = xfer->c_chp; 1176 int s = splbio(); 1177 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1178 siisata_device_reset(chp); 1179 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1180 xfer->c_flags |= C_TIMEOU; 1181 xfer->c_intr(chp, xfer, 0); 1182 } 1183 splx(s); 1184 } 1185 1186 static int 1187 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1188 size_t count, int op) 1189 { 1190 1191 int error, seg; 1192 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1193 struct siisata_channel *schp = (struct siisata_channel *)chp; 1194 1195 struct siisata_prb *prbp; 1196 1197 prbp = schp->sch_prb[slot]; 1198 1199 if (data == NULL) { 1200 goto end; 1201 } 1202 1203 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1204 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1205 if (error) { 1206 aprint_error("%s port %d: " 1207 "failed to load xfer in slot %d: error %d\n", 1208 SIISATANAME(sc), chp->ch_channel, slot, error); 1209 return error; 1210 } 1211 1212 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1213 schp->sch_datad[slot]->dm_mapsize, 1214 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1215 1216 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1217 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1218 DEBUG_FUNCS | DEBUG_DEBUG); 1219 1220 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1221 prbp->prb_sge[seg].sge_da = 1222 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1223 prbp->prb_sge[seg].sge_dc = 1224 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1225 prbp->prb_sge[seg].sge_flags = htole32(0); 1226 } 1227 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1228 end: 1229 return 0; 1230 } 1231 1232 static void 1233 siisata_activate_prb(struct siisata_channel *schp, int slot) 1234 { 1235 struct siisata_softc *sc; 1236 bus_size_t offset; 1237 uint64_t pprb; 1238 1239 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1240 1241 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != __BIT(slot), 1242 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1243 1244 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1245 /* keep track of what's going on */ 1246 schp->sch_active_slots |= __BIT(slot); 1247 1248 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1249 1250 pprb = schp->sch_bus_prb[slot]; 1251 1252 PRWRITE(sc, offset + 0, pprb >> 0); 1253 PRWRITE(sc, offset + 4, pprb >> 32); 1254 } 1255 1256 static void 1257 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1258 { 1259 struct siisata_softc *sc; 1260 1261 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1262 1263 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1264 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1265 slot); 1266 1267 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1268 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1269 } 1270 1271 static void 1272 siisata_reinit_port(struct ata_channel *chp) 1273 { 1274 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1275 1276 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1277 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1278 DELAY(10); 1279 if (chp->ch_ndrives > 1) 1280 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1281 } 1282 1283 static void 1284 siisata_device_reset(struct ata_channel *chp) 1285 { 1286 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1287 1288 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1289 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1290 DELAY(10); 1291 } 1292 1293 1294 #if NATAPIBUS > 0 1295 void 1296 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1297 { 1298 struct ata_channel *chp = ata_sc->sc_chan; 1299 struct atac_softc *atac = chp->ch_atac; 1300 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1301 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1302 1303 /* 1304 * Fill in the scsipi_adapter. 1305 */ 1306 adapt->adapt_dev = atac->atac_dev; 1307 adapt->adapt_nchannels = atac->atac_nchannels; 1308 adapt->adapt_request = siisata_atapi_scsipi_request; 1309 adapt->adapt_minphys = siisata_atapi_minphys; 1310 atac->atac_atapi_adapter.atapi_probe_device = 1311 siisata_atapi_probe_device; 1312 1313 /* 1314 * Fill in the scsipi_channel. 1315 */ 1316 memset(chan, 0, sizeof(*chan)); 1317 chan->chan_adapter = adapt; 1318 chan->chan_bustype = &siisata_atapi_bustype; 1319 chan->chan_channel = chp->ch_channel; 1320 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1321 chan->chan_openings = 1; 1322 chan->chan_max_periph = 1; 1323 chan->chan_ntargets = 1; 1324 chan->chan_nluns = 1; 1325 1326 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1327 atapiprint); 1328 } 1329 1330 void 1331 siisata_atapi_minphys(struct buf *bp) 1332 { 1333 if (bp->b_bcount > MAXPHYS) 1334 bp->b_bcount = MAXPHYS; 1335 minphys(bp); 1336 } 1337 1338 /* 1339 * Kill off all pending xfers for a periph. 1340 * 1341 * Must be called at splbio(). 1342 */ 1343 void 1344 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1345 { 1346 struct atac_softc *atac = 1347 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1348 struct ata_channel *chp = 1349 atac->atac_channels[periph->periph_channel->chan_channel]; 1350 1351 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1352 } 1353 1354 void 1355 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1356 int reason) 1357 { 1358 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1359 1360 /* remove this command from xfer queue */ 1361 switch (reason) { 1362 case KILL_GONE: 1363 sc_xfer->error = XS_DRIVER_STUFFUP; 1364 break; 1365 case KILL_RESET: 1366 sc_xfer->error = XS_RESET; 1367 break; 1368 default: 1369 panic("%s: port %d: unknown reason %d", 1370 __func__, chp->ch_channel, reason); 1371 } 1372 ata_free_xfer(chp, xfer); 1373 scsipi_done(sc_xfer); 1374 } 1375 1376 void 1377 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1378 { 1379 struct scsipi_channel *chan = sc->sc_channel; 1380 struct scsipi_periph *periph; 1381 struct ataparams ids; 1382 struct ataparams *id = &ids; 1383 struct siisata_softc *siic = 1384 device_private(chan->chan_adapter->adapt_dev); 1385 struct atac_softc *atac = &siic->sc_atac; 1386 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1387 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1388 struct scsipibus_attach_args sa; 1389 char serial_number[21], model[41], firmware_revision[9]; 1390 int s; 1391 1392 /* skip if already attached */ 1393 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1394 return; 1395 1396 /* if no ATAPI device detected at attach time, skip */ 1397 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1398 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1399 target), DEBUG_PROBE); 1400 return; 1401 } 1402 1403 /* Some ATAPI devices need a bit more time after software reset. */ 1404 DELAY(5000); 1405 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1406 #ifdef ATAPI_DEBUG_PROBE 1407 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1408 device_xname(sc->sc_dev), target, 1409 id->atap_config & ATAPI_CFG_CMD_MASK, 1410 id->atap_config & ATAPI_CFG_DRQ_MASK); 1411 #endif 1412 periph = scsipi_alloc_periph(M_NOWAIT); 1413 if (periph == NULL) { 1414 aprint_error_dev(sc->sc_dev, 1415 "%s: unable to allocate periph for " 1416 "channel %d drive %d\n", __func__, 1417 chp->ch_channel, target); 1418 return; 1419 } 1420 periph->periph_dev = NULL; 1421 periph->periph_channel = chan; 1422 periph->periph_switch = &atapi_probe_periphsw; 1423 periph->periph_target = target; 1424 periph->periph_lun = 0; 1425 periph->periph_quirks = PQUIRK_ONLYBIG; 1426 1427 #ifdef SCSIPI_DEBUG 1428 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1429 SCSIPI_DEBUG_TARGET == target) 1430 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1431 #endif 1432 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1433 if (id->atap_config & ATAPI_CFG_REMOV) 1434 periph->periph_flags |= PERIPH_REMOVABLE; 1435 sa.sa_periph = periph; 1436 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1437 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1438 T_REMOV : T_FIXED; 1439 strnvisx(model, sizeof(model), id->atap_model, 40, 1440 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1441 strnvisx(serial_number, sizeof(serial_number), 1442 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1443 strnvisx(firmware_revision, sizeof(firmware_revision), 1444 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1445 sa.sa_inqbuf.vendor = model; 1446 sa.sa_inqbuf.product = serial_number; 1447 sa.sa_inqbuf.revision = firmware_revision; 1448 1449 /* 1450 * Determine the operating mode capabilities of the device. 1451 */ 1452 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1453 == ATAPI_CFG_CMD_16) { 1454 periph->periph_cap |= PERIPH_CAP_CMD16; 1455 1456 /* configure port for packet length */ 1457 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1458 PR_PC_PACKET_LENGTH); 1459 } else { 1460 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1461 PR_PC_PACKET_LENGTH); 1462 } 1463 1464 /* XXX This is gross. */ 1465 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1466 1467 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1468 1469 if (drvp->drv_softc) 1470 ata_probe_caps(drvp); 1471 else { 1472 s = splbio(); 1473 drvp->drive_type &= ATA_DRIVET_NONE; 1474 splx(s); 1475 } 1476 } else { 1477 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1478 "failed for drive %s:%d:%d: error 0x%x\n", 1479 __func__, SIISATANAME(siic), chp->ch_channel, target, 1480 chp->ch_error), DEBUG_PROBE); 1481 s = splbio(); 1482 drvp->drive_type &= ATA_DRIVET_NONE; 1483 splx(s); 1484 } 1485 } 1486 1487 void 1488 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1489 scsipi_adapter_req_t req, void *arg) 1490 { 1491 struct scsipi_adapter *adapt = chan->chan_adapter; 1492 struct scsipi_periph *periph; 1493 struct scsipi_xfer *sc_xfer; 1494 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1495 struct atac_softc *atac = &sc->sc_atac; 1496 struct ata_xfer *xfer; 1497 int channel = chan->chan_channel; 1498 int drive, s; 1499 1500 switch (req) { 1501 case ADAPTER_REQ_RUN_XFER: 1502 sc_xfer = arg; 1503 periph = sc_xfer->xs_periph; 1504 drive = periph->periph_target; 1505 1506 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1507 device_xname(atac->atac_dev), channel, drive), 1508 DEBUG_XFERS); 1509 1510 if (!device_is_active(atac->atac_dev)) { 1511 sc_xfer->error = XS_DRIVER_STUFFUP; 1512 scsipi_done(sc_xfer); 1513 return; 1514 } 1515 xfer = ata_get_xfer(atac->atac_channels[channel]); 1516 if (xfer == NULL) { 1517 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1518 scsipi_done(sc_xfer); 1519 return; 1520 } 1521 1522 if (sc_xfer->xs_control & XS_CTL_POLL) 1523 xfer->c_flags |= C_POLL; 1524 xfer->c_drive = drive; 1525 xfer->c_flags |= C_ATAPI; 1526 xfer->c_scsipi = sc_xfer; 1527 xfer->c_databuf = sc_xfer->data; 1528 xfer->c_bcount = sc_xfer->datalen; 1529 xfer->c_start = siisata_atapi_start; 1530 xfer->c_intr = siisata_atapi_complete; 1531 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1532 xfer->c_dscpoll = 0; 1533 s = splbio(); 1534 ata_exec_xfer(atac->atac_channels[channel], xfer); 1535 #ifdef DIAGNOSTIC 1536 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1537 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1538 panic("%s: polled command not done", __func__); 1539 #endif 1540 splx(s); 1541 return; 1542 1543 default: 1544 /* Not supported, nothing to do. */ 1545 ; 1546 } 1547 } 1548 1549 void 1550 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1551 { 1552 struct siisata_channel *schp = (struct siisata_channel *)chp; 1553 struct siisata_prb *prbp; 1554 1555 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1556 1557 int slot = SIISATA_NON_NCQ_SLOT; 1558 int i; 1559 1560 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1561 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1562 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1563 DEBUG_XFERS); 1564 1565 chp->ch_status = 0; 1566 chp->ch_error = 0; 1567 1568 prbp = schp->sch_prb[slot]; 1569 memset(prbp, 0, SIISATA_CMD_SIZE); 1570 1571 /* fill in direction for ATAPI command */ 1572 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1573 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1574 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1575 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1576 1577 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1578 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1579 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1580 1581 /* copy over ATAPI command */ 1582 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1583 1584 if (siisata_dma_setup(chp, slot, 1585 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1586 xfer->c_databuf : NULL, 1587 xfer->c_bcount, 1588 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1589 BUS_DMA_READ : BUS_DMA_WRITE) 1590 ) 1591 panic("%s", __func__); 1592 1593 if (xfer->c_flags & C_POLL) { 1594 /* polled command, disable interrupts */ 1595 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1596 siisata_disable_port_interrupt(chp); 1597 } 1598 1599 siisata_activate_prb(schp, slot); 1600 1601 if ((xfer->c_flags & C_POLL) == 0) { 1602 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1603 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1604 siisata_timeout, xfer); 1605 goto out; 1606 } 1607 1608 /* 1609 * polled command 1610 */ 1611 for (i = 0; i < ATA_DELAY / 10; i++) { 1612 if (sc_xfer->xs_status & XS_STS_DONE) 1613 break; 1614 siisata_intr_port(schp); 1615 DELAY(1000); 1616 } 1617 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1618 siisata_timeout(xfer); 1619 } 1620 /* reenable interrupts */ 1621 siisata_enable_port_interrupt(chp); 1622 out: 1623 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1624 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1625 DEBUG_FUNCS); 1626 return; 1627 } 1628 1629 int 1630 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1631 int is) 1632 { 1633 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1634 struct siisata_channel *schp = (struct siisata_channel *)chp; 1635 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1636 int slot = SIISATA_NON_NCQ_SLOT; 1637 1638 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1639 DEBUG_INTR); 1640 1641 /* this command is not active any more */ 1642 schp->sch_active_slots &= ~__BIT(slot); 1643 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1644 if (xfer->c_flags & C_TIMEOU) { 1645 sc_xfer->error = XS_TIMEOUT; 1646 } else { 1647 callout_stop(&xfer->c_timo_callout); 1648 sc_xfer->error = XS_NOERROR; 1649 } 1650 1651 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1652 schp->sch_datad[slot]->dm_mapsize, 1653 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1654 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1655 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1656 1657 ata_deactivate_xfer(chp, xfer); 1658 1659 if (ata_waitdrain_xfer_check(chp, xfer)) { 1660 sc_xfer->error = XS_DRIVER_STUFFUP; 1661 return 0; /* XXX verify */ 1662 } 1663 1664 ata_free_xfer(chp, xfer); 1665 sc_xfer->resid = sc_xfer->datalen; 1666 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1667 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1668 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1669 if ((chp->ch_status & WDCS_ERR) && 1670 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1671 sc_xfer->resid == sc_xfer->datalen)) { 1672 sc_xfer->error = XS_SHORTSENSE; 1673 sc_xfer->sense.atapi_sense = chp->ch_error; 1674 if ((sc_xfer->xs_periph->periph_quirks & 1675 PQUIRK_NOSENSE) == 0) { 1676 /* request sense */ 1677 sc_xfer->error = XS_BUSY; 1678 sc_xfer->status = SCSI_CHECK; 1679 } 1680 } 1681 scsipi_done(sc_xfer); 1682 atastart(chp); 1683 return 0; /* XXX verify */ 1684 } 1685 1686 #endif /* NATAPIBUS */ 1687
Indexes created Wed Oct 22 06:10:02 GMT 2025