siisata.c revision 1.30.4.19
1 /* $NetBSD: siisata.c,v 1.30.4.19 2017/06/21 19:38:43 jdolecek Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.30.4.19 2017/06/21 19:38:43 jdolecek Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 113 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 114 #if _BYTE_ORDER == _LITTLE_ENDIAN 115 #define bus_space_read_stream_4 bus_space_read_4 116 #define bus_space_read_region_stream_4 bus_space_read_region_4 117 #else 118 static inline uint32_t 119 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 120 { 121 return htole32(bus_space_read_4(t, h, o)); 122 } 123 124 static inline void 125 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 126 bus_size_t o, uint32_t *p, bus_size_t c) 127 { 128 bus_space_read_region_4(t, h, o, p, c); 129 for (bus_size_t i = 0; i < c; i++) { 130 p[i] = htole32(p[i]); 131 } 132 } 133 #endif 134 #endif 135 136 static void siisata_attach_port(struct siisata_softc *, int); 137 static void siisata_intr_port(struct siisata_channel *); 138 139 void siisata_probe_drive(struct ata_channel *); 140 void siisata_setup_channel(struct ata_channel *); 141 142 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 143 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 144 void siisata_reset_channel(struct ata_channel *, int); 145 int siisata_ata_addref(struct ata_drive_datas *); 146 void siisata_ata_delref(struct ata_drive_datas *); 147 void siisata_killpending(struct ata_drive_datas *); 148 149 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 150 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 151 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *); 152 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 153 154 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 155 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 156 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 158 159 void siisata_timeout(void *); 160 161 static void siisata_reinit_port(struct ata_channel *); 162 static void siisata_device_reset(struct ata_channel *); 163 static void siisata_activate_prb(struct siisata_channel *, int); 164 static void siisata_deactivate_prb(struct siisata_channel *, int); 165 static int siisata_dma_setup(struct ata_channel *chp, int, void *, 166 size_t, int); 167 168 #if NATAPIBUS > 0 169 void siisata_atapibus_attach(struct atabus_softc *); 170 void siisata_atapi_probe_device(struct atapibus_softc *, int); 171 void siisata_atapi_minphys(struct buf *); 172 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 173 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 174 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 175 void siisata_atapi_scsipi_request(struct scsipi_channel *, 176 scsipi_adapter_req_t, void *); 177 void siisata_atapi_kill_pending(struct scsipi_periph *); 178 #endif /* NATAPIBUS */ 179 180 const struct ata_bustype siisata_ata_bustype = { 181 SCSIPI_BUSTYPE_ATA, 182 siisata_ata_bio, 183 siisata_reset_drive, 184 siisata_reset_channel, 185 siisata_exec_command, 186 ata_get_params, 187 siisata_ata_addref, 188 siisata_ata_delref, 189 siisata_killpending 190 }; 191 192 #if NATAPIBUS > 0 193 static const struct scsipi_bustype siisata_atapi_bustype = { 194 SCSIPI_BUSTYPE_ATAPI, 195 atapi_scsipi_cmd, 196 atapi_interpret_sense, 197 atapi_print_addr, 198 siisata_atapi_kill_pending, 199 NULL, 200 }; 201 #endif /* NATAPIBUS */ 202 203 204 void 205 siisata_attach(struct siisata_softc *sc) 206 { 207 int i; 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 211 212 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 213 sc->sc_atac.atac_pio_cap = 4; 214 sc->sc_atac.atac_dma_cap = 2; 215 sc->sc_atac.atac_udma_cap = 6; 216 sc->sc_atac.atac_channels = sc->sc_chanarray; 217 sc->sc_atac.atac_probe = siisata_probe_drive; 218 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 219 sc->sc_atac.atac_set_modes = siisata_setup_channel; 220 #if NATAPIBUS > 0 221 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 222 #endif 223 224 /* come out of reset state */ 225 GRWRITE(sc, GR_GC, 0); 226 227 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 228 siisata_attach_port(sc, i); 229 } 230 231 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 232 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 233 return; 234 } 235 236 static void 237 siisata_disable_port_interrupt(struct ata_channel *chp) 238 { 239 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 240 241 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 242 } 243 244 static void 245 siisata_enable_port_interrupt(struct ata_channel *chp) 246 { 247 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 248 249 /* enable CmdErrr+CmdCmpl interrupting */ 250 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 251 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 252 } 253 254 static void 255 siisata_init_port(struct siisata_softc *sc, int port) 256 { 257 struct siisata_channel *schp; 258 struct ata_channel *chp; 259 260 schp = &sc->sc_channels[port]; 261 chp = (struct ata_channel *)schp; 262 263 /* 264 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 265 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 266 */ 267 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 268 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 269 /* initialize port */ 270 siisata_reinit_port(chp); 271 /* enable CmdErrr+CmdCmpl interrupting */ 272 siisata_enable_port_interrupt(chp); 273 /* enable port interrupt */ 274 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 275 } 276 277 static void 278 siisata_attach_port(struct siisata_softc *sc, int port) 279 { 280 int j; 281 int dmasize; 282 int error; 283 void *prbp; 284 struct siisata_channel *schp; 285 struct ata_channel *chp; 286 287 schp = &sc->sc_channels[port]; 288 chp = (struct ata_channel *)schp; 289 sc->sc_chanarray[port] = chp; 290 chp->ch_channel = port; 291 chp->ch_atac = &sc->sc_atac; 292 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 293 if (chp->ch_queue == NULL) { 294 aprint_error_dev(sc->sc_atac.atac_dev, 295 "port %d: can't allocate memory " 296 "for command queue\n", chp->ch_channel); 297 return; 298 } 299 300 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 301 302 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 303 __func__, dmasize), DEBUG_FUNCS); 304 305 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 306 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 307 if (error) { 308 aprint_error_dev(sc->sc_atac.atac_dev, 309 "unable to allocate PRB table memory, " 310 "error=%d\n", error); 311 return; 312 } 313 314 error = bus_dmamem_map(sc->sc_dmat, 315 &schp->sch_prb_seg, schp->sch_prb_nseg, 316 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 317 if (error) { 318 aprint_error_dev(sc->sc_atac.atac_dev, 319 "unable to map PRB table memory, " 320 "error=%d\n", error); 321 bus_dmamem_free(sc->sc_dmat, 322 &schp->sch_prb_seg, schp->sch_prb_nseg); 323 return; 324 } 325 326 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 327 BUS_DMA_NOWAIT, &schp->sch_prbd); 328 if (error) { 329 aprint_error_dev(sc->sc_atac.atac_dev, 330 "unable to create PRB table map, " 331 "error=%d\n", error); 332 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 333 bus_dmamem_free(sc->sc_dmat, 334 &schp->sch_prb_seg, schp->sch_prb_nseg); 335 return; 336 } 337 338 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 339 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 340 if (error) { 341 aprint_error_dev(sc->sc_atac.atac_dev, 342 "unable to load PRB table map, " 343 "error=%d\n", error); 344 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 345 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 346 bus_dmamem_free(sc->sc_dmat, 347 &schp->sch_prb_seg, schp->sch_prb_nseg); 348 return; 349 } 350 351 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 352 schp->sch_prb[j] = (struct siisata_prb *) 353 ((char *)prbp + SIISATA_CMD_SIZE * j); 354 schp->sch_bus_prb[j] = 355 schp->sch_prbd->dm_segs[0].ds_addr + 356 SIISATA_CMD_SIZE * j; 357 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 358 SIISATA_NSGE, MAXPHYS, 0, 359 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 360 &schp->sch_datad[j]); 361 if (error) { 362 aprint_error_dev(sc->sc_atac.atac_dev, 363 "couldn't create xfer DMA map, error=%d\n", 364 error); 365 return; 366 } 367 } 368 369 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 370 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 371 aprint_error_dev(sc->sc_atac.atac_dev, 372 "couldn't map port %d SStatus regs\n", 373 chp->ch_channel); 374 return; 375 } 376 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 377 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 378 aprint_error_dev(sc->sc_atac.atac_dev, 379 "couldn't map port %d SControl regs\n", 380 chp->ch_channel); 381 return; 382 } 383 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 384 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 385 aprint_error_dev(sc->sc_atac.atac_dev, 386 "couldn't map port %d SError regs\n", 387 chp->ch_channel); 388 return; 389 } 390 391 siisata_init_port(sc, port); 392 393 ata_channel_attach(chp); 394 395 return; 396 } 397 398 int 399 siisata_detach(struct siisata_softc *sc, int flags) 400 { 401 struct atac_softc *atac = &sc->sc_atac; 402 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 403 struct siisata_channel *schp; 404 struct ata_channel *chp; 405 int i, j, error; 406 407 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 408 schp = &sc->sc_channels[i]; 409 chp = sc->sc_chanarray[i]; 410 411 if (chp->atabus == NULL) 412 continue; 413 if ((error = config_detach(chp->atabus, flags)) != 0) 414 return error; 415 416 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 417 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 418 419 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 420 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 421 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 422 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 423 bus_dmamem_free(sc->sc_dmat, 424 &schp->sch_prb_seg, schp->sch_prb_nseg); 425 426 free(chp->ch_queue, M_DEVBUF); 427 chp->atabus = NULL; 428 429 ata_channel_detach(chp); 430 } 431 432 if (adapt->adapt_refcnt != 0) 433 return EBUSY; 434 435 /* leave the chip in reset */ 436 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 437 438 return 0; 439 } 440 441 void 442 siisata_resume(struct siisata_softc *sc) 443 { 444 int i; 445 446 /* come out of reset state */ 447 GRWRITE(sc, GR_GC, 0); 448 449 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 450 siisata_init_port(sc, i); 451 } 452 453 } 454 455 int 456 siisata_intr(void *v) 457 { 458 struct siisata_softc *sc = v; 459 uint32_t is; 460 int i, r = 0; 461 while ((is = GRREAD(sc, GR_GIS))) { 462 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 463 SIISATANAME(sc), __func__, is), DEBUG_INTR); 464 r = 1; 465 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 466 if (is & GR_GIS_PXIS(i)) 467 siisata_intr_port(&sc->sc_channels[i]); 468 } 469 return r; 470 } 471 472 static void 473 siisata_intr_port(struct siisata_channel *schp) 474 { 475 struct siisata_softc *sc; 476 struct ata_channel *chp; 477 struct ata_xfer *xfer; 478 u_int slot; 479 uint32_t pss, pis; 480 uint32_t prbfis; 481 482 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 483 chp = &schp->ata_channel; 484 485 /* get slot status, clearing completion interrupt (PR_PIS_CMDCMPL) */ 486 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 487 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x\n", 488 SIISATANAME(sc), __func__, chp->ch_channel, pss), DEBUG_INTR); 489 490 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 491 if (((schp->sch_active_slots >> slot) & 1) == 0) 492 /* there's nothing executing here, skip */ 493 continue; 494 if (((pss >> slot) & 1) != 0) 495 /* execution is incomplete or unsuccessful, skip for now */ 496 continue; 497 xfer = ata_queue_hwslot_to_xfer(chp, slot); 498 if (xfer->c_intr == NULL) { 499 wakeup(schp); 500 continue; 501 } 502 KASSERT(xfer != NULL); 503 KASSERT(xfer->c_intr != NULL); 504 xfer->c_intr(chp, xfer, 0); 505 } 506 /* if no errors, we're done now */ 507 if ((pss & PR_PSS_ATTENTION) == 0) { 508 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 509 pis &= 0xffff; 510 if (pis) { 511 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 512 pis & 0xfffcfffc); 513 } 514 return; 515 } 516 517 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 518 519 SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x ", SIISATANAME(sc), 520 __func__, chp->ch_channel, pis), DEBUG_INTR); 521 522 if (pis & PR_PIS_CMDERRR) { 523 uint32_t ec; 524 uint32_t ps; 525 526 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 527 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 528 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 529 530 slot = PR_PS_ACTIVE_SLOT(ps); /* XXX invalid for NCQ? */ 531 532 /* emulate a CRC error by default */ 533 chp->ch_status = WDCS_ERR; 534 chp->ch_error = WDCE_CRC; 535 536 if (ec <= PR_PCE_DATAFISERROR) { 537 if (ec == PR_PCE_DEVICEERROR) { 538 /* read in specific information about error */ 539 prbfis = bus_space_read_stream_4( 540 sc->sc_prt, sc->sc_prh, 541 PRSX(chp->ch_channel, slot, 542 PRSO_FIS)); 543 /* set ch_status and ch_error */ 544 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 545 } 546 siisata_reinit_port(chp); 547 } else { 548 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 549 " on channel %d (ctx 0x%x), resetting\n", 550 ec, chp->ch_channel, 551 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 552 /* okay, we have a "Fatal Error" */ 553 siisata_device_reset(chp); 554 } 555 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 556 /* there's nothing executing here, skip */ 557 if (((schp->sch_active_slots >> slot) & 1) == 0) 558 continue; 559 xfer = ata_queue_hwslot_to_xfer(chp, slot); 560 if (xfer == NULL) 561 continue; 562 xfer->c_intr(chp, xfer, 0); 563 } 564 } 565 566 /* clear */ 567 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis); 568 569 return; 570 } 571 572 void 573 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 574 { 575 struct ata_channel *chp = drvp->chnl_softc; 576 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 577 struct siisata_channel *schp = (struct siisata_channel *)chp; 578 struct siisata_prb *prb; 579 struct ata_xfer *xfer; 580 uint32_t pss, pis; 581 int i; 582 583 /* wait for ready */ 584 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 585 DELAY(10); 586 587 /* 588 * Try to get available slot. If there is none available, must 589 * do full channel reset. 590 */ 591 xfer = ata_get_xfer_ext(chp, false, 0); 592 if (xfer == NULL) { 593 siisata_reset_channel(chp, flags); 594 return; 595 } 596 597 prb = schp->sch_prb[xfer->c_slot]; 598 memset(prb, 0, SIISATA_CMD_SIZE); 599 prb->prb_control = 600 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 601 KASSERT(drvp->drive <= PMP_PORT_CTL); 602 prb->prb_fis[rhd_c] = drvp->drive; 603 604 siisata_disable_port_interrupt(chp); 605 606 siisata_activate_prb(schp, xfer->c_slot); 607 608 for(i = 0; i < 3100; i++) { 609 #if 1 /* XXX-jak-jd-ncq this block needs re-work... XXX */ 610 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_INCOR); 611 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 612 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_INCOR); 613 if ((pss & PR_PXSS(xfer->c_slot)) == 0) 614 break; 615 if (pss & PR_PSS_ATTENTION) 616 break; 617 #else 618 pss = PR_PXSS(xfer->c_slot); 619 /* XXX DO NOT MERGE UNTIL THIS IS FIXED XXX */ 620 #endif 621 ata_delay(10, "siiprb", flags); 622 } 623 624 siisata_deactivate_prb(schp, xfer->c_slot); 625 626 if ((pss & PR_PSS_ATTENTION) != 0) { 627 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 628 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 629 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 630 if (slot != xfer->c_slot) 631 device_printf(sc->sc_atac.atac_dev, "%s port %d " 632 "drive %d slot %d c_slot %d", __func__, 633 chp->ch_channel, drvp->drive, slot, xfer->c_slot); 634 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 635 PR_PIS_CMDERRR); 636 } 637 638 siisata_enable_port_interrupt(chp); 639 640 if (i == 3100) { 641 /* timeout */ 642 siisata_device_reset(chp); /* XXX is this right? */ 643 if (sigp) 644 *sigp = 0xffffffff; 645 } else { 646 /* read the signature out of the FIS */ 647 if (sigp) { 648 *sigp = 0; 649 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 650 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 651 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 652 PRSO_FIS+0xc)) & 0xff; 653 } 654 } 655 656 ata_free_xfer(chp, xfer); 657 658 #if 1 659 /* attempt to downgrade signaling in event of CRC error */ 660 /* XXX should be part of the MI (S)ATA subsystem */ 661 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 662 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 663 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 664 DELAY(10); 665 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 666 SControl_IPM_NONE | SControl_SPD_G1); 667 DELAY(10); 668 for (;;) { 669 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 670 & SStatus_DET_mask) == SStatus_DET_DEV) 671 break; 672 DELAY(10); 673 } 674 } 675 #endif 676 677 #if 1 678 chp->ch_status = 0; 679 chp->ch_error = 0; 680 #endif 681 return; 682 } 683 684 void 685 siisata_reset_channel(struct ata_channel *chp, int flags) 686 { 687 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 688 struct siisata_channel *schp = (struct siisata_channel *)chp; 689 690 SIISATA_DEBUG_PRINT(("%s: %s channel %d\n", SIISATANAME(sc), __func__, 691 chp->ch_channel), DEBUG_FUNCS); 692 693 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 694 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 695 aprint_error("%s port %d: reset failed\n", 696 SIISATANAME(sc), chp->ch_channel); 697 /* XXX and then ? */ 698 } 699 /* wait for ready */ 700 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 701 DELAY(10); 702 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 703 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 704 ata_kill_active(chp, KILL_RESET, flags); 705 706 return; 707 } 708 709 int 710 siisata_ata_addref(struct ata_drive_datas *drvp) 711 { 712 return 0; 713 } 714 715 void 716 siisata_ata_delref(struct ata_drive_datas *drvp) 717 { 718 return; 719 } 720 721 void 722 siisata_killpending(struct ata_drive_datas *drvp) 723 { 724 return; 725 } 726 727 void 728 siisata_probe_drive(struct ata_channel *chp) 729 { 730 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 731 struct siisata_channel *schp = (struct siisata_channel *)chp; 732 int i; 733 uint32_t sig; 734 struct siisata_prb *prb; 735 bool timed_out; 736 struct ata_xfer *xfer; 737 738 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 739 __func__, chp->ch_channel), DEBUG_FUNCS); 740 741 xfer = ata_get_xfer(chp); 742 if (xfer == NULL) { 743 aprint_error_dev(sc->sc_atac.atac_dev, 744 "failed to get xfer port %d\n", 745 chp->ch_channel); 746 return; 747 } 748 749 /* 750 * disable port interrupt as we're polling for PHY up and 751 * prb completion 752 */ 753 siisata_disable_port_interrupt(chp); 754 755 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 756 schp->sch_sstatus, AT_WAIT)) { 757 case SStatus_DET_DEV: 758 #if 0 /* XXX Including this seems to cause problems. */ 759 /* XXX DO NOT MERGE UNTIL THIS IS ADDRESSED PROPERLY XXX */ 760 /* clear any interrupts */ 761 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 762 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 763 #endif 764 /* wait for ready */ 765 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 766 & PR_PS_PORT_READY)) 767 DELAY(10); 768 prb = schp->sch_prb[xfer->c_slot]; 769 memset(prb, 0, SIISATA_CMD_SIZE); 770 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 771 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 772 773 siisata_activate_prb(schp, xfer->c_slot); 774 775 timed_out = 1; 776 for(i = 0; i < 3100; i++) { 777 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 778 PR_PXSS(xfer->c_slot)) == 0) { 779 /* prb completed */ 780 timed_out = 0; 781 break; 782 } 783 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 784 (PR_PIS_CMDERRR << 16)) { 785 /* we got an error; handle as timeout */ 786 break; 787 } 788 789 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 790 } 791 792 siisata_deactivate_prb(schp, xfer->c_slot); 793 794 if (timed_out) { 795 aprint_error_dev(sc->sc_atac.atac_dev, 796 "SOFT_RESET failed on port %d (error %d PSS 0x%x), " 797 "resetting\n", chp->ch_channel, 798 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 799 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); 800 siisata_reinit_port(chp); 801 break; 802 } 803 804 /* read the signature out of the FIS */ 805 sig = 0; 806 sig |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 807 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 808 sig |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 809 PRSO_FIS+0xc)) & 0xff; 810 811 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 812 __func__, sig), DEBUG_PROBE); 813 814 if (sig == 0x96690101) 815 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 816 PR_PC_PMP_ENABLE); 817 sata_interpret_sig(chp, 0, sig); 818 break; 819 default: 820 break; 821 } 822 823 siisata_enable_port_interrupt(chp); 824 825 ata_free_xfer(chp, xfer); 826 827 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 828 __func__, chp->ch_channel), DEBUG_PROBE); 829 return; 830 } 831 832 void 833 siisata_setup_channel(struct ata_channel *chp) 834 { 835 return; 836 } 837 838 int 839 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 840 { 841 struct ata_channel *chp = drvp->chnl_softc; 842 struct ata_command *ata_c = &xfer->c_ata_c; 843 int ret; 844 int s; 845 846 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 847 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 848 DEBUG_FUNCS); 849 850 if (ata_c->flags & AT_POLL) 851 xfer->c_flags |= C_POLL; 852 if (ata_c->flags & AT_WAIT) 853 xfer->c_flags |= C_WAIT; 854 xfer->c_drive = drvp->drive; 855 xfer->c_databuf = ata_c->data; 856 xfer->c_bcount = ata_c->bcount; 857 xfer->c_start = siisata_cmd_start; 858 xfer->c_intr = siisata_cmd_complete; 859 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 860 s = splbio(); 861 ata_exec_xfer(chp, xfer); 862 #ifdef DIAGNOSTIC 863 if ((ata_c->flags & AT_POLL) != 0 && 864 (ata_c->flags & AT_DONE) == 0) 865 panic("%s: polled command not done", __func__); 866 #endif 867 if (ata_c->flags & AT_DONE) { 868 ret = ATACMD_COMPLETE; 869 } else { 870 if (ata_c->flags & AT_WAIT) { 871 while ((ata_c->flags & AT_DONE) == 0) { 872 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 873 SIISATANAME( 874 (struct siisata_softc *)chp->ch_atac), 875 __func__), DEBUG_FUNCS); 876 tsleep(ata_c, PRIBIO, "siicmd", 0); 877 } 878 ret = ATACMD_COMPLETE; 879 } else { 880 ret = ATACMD_QUEUED; 881 } 882 } 883 splx(s); 884 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 885 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 886 DEBUG_FUNCS); 887 return ret; 888 } 889 890 void 891 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 892 { 893 struct siisata_channel *schp = (struct siisata_channel *)chp; 894 struct ata_command *ata_c = &xfer->c_ata_c; 895 struct siisata_prb *prb; 896 int i; 897 898 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 899 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 900 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 901 DEBUG_FUNCS|DEBUG_XFERS); 902 903 chp->ch_status = 0; 904 chp->ch_error = 0; 905 906 prb = schp->sch_prb[xfer->c_slot]; 907 memset(prb, 0, SIISATA_CMD_SIZE); 908 909 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 910 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 911 prb->prb_fis[rhd_c] |= xfer->c_drive; 912 913 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 914 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 915 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 916 } 917 918 if (siisata_dma_setup(chp, xfer->c_slot, 919 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 920 ata_c->bcount, 921 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 922 ata_c->flags |= AT_DF; 923 siisata_cmd_complete(chp, xfer, 0); 924 return; 925 } 926 927 if (xfer->c_flags & C_POLL) { 928 /* polled command, disable interrupts */ 929 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 930 siisata_disable_port_interrupt(chp); 931 } 932 933 /* go for it */ 934 siisata_activate_prb(schp, xfer->c_slot); 935 936 if ((ata_c->flags & AT_POLL) == 0) { 937 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 938 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 939 siisata_timeout, xfer); 940 goto out; 941 } 942 943 /* 944 * polled command 945 */ 946 for (i = 0; i < ata_c->timeout / 10; i++) { 947 if (ata_c->flags & AT_DONE) 948 break; 949 siisata_intr_port(schp); 950 DELAY(1000); 951 } 952 953 if ((ata_c->flags & AT_DONE) == 0) { 954 siisata_timeout(xfer); 955 } 956 957 /* reenable interrupts */ 958 siisata_enable_port_interrupt(chp); 959 out: 960 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 961 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 962 DEBUG_FUNCS); 963 return; 964 } 965 966 void 967 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 968 int reason) 969 { 970 struct ata_command *ata_c = &xfer->c_ata_c; 971 struct siisata_channel *schp = (struct siisata_channel *)chp; 972 973 siisata_deactivate_prb(schp, xfer->c_slot); 974 ata_deactivate_xfer(chp, xfer); 975 976 switch (reason) { 977 case KILL_GONE: 978 ata_c->flags |= AT_GONE; 979 break; 980 case KILL_RESET: 981 ata_c->flags |= AT_RESET; 982 break; 983 default: 984 panic("%s: port %d: unknown reason %d", 985 __func__, chp->ch_channel, reason); 986 } 987 siisata_cmd_done(chp, xfer); 988 } 989 990 int 991 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 992 { 993 struct siisata_channel *schp = (struct siisata_channel *)chp; 994 struct ata_command *ata_c = &xfer->c_ata_c; 995 #ifdef SIISATA_DEBUG 996 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 997 #endif 998 999 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1000 SIISATANAME(sc), __func__, 1001 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1002 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1003 DEBUG_FUNCS|DEBUG_XFERS); 1004 1005 siisata_deactivate_prb(schp, xfer->c_slot); 1006 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1007 if (xfer->c_flags & C_TIMEOU) 1008 ata_c->flags |= AT_TIMEOU; 1009 else 1010 callout_stop(&xfer->c_timo_callout); 1011 1012 if (chp->ch_status & WDCS_BSY) { 1013 ata_c->flags |= AT_TIMEOU; 1014 } else if (chp->ch_status & WDCS_ERR) { 1015 ata_c->r_error = chp->ch_error; 1016 ata_c->flags |= AT_ERROR; 1017 } 1018 1019 ata_deactivate_xfer(chp, xfer); 1020 1021 if (!ata_waitdrain_xfer_check(chp, xfer)) { 1022 siisata_cmd_done(chp, xfer); 1023 } 1024 1025 return 0; 1026 } 1027 1028 void 1029 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1030 { 1031 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1032 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1033 struct siisata_channel *schp = (struct siisata_channel *)chp; 1034 struct ata_command *ata_c = &xfer->c_ata_c; 1035 uint16_t *idwordbuf; 1036 int i; 1037 1038 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1039 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1040 1041 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1042 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1043 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1044 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1045 BUS_DMASYNC_POSTWRITE); 1046 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1047 } 1048 1049 if (ata_c->flags & AT_READREG) { 1050 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1051 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1052 fis, __arraycount(fis)); 1053 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1054 } 1055 1056 /* correct the endianess of IDENTIFY data */ 1057 if (ata_c->r_command == WDCC_IDENTIFY || 1058 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1059 idwordbuf = xfer->c_databuf; 1060 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1061 idwordbuf[i] = le16toh(idwordbuf[i]); 1062 } 1063 } 1064 1065 ata_c->flags |= AT_DONE; 1066 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1067 ata_c->flags |= AT_XFDONE; 1068 1069 if (ata_c->flags & AT_WAIT) 1070 wakeup(ata_c); 1071 else if (ata_c->callback) 1072 ata_c->callback(ata_c->callback_arg); 1073 atastart(chp); 1074 return; 1075 } 1076 1077 int 1078 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1079 { 1080 struct ata_channel *chp = drvp->chnl_softc; 1081 struct ata_bio *ata_bio = &xfer->c_bio; 1082 1083 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1084 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1085 DEBUG_FUNCS); 1086 1087 if (xfer == NULL) 1088 return ATACMD_TRY_AGAIN; 1089 if (ata_bio->flags & ATA_POLL) 1090 xfer->c_flags |= C_POLL; 1091 xfer->c_drive = drvp->drive; 1092 xfer->c_databuf = ata_bio->databuf; 1093 xfer->c_bcount = ata_bio->bcount; 1094 xfer->c_start = siisata_bio_start; 1095 xfer->c_intr = siisata_bio_complete; 1096 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1097 ata_exec_xfer(chp, xfer); 1098 return (ata_bio->flags & ATA_ITSDONE) ? 1099 ATACMD_COMPLETE : ATACMD_QUEUED; 1100 } 1101 1102 void 1103 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1104 { 1105 struct siisata_channel *schp = (struct siisata_channel *)chp; 1106 struct siisata_prb *prb; 1107 struct ata_bio *ata_bio = &xfer->c_bio; 1108 int i; 1109 1110 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1111 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1112 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1113 1114 chp->ch_status = 0; 1115 chp->ch_error = 0; 1116 1117 prb = schp->sch_prb[xfer->c_slot]; 1118 memset(prb, 0, SIISATA_CMD_SIZE); 1119 1120 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1121 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1122 prb->prb_fis[rhd_c] |= xfer->c_drive; 1123 1124 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1125 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1126 ata_bio->error = ERR_DMA; 1127 ata_bio->r_error = 0; 1128 siisata_bio_complete(chp, xfer, 0); 1129 return; 1130 } 1131 1132 if (xfer->c_flags & C_POLL) { 1133 /* polled command, disable interrupts */ 1134 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1135 siisata_disable_port_interrupt(chp); 1136 } 1137 1138 siisata_activate_prb(schp, xfer->c_slot); 1139 1140 if ((ata_bio->flags & ATA_POLL) == 0) { 1141 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1142 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1143 siisata_timeout, xfer); 1144 goto out; 1145 } 1146 1147 /* 1148 * polled command 1149 */ 1150 for (i = 0; i < ATA_DELAY / 10; i++) { 1151 if (ata_bio->flags & ATA_ITSDONE) 1152 break; 1153 siisata_intr_port(schp); 1154 DELAY(1000); 1155 } 1156 1157 siisata_enable_port_interrupt(chp); 1158 out: 1159 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1160 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1161 DEBUG_FUNCS); 1162 return; 1163 } 1164 1165 void 1166 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1167 int reason) 1168 { 1169 struct siisata_channel *schp = (struct siisata_channel *)chp; 1170 struct ata_bio *ata_bio = &xfer->c_bio; 1171 int drive = xfer->c_drive; 1172 1173 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1174 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1175 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1176 1177 siisata_deactivate_prb(schp, xfer->c_slot); 1178 ata_deactivate_xfer(chp, xfer); 1179 1180 ata_bio->flags |= ATA_ITSDONE; 1181 switch (reason) { 1182 case KILL_GONE: 1183 ata_bio->error = ERR_NODEV; 1184 break; 1185 case KILL_RESET: 1186 ata_bio->error = ERR_RESET; 1187 break; 1188 default: 1189 panic("%s: port %d: unknown reason %d", 1190 __func__, chp->ch_channel, reason); 1191 } 1192 ata_bio->r_error = WDCE_ABRT; 1193 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1194 } 1195 1196 int 1197 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1198 { 1199 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1200 struct siisata_channel *schp = (struct siisata_channel *)chp; 1201 struct ata_bio *ata_bio = &xfer->c_bio; 1202 int drive = xfer->c_drive; 1203 1204 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d\n", 1205 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1206 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1207 1208 siisata_deactivate_prb(schp, xfer->c_slot); 1209 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1210 if (xfer->c_flags & C_TIMEOU) { 1211 ata_bio->error = TIMEOUT; 1212 } else { 1213 callout_stop(&xfer->c_timo_callout); 1214 ata_bio->error = NOERROR; 1215 } 1216 1217 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1218 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1219 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1220 BUS_DMASYNC_POSTWRITE); 1221 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1222 1223 ata_deactivate_xfer(chp, xfer); 1224 1225 if (ata_waitdrain_xfer_check(chp, xfer)) { 1226 return 0; 1227 } 1228 1229 ata_bio->flags |= ATA_ITSDONE; 1230 if (chp->ch_status & WDCS_DWF) { 1231 ata_bio->error = ERR_DF; 1232 } else if (chp->ch_status & WDCS_ERR) { 1233 ata_bio->error = ERROR; 1234 ata_bio->r_error = chp->ch_error; 1235 } else if (chp->ch_status & WDCS_CORR) 1236 ata_bio->flags |= ATA_CORR; 1237 1238 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1239 ata_bio->bcount), DEBUG_XFERS); 1240 if (ata_bio->error == NOERROR) { 1241 if (ata_bio->flags & ATA_READ) 1242 ata_bio->bcount -= 1243 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1244 else 1245 ata_bio->bcount = 0; 1246 } 1247 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1248 if (ata_bio->flags & ATA_POLL) 1249 return 1; 1250 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1251 atastart(chp); 1252 return 0; 1253 } 1254 1255 void 1256 siisata_timeout(void *v) 1257 { 1258 struct ata_xfer *xfer = v; 1259 struct ata_channel *chp = xfer->c_chp; 1260 int s = splbio(); 1261 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1262 siisata_device_reset(chp); 1263 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1264 xfer->c_flags |= C_TIMEOU; 1265 xfer->c_intr(chp, xfer, 0); 1266 } 1267 splx(s); 1268 } 1269 1270 static int 1271 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1272 size_t count, int op) 1273 { 1274 1275 int error, seg; 1276 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1277 struct siisata_channel *schp = (struct siisata_channel *)chp; 1278 1279 struct siisata_prb *prbp; 1280 1281 prbp = schp->sch_prb[slot]; 1282 1283 if (data == NULL) { 1284 goto end; 1285 } 1286 1287 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1288 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1289 if (error) { 1290 aprint_error("%s port %d: " 1291 "failed to load xfer in slot %d: error %d\n", 1292 SIISATANAME(sc), chp->ch_channel, slot, error); 1293 return error; 1294 } 1295 1296 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1297 schp->sch_datad[slot]->dm_mapsize, 1298 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1299 1300 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1301 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1302 DEBUG_FUNCS | DEBUG_DEBUG); 1303 1304 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1305 prbp->prb_sge[seg].sge_da = 1306 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1307 prbp->prb_sge[seg].sge_dc = 1308 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1309 prbp->prb_sge[seg].sge_flags = htole32(0); 1310 } 1311 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1312 end: 1313 return 0; 1314 } 1315 1316 static void 1317 siisata_activate_prb(struct siisata_channel *schp, int slot) 1318 { 1319 struct siisata_softc *sc; 1320 bus_size_t offset; 1321 uint64_t pprb; 1322 1323 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1324 1325 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != __BIT(slot), 1326 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1327 1328 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1329 /* keep track of what's going on */ 1330 schp->sch_active_slots |= __BIT(slot); 1331 1332 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1333 1334 pprb = schp->sch_bus_prb[slot]; 1335 1336 PRWRITE(sc, offset + 0, pprb >> 0); 1337 PRWRITE(sc, offset + 4, pprb >> 32); 1338 } 1339 1340 static void 1341 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1342 { 1343 struct siisata_softc *sc; 1344 1345 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1346 1347 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1348 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1349 slot); 1350 1351 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1352 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1353 } 1354 1355 static void 1356 siisata_reinit_port(struct ata_channel *chp) 1357 { 1358 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1359 1360 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1361 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1362 DELAY(10); 1363 if (chp->ch_ndrives > 1) 1364 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1365 } 1366 1367 static void 1368 siisata_device_reset(struct ata_channel *chp) 1369 { 1370 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1371 1372 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1373 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1374 DELAY(10); 1375 } 1376 1377 1378 #if NATAPIBUS > 0 1379 void 1380 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1381 { 1382 struct ata_channel *chp = ata_sc->sc_chan; 1383 struct atac_softc *atac = chp->ch_atac; 1384 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1385 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1386 1387 /* 1388 * Fill in the scsipi_adapter. 1389 */ 1390 adapt->adapt_dev = atac->atac_dev; 1391 adapt->adapt_nchannels = atac->atac_nchannels; 1392 adapt->adapt_request = siisata_atapi_scsipi_request; 1393 adapt->adapt_minphys = siisata_atapi_minphys; 1394 atac->atac_atapi_adapter.atapi_probe_device = 1395 siisata_atapi_probe_device; 1396 1397 /* 1398 * Fill in the scsipi_channel. 1399 */ 1400 memset(chan, 0, sizeof(*chan)); 1401 chan->chan_adapter = adapt; 1402 chan->chan_bustype = &siisata_atapi_bustype; 1403 chan->chan_channel = chp->ch_channel; 1404 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1405 chan->chan_openings = 1; 1406 chan->chan_max_periph = 1; 1407 chan->chan_ntargets = 1; 1408 chan->chan_nluns = 1; 1409 1410 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1411 atapiprint); 1412 } 1413 1414 void 1415 siisata_atapi_minphys(struct buf *bp) 1416 { 1417 if (bp->b_bcount > MAXPHYS) 1418 bp->b_bcount = MAXPHYS; 1419 minphys(bp); 1420 } 1421 1422 /* 1423 * Kill off all pending xfers for a periph. 1424 * 1425 * Must be called at splbio(). 1426 */ 1427 void 1428 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1429 { 1430 struct atac_softc *atac = 1431 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1432 struct ata_channel *chp = 1433 atac->atac_channels[periph->periph_channel->chan_channel]; 1434 1435 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1436 } 1437 1438 void 1439 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1440 int reason) 1441 { 1442 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1443 struct siisata_channel *schp = (struct siisata_channel *)chp; 1444 1445 siisata_deactivate_prb(schp, xfer->c_slot); 1446 ata_deactivate_xfer(chp, xfer); 1447 1448 /* remove this command from xfer queue */ 1449 switch (reason) { 1450 case KILL_GONE: 1451 sc_xfer->error = XS_DRIVER_STUFFUP; 1452 break; 1453 case KILL_RESET: 1454 sc_xfer->error = XS_RESET; 1455 break; 1456 default: 1457 panic("%s: port %d: unknown reason %d", 1458 __func__, chp->ch_channel, reason); 1459 } 1460 ata_free_xfer(chp, xfer); 1461 scsipi_done(sc_xfer); 1462 } 1463 1464 void 1465 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1466 { 1467 struct scsipi_channel *chan = sc->sc_channel; 1468 struct scsipi_periph *periph; 1469 struct ataparams ids; 1470 struct ataparams *id = &ids; 1471 struct siisata_softc *siic = 1472 device_private(chan->chan_adapter->adapt_dev); 1473 struct atac_softc *atac = &siic->sc_atac; 1474 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1475 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1476 struct scsipibus_attach_args sa; 1477 char serial_number[21], model[41], firmware_revision[9]; 1478 int s; 1479 1480 /* skip if already attached */ 1481 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1482 return; 1483 1484 /* if no ATAPI device detected at attach time, skip */ 1485 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1486 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1487 target), DEBUG_PROBE); 1488 return; 1489 } 1490 1491 /* Some ATAPI devices need a bit more time after software reset. */ 1492 DELAY(5000); 1493 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1494 #ifdef ATAPI_DEBUG_PROBE 1495 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1496 device_xname(sc->sc_dev), target, 1497 id->atap_config & ATAPI_CFG_CMD_MASK, 1498 id->atap_config & ATAPI_CFG_DRQ_MASK); 1499 #endif 1500 periph = scsipi_alloc_periph(M_NOWAIT); 1501 if (periph == NULL) { 1502 aprint_error_dev(sc->sc_dev, 1503 "%s: unable to allocate periph for " 1504 "channel %d drive %d\n", __func__, 1505 chp->ch_channel, target); 1506 return; 1507 } 1508 periph->periph_dev = NULL; 1509 periph->periph_channel = chan; 1510 periph->periph_switch = &atapi_probe_periphsw; 1511 periph->periph_target = target; 1512 periph->periph_lun = 0; 1513 periph->periph_quirks = PQUIRK_ONLYBIG; 1514 1515 #ifdef SCSIPI_DEBUG 1516 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1517 SCSIPI_DEBUG_TARGET == target) 1518 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1519 #endif 1520 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1521 if (id->atap_config & ATAPI_CFG_REMOV) 1522 periph->periph_flags |= PERIPH_REMOVABLE; 1523 sa.sa_periph = periph; 1524 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1525 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1526 T_REMOV : T_FIXED; 1527 strnvisx(model, sizeof(model), id->atap_model, 40, 1528 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1529 strnvisx(serial_number, sizeof(serial_number), 1530 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1531 strnvisx(firmware_revision, sizeof(firmware_revision), 1532 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1533 sa.sa_inqbuf.vendor = model; 1534 sa.sa_inqbuf.product = serial_number; 1535 sa.sa_inqbuf.revision = firmware_revision; 1536 1537 /* 1538 * Determine the operating mode capabilities of the device. 1539 */ 1540 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1541 == ATAPI_CFG_CMD_16) { 1542 periph->periph_cap |= PERIPH_CAP_CMD16; 1543 1544 /* configure port for packet length */ 1545 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1546 PR_PC_PACKET_LENGTH); 1547 } else { 1548 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1549 PR_PC_PACKET_LENGTH); 1550 } 1551 1552 /* XXX This is gross. */ 1553 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1554 1555 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1556 1557 if (drvp->drv_softc) 1558 ata_probe_caps(drvp); 1559 else { 1560 s = splbio(); 1561 drvp->drive_type &= ATA_DRIVET_NONE; 1562 splx(s); 1563 } 1564 } else { 1565 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1566 "failed for drive %s:%d:%d: error 0x%x\n", 1567 __func__, SIISATANAME(siic), chp->ch_channel, target, 1568 chp->ch_error), DEBUG_PROBE); 1569 s = splbio(); 1570 drvp->drive_type &= ATA_DRIVET_NONE; 1571 splx(s); 1572 } 1573 } 1574 1575 void 1576 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1577 scsipi_adapter_req_t req, void *arg) 1578 { 1579 struct scsipi_adapter *adapt = chan->chan_adapter; 1580 struct scsipi_periph *periph; 1581 struct scsipi_xfer *sc_xfer; 1582 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1583 struct atac_softc *atac = &sc->sc_atac; 1584 struct ata_xfer *xfer; 1585 int channel = chan->chan_channel; 1586 int drive, s; 1587 1588 switch (req) { 1589 case ADAPTER_REQ_RUN_XFER: 1590 sc_xfer = arg; 1591 periph = sc_xfer->xs_periph; 1592 drive = periph->periph_target; 1593 1594 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1595 device_xname(atac->atac_dev), channel, drive), 1596 DEBUG_XFERS); 1597 1598 if (!device_is_active(atac->atac_dev)) { 1599 sc_xfer->error = XS_DRIVER_STUFFUP; 1600 scsipi_done(sc_xfer); 1601 return; 1602 } 1603 xfer = ata_get_xfer_ext(atac->atac_channels[channel], false, 0); 1604 if (xfer == NULL) { 1605 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1606 scsipi_done(sc_xfer); 1607 return; 1608 } 1609 1610 if (sc_xfer->xs_control & XS_CTL_POLL) 1611 xfer->c_flags |= C_POLL; 1612 xfer->c_drive = drive; 1613 xfer->c_flags |= C_ATAPI; 1614 xfer->c_scsipi = sc_xfer; 1615 xfer->c_databuf = sc_xfer->data; 1616 xfer->c_bcount = sc_xfer->datalen; 1617 xfer->c_start = siisata_atapi_start; 1618 xfer->c_intr = siisata_atapi_complete; 1619 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1620 xfer->c_dscpoll = 0; 1621 s = splbio(); 1622 ata_exec_xfer(atac->atac_channels[channel], xfer); 1623 #ifdef DIAGNOSTIC 1624 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1625 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1626 panic("%s: polled command not done", __func__); 1627 #endif 1628 splx(s); 1629 return; 1630 1631 default: 1632 /* Not supported, nothing to do. */ 1633 ; 1634 } 1635 } 1636 1637 void 1638 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1639 { 1640 struct siisata_channel *schp = (struct siisata_channel *)chp; 1641 struct siisata_prb *prbp; 1642 1643 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1644 int i; 1645 1646 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1647 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1648 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1649 DEBUG_XFERS); 1650 1651 chp->ch_status = 0; 1652 chp->ch_error = 0; 1653 1654 prbp = schp->sch_prb[xfer->c_slot]; 1655 memset(prbp, 0, SIISATA_CMD_SIZE); 1656 1657 /* fill in direction for ATAPI command */ 1658 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1659 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1660 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1661 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1662 1663 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1664 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1665 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1666 1667 /* copy over ATAPI command */ 1668 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1669 1670 if (siisata_dma_setup(chp, xfer->c_slot, 1671 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1672 xfer->c_databuf : NULL, 1673 xfer->c_bcount, 1674 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1675 BUS_DMA_READ : BUS_DMA_WRITE) 1676 ) 1677 panic("%s", __func__); 1678 1679 if (xfer->c_flags & C_POLL) { 1680 /* polled command, disable interrupts */ 1681 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1682 siisata_disable_port_interrupt(chp); 1683 } 1684 1685 siisata_activate_prb(schp, xfer->c_slot); 1686 1687 if ((xfer->c_flags & C_POLL) == 0) { 1688 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1689 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1690 siisata_timeout, xfer); 1691 goto out; 1692 } 1693 1694 /* 1695 * polled command 1696 */ 1697 for (i = 0; i < ATA_DELAY / 10; i++) { 1698 if (sc_xfer->xs_status & XS_STS_DONE) 1699 break; 1700 siisata_intr_port(schp); 1701 DELAY(1000); 1702 } 1703 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1704 siisata_timeout(xfer); 1705 } 1706 /* reenable interrupts */ 1707 siisata_enable_port_interrupt(chp); 1708 out: 1709 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1710 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1711 DEBUG_FUNCS); 1712 return; 1713 } 1714 1715 int 1716 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1717 int is) 1718 { 1719 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1720 struct siisata_channel *schp = (struct siisata_channel *)chp; 1721 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1722 1723 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1724 DEBUG_INTR); 1725 1726 /* this command is not active any more */ 1727 siisata_deactivate_prb(schp, xfer->c_slot); 1728 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1729 if (xfer->c_flags & C_TIMEOU) { 1730 sc_xfer->error = XS_TIMEOUT; 1731 } else { 1732 callout_stop(&xfer->c_timo_callout); 1733 sc_xfer->error = XS_NOERROR; 1734 } 1735 1736 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1737 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1738 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1739 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1740 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1741 1742 ata_deactivate_xfer(chp, xfer); 1743 1744 if (ata_waitdrain_xfer_check(chp, xfer)) { 1745 sc_xfer->error = XS_DRIVER_STUFFUP; 1746 return 0; /* XXX verify */ 1747 } 1748 1749 ata_free_xfer(chp, xfer); 1750 sc_xfer->resid = sc_xfer->datalen; 1751 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1752 PRSO_RTC)); 1753 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1754 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1755 if ((chp->ch_status & WDCS_ERR) && 1756 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1757 sc_xfer->resid == sc_xfer->datalen)) { 1758 sc_xfer->error = XS_SHORTSENSE; 1759 sc_xfer->sense.atapi_sense = chp->ch_error; 1760 if ((sc_xfer->xs_periph->periph_quirks & 1761 PQUIRK_NOSENSE) == 0) { 1762 /* request sense */ 1763 sc_xfer->error = XS_BUSY; 1764 sc_xfer->status = SCSI_CHECK; 1765 } 1766 } 1767 scsipi_done(sc_xfer); 1768 atastart(chp); 1769 return 0; /* XXX verify */ 1770 } 1771 1772 #endif /* NATAPIBUS */ 1773
Indexes created Thu Oct 23 22:10:10 GMT 2025