siisata.c revision 1.30.4.20
1 /* $NetBSD: siisata.c,v 1.30.4.20 2017/06/23 23:45:56 jdolecek Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.30.4.20 2017/06/23 23:45:56 jdolecek Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 113 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 114 #if _BYTE_ORDER == _LITTLE_ENDIAN 115 #define bus_space_read_stream_4 bus_space_read_4 116 #define bus_space_read_region_stream_4 bus_space_read_region_4 117 #else 118 static inline uint32_t 119 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 120 { 121 return htole32(bus_space_read_4(t, h, o)); 122 } 123 124 static inline void 125 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 126 bus_size_t o, uint32_t *p, bus_size_t c) 127 { 128 bus_space_read_region_4(t, h, o, p, c); 129 for (bus_size_t i = 0; i < c; i++) { 130 p[i] = htole32(p[i]); 131 } 132 } 133 #endif 134 #endif 135 136 static void siisata_attach_port(struct siisata_softc *, int); 137 static void siisata_intr_port(struct siisata_channel *); 138 139 void siisata_probe_drive(struct ata_channel *); 140 void siisata_setup_channel(struct ata_channel *); 141 142 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 143 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 144 void siisata_reset_channel(struct ata_channel *, int); 145 int siisata_ata_addref(struct ata_drive_datas *); 146 void siisata_ata_delref(struct ata_drive_datas *); 147 void siisata_killpending(struct ata_drive_datas *); 148 149 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 150 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 151 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *); 152 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 153 154 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 155 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 156 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 158 159 void siisata_timeout(void *); 160 161 static void siisata_reinit_port(struct ata_channel *); 162 static void siisata_device_reset(struct ata_channel *); 163 static void siisata_activate_prb(struct siisata_channel *, int); 164 static void siisata_deactivate_prb(struct siisata_channel *, int); 165 static int siisata_dma_setup(struct ata_channel *chp, int, void *, 166 size_t, int); 167 168 #if NATAPIBUS > 0 169 void siisata_atapibus_attach(struct atabus_softc *); 170 void siisata_atapi_probe_device(struct atapibus_softc *, int); 171 void siisata_atapi_minphys(struct buf *); 172 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 173 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 174 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 175 void siisata_atapi_scsipi_request(struct scsipi_channel *, 176 scsipi_adapter_req_t, void *); 177 void siisata_atapi_kill_pending(struct scsipi_periph *); 178 #endif /* NATAPIBUS */ 179 180 const struct ata_bustype siisata_ata_bustype = { 181 SCSIPI_BUSTYPE_ATA, 182 siisata_ata_bio, 183 siisata_reset_drive, 184 siisata_reset_channel, 185 siisata_exec_command, 186 ata_get_params, 187 siisata_ata_addref, 188 siisata_ata_delref, 189 siisata_killpending 190 }; 191 192 #if NATAPIBUS > 0 193 static const struct scsipi_bustype siisata_atapi_bustype = { 194 SCSIPI_BUSTYPE_ATAPI, 195 atapi_scsipi_cmd, 196 atapi_interpret_sense, 197 atapi_print_addr, 198 siisata_atapi_kill_pending, 199 NULL, 200 }; 201 #endif /* NATAPIBUS */ 202 203 204 void 205 siisata_attach(struct siisata_softc *sc) 206 { 207 int i; 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 211 212 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 213 sc->sc_atac.atac_pio_cap = 4; 214 sc->sc_atac.atac_dma_cap = 2; 215 sc->sc_atac.atac_udma_cap = 6; 216 sc->sc_atac.atac_channels = sc->sc_chanarray; 217 sc->sc_atac.atac_probe = siisata_probe_drive; 218 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 219 sc->sc_atac.atac_set_modes = siisata_setup_channel; 220 #if NATAPIBUS > 0 221 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 222 #endif 223 224 /* come out of reset state */ 225 GRWRITE(sc, GR_GC, 0); 226 227 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 228 siisata_attach_port(sc, i); 229 } 230 231 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 232 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 233 return; 234 } 235 236 static void 237 siisata_disable_port_interrupt(struct ata_channel *chp) 238 { 239 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 240 241 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 242 } 243 244 static void 245 siisata_enable_port_interrupt(struct ata_channel *chp) 246 { 247 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 248 249 /* enable CmdErrr+CmdCmpl interrupting */ 250 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 251 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 252 } 253 254 static void 255 siisata_init_port(struct siisata_softc *sc, int port) 256 { 257 struct siisata_channel *schp; 258 struct ata_channel *chp; 259 260 schp = &sc->sc_channels[port]; 261 chp = (struct ata_channel *)schp; 262 263 /* 264 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 265 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 266 */ 267 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 268 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 269 /* initialize port */ 270 siisata_reinit_port(chp); 271 /* enable CmdErrr+CmdCmpl interrupting */ 272 siisata_enable_port_interrupt(chp); 273 /* enable port interrupt */ 274 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 275 } 276 277 static void 278 siisata_attach_port(struct siisata_softc *sc, int port) 279 { 280 int j; 281 int dmasize; 282 int error; 283 void *prbp; 284 struct siisata_channel *schp; 285 struct ata_channel *chp; 286 287 schp = &sc->sc_channels[port]; 288 chp = (struct ata_channel *)schp; 289 sc->sc_chanarray[port] = chp; 290 chp->ch_channel = port; 291 chp->ch_atac = &sc->sc_atac; 292 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 293 if (chp->ch_queue == NULL) { 294 aprint_error_dev(sc->sc_atac.atac_dev, 295 "port %d: can't allocate memory " 296 "for command queue\n", chp->ch_channel); 297 return; 298 } 299 300 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 301 302 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 303 __func__, dmasize), DEBUG_FUNCS); 304 305 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 306 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 307 if (error) { 308 aprint_error_dev(sc->sc_atac.atac_dev, 309 "unable to allocate PRB table memory, " 310 "error=%d\n", error); 311 return; 312 } 313 314 error = bus_dmamem_map(sc->sc_dmat, 315 &schp->sch_prb_seg, schp->sch_prb_nseg, 316 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 317 if (error) { 318 aprint_error_dev(sc->sc_atac.atac_dev, 319 "unable to map PRB table memory, " 320 "error=%d\n", error); 321 bus_dmamem_free(sc->sc_dmat, 322 &schp->sch_prb_seg, schp->sch_prb_nseg); 323 return; 324 } 325 326 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 327 BUS_DMA_NOWAIT, &schp->sch_prbd); 328 if (error) { 329 aprint_error_dev(sc->sc_atac.atac_dev, 330 "unable to create PRB table map, " 331 "error=%d\n", error); 332 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 333 bus_dmamem_free(sc->sc_dmat, 334 &schp->sch_prb_seg, schp->sch_prb_nseg); 335 return; 336 } 337 338 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 339 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 340 if (error) { 341 aprint_error_dev(sc->sc_atac.atac_dev, 342 "unable to load PRB table map, " 343 "error=%d\n", error); 344 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 345 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 346 bus_dmamem_free(sc->sc_dmat, 347 &schp->sch_prb_seg, schp->sch_prb_nseg); 348 return; 349 } 350 351 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 352 schp->sch_prb[j] = (struct siisata_prb *) 353 ((char *)prbp + SIISATA_CMD_SIZE * j); 354 schp->sch_bus_prb[j] = 355 schp->sch_prbd->dm_segs[0].ds_addr + 356 SIISATA_CMD_SIZE * j; 357 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 358 SIISATA_NSGE, MAXPHYS, 0, 359 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 360 &schp->sch_datad[j]); 361 if (error) { 362 aprint_error_dev(sc->sc_atac.atac_dev, 363 "couldn't create xfer DMA map, error=%d\n", 364 error); 365 return; 366 } 367 } 368 369 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 370 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 371 aprint_error_dev(sc->sc_atac.atac_dev, 372 "couldn't map port %d SStatus regs\n", 373 chp->ch_channel); 374 return; 375 } 376 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 377 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 378 aprint_error_dev(sc->sc_atac.atac_dev, 379 "couldn't map port %d SControl regs\n", 380 chp->ch_channel); 381 return; 382 } 383 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 384 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 385 aprint_error_dev(sc->sc_atac.atac_dev, 386 "couldn't map port %d SError regs\n", 387 chp->ch_channel); 388 return; 389 } 390 391 siisata_init_port(sc, port); 392 393 ata_channel_attach(chp); 394 395 return; 396 } 397 398 int 399 siisata_detach(struct siisata_softc *sc, int flags) 400 { 401 struct atac_softc *atac = &sc->sc_atac; 402 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 403 struct siisata_channel *schp; 404 struct ata_channel *chp; 405 int i, j, error; 406 407 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 408 schp = &sc->sc_channels[i]; 409 chp = sc->sc_chanarray[i]; 410 411 if (chp->atabus == NULL) 412 continue; 413 if ((error = config_detach(chp->atabus, flags)) != 0) 414 return error; 415 416 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 417 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 418 419 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 420 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 421 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 422 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 423 bus_dmamem_free(sc->sc_dmat, 424 &schp->sch_prb_seg, schp->sch_prb_nseg); 425 426 free(chp->ch_queue, M_DEVBUF); 427 chp->atabus = NULL; 428 429 ata_channel_detach(chp); 430 } 431 432 if (adapt->adapt_refcnt != 0) 433 return EBUSY; 434 435 /* leave the chip in reset */ 436 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 437 438 return 0; 439 } 440 441 void 442 siisata_resume(struct siisata_softc *sc) 443 { 444 int i; 445 446 /* come out of reset state */ 447 GRWRITE(sc, GR_GC, 0); 448 449 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 450 siisata_init_port(sc, i); 451 } 452 453 } 454 455 int 456 siisata_intr(void *v) 457 { 458 struct siisata_softc *sc = v; 459 uint32_t is; 460 int i, r = 0; 461 while ((is = GRREAD(sc, GR_GIS))) { 462 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 463 SIISATANAME(sc), __func__, is), DEBUG_INTR); 464 r = 1; 465 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 466 if (is & GR_GIS_PXIS(i)) 467 siisata_intr_port(&sc->sc_channels[i]); 468 } 469 return r; 470 } 471 472 static void 473 siisata_intr_port(struct siisata_channel *schp) 474 { 475 struct siisata_softc *sc; 476 struct ata_channel *chp; 477 struct ata_xfer *xfer; 478 u_int slot; 479 uint32_t pss, pis; 480 uint32_t prbfis; 481 482 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 483 chp = &schp->ata_channel; 484 485 /* get slot status, clearing completion interrupt (PR_PIS_CMDCMPL) */ 486 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 487 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x\n", 488 SIISATANAME(sc), __func__, chp->ch_channel, pss), DEBUG_INTR); 489 490 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 491 if (((schp->sch_active_slots >> slot) & 1) == 0) 492 /* there's nothing executing here, skip */ 493 continue; 494 if (((pss >> slot) & 1) != 0) 495 /* execution is incomplete or unsuccessful, skip for now */ 496 continue; 497 xfer = ata_queue_hwslot_to_xfer(chp, slot); 498 if (xfer->c_intr == NULL) { 499 wakeup(schp); 500 continue; 501 } 502 KASSERT(xfer != NULL); 503 KASSERT(xfer->c_intr != NULL); 504 xfer->c_intr(chp, xfer, 0); 505 } 506 /* if no errors, we're done now */ 507 if ((pss & PR_PSS_ATTENTION) == 0) { 508 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 509 pis &= 0xffff; 510 if (pis) { 511 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 512 pis & 0xfffcfffc); 513 } 514 return; 515 } 516 517 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 518 519 SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x ", SIISATANAME(sc), 520 __func__, chp->ch_channel, pis), DEBUG_INTR); 521 522 if (pis & PR_PIS_CMDERRR) { 523 uint32_t ec; 524 uint32_t ps; 525 526 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 527 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 528 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 529 530 slot = PR_PS_ACTIVE_SLOT(ps); /* XXX invalid for NCQ? */ 531 532 /* emulate a CRC error by default */ 533 chp->ch_status = WDCS_ERR; 534 chp->ch_error = WDCE_CRC; 535 536 if (ec <= PR_PCE_DATAFISERROR) { 537 if (ec == PR_PCE_DEVICEERROR) { 538 /* read in specific information about error */ 539 prbfis = bus_space_read_stream_4( 540 sc->sc_prt, sc->sc_prh, 541 PRSX(chp->ch_channel, slot, 542 PRSO_FIS)); 543 /* set ch_status and ch_error */ 544 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 545 } 546 siisata_reinit_port(chp); 547 } else { 548 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 549 " on channel %d (ctx 0x%x), resetting\n", 550 ec, chp->ch_channel, 551 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 552 /* okay, we have a "Fatal Error" */ 553 siisata_device_reset(chp); 554 } 555 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 556 /* there's nothing executing here, skip */ 557 if (((schp->sch_active_slots >> slot) & 1) == 0) 558 continue; 559 xfer = ata_queue_hwslot_to_xfer(chp, slot); 560 if (xfer == NULL) 561 continue; 562 xfer->c_intr(chp, xfer, 0); 563 } 564 } 565 566 /* clear */ 567 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis); 568 569 return; 570 } 571 572 void 573 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 574 { 575 struct ata_channel *chp = drvp->chnl_softc; 576 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 577 struct siisata_channel *schp = (struct siisata_channel *)chp; 578 struct siisata_prb *prb; 579 struct ata_xfer *xfer; 580 uint32_t pss, pis; 581 int i; 582 583 /* wait for ready */ 584 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 585 DELAY(10); 586 587 /* 588 * Try to get available slot. If there is none available, must 589 * do full channel reset. 590 */ 591 xfer = ata_get_xfer_ext(chp, false, 0); 592 if (xfer == NULL) { 593 printf("%s: no xfer\n", __func__); 594 siisata_reset_channel(chp, flags); 595 return; 596 } 597 598 prb = schp->sch_prb[xfer->c_slot]; 599 memset(prb, 0, SIISATA_CMD_SIZE); 600 prb->prb_control = 601 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 602 KASSERT(drvp->drive <= PMP_PORT_CTL); 603 prb->prb_fis[rhd_c] = drvp->drive; 604 605 siisata_disable_port_interrupt(chp); 606 607 siisata_activate_prb(schp, xfer->c_slot); 608 609 for(i = 0; i < 3100; i++) { 610 #if 1 /* XXX-jak-jd-ncq this block needs re-work... XXX */ 611 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_INCOR); 612 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 613 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_INCOR); 614 if ((pss & PR_PXSS(xfer->c_slot)) == 0) 615 break; 616 if (pss & PR_PSS_ATTENTION) 617 break; 618 #else 619 pss = PR_PXSS(xfer->c_slot); 620 /* XXX DO NOT MERGE UNTIL THIS IS FIXED XXX */ 621 #endif 622 ata_delay(10, "siiprb", flags); 623 } 624 625 siisata_deactivate_prb(schp, xfer->c_slot); 626 627 if ((pss & PR_PSS_ATTENTION) != 0) { 628 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 629 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 630 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 631 if (slot != xfer->c_slot) 632 device_printf(sc->sc_atac.atac_dev, "%s port %d " 633 "drive %d slot %d c_slot %d", __func__, 634 chp->ch_channel, drvp->drive, slot, xfer->c_slot); 635 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 636 PR_PIS_CMDERRR); 637 } 638 639 siisata_enable_port_interrupt(chp); 640 641 if (i == 3100) { 642 /* timeout */ 643 siisata_device_reset(chp); /* XXX is this right? */ 644 if (sigp) 645 *sigp = 0xffffffff; 646 } else { 647 /* read the signature out of the FIS */ 648 if (sigp) { 649 *sigp = 0; 650 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 651 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 652 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 653 PRSO_FIS+0xc)) & 0xff; 654 } 655 } 656 657 ata_free_xfer(chp, xfer); 658 659 #if 1 660 /* attempt to downgrade signaling in event of CRC error */ 661 /* XXX should be part of the MI (S)ATA subsystem */ 662 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 663 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 664 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 665 DELAY(10); 666 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 667 SControl_IPM_NONE | SControl_SPD_G1); 668 DELAY(10); 669 for (;;) { 670 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 671 & SStatus_DET_mask) == SStatus_DET_DEV) 672 break; 673 DELAY(10); 674 } 675 } 676 #endif 677 678 #if 1 679 chp->ch_status = 0; 680 chp->ch_error = 0; 681 #endif 682 return; 683 } 684 685 void 686 siisata_reset_channel(struct ata_channel *chp, int flags) 687 { 688 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 689 struct siisata_channel *schp = (struct siisata_channel *)chp; 690 691 SIISATA_DEBUG_PRINT(("%s: %s channel %d\n", SIISATANAME(sc), __func__, 692 chp->ch_channel), DEBUG_FUNCS); 693 694 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 695 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 696 aprint_error("%s port %d: reset failed\n", 697 SIISATANAME(sc), chp->ch_channel); 698 /* XXX and then ? */ 699 } 700 /* wait for ready */ 701 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 702 DELAY(10); 703 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 704 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 705 ata_kill_active(chp, KILL_RESET, flags); 706 707 return; 708 } 709 710 int 711 siisata_ata_addref(struct ata_drive_datas *drvp) 712 { 713 return 0; 714 } 715 716 void 717 siisata_ata_delref(struct ata_drive_datas *drvp) 718 { 719 return; 720 } 721 722 void 723 siisata_killpending(struct ata_drive_datas *drvp) 724 { 725 return; 726 } 727 728 void 729 siisata_probe_drive(struct ata_channel *chp) 730 { 731 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 732 struct siisata_channel *schp = (struct siisata_channel *)chp; 733 int i; 734 uint32_t sig; 735 struct siisata_prb *prb; 736 bool timed_out; 737 struct ata_xfer *xfer; 738 739 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 740 __func__, chp->ch_channel), DEBUG_FUNCS); 741 742 xfer = ata_get_xfer(chp); 743 if (xfer == NULL) { 744 aprint_error_dev(sc->sc_atac.atac_dev, 745 "failed to get xfer port %d\n", 746 chp->ch_channel); 747 return; 748 } 749 750 /* 751 * disable port interrupt as we're polling for PHY up and 752 * prb completion 753 */ 754 siisata_disable_port_interrupt(chp); 755 756 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 757 schp->sch_sstatus, AT_WAIT)) { 758 case SStatus_DET_DEV: 759 #if 0 /* XXX Including this seems to cause problems. */ 760 /* XXX DO NOT MERGE UNTIL THIS IS ADDRESSED PROPERLY XXX */ 761 /* clear any interrupts */ 762 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 763 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 764 #endif 765 /* wait for ready */ 766 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 767 & PR_PS_PORT_READY)) 768 DELAY(10); 769 prb = schp->sch_prb[xfer->c_slot]; 770 memset(prb, 0, SIISATA_CMD_SIZE); 771 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 772 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 773 774 siisata_activate_prb(schp, xfer->c_slot); 775 776 timed_out = 1; 777 for(i = 0; i < 3100; i++) { 778 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 779 PR_PXSS(xfer->c_slot)) == 0) { 780 /* prb completed */ 781 timed_out = 0; 782 break; 783 } 784 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 785 (PR_PIS_CMDERRR << 16)) { 786 /* we got an error; handle as timeout */ 787 break; 788 } 789 790 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 791 } 792 793 siisata_deactivate_prb(schp, xfer->c_slot); 794 795 if (timed_out) { 796 aprint_error_dev(sc->sc_atac.atac_dev, 797 "SOFT_RESET failed on port %d (error %d PSS 0x%x), " 798 "resetting\n", chp->ch_channel, 799 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 800 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); 801 siisata_reinit_port(chp); 802 break; 803 } 804 805 /* read the signature out of the FIS */ 806 sig = 0; 807 sig |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 808 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 809 sig |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 810 PRSO_FIS+0xc)) & 0xff; 811 812 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 813 __func__, sig), DEBUG_PROBE); 814 815 if (sig == 0x96690101) 816 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 817 PR_PC_PMP_ENABLE); 818 sata_interpret_sig(chp, 0, sig); 819 break; 820 default: 821 break; 822 } 823 824 siisata_enable_port_interrupt(chp); 825 826 ata_free_xfer(chp, xfer); 827 828 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 829 __func__, chp->ch_channel), DEBUG_PROBE); 830 return; 831 } 832 833 void 834 siisata_setup_channel(struct ata_channel *chp) 835 { 836 return; 837 } 838 839 int 840 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 841 { 842 struct ata_channel *chp = drvp->chnl_softc; 843 struct ata_command *ata_c = &xfer->c_ata_c; 844 int ret; 845 int s; 846 847 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 848 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 849 DEBUG_FUNCS); 850 851 if (ata_c->flags & AT_POLL) 852 xfer->c_flags |= C_POLL; 853 if (ata_c->flags & AT_WAIT) 854 xfer->c_flags |= C_WAIT; 855 xfer->c_drive = drvp->drive; 856 xfer->c_databuf = ata_c->data; 857 xfer->c_bcount = ata_c->bcount; 858 xfer->c_start = siisata_cmd_start; 859 xfer->c_intr = siisata_cmd_complete; 860 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 861 s = splbio(); 862 ata_exec_xfer(chp, xfer); 863 #ifdef DIAGNOSTIC 864 if ((ata_c->flags & AT_POLL) != 0 && 865 (ata_c->flags & AT_DONE) == 0) 866 panic("%s: polled command not done", __func__); 867 #endif 868 if (ata_c->flags & AT_DONE) { 869 ret = ATACMD_COMPLETE; 870 } else { 871 if (ata_c->flags & AT_WAIT) { 872 while ((ata_c->flags & AT_DONE) == 0) { 873 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 874 SIISATANAME( 875 (struct siisata_softc *)chp->ch_atac), 876 __func__), DEBUG_FUNCS); 877 tsleep(ata_c, PRIBIO, "siicmd", 0); 878 } 879 ret = ATACMD_COMPLETE; 880 } else { 881 ret = ATACMD_QUEUED; 882 } 883 } 884 splx(s); 885 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 886 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 887 DEBUG_FUNCS); 888 return ret; 889 } 890 891 void 892 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 893 { 894 struct siisata_channel *schp = (struct siisata_channel *)chp; 895 struct ata_command *ata_c = &xfer->c_ata_c; 896 struct siisata_prb *prb; 897 int i; 898 899 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 900 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 901 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 902 DEBUG_FUNCS|DEBUG_XFERS); 903 904 chp->ch_status = 0; 905 chp->ch_error = 0; 906 907 prb = schp->sch_prb[xfer->c_slot]; 908 memset(prb, 0, SIISATA_CMD_SIZE); 909 910 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 911 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 912 prb->prb_fis[rhd_c] |= xfer->c_drive; 913 914 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 915 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 916 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 917 } 918 919 if (siisata_dma_setup(chp, xfer->c_slot, 920 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 921 ata_c->bcount, 922 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 923 ata_c->flags |= AT_DF; 924 siisata_cmd_complete(chp, xfer, 0); 925 return; 926 } 927 928 if (xfer->c_flags & C_POLL) { 929 /* polled command, disable interrupts */ 930 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 931 siisata_disable_port_interrupt(chp); 932 } 933 934 /* go for it */ 935 siisata_activate_prb(schp, xfer->c_slot); 936 937 if ((ata_c->flags & AT_POLL) == 0) { 938 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 939 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 940 siisata_timeout, xfer); 941 goto out; 942 } 943 944 /* 945 * polled command 946 */ 947 for (i = 0; i < ata_c->timeout / 10; i++) { 948 if (ata_c->flags & AT_DONE) 949 break; 950 siisata_intr_port(schp); 951 DELAY(1000); 952 } 953 954 if ((ata_c->flags & AT_DONE) == 0) { 955 siisata_timeout(xfer); 956 } 957 958 /* reenable interrupts */ 959 siisata_enable_port_interrupt(chp); 960 out: 961 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 962 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 963 DEBUG_FUNCS); 964 return; 965 } 966 967 void 968 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 969 int reason) 970 { 971 struct ata_command *ata_c = &xfer->c_ata_c; 972 struct siisata_channel *schp = (struct siisata_channel *)chp; 973 974 siisata_deactivate_prb(schp, xfer->c_slot); 975 ata_deactivate_xfer(chp, xfer); 976 977 switch (reason) { 978 case KILL_GONE: 979 ata_c->flags |= AT_GONE; 980 break; 981 case KILL_RESET: 982 ata_c->flags |= AT_RESET; 983 break; 984 default: 985 panic("%s: port %d: unknown reason %d", 986 __func__, chp->ch_channel, reason); 987 } 988 siisata_cmd_done(chp, xfer); 989 } 990 991 int 992 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 993 { 994 struct siisata_channel *schp = (struct siisata_channel *)chp; 995 struct ata_command *ata_c = &xfer->c_ata_c; 996 #ifdef SIISATA_DEBUG 997 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 998 #endif 999 1000 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1001 SIISATANAME(sc), __func__, 1002 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1003 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1004 DEBUG_FUNCS|DEBUG_XFERS); 1005 1006 siisata_deactivate_prb(schp, xfer->c_slot); 1007 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1008 if (xfer->c_flags & C_TIMEOU) 1009 ata_c->flags |= AT_TIMEOU; 1010 else 1011 callout_stop(&xfer->c_timo_callout); 1012 1013 if (chp->ch_status & WDCS_BSY) { 1014 ata_c->flags |= AT_TIMEOU; 1015 } else if (chp->ch_status & WDCS_ERR) { 1016 ata_c->r_error = chp->ch_error; 1017 ata_c->flags |= AT_ERROR; 1018 } 1019 1020 ata_deactivate_xfer(chp, xfer); 1021 1022 if (!ata_waitdrain_xfer_check(chp, xfer)) { 1023 siisata_cmd_done(chp, xfer); 1024 } 1025 1026 return 0; 1027 } 1028 1029 void 1030 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer) 1031 { 1032 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1033 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1034 struct siisata_channel *schp = (struct siisata_channel *)chp; 1035 struct ata_command *ata_c = &xfer->c_ata_c; 1036 uint16_t *idwordbuf; 1037 int i; 1038 1039 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1040 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1041 1042 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1043 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1044 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1045 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1046 BUS_DMASYNC_POSTWRITE); 1047 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1048 } 1049 1050 if (ata_c->flags & AT_READREG) { 1051 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1052 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1053 fis, __arraycount(fis)); 1054 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1055 } 1056 1057 /* correct the endianess of IDENTIFY data */ 1058 if (ata_c->r_command == WDCC_IDENTIFY || 1059 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1060 idwordbuf = xfer->c_databuf; 1061 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1062 idwordbuf[i] = le16toh(idwordbuf[i]); 1063 } 1064 } 1065 1066 ata_c->flags |= AT_DONE; 1067 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1068 ata_c->flags |= AT_XFDONE; 1069 1070 if (ata_c->flags & AT_WAIT) 1071 wakeup(ata_c); 1072 else if (ata_c->callback) 1073 ata_c->callback(ata_c->callback_arg); 1074 atastart(chp); 1075 return; 1076 } 1077 1078 int 1079 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1080 { 1081 struct ata_channel *chp = drvp->chnl_softc; 1082 struct ata_bio *ata_bio = &xfer->c_bio; 1083 1084 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1085 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1086 DEBUG_FUNCS); 1087 1088 if (xfer == NULL) 1089 return ATACMD_TRY_AGAIN; 1090 if (ata_bio->flags & ATA_POLL) 1091 xfer->c_flags |= C_POLL; 1092 xfer->c_drive = drvp->drive; 1093 xfer->c_databuf = ata_bio->databuf; 1094 xfer->c_bcount = ata_bio->bcount; 1095 xfer->c_start = siisata_bio_start; 1096 xfer->c_intr = siisata_bio_complete; 1097 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1098 ata_exec_xfer(chp, xfer); 1099 return (ata_bio->flags & ATA_ITSDONE) ? 1100 ATACMD_COMPLETE : ATACMD_QUEUED; 1101 } 1102 1103 void 1104 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1105 { 1106 struct siisata_channel *schp = (struct siisata_channel *)chp; 1107 struct siisata_prb *prb; 1108 struct ata_bio *ata_bio = &xfer->c_bio; 1109 int i; 1110 1111 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1112 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1113 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1114 1115 chp->ch_status = 0; 1116 chp->ch_error = 0; 1117 1118 prb = schp->sch_prb[xfer->c_slot]; 1119 memset(prb, 0, SIISATA_CMD_SIZE); 1120 1121 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1122 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1123 prb->prb_fis[rhd_c] |= xfer->c_drive; 1124 1125 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1126 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1127 ata_bio->error = ERR_DMA; 1128 ata_bio->r_error = 0; 1129 siisata_bio_complete(chp, xfer, 0); 1130 return; 1131 } 1132 1133 if (xfer->c_flags & C_POLL) { 1134 /* polled command, disable interrupts */ 1135 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1136 siisata_disable_port_interrupt(chp); 1137 } 1138 1139 siisata_activate_prb(schp, xfer->c_slot); 1140 1141 if ((ata_bio->flags & ATA_POLL) == 0) { 1142 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1143 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1144 siisata_timeout, xfer); 1145 goto out; 1146 } 1147 1148 /* 1149 * polled command 1150 */ 1151 for (i = 0; i < ATA_DELAY / 10; i++) { 1152 if (ata_bio->flags & ATA_ITSDONE) 1153 break; 1154 siisata_intr_port(schp); 1155 DELAY(100); 1156 } 1157 1158 siisata_enable_port_interrupt(chp); 1159 out: 1160 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1161 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1162 DEBUG_FUNCS); 1163 return; 1164 } 1165 1166 void 1167 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1168 int reason) 1169 { 1170 struct siisata_channel *schp = (struct siisata_channel *)chp; 1171 struct ata_bio *ata_bio = &xfer->c_bio; 1172 int drive = xfer->c_drive; 1173 1174 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1175 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1176 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1177 1178 siisata_deactivate_prb(schp, xfer->c_slot); 1179 ata_deactivate_xfer(chp, xfer); 1180 1181 ata_bio->flags |= ATA_ITSDONE; 1182 switch (reason) { 1183 case KILL_GONE: 1184 ata_bio->error = ERR_NODEV; 1185 break; 1186 case KILL_RESET: 1187 ata_bio->error = ERR_RESET; 1188 break; 1189 default: 1190 panic("%s: port %d: unknown reason %d", 1191 __func__, chp->ch_channel, reason); 1192 } 1193 ata_bio->r_error = WDCE_ABRT; 1194 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1195 } 1196 1197 int 1198 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1199 { 1200 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1201 struct siisata_channel *schp = (struct siisata_channel *)chp; 1202 struct ata_bio *ata_bio = &xfer->c_bio; 1203 int drive = xfer->c_drive; 1204 1205 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d\n", 1206 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1207 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1208 1209 siisata_deactivate_prb(schp, xfer->c_slot); 1210 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1211 if (xfer->c_flags & C_TIMEOU) { 1212 ata_bio->error = TIMEOUT; 1213 } else { 1214 callout_stop(&xfer->c_timo_callout); 1215 ata_bio->error = NOERROR; 1216 } 1217 1218 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1219 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1220 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1221 BUS_DMASYNC_POSTWRITE); 1222 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1223 1224 ata_deactivate_xfer(chp, xfer); 1225 1226 if (ata_waitdrain_xfer_check(chp, xfer)) { 1227 return 0; 1228 } 1229 1230 ata_bio->flags |= ATA_ITSDONE; 1231 if (chp->ch_status & WDCS_DWF) { 1232 ata_bio->error = ERR_DF; 1233 } else if (chp->ch_status & WDCS_ERR) { 1234 ata_bio->error = ERROR; 1235 ata_bio->r_error = chp->ch_error; 1236 } else if (chp->ch_status & WDCS_CORR) 1237 ata_bio->flags |= ATA_CORR; 1238 1239 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1240 ata_bio->bcount), DEBUG_XFERS); 1241 if (ata_bio->error == NOERROR) { 1242 if (ata_bio->flags & ATA_READ) 1243 ata_bio->bcount -= 1244 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1245 else 1246 ata_bio->bcount = 0; 1247 } 1248 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1249 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1250 atastart(chp); 1251 return 0; 1252 } 1253 1254 void 1255 siisata_timeout(void *v) 1256 { 1257 struct ata_xfer *xfer = v; 1258 struct ata_channel *chp = xfer->c_chp; 1259 int s = splbio(); 1260 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1261 siisata_device_reset(chp); 1262 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1263 xfer->c_flags |= C_TIMEOU; 1264 xfer->c_intr(chp, xfer, 0); 1265 } 1266 splx(s); 1267 } 1268 1269 static int 1270 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1271 size_t count, int op) 1272 { 1273 1274 int error, seg; 1275 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1276 struct siisata_channel *schp = (struct siisata_channel *)chp; 1277 1278 struct siisata_prb *prbp; 1279 1280 prbp = schp->sch_prb[slot]; 1281 1282 if (data == NULL) { 1283 goto end; 1284 } 1285 1286 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1287 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1288 if (error) { 1289 aprint_error("%s port %d: " 1290 "failed to load xfer in slot %d: error %d\n", 1291 SIISATANAME(sc), chp->ch_channel, slot, error); 1292 return error; 1293 } 1294 1295 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1296 schp->sch_datad[slot]->dm_mapsize, 1297 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1298 1299 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1300 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1301 DEBUG_FUNCS | DEBUG_DEBUG); 1302 1303 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1304 prbp->prb_sge[seg].sge_da = 1305 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1306 prbp->prb_sge[seg].sge_dc = 1307 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1308 prbp->prb_sge[seg].sge_flags = htole32(0); 1309 } 1310 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1311 end: 1312 return 0; 1313 } 1314 1315 static void 1316 siisata_activate_prb(struct siisata_channel *schp, int slot) 1317 { 1318 struct siisata_softc *sc; 1319 bus_size_t offset; 1320 uint64_t pprb; 1321 1322 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1323 1324 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != __BIT(slot), 1325 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1326 1327 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1328 /* keep track of what's going on */ 1329 schp->sch_active_slots |= __BIT(slot); 1330 1331 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1332 1333 pprb = schp->sch_bus_prb[slot]; 1334 1335 PRWRITE(sc, offset + 0, pprb >> 0); 1336 PRWRITE(sc, offset + 4, pprb >> 32); 1337 } 1338 1339 static void 1340 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1341 { 1342 struct siisata_softc *sc; 1343 1344 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1345 1346 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1347 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1348 slot); 1349 1350 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1351 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1352 } 1353 1354 static void 1355 siisata_reinit_port(struct ata_channel *chp) 1356 { 1357 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1358 1359 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1360 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1361 DELAY(10); 1362 if (chp->ch_ndrives > 1) 1363 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1364 } 1365 1366 static void 1367 siisata_device_reset(struct ata_channel *chp) 1368 { 1369 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1370 1371 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1372 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1373 DELAY(10); 1374 } 1375 1376 1377 #if NATAPIBUS > 0 1378 void 1379 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1380 { 1381 struct ata_channel *chp = ata_sc->sc_chan; 1382 struct atac_softc *atac = chp->ch_atac; 1383 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1384 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1385 1386 /* 1387 * Fill in the scsipi_adapter. 1388 */ 1389 adapt->adapt_dev = atac->atac_dev; 1390 adapt->adapt_nchannels = atac->atac_nchannels; 1391 adapt->adapt_request = siisata_atapi_scsipi_request; 1392 adapt->adapt_minphys = siisata_atapi_minphys; 1393 atac->atac_atapi_adapter.atapi_probe_device = 1394 siisata_atapi_probe_device; 1395 1396 /* 1397 * Fill in the scsipi_channel. 1398 */ 1399 memset(chan, 0, sizeof(*chan)); 1400 chan->chan_adapter = adapt; 1401 chan->chan_bustype = &siisata_atapi_bustype; 1402 chan->chan_channel = chp->ch_channel; 1403 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1404 chan->chan_openings = 1; 1405 chan->chan_max_periph = 1; 1406 chan->chan_ntargets = 1; 1407 chan->chan_nluns = 1; 1408 1409 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1410 atapiprint); 1411 } 1412 1413 void 1414 siisata_atapi_minphys(struct buf *bp) 1415 { 1416 if (bp->b_bcount > MAXPHYS) 1417 bp->b_bcount = MAXPHYS; 1418 minphys(bp); 1419 } 1420 1421 /* 1422 * Kill off all pending xfers for a periph. 1423 * 1424 * Must be called at splbio(). 1425 */ 1426 void 1427 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1428 { 1429 struct atac_softc *atac = 1430 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1431 struct ata_channel *chp = 1432 atac->atac_channels[periph->periph_channel->chan_channel]; 1433 1434 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1435 } 1436 1437 void 1438 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1439 int reason) 1440 { 1441 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1442 struct siisata_channel *schp = (struct siisata_channel *)chp; 1443 1444 siisata_deactivate_prb(schp, xfer->c_slot); 1445 ata_deactivate_xfer(chp, xfer); 1446 1447 /* remove this command from xfer queue */ 1448 switch (reason) { 1449 case KILL_GONE: 1450 sc_xfer->error = XS_DRIVER_STUFFUP; 1451 break; 1452 case KILL_RESET: 1453 sc_xfer->error = XS_RESET; 1454 break; 1455 default: 1456 panic("%s: port %d: unknown reason %d", 1457 __func__, chp->ch_channel, reason); 1458 } 1459 ata_free_xfer(chp, xfer); 1460 scsipi_done(sc_xfer); 1461 } 1462 1463 void 1464 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1465 { 1466 struct scsipi_channel *chan = sc->sc_channel; 1467 struct scsipi_periph *periph; 1468 struct ataparams ids; 1469 struct ataparams *id = &ids; 1470 struct siisata_softc *siic = 1471 device_private(chan->chan_adapter->adapt_dev); 1472 struct atac_softc *atac = &siic->sc_atac; 1473 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1474 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1475 struct scsipibus_attach_args sa; 1476 char serial_number[21], model[41], firmware_revision[9]; 1477 int s; 1478 1479 /* skip if already attached */ 1480 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1481 return; 1482 1483 /* if no ATAPI device detected at attach time, skip */ 1484 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1485 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1486 target), DEBUG_PROBE); 1487 return; 1488 } 1489 1490 /* Some ATAPI devices need a bit more time after software reset. */ 1491 DELAY(5000); 1492 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1493 #ifdef ATAPI_DEBUG_PROBE 1494 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1495 device_xname(sc->sc_dev), target, 1496 id->atap_config & ATAPI_CFG_CMD_MASK, 1497 id->atap_config & ATAPI_CFG_DRQ_MASK); 1498 #endif 1499 periph = scsipi_alloc_periph(M_NOWAIT); 1500 if (periph == NULL) { 1501 aprint_error_dev(sc->sc_dev, 1502 "%s: unable to allocate periph for " 1503 "channel %d drive %d\n", __func__, 1504 chp->ch_channel, target); 1505 return; 1506 } 1507 periph->periph_dev = NULL; 1508 periph->periph_channel = chan; 1509 periph->periph_switch = &atapi_probe_periphsw; 1510 periph->periph_target = target; 1511 periph->periph_lun = 0; 1512 periph->periph_quirks = PQUIRK_ONLYBIG; 1513 1514 #ifdef SCSIPI_DEBUG 1515 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1516 SCSIPI_DEBUG_TARGET == target) 1517 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1518 #endif 1519 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1520 if (id->atap_config & ATAPI_CFG_REMOV) 1521 periph->periph_flags |= PERIPH_REMOVABLE; 1522 sa.sa_periph = periph; 1523 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1524 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1525 T_REMOV : T_FIXED; 1526 strnvisx(model, sizeof(model), id->atap_model, 40, 1527 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1528 strnvisx(serial_number, sizeof(serial_number), 1529 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1530 strnvisx(firmware_revision, sizeof(firmware_revision), 1531 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1532 sa.sa_inqbuf.vendor = model; 1533 sa.sa_inqbuf.product = serial_number; 1534 sa.sa_inqbuf.revision = firmware_revision; 1535 1536 /* 1537 * Determine the operating mode capabilities of the device. 1538 */ 1539 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1540 == ATAPI_CFG_CMD_16) { 1541 periph->periph_cap |= PERIPH_CAP_CMD16; 1542 1543 /* configure port for packet length */ 1544 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1545 PR_PC_PACKET_LENGTH); 1546 } else { 1547 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1548 PR_PC_PACKET_LENGTH); 1549 } 1550 1551 /* XXX This is gross. */ 1552 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1553 1554 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1555 1556 if (drvp->drv_softc) 1557 ata_probe_caps(drvp); 1558 else { 1559 s = splbio(); 1560 drvp->drive_type &= ATA_DRIVET_NONE; 1561 splx(s); 1562 } 1563 } else { 1564 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1565 "failed for drive %s:%d:%d: error 0x%x\n", 1566 __func__, SIISATANAME(siic), chp->ch_channel, target, 1567 chp->ch_error), DEBUG_PROBE); 1568 s = splbio(); 1569 drvp->drive_type &= ATA_DRIVET_NONE; 1570 splx(s); 1571 } 1572 } 1573 1574 void 1575 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1576 scsipi_adapter_req_t req, void *arg) 1577 { 1578 struct scsipi_adapter *adapt = chan->chan_adapter; 1579 struct scsipi_periph *periph; 1580 struct scsipi_xfer *sc_xfer; 1581 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1582 struct atac_softc *atac = &sc->sc_atac; 1583 struct ata_xfer *xfer; 1584 int channel = chan->chan_channel; 1585 int drive, s; 1586 1587 switch (req) { 1588 case ADAPTER_REQ_RUN_XFER: 1589 sc_xfer = arg; 1590 periph = sc_xfer->xs_periph; 1591 drive = periph->periph_target; 1592 1593 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1594 device_xname(atac->atac_dev), channel, drive), 1595 DEBUG_XFERS); 1596 1597 if (!device_is_active(atac->atac_dev)) { 1598 sc_xfer->error = XS_DRIVER_STUFFUP; 1599 scsipi_done(sc_xfer); 1600 return; 1601 } 1602 xfer = ata_get_xfer_ext(atac->atac_channels[channel], false, 0); 1603 if (xfer == NULL) { 1604 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1605 scsipi_done(sc_xfer); 1606 return; 1607 } 1608 1609 if (sc_xfer->xs_control & XS_CTL_POLL) 1610 xfer->c_flags |= C_POLL; 1611 xfer->c_drive = drive; 1612 xfer->c_flags |= C_ATAPI; 1613 xfer->c_scsipi = sc_xfer; 1614 xfer->c_databuf = sc_xfer->data; 1615 xfer->c_bcount = sc_xfer->datalen; 1616 xfer->c_start = siisata_atapi_start; 1617 xfer->c_intr = siisata_atapi_complete; 1618 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1619 xfer->c_dscpoll = 0; 1620 s = splbio(); 1621 ata_exec_xfer(atac->atac_channels[channel], xfer); 1622 #ifdef DIAGNOSTIC 1623 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1624 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1625 panic("%s: polled command not done", __func__); 1626 #endif 1627 splx(s); 1628 return; 1629 1630 default: 1631 /* Not supported, nothing to do. */ 1632 ; 1633 } 1634 } 1635 1636 void 1637 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1638 { 1639 struct siisata_channel *schp = (struct siisata_channel *)chp; 1640 struct siisata_prb *prbp; 1641 1642 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1643 int i; 1644 1645 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1646 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1647 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1648 DEBUG_XFERS); 1649 1650 chp->ch_status = 0; 1651 chp->ch_error = 0; 1652 1653 prbp = schp->sch_prb[xfer->c_slot]; 1654 memset(prbp, 0, SIISATA_CMD_SIZE); 1655 1656 /* fill in direction for ATAPI command */ 1657 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1658 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1659 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1660 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1661 1662 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1663 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1664 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1665 1666 /* copy over ATAPI command */ 1667 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1668 1669 if (siisata_dma_setup(chp, xfer->c_slot, 1670 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1671 xfer->c_databuf : NULL, 1672 xfer->c_bcount, 1673 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1674 BUS_DMA_READ : BUS_DMA_WRITE) 1675 ) 1676 panic("%s", __func__); 1677 1678 if (xfer->c_flags & C_POLL) { 1679 /* polled command, disable interrupts */ 1680 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1681 siisata_disable_port_interrupt(chp); 1682 } 1683 1684 siisata_activate_prb(schp, xfer->c_slot); 1685 1686 if ((xfer->c_flags & C_POLL) == 0) { 1687 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1688 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1689 siisata_timeout, xfer); 1690 goto out; 1691 } 1692 1693 /* 1694 * polled command 1695 */ 1696 for (i = 0; i < ATA_DELAY / 10; i++) { 1697 if (sc_xfer->xs_status & XS_STS_DONE) 1698 break; 1699 siisata_intr_port(schp); 1700 DELAY(1000); 1701 } 1702 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1703 siisata_timeout(xfer); 1704 } 1705 /* reenable interrupts */ 1706 siisata_enable_port_interrupt(chp); 1707 out: 1708 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1709 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1710 DEBUG_FUNCS); 1711 return; 1712 } 1713 1714 int 1715 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1716 int is) 1717 { 1718 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1719 struct siisata_channel *schp = (struct siisata_channel *)chp; 1720 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1721 1722 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1723 DEBUG_INTR); 1724 1725 /* this command is not active any more */ 1726 siisata_deactivate_prb(schp, xfer->c_slot); 1727 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1728 if (xfer->c_flags & C_TIMEOU) { 1729 sc_xfer->error = XS_TIMEOUT; 1730 } else { 1731 callout_stop(&xfer->c_timo_callout); 1732 sc_xfer->error = XS_NOERROR; 1733 } 1734 1735 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1736 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1737 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1738 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1739 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1740 1741 ata_deactivate_xfer(chp, xfer); 1742 1743 if (ata_waitdrain_xfer_check(chp, xfer)) { 1744 sc_xfer->error = XS_DRIVER_STUFFUP; 1745 return 0; /* XXX verify */ 1746 } 1747 1748 ata_free_xfer(chp, xfer); 1749 sc_xfer->resid = sc_xfer->datalen; 1750 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1751 PRSO_RTC)); 1752 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1753 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1754 if ((chp->ch_status & WDCS_ERR) && 1755 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1756 sc_xfer->resid == sc_xfer->datalen)) { 1757 sc_xfer->error = XS_SHORTSENSE; 1758 sc_xfer->sense.atapi_sense = chp->ch_error; 1759 if ((sc_xfer->xs_periph->periph_quirks & 1760 PQUIRK_NOSENSE) == 0) { 1761 /* request sense */ 1762 sc_xfer->error = XS_BUSY; 1763 sc_xfer->status = SCSI_CHECK; 1764 } 1765 } 1766 scsipi_done(sc_xfer); 1767 atastart(chp); 1768 return 0; /* XXX verify */ 1769 } 1770 1771 #endif /* NATAPIBUS */ 1772
Indexes created Tue Oct 21 12:09:54 GMT 2025