siisata.c revision 1.30.4.27
1 /* $NetBSD: siisata.c,v 1.30.4.27 2017/07/19 20:24:59 jdolecek Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.30.4.27 2017/07/19 20:24:59 jdolecek Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 113 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 114 #if _BYTE_ORDER == _LITTLE_ENDIAN 115 #define bus_space_read_stream_4 bus_space_read_4 116 #define bus_space_read_region_stream_4 bus_space_read_region_4 117 #else 118 static inline uint32_t 119 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 120 { 121 return htole32(bus_space_read_4(t, h, o)); 122 } 123 124 static inline void 125 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 126 bus_size_t o, uint32_t *p, bus_size_t c) 127 { 128 bus_space_read_region_4(t, h, o, p, c); 129 for (bus_size_t i = 0; i < c; i++) { 130 p[i] = htole32(p[i]); 131 } 132 } 133 #endif 134 #endif 135 136 static void siisata_attach_port(struct siisata_softc *, int); 137 static void siisata_intr_port(struct siisata_channel *); 138 139 void siisata_probe_drive(struct ata_channel *); 140 void siisata_setup_channel(struct ata_channel *); 141 142 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 143 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 144 void siisata_reset_channel(struct ata_channel *, int); 145 int siisata_ata_addref(struct ata_drive_datas *); 146 void siisata_ata_delref(struct ata_drive_datas *); 147 void siisata_killpending(struct ata_drive_datas *); 148 149 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 150 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 151 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 152 static void siisata_cmd_done_end(struct ata_channel *, struct ata_xfer *); 153 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 154 155 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 156 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 157 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 158 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 159 160 static void siisata_reinit_port(struct ata_channel *); 161 static void siisata_device_reset(struct ata_channel *); 162 static void siisata_activate_prb(struct siisata_channel *, int); 163 static void siisata_deactivate_prb(struct siisata_channel *, int); 164 static int siisata_dma_setup(struct ata_channel *, int, void *, size_t, int); 165 static void siisata_channel_recover(struct ata_channel *, int, int); 166 167 #if NATAPIBUS > 0 168 void siisata_atapibus_attach(struct atabus_softc *); 169 void siisata_atapi_probe_device(struct atapibus_softc *, int); 170 void siisata_atapi_minphys(struct buf *); 171 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 172 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 173 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 174 void siisata_atapi_scsipi_request(struct scsipi_channel *, 175 scsipi_adapter_req_t, void *); 176 void siisata_atapi_kill_pending(struct scsipi_periph *); 177 #endif /* NATAPIBUS */ 178 179 const struct ata_bustype siisata_ata_bustype = { 180 SCSIPI_BUSTYPE_ATA, 181 siisata_ata_bio, 182 siisata_reset_drive, 183 siisata_reset_channel, 184 siisata_exec_command, 185 ata_get_params, 186 siisata_ata_addref, 187 siisata_ata_delref, 188 siisata_killpending 189 }; 190 191 #if NATAPIBUS > 0 192 static const struct scsipi_bustype siisata_atapi_bustype = { 193 SCSIPI_BUSTYPE_ATAPI, 194 atapi_scsipi_cmd, 195 atapi_interpret_sense, 196 atapi_print_addr, 197 siisata_atapi_kill_pending, 198 NULL, 199 }; 200 #endif /* NATAPIBUS */ 201 202 203 void 204 siisata_attach(struct siisata_softc *sc) 205 { 206 int i; 207 208 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 209 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 210 211 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 212 sc->sc_atac.atac_pio_cap = 4; 213 sc->sc_atac.atac_dma_cap = 2; 214 sc->sc_atac.atac_udma_cap = 6; 215 sc->sc_atac.atac_channels = sc->sc_chanarray; 216 sc->sc_atac.atac_probe = siisata_probe_drive; 217 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 218 sc->sc_atac.atac_set_modes = siisata_setup_channel; 219 #if NATAPIBUS > 0 220 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 221 #endif 222 223 /* come out of reset state */ 224 GRWRITE(sc, GR_GC, 0); 225 226 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 227 siisata_attach_port(sc, i); 228 } 229 230 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 231 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 232 return; 233 } 234 235 static void 236 siisata_disable_port_interrupt(struct ata_channel *chp) 237 { 238 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 239 240 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 241 } 242 243 static void 244 siisata_enable_port_interrupt(struct ata_channel *chp) 245 { 246 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 247 248 /* enable CmdErrr+CmdCmpl interrupting */ 249 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 250 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 251 } 252 253 static void 254 siisata_init_port(struct siisata_softc *sc, int port) 255 { 256 struct siisata_channel *schp; 257 struct ata_channel *chp; 258 259 schp = &sc->sc_channels[port]; 260 chp = (struct ata_channel *)schp; 261 262 /* 263 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 264 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 265 */ 266 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 267 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 268 /* initialize port */ 269 siisata_reinit_port(chp); 270 /* enable CmdErrr+CmdCmpl interrupting */ 271 siisata_enable_port_interrupt(chp); 272 /* enable port interrupt */ 273 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 274 } 275 276 static void 277 siisata_attach_port(struct siisata_softc *sc, int port) 278 { 279 int j; 280 int dmasize; 281 int error; 282 void *prbp; 283 struct siisata_channel *schp; 284 struct ata_channel *chp; 285 286 schp = &sc->sc_channels[port]; 287 chp = (struct ata_channel *)schp; 288 sc->sc_chanarray[port] = chp; 289 chp->ch_channel = port; 290 chp->ch_atac = &sc->sc_atac; 291 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 292 if (chp->ch_queue == NULL) { 293 aprint_error_dev(sc->sc_atac.atac_dev, 294 "port %d: can't allocate memory " 295 "for command queue\n", chp->ch_channel); 296 return; 297 } 298 299 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 300 301 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 302 __func__, dmasize), DEBUG_FUNCS); 303 304 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 305 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 306 if (error) { 307 aprint_error_dev(sc->sc_atac.atac_dev, 308 "unable to allocate PRB table memory, " 309 "error=%d\n", error); 310 return; 311 } 312 313 error = bus_dmamem_map(sc->sc_dmat, 314 &schp->sch_prb_seg, schp->sch_prb_nseg, 315 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 316 if (error) { 317 aprint_error_dev(sc->sc_atac.atac_dev, 318 "unable to map PRB table memory, " 319 "error=%d\n", error); 320 bus_dmamem_free(sc->sc_dmat, 321 &schp->sch_prb_seg, schp->sch_prb_nseg); 322 return; 323 } 324 325 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 326 BUS_DMA_NOWAIT, &schp->sch_prbd); 327 if (error) { 328 aprint_error_dev(sc->sc_atac.atac_dev, 329 "unable to create PRB table map, " 330 "error=%d\n", error); 331 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 332 bus_dmamem_free(sc->sc_dmat, 333 &schp->sch_prb_seg, schp->sch_prb_nseg); 334 return; 335 } 336 337 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 338 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 339 if (error) { 340 aprint_error_dev(sc->sc_atac.atac_dev, 341 "unable to load PRB table map, " 342 "error=%d\n", error); 343 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 344 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 345 bus_dmamem_free(sc->sc_dmat, 346 &schp->sch_prb_seg, schp->sch_prb_nseg); 347 return; 348 } 349 350 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 351 schp->sch_prb[j] = (struct siisata_prb *) 352 ((char *)prbp + SIISATA_CMD_SIZE * j); 353 schp->sch_bus_prb[j] = 354 schp->sch_prbd->dm_segs[0].ds_addr + 355 SIISATA_CMD_SIZE * j; 356 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 357 SIISATA_NSGE, MAXPHYS, 0, 358 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 359 &schp->sch_datad[j]); 360 if (error) { 361 aprint_error_dev(sc->sc_atac.atac_dev, 362 "couldn't create xfer DMA map, error=%d\n", 363 error); 364 return; 365 } 366 } 367 368 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 369 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 370 aprint_error_dev(sc->sc_atac.atac_dev, 371 "couldn't map port %d SStatus regs\n", 372 chp->ch_channel); 373 return; 374 } 375 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 376 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 377 aprint_error_dev(sc->sc_atac.atac_dev, 378 "couldn't map port %d SControl regs\n", 379 chp->ch_channel); 380 return; 381 } 382 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 383 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 384 aprint_error_dev(sc->sc_atac.atac_dev, 385 "couldn't map port %d SError regs\n", 386 chp->ch_channel); 387 return; 388 } 389 390 siisata_init_port(sc, port); 391 392 ata_channel_attach(chp); 393 394 return; 395 } 396 397 int 398 siisata_detach(struct siisata_softc *sc, int flags) 399 { 400 struct atac_softc *atac = &sc->sc_atac; 401 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 402 struct siisata_channel *schp; 403 struct ata_channel *chp; 404 int i, j, error; 405 406 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 407 schp = &sc->sc_channels[i]; 408 chp = sc->sc_chanarray[i]; 409 410 if (chp->atabus == NULL) 411 continue; 412 if ((error = config_detach(chp->atabus, flags)) != 0) 413 return error; 414 415 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 416 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 417 418 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 419 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 420 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 421 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 422 bus_dmamem_free(sc->sc_dmat, 423 &schp->sch_prb_seg, schp->sch_prb_nseg); 424 425 free(chp->ch_queue, M_DEVBUF); 426 chp->atabus = NULL; 427 428 ata_channel_detach(chp); 429 } 430 431 if (adapt->adapt_refcnt != 0) 432 return EBUSY; 433 434 /* leave the chip in reset */ 435 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 436 437 return 0; 438 } 439 440 void 441 siisata_resume(struct siisata_softc *sc) 442 { 443 int i; 444 445 /* come out of reset state */ 446 GRWRITE(sc, GR_GC, 0); 447 448 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 449 siisata_init_port(sc, i); 450 } 451 452 } 453 454 int 455 siisata_intr(void *v) 456 { 457 struct siisata_softc *sc = v; 458 uint32_t is; 459 int i, r = 0; 460 while ((is = GRREAD(sc, GR_GIS))) { 461 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 462 SIISATANAME(sc), __func__, is), DEBUG_INTR); 463 r = 1; 464 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 465 if (is & GR_GIS_PXIS(i)) 466 siisata_intr_port(&sc->sc_channels[i]); 467 } 468 return r; 469 } 470 471 static void 472 siisata_intr_port(struct siisata_channel *schp) 473 { 474 struct siisata_softc *sc; 475 struct ata_channel *chp; 476 struct ata_xfer *xfer; 477 u_int slot; 478 uint32_t pss, pis; 479 480 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 481 chp = &schp->ata_channel; 482 483 /* get slot status, clearing completion interrupt (PR_PIS_CMDCMPL) */ 484 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 485 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x\n", 486 SIISATANAME(sc), __func__, chp->ch_channel, pss), DEBUG_INTR); 487 488 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 489 if (((schp->sch_active_slots >> slot) & 1) == 0) { 490 /* there's nothing executing here, skip */ 491 continue; 492 } 493 if (((pss >> slot) & 1) != 0) { 494 /* execution is incomplete or unsuccessful, skip 495 * for now */ 496 continue; 497 } 498 xfer = ata_queue_hwslot_to_xfer(chp, slot); 499 if (xfer->c_intr == NULL) { 500 wakeup(schp); 501 continue; 502 } 503 KASSERT(xfer != NULL); 504 KASSERT(xfer->c_intr != NULL); 505 xfer->c_intr(chp, xfer, 0); 506 } 507 /* if no errors, we're done now */ 508 if ((pss & PR_PSS_ATTENTION) == 0) { 509 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 510 pis &= 0xffff; 511 if (pis) { 512 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 513 pis & 0xfffcfffc); 514 } 515 return; 516 } 517 518 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 519 520 SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x ", SIISATANAME(sc), 521 __func__, chp->ch_channel, pis), DEBUG_INTR); 522 523 /* clear */ 524 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis); 525 526 if (pis & PR_PIS_CMDERRR) { 527 uint32_t ec; 528 529 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 530 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 531 532 /* emulate a CRC error by default */ 533 int tfd = ATACH_ERR_ST(WDCE_CRC, WDCS_ERR); 534 535 if (ec <= PR_PCE_DATAFISERROR && !schp->sch_recovering) { 536 siisata_channel_recover(chp, ec, tfd); 537 } else { 538 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 539 " on channel %d (ctx 0x%x), resetting\n", 540 ec, chp->ch_channel, 541 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 542 543 /* okay, we have a "Fatal Error" */ 544 siisata_device_reset(chp); 545 546 /* Complete any non-finished commands with the error */ 547 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 548 if (((schp->sch_active_slots >> slot) & 1) == 0) { 549 /* nothing executing here, skip */ 550 continue; 551 } 552 xfer = ata_queue_hwslot_to_xfer(chp, slot); 553 xfer->c_intr(chp, xfer, tfd); 554 } 555 } 556 } 557 558 return; 559 } 560 561 static void 562 siisata_hold(struct siisata_channel *schp) 563 { 564 schp->sch_hold_slots |= schp->sch_active_slots; 565 schp->sch_active_slots = 0; 566 } 567 568 static void 569 siisata_unhold(struct siisata_channel *schp) 570 { 571 schp->sch_active_slots = schp->sch_hold_slots; 572 schp->sch_hold_slots = 0; 573 } 574 575 /* Recover channel after transfer aborted */ 576 static void 577 siisata_channel_recover(struct ata_channel *chp, int ec, int tfd) 578 { 579 struct siisata_channel *schp = (struct siisata_channel *)chp; 580 struct siisata_softc *sc = 581 (struct siisata_softc *)schp->ata_channel.ch_atac; 582 struct ata_drive_datas *drvp; 583 int ps, drive, error; 584 uint8_t slot, st, err; 585 struct ata_xfer *xfer; 586 uint32_t prbfis; 587 588 KASSERT(!schp->sch_recovering); 589 590 schp->sch_recovering = true; 591 592 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 593 594 if (chp->ch_ndrives > PMP_PORT_CTL) { 595 /* Get PM port number for the device in error */ 596 int pcr = PRREAD(sc, PRX(chp->ch_channel, PRO_PCR)); 597 drive = PRO_PCR_PMP(pcr); 598 } else 599 drive = 0; 600 601 drvp = &chp->ch_drive[drive]; 602 603 siisata_hold(schp); 604 605 siisata_reinit_port(chp); 606 607 /* 608 * When running NCQ commands, READ LOG EXT is necessary to clear the 609 * error condition and unblock the device. 610 */ 611 error = ata_read_log_ext_ncq(drvp, AT_POLL, &slot, &st, &err); 612 613 siisata_unhold(schp); 614 615 if (error == EOPNOTSUPP) { 616 /* 617 * Not NCQ command or not NCQ device, there is only 618 * one outstanding tranfer, so find the active one, 619 * and send the error. 620 */ 621 xfer = ata_queue_drive_active_xfer(chp, drive); 622 if (ec == PR_PCE_DEVICEERROR) { 623 slot = PR_PS_ACTIVE_SLOT(ps); 624 625 /* read in specific information about error */ 626 prbfis = bus_space_read_stream_4( 627 sc->sc_prt, sc->sc_prh, 628 PRSX(chp->ch_channel, slot, 629 PRSO_FIS)); 630 631 /* get status and error */ 632 int ntfd = satafis_rdh_parse(chp, (uint8_t *)&prbfis); 633 634 if (ATACH_ST(ntfd) & WDCS_ERR) 635 tfd = ntfd; 636 } 637 638 xfer->c_intr(chp, xfer, tfd); 639 } else if (error == 0) { 640 xfer = ata_queue_hwslot_to_xfer(chp, slot); 641 xfer->c_intr(chp, xfer, ATACH_ERR_ST(err, st)); 642 } else { 643 /* Other error, do full device reset */ 644 drive = -1; 645 siisata_device_reset(chp); 646 } 647 648 /* Requeue the non-errorred commands */ 649 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 650 if (((schp->sch_active_slots >> slot) & 1) == 0) 651 continue; 652 653 xfer = ata_queue_hwslot_to_xfer(chp, slot); 654 if (drive >= 0 && xfer->c_drive != drive) 655 continue; 656 657 xfer->c_kill_xfer(chp, xfer, 658 drive >= 0 ? KILL_REQUEUE : KILL_RESET); 659 } 660 661 schp->sch_recovering = false; 662 } 663 664 void 665 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 666 { 667 struct ata_channel *chp = drvp->chnl_softc; 668 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 669 struct siisata_channel *schp = (struct siisata_channel *)chp; 670 struct siisata_prb *prb; 671 struct ata_xfer *xfer; 672 uint32_t pss, pis; 673 int i; 674 675 /* wait for ready */ 676 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 677 DELAY(10); 678 679 /* 680 * Try to get available slot. If there is none available, must 681 * do full channel reset. 682 */ 683 xfer = ata_get_xfer_ext(chp, false, 0); 684 if (xfer == NULL) { 685 printf("%s: no xfer\n", __func__); 686 siisata_reset_channel(chp, flags); 687 return; 688 } 689 690 prb = schp->sch_prb[xfer->c_slot]; 691 memset(prb, 0, SIISATA_CMD_SIZE); 692 prb->prb_control = 693 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 694 KASSERT(drvp->drive <= PMP_PORT_CTL); 695 prb->prb_fis[rhd_c] = drvp->drive; 696 697 siisata_disable_port_interrupt(chp); 698 699 siisata_activate_prb(schp, xfer->c_slot); 700 701 for(i = 0; i < 3100; i++) { 702 #if 1 /* XXX-jak-jd-ncq this block needs re-work... XXX */ 703 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_INCOR); 704 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 705 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_INCOR); 706 if ((pss & PR_PXSS(xfer->c_slot)) == 0) 707 break; 708 if (pss & PR_PSS_ATTENTION) 709 break; 710 #else 711 pss = PR_PXSS(xfer->c_slot); 712 /* XXX DO NOT MERGE UNTIL THIS IS FIXED XXX */ 713 #endif 714 ata_delay(10, "siiprb", flags); 715 } 716 717 siisata_deactivate_prb(schp, xfer->c_slot); 718 719 if ((pss & PR_PSS_ATTENTION) != 0) { 720 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 721 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 722 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 723 724 if (slot != xfer->c_slot) 725 device_printf(sc->sc_atac.atac_dev, "%s port %d " 726 "drive %d slot %d c_slot %d", __func__, 727 chp->ch_channel, drvp->drive, slot, xfer->c_slot); 728 729 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 730 PR_PIS_CMDERRR); 731 } 732 733 siisata_enable_port_interrupt(chp); 734 735 if (i == 3100) { 736 /* timeout */ 737 siisata_device_reset(chp); /* XXX is this right? */ 738 if (sigp) 739 *sigp = 0xffffffff; 740 } else { 741 /* read the signature out of the FIS */ 742 if (sigp) { 743 *sigp = 0; 744 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 745 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 746 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 747 PRSO_FIS+0xc)) & 0xff; 748 } 749 } 750 751 ata_free_xfer(chp, xfer); 752 753 return; 754 } 755 756 void 757 siisata_reset_channel(struct ata_channel *chp, int flags) 758 { 759 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 760 struct siisata_channel *schp = (struct siisata_channel *)chp; 761 762 SIISATA_DEBUG_PRINT(("%s: %s channel %d\n", SIISATANAME(sc), __func__, 763 chp->ch_channel), DEBUG_FUNCS); 764 765 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 766 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 767 aprint_error("%s port %d: reset failed\n", 768 SIISATANAME(sc), chp->ch_channel); 769 /* XXX and then ? */ 770 } 771 /* wait for ready */ 772 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 773 DELAY(10); 774 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 775 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 776 ata_kill_active(chp, KILL_RESET, flags); 777 778 return; 779 } 780 781 int 782 siisata_ata_addref(struct ata_drive_datas *drvp) 783 { 784 return 0; 785 } 786 787 void 788 siisata_ata_delref(struct ata_drive_datas *drvp) 789 { 790 return; 791 } 792 793 void 794 siisata_killpending(struct ata_drive_datas *drvp) 795 { 796 return; 797 } 798 799 void 800 siisata_probe_drive(struct ata_channel *chp) 801 { 802 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 803 struct siisata_channel *schp = (struct siisata_channel *)chp; 804 int i; 805 uint32_t sig; 806 struct siisata_prb *prb; 807 bool timed_out; 808 struct ata_xfer *xfer; 809 810 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 811 __func__, chp->ch_channel), DEBUG_FUNCS); 812 813 xfer = ata_get_xfer(chp); 814 if (xfer == NULL) { 815 aprint_error_dev(sc->sc_atac.atac_dev, 816 "failed to get xfer port %d\n", 817 chp->ch_channel); 818 return; 819 } 820 821 /* 822 * disable port interrupt as we're polling for PHY up and 823 * prb completion 824 */ 825 siisata_disable_port_interrupt(chp); 826 827 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 828 schp->sch_sstatus, AT_WAIT)) { 829 case SStatus_DET_DEV: 830 #if 0 /* XXX Including this seems to cause problems. */ 831 /* XXX DO NOT MERGE UNTIL THIS IS ADDRESSED PROPERLY XXX */ 832 /* clear any interrupts */ 833 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 834 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 835 #endif 836 /* wait for ready */ 837 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 838 & PR_PS_PORT_READY)) 839 DELAY(10); 840 prb = schp->sch_prb[xfer->c_slot]; 841 memset(prb, 0, SIISATA_CMD_SIZE); 842 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 843 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 844 845 siisata_activate_prb(schp, xfer->c_slot); 846 847 timed_out = 1; 848 for(i = 0; i < 3100; i++) { 849 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 850 PR_PXSS(xfer->c_slot)) == 0) { 851 /* prb completed */ 852 timed_out = 0; 853 break; 854 } 855 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 856 (PR_PIS_CMDERRR << 16)) { 857 /* we got an error; handle as timeout */ 858 break; 859 } 860 861 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 862 } 863 864 siisata_deactivate_prb(schp, xfer->c_slot); 865 866 if (timed_out) { 867 aprint_error_dev(sc->sc_atac.atac_dev, 868 "SOFT_RESET failed on port %d (error %d PSS 0x%x), " 869 "resetting\n", chp->ch_channel, 870 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 871 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); 872 siisata_reinit_port(chp); 873 break; 874 } 875 876 /* read the signature out of the FIS */ 877 sig = 0; 878 sig |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 879 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 880 sig |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 881 PRSO_FIS+0xc)) & 0xff; 882 883 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 884 __func__, sig), DEBUG_PROBE); 885 886 if (sig == 0x96690101) 887 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 888 PR_PC_PMP_ENABLE); 889 sata_interpret_sig(chp, 0, sig); 890 break; 891 default: 892 break; 893 } 894 895 siisata_enable_port_interrupt(chp); 896 897 ata_free_xfer(chp, xfer); 898 899 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 900 __func__, chp->ch_channel), DEBUG_PROBE); 901 return; 902 } 903 904 void 905 siisata_setup_channel(struct ata_channel *chp) 906 { 907 return; 908 } 909 910 int 911 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 912 { 913 struct ata_channel *chp = drvp->chnl_softc; 914 struct ata_command *ata_c = &xfer->c_ata_c; 915 int ret; 916 int s; 917 918 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 919 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 920 DEBUG_FUNCS); 921 922 if (ata_c->flags & AT_POLL) 923 xfer->c_flags |= C_POLL; 924 if (ata_c->flags & AT_WAIT) 925 xfer->c_flags |= C_WAIT; 926 xfer->c_drive = drvp->drive; 927 xfer->c_databuf = ata_c->data; 928 xfer->c_bcount = ata_c->bcount; 929 xfer->c_start = siisata_cmd_start; 930 xfer->c_intr = siisata_cmd_complete; 931 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 932 s = splbio(); 933 ata_exec_xfer(chp, xfer); 934 #ifdef DIAGNOSTIC 935 if ((ata_c->flags & AT_POLL) != 0 && 936 (ata_c->flags & AT_DONE) == 0) 937 panic("%s: polled command not done", __func__); 938 #endif 939 if (ata_c->flags & AT_DONE) { 940 ret = ATACMD_COMPLETE; 941 } else { 942 if (ata_c->flags & AT_WAIT) { 943 while ((ata_c->flags & AT_DONE) == 0) { 944 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 945 SIISATANAME( 946 (struct siisata_softc *)chp->ch_atac), 947 __func__), DEBUG_FUNCS); 948 tsleep(ata_c, PRIBIO, "siicmd", 0); 949 } 950 ret = ATACMD_COMPLETE; 951 } else { 952 ret = ATACMD_QUEUED; 953 } 954 } 955 splx(s); 956 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 957 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 958 DEBUG_FUNCS); 959 return ret; 960 } 961 962 void 963 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 964 { 965 struct siisata_channel *schp = (struct siisata_channel *)chp; 966 struct ata_command *ata_c = &xfer->c_ata_c; 967 struct siisata_prb *prb; 968 int i; 969 970 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 971 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 972 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 973 DEBUG_FUNCS|DEBUG_XFERS); 974 975 prb = schp->sch_prb[xfer->c_slot]; 976 memset(prb, 0, SIISATA_CMD_SIZE); 977 978 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 979 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 980 prb->prb_fis[rhd_c] |= xfer->c_drive; 981 982 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 983 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 984 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 985 } 986 987 if (siisata_dma_setup(chp, xfer->c_slot, 988 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 989 ata_c->bcount, 990 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 991 ata_c->flags |= AT_DF; 992 siisata_cmd_complete(chp, xfer, 0); 993 return; 994 } 995 996 if (xfer->c_flags & C_POLL) { 997 /* polled command, disable interrupts */ 998 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 999 siisata_disable_port_interrupt(chp); 1000 } 1001 1002 /* go for it */ 1003 siisata_activate_prb(schp, xfer->c_slot); 1004 1005 if ((ata_c->flags & AT_POLL) == 0) { 1006 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 1007 ata_timeout, xfer); 1008 goto out; 1009 } 1010 1011 /* 1012 * polled command 1013 */ 1014 for (i = 0; i < ata_c->timeout * 10; i++) { 1015 if (ata_c->flags & AT_DONE) 1016 break; 1017 siisata_intr_port(schp); 1018 DELAY(100); 1019 } 1020 1021 if ((ata_c->flags & AT_DONE) == 0) { 1022 ata_timeout(xfer); 1023 } 1024 1025 /* reenable interrupts */ 1026 siisata_enable_port_interrupt(chp); 1027 out: 1028 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1029 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1030 DEBUG_FUNCS); 1031 return; 1032 } 1033 1034 void 1035 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1036 int reason) 1037 { 1038 struct ata_command *ata_c = &xfer->c_ata_c; 1039 struct siisata_channel *schp = (struct siisata_channel *)chp; 1040 bool deactivate = true; 1041 1042 switch (reason) { 1043 case KILL_GONE_INACTIVE: 1044 deactivate = false; 1045 /* FALLTHROUGH */ 1046 case KILL_GONE: 1047 ata_c->flags |= AT_GONE; 1048 break; 1049 case KILL_RESET: 1050 ata_c->flags |= AT_RESET; 1051 break; 1052 case KILL_REQUEUE: 1053 panic("%s: not supposed to be requeued\n", __func__); 1054 break; 1055 default: 1056 panic("%s: port %d: unknown reason %d", 1057 __func__, chp->ch_channel, reason); 1058 } 1059 1060 if (deactivate) { 1061 siisata_deactivate_prb(schp, xfer->c_slot); 1062 ata_deactivate_xfer(chp, xfer); 1063 } 1064 1065 siisata_cmd_done_end(chp, xfer); 1066 } 1067 1068 int 1069 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1070 { 1071 struct siisata_channel *schp = (struct siisata_channel *)chp; 1072 struct ata_command *ata_c = &xfer->c_ata_c; 1073 #ifdef SIISATA_DEBUG 1074 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1075 #endif 1076 1077 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1078 SIISATANAME(sc), __func__, 1079 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1080 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1081 DEBUG_FUNCS|DEBUG_XFERS); 1082 1083 if (ata_waitdrain_xfer_check(chp, xfer)) 1084 return 0; 1085 1086 siisata_deactivate_prb(schp, xfer->c_slot); 1087 ata_deactivate_xfer(chp, xfer); 1088 1089 if (xfer->c_flags & C_TIMEOU) 1090 ata_c->flags |= AT_TIMEOU; 1091 1092 if (ATACH_ST(tfd) & WDCS_BSY) { 1093 ata_c->flags |= AT_TIMEOU; 1094 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1095 ata_c->r_error = ATACH_ERR(tfd); 1096 ata_c->flags |= AT_ERROR; 1097 } 1098 1099 siisata_cmd_done(chp, xfer, tfd); 1100 1101 return 0; 1102 } 1103 1104 void 1105 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1106 { 1107 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1108 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1109 struct siisata_channel *schp = (struct siisata_channel *)chp; 1110 struct ata_command *ata_c = &xfer->c_ata_c; 1111 uint16_t *idwordbuf; 1112 int i; 1113 1114 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1115 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1116 1117 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1118 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1119 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1120 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1121 BUS_DMASYNC_POSTWRITE); 1122 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1123 } 1124 1125 if (ata_c->flags & AT_READREG) { 1126 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1127 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1128 fis, __arraycount(fis)); 1129 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1130 } 1131 1132 /* correct the endianess of IDENTIFY data */ 1133 if (ata_c->r_command == WDCC_IDENTIFY || 1134 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1135 idwordbuf = xfer->c_databuf; 1136 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1137 idwordbuf[i] = le16toh(idwordbuf[i]); 1138 } 1139 } 1140 1141 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1142 ata_c->flags |= AT_XFDONE; 1143 1144 siisata_cmd_done_end(chp, xfer); 1145 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1146 atastart(chp); 1147 } 1148 1149 static void 1150 siisata_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1151 { 1152 struct ata_command *ata_c = &xfer->c_ata_c; 1153 1154 ata_c->flags |= AT_DONE; 1155 1156 if (ata_c->flags & AT_WAIT) 1157 wakeup(ata_c); 1158 return; 1159 } 1160 1161 int 1162 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1163 { 1164 struct ata_channel *chp = drvp->chnl_softc; 1165 struct ata_bio *ata_bio = &xfer->c_bio; 1166 1167 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1168 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1169 DEBUG_FUNCS); 1170 1171 if (xfer == NULL) 1172 return ATACMD_TRY_AGAIN; 1173 if (ata_bio->flags & ATA_POLL) 1174 xfer->c_flags |= C_POLL; 1175 xfer->c_drive = drvp->drive; 1176 xfer->c_databuf = ata_bio->databuf; 1177 xfer->c_bcount = ata_bio->bcount; 1178 xfer->c_start = siisata_bio_start; 1179 xfer->c_intr = siisata_bio_complete; 1180 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1181 ata_exec_xfer(chp, xfer); 1182 return (ata_bio->flags & ATA_ITSDONE) ? 1183 ATACMD_COMPLETE : ATACMD_QUEUED; 1184 } 1185 1186 void 1187 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1188 { 1189 struct siisata_channel *schp = (struct siisata_channel *)chp; 1190 struct siisata_prb *prb; 1191 struct ata_bio *ata_bio = &xfer->c_bio; 1192 int i; 1193 1194 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1195 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1196 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1197 1198 prb = schp->sch_prb[xfer->c_slot]; 1199 memset(prb, 0, SIISATA_CMD_SIZE); 1200 1201 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1202 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1203 prb->prb_fis[rhd_c] |= xfer->c_drive; 1204 1205 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1206 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1207 ata_bio->error = ERR_DMA; 1208 ata_bio->r_error = 0; 1209 siisata_bio_complete(chp, xfer, 0); 1210 return; 1211 } 1212 1213 if (xfer->c_flags & C_POLL) { 1214 /* polled command, disable interrupts */ 1215 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1216 siisata_disable_port_interrupt(chp); 1217 } 1218 1219 siisata_activate_prb(schp, xfer->c_slot); 1220 1221 if ((ata_bio->flags & ATA_POLL) == 0) { 1222 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1223 ata_timeout, xfer); 1224 goto out; 1225 } 1226 1227 /* 1228 * polled command 1229 */ 1230 for (i = 0; i < ATA_DELAY * 10; i++) { 1231 if (ata_bio->flags & ATA_ITSDONE) 1232 break; 1233 siisata_intr_port(schp); 1234 DELAY(100); 1235 } 1236 1237 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1238 ata_timeout(xfer); 1239 } 1240 1241 siisata_enable_port_interrupt(chp); 1242 out: 1243 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1244 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1245 DEBUG_FUNCS); 1246 return; 1247 } 1248 1249 void 1250 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1251 int reason) 1252 { 1253 struct siisata_channel *schp = (struct siisata_channel *)chp; 1254 struct ata_bio *ata_bio = &xfer->c_bio; 1255 int drive = xfer->c_drive; 1256 bool deactivate = true; 1257 1258 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1259 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1260 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1261 1262 ata_bio->flags |= ATA_ITSDONE; 1263 switch (reason) { 1264 case KILL_GONE_INACTIVE: 1265 deactivate = false; 1266 /* FALLTHROUGH */ 1267 case KILL_GONE: 1268 ata_bio->error = ERR_NODEV; 1269 break; 1270 case KILL_RESET: 1271 ata_bio->error = ERR_RESET; 1272 break; 1273 case KILL_REQUEUE: 1274 ata_bio->error = REQUEUE; 1275 break; 1276 default: 1277 panic("%s: port %d: unknown reason %d", 1278 __func__, chp->ch_channel, reason); 1279 } 1280 ata_bio->r_error = WDCE_ABRT; 1281 1282 if (deactivate) { 1283 siisata_deactivate_prb(schp, xfer->c_slot); 1284 ata_deactivate_xfer(chp, xfer); 1285 } 1286 1287 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1288 } 1289 1290 int 1291 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1292 { 1293 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1294 struct siisata_channel *schp = (struct siisata_channel *)chp; 1295 struct ata_bio *ata_bio = &xfer->c_bio; 1296 int drive = xfer->c_drive; 1297 1298 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d\n", 1299 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1300 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1301 1302 if (ata_waitdrain_xfer_check(chp, xfer)) 1303 return 0; 1304 1305 siisata_deactivate_prb(schp, xfer->c_slot); 1306 ata_deactivate_xfer(chp, xfer); 1307 1308 if (xfer->c_flags & C_TIMEOU) { 1309 ata_bio->error = TIMEOUT; 1310 } 1311 1312 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1313 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1314 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1315 BUS_DMASYNC_POSTWRITE); 1316 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1317 1318 ata_bio->flags |= ATA_ITSDONE; 1319 if (ATACH_ST(tfd) & WDCS_DWF) { 1320 ata_bio->error = ERR_DF; 1321 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1322 ata_bio->error = ERROR; 1323 ata_bio->r_error = ATACH_ERR(tfd); 1324 } else if (ATACH_ST(tfd) & WDCS_CORR) 1325 ata_bio->flags |= ATA_CORR; 1326 1327 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1328 ata_bio->bcount), DEBUG_XFERS); 1329 if (ata_bio->error == NOERROR) { 1330 if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ) 1331 ata_bio->bcount -= 1332 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1333 else 1334 ata_bio->bcount = 0; 1335 } 1336 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1337 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1338 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1339 atastart(chp); 1340 return 0; 1341 } 1342 1343 static int 1344 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1345 size_t count, int op) 1346 { 1347 1348 int error, seg; 1349 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1350 struct siisata_channel *schp = (struct siisata_channel *)chp; 1351 1352 struct siisata_prb *prbp; 1353 1354 prbp = schp->sch_prb[slot]; 1355 1356 if (data == NULL) { 1357 goto end; 1358 } 1359 1360 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1361 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1362 if (error) { 1363 aprint_error("%s port %d: " 1364 "failed to load xfer in slot %d: error %d\n", 1365 SIISATANAME(sc), chp->ch_channel, slot, error); 1366 return error; 1367 } 1368 1369 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1370 schp->sch_datad[slot]->dm_mapsize, 1371 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1372 1373 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1374 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1375 DEBUG_FUNCS | DEBUG_DEBUG); 1376 1377 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1378 prbp->prb_sge[seg].sge_da = 1379 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1380 prbp->prb_sge[seg].sge_dc = 1381 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1382 prbp->prb_sge[seg].sge_flags = htole32(0); 1383 } 1384 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1385 end: 1386 return 0; 1387 } 1388 1389 static void 1390 siisata_activate_prb(struct siisata_channel *schp, int slot) 1391 { 1392 struct siisata_softc *sc; 1393 bus_size_t offset; 1394 uint64_t pprb; 1395 1396 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1397 1398 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) == 0, 1399 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1400 1401 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1402 /* keep track of what's going on */ 1403 schp->sch_active_slots |= __BIT(slot); 1404 1405 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1406 1407 pprb = schp->sch_bus_prb[slot]; 1408 1409 PRWRITE(sc, offset + 0, pprb >> 0); 1410 PRWRITE(sc, offset + 4, pprb >> 32); 1411 } 1412 1413 static void 1414 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1415 { 1416 struct siisata_softc *sc; 1417 1418 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1419 1420 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1421 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1422 slot); 1423 1424 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1425 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1426 } 1427 1428 static void 1429 siisata_reinit_port(struct ata_channel *chp) 1430 { 1431 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1432 int ps; 1433 1434 1435 if (chp->ch_ndrives > 1) { 1436 /* 1437 * Proper recovery would SET this bit, which makes it 1438 * not possible to submit new commands and resume execution 1439 * on non-errored drives, then wait for those commands, 1440 * to finish, and only then clear the bit and reset the state. 1441 * For now this is okay, since we never queue commands for 1442 * more than one drive. 1443 * XXX FIS-based switching 1444 */ 1445 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_RESUME); 1446 1447 for (int i = 0; i < chp->ch_ndrives; i++) { 1448 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPSTS(i)), 0); 1449 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPQACT(i)), 0); 1450 } 1451 } 1452 1453 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1454 for (int i = 0; i < ATA_DELAY * 100; i++) { 1455 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1456 if ((ps & PR_PS_PORT_READY) != 0) 1457 break; 1458 1459 DELAY(10); 1460 } 1461 if ((ps & PR_PS_PORT_READY) == 0) 1462 printf("%s: timeout waiting for port to be ready", __func__); 1463 1464 if (chp->ch_ndrives > 1) 1465 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1466 } 1467 1468 static void 1469 siisata_device_reset(struct ata_channel *chp) 1470 { 1471 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1472 int ps; 1473 1474 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1475 1476 for (int i = 0; i < ATA_DELAY * 100; i++) { 1477 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1478 if ((ps & PR_PS_PORT_READY) != 0) 1479 break; 1480 1481 DELAY(10); 1482 } 1483 if ((ps & PR_PS_PORT_READY) == 0) 1484 printf("%s: timeout waiting for port to be ready", __func__); 1485 } 1486 1487 1488 #if NATAPIBUS > 0 1489 void 1490 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1491 { 1492 struct ata_channel *chp = ata_sc->sc_chan; 1493 struct atac_softc *atac = chp->ch_atac; 1494 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1495 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1496 1497 /* 1498 * Fill in the scsipi_adapter. 1499 */ 1500 adapt->adapt_dev = atac->atac_dev; 1501 adapt->adapt_nchannels = atac->atac_nchannels; 1502 adapt->adapt_request = siisata_atapi_scsipi_request; 1503 adapt->adapt_minphys = siisata_atapi_minphys; 1504 atac->atac_atapi_adapter.atapi_probe_device = 1505 siisata_atapi_probe_device; 1506 1507 /* 1508 * Fill in the scsipi_channel. 1509 */ 1510 memset(chan, 0, sizeof(*chan)); 1511 chan->chan_adapter = adapt; 1512 chan->chan_bustype = &siisata_atapi_bustype; 1513 chan->chan_channel = chp->ch_channel; 1514 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1515 chan->chan_openings = 1; 1516 chan->chan_max_periph = 1; 1517 chan->chan_ntargets = 1; 1518 chan->chan_nluns = 1; 1519 1520 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1521 atapiprint); 1522 } 1523 1524 void 1525 siisata_atapi_minphys(struct buf *bp) 1526 { 1527 if (bp->b_bcount > MAXPHYS) 1528 bp->b_bcount = MAXPHYS; 1529 minphys(bp); 1530 } 1531 1532 /* 1533 * Kill off all pending xfers for a periph. 1534 * 1535 * Must be called at splbio(). 1536 */ 1537 void 1538 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1539 { 1540 struct atac_softc *atac = 1541 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1542 struct ata_channel *chp = 1543 atac->atac_channels[periph->periph_channel->chan_channel]; 1544 1545 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1546 } 1547 1548 void 1549 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1550 int reason) 1551 { 1552 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1553 struct siisata_channel *schp = (struct siisata_channel *)chp; 1554 bool deactivate = true; 1555 1556 /* remove this command from xfer queue */ 1557 switch (reason) { 1558 case KILL_GONE_INACTIVE: 1559 deactivate = false; 1560 /* FALLTHROUGH */ 1561 case KILL_GONE: 1562 sc_xfer->error = XS_DRIVER_STUFFUP; 1563 break; 1564 case KILL_RESET: 1565 sc_xfer->error = XS_RESET; 1566 break; 1567 case KILL_REQUEUE: 1568 sc_xfer->error = XS_REQUEUE; 1569 break; 1570 default: 1571 panic("%s: port %d: unknown reason %d", 1572 __func__, chp->ch_channel, reason); 1573 } 1574 1575 if (deactivate) { 1576 siisata_deactivate_prb(schp, xfer->c_slot); 1577 ata_deactivate_xfer(chp, xfer); 1578 } 1579 1580 ata_free_xfer(chp, xfer); 1581 scsipi_done(sc_xfer); 1582 } 1583 1584 void 1585 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1586 { 1587 struct scsipi_channel *chan = sc->sc_channel; 1588 struct scsipi_periph *periph; 1589 struct ataparams ids; 1590 struct ataparams *id = &ids; 1591 struct siisata_softc *siic = 1592 device_private(chan->chan_adapter->adapt_dev); 1593 struct atac_softc *atac = &siic->sc_atac; 1594 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1595 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1596 struct scsipibus_attach_args sa; 1597 char serial_number[21], model[41], firmware_revision[9]; 1598 int s; 1599 1600 /* skip if already attached */ 1601 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1602 return; 1603 1604 /* if no ATAPI device detected at attach time, skip */ 1605 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1606 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1607 target), DEBUG_PROBE); 1608 return; 1609 } 1610 1611 /* Some ATAPI devices need a bit more time after software reset. */ 1612 DELAY(5000); 1613 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1614 #ifdef ATAPI_DEBUG_PROBE 1615 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1616 device_xname(sc->sc_dev), target, 1617 id->atap_config & ATAPI_CFG_CMD_MASK, 1618 id->atap_config & ATAPI_CFG_DRQ_MASK); 1619 #endif 1620 periph = scsipi_alloc_periph(M_NOWAIT); 1621 if (periph == NULL) { 1622 aprint_error_dev(sc->sc_dev, 1623 "%s: unable to allocate periph for " 1624 "channel %d drive %d\n", __func__, 1625 chp->ch_channel, target); 1626 return; 1627 } 1628 periph->periph_dev = NULL; 1629 periph->periph_channel = chan; 1630 periph->periph_switch = &atapi_probe_periphsw; 1631 periph->periph_target = target; 1632 periph->periph_lun = 0; 1633 periph->periph_quirks = PQUIRK_ONLYBIG; 1634 1635 #ifdef SCSIPI_DEBUG 1636 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1637 SCSIPI_DEBUG_TARGET == target) 1638 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1639 #endif 1640 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1641 if (id->atap_config & ATAPI_CFG_REMOV) 1642 periph->periph_flags |= PERIPH_REMOVABLE; 1643 sa.sa_periph = periph; 1644 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1645 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1646 T_REMOV : T_FIXED; 1647 strnvisx(model, sizeof(model), id->atap_model, 40, 1648 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1649 strnvisx(serial_number, sizeof(serial_number), 1650 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1651 strnvisx(firmware_revision, sizeof(firmware_revision), 1652 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1653 sa.sa_inqbuf.vendor = model; 1654 sa.sa_inqbuf.product = serial_number; 1655 sa.sa_inqbuf.revision = firmware_revision; 1656 1657 /* 1658 * Determine the operating mode capabilities of the device. 1659 */ 1660 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1661 == ATAPI_CFG_CMD_16) { 1662 periph->periph_cap |= PERIPH_CAP_CMD16; 1663 1664 /* configure port for packet length */ 1665 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1666 PR_PC_PACKET_LENGTH); 1667 } else { 1668 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1669 PR_PC_PACKET_LENGTH); 1670 } 1671 1672 /* XXX This is gross. */ 1673 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1674 1675 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1676 1677 if (drvp->drv_softc) 1678 ata_probe_caps(drvp); 1679 else { 1680 s = splbio(); 1681 drvp->drive_type &= ATA_DRIVET_NONE; 1682 splx(s); 1683 } 1684 } else { 1685 s = splbio(); 1686 drvp->drive_type &= ATA_DRIVET_NONE; 1687 splx(s); 1688 } 1689 } 1690 1691 void 1692 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1693 scsipi_adapter_req_t req, void *arg) 1694 { 1695 struct scsipi_adapter *adapt = chan->chan_adapter; 1696 struct scsipi_periph *periph; 1697 struct scsipi_xfer *sc_xfer; 1698 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1699 struct atac_softc *atac = &sc->sc_atac; 1700 struct ata_xfer *xfer; 1701 int channel = chan->chan_channel; 1702 int drive, s; 1703 1704 switch (req) { 1705 case ADAPTER_REQ_RUN_XFER: 1706 sc_xfer = arg; 1707 periph = sc_xfer->xs_periph; 1708 drive = periph->periph_target; 1709 1710 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1711 device_xname(atac->atac_dev), channel, drive), 1712 DEBUG_XFERS); 1713 1714 if (!device_is_active(atac->atac_dev)) { 1715 sc_xfer->error = XS_DRIVER_STUFFUP; 1716 scsipi_done(sc_xfer); 1717 return; 1718 } 1719 xfer = ata_get_xfer_ext(atac->atac_channels[channel], false, 0); 1720 if (xfer == NULL) { 1721 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1722 scsipi_done(sc_xfer); 1723 return; 1724 } 1725 1726 if (sc_xfer->xs_control & XS_CTL_POLL) 1727 xfer->c_flags |= C_POLL; 1728 xfer->c_drive = drive; 1729 xfer->c_flags |= C_ATAPI; 1730 xfer->c_scsipi = sc_xfer; 1731 xfer->c_databuf = sc_xfer->data; 1732 xfer->c_bcount = sc_xfer->datalen; 1733 xfer->c_start = siisata_atapi_start; 1734 xfer->c_intr = siisata_atapi_complete; 1735 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1736 xfer->c_dscpoll = 0; 1737 s = splbio(); 1738 ata_exec_xfer(atac->atac_channels[channel], xfer); 1739 #ifdef DIAGNOSTIC 1740 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1741 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1742 panic("%s: polled command not done", __func__); 1743 #endif 1744 splx(s); 1745 return; 1746 1747 default: 1748 /* Not supported, nothing to do. */ 1749 ; 1750 } 1751 } 1752 1753 void 1754 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1755 { 1756 struct siisata_channel *schp = (struct siisata_channel *)chp; 1757 struct siisata_prb *prbp; 1758 1759 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1760 int i; 1761 1762 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1763 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1764 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1765 DEBUG_XFERS); 1766 1767 prbp = schp->sch_prb[xfer->c_slot]; 1768 memset(prbp, 0, SIISATA_CMD_SIZE); 1769 1770 /* fill in direction for ATAPI command */ 1771 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1772 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1773 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1774 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1775 1776 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1777 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1778 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1779 1780 /* copy over ATAPI command */ 1781 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1782 1783 if (siisata_dma_setup(chp, xfer->c_slot, 1784 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1785 xfer->c_databuf : NULL, 1786 xfer->c_bcount, 1787 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1788 BUS_DMA_READ : BUS_DMA_WRITE) 1789 ) 1790 panic("%s", __func__); 1791 1792 if (xfer->c_flags & C_POLL) { 1793 /* polled command, disable interrupts */ 1794 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1795 siisata_disable_port_interrupt(chp); 1796 } 1797 1798 siisata_activate_prb(schp, xfer->c_slot); 1799 1800 if ((xfer->c_flags & C_POLL) == 0) { 1801 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1802 ata_timeout, xfer); 1803 goto out; 1804 } 1805 1806 /* 1807 * polled command 1808 */ 1809 for (i = 0; i < ATA_DELAY * 10; i++) { 1810 if (sc_xfer->xs_status & XS_STS_DONE) 1811 break; 1812 siisata_intr_port(schp); 1813 DELAY(100); 1814 } 1815 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1816 ata_timeout(xfer); 1817 } 1818 /* reenable interrupts */ 1819 siisata_enable_port_interrupt(chp); 1820 out: 1821 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1822 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1823 DEBUG_FUNCS); 1824 return; 1825 } 1826 1827 int 1828 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1829 int tfd) 1830 { 1831 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1832 struct siisata_channel *schp = (struct siisata_channel *)chp; 1833 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1834 1835 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1836 DEBUG_INTR); 1837 1838 if (ata_waitdrain_xfer_check(chp, xfer)) 1839 return 0; 1840 1841 /* this command is not active any more */ 1842 siisata_deactivate_prb(schp, xfer->c_slot); 1843 ata_deactivate_xfer(chp, xfer); 1844 1845 if (xfer->c_flags & C_TIMEOU) { 1846 sc_xfer->error = XS_TIMEOUT; 1847 } else if ((ATACH_ST(tfd) & WDCS_ERR) == 0) { 1848 sc_xfer->error = XS_NOERROR; 1849 } 1850 1851 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1852 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1853 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1854 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1855 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1856 1857 sc_xfer->resid = sc_xfer->datalen; 1858 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1859 PRSO_RTC)); 1860 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1861 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1862 if ((ATACH_ST(tfd) & WDCS_ERR) && 1863 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1864 sc_xfer->resid == sc_xfer->datalen)) { 1865 sc_xfer->error = XS_SHORTSENSE; 1866 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1867 if ((sc_xfer->xs_periph->periph_quirks & 1868 PQUIRK_NOSENSE) == 0) { 1869 /* request sense */ 1870 sc_xfer->error = XS_BUSY; 1871 sc_xfer->status = SCSI_CHECK; 1872 } 1873 } 1874 ata_free_xfer(chp, xfer); 1875 scsipi_done(sc_xfer); 1876 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1877 atastart(chp); 1878 return 0; 1879 } 1880 1881 #endif /* NATAPIBUS */ 1882
Indexes created Thu Oct 23 22:10:10 GMT 2025