siisata.c revision 1.30.4.34
1 /* $NetBSD: siisata.c,v 1.30.4.34 2017/08/11 18:20:13 jdolecek Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.30.4.34 2017/08/11 18:20:13 jdolecek Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define WDC_RESET_WAIT 31000 /* 31s for drive reset */ 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #if _BYTE_ORDER == _LITTLE_ENDIAN 116 #define bus_space_read_stream_4 bus_space_read_4 117 #define bus_space_read_region_stream_4 bus_space_read_region_4 118 #else 119 static inline uint32_t 120 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 121 { 122 return htole32(bus_space_read_4(t, h, o)); 123 } 124 125 static inline void 126 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 127 bus_size_t o, uint32_t *p, bus_size_t c) 128 { 129 bus_space_read_region_4(t, h, o, p, c); 130 for (bus_size_t i = 0; i < c; i++) { 131 p[i] = htole32(p[i]); 132 } 133 } 134 #endif 135 #endif 136 137 static void siisata_attach_port(struct siisata_softc *, int); 138 static void siisata_intr_port(struct siisata_channel *); 139 140 void siisata_probe_drive(struct ata_channel *); 141 void siisata_setup_channel(struct ata_channel *); 142 143 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 144 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 145 void siisata_reset_channel(struct ata_channel *, int); 146 int siisata_ata_addref(struct ata_drive_datas *); 147 void siisata_ata_delref(struct ata_drive_datas *); 148 void siisata_killpending(struct ata_drive_datas *); 149 150 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 151 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 153 static void siisata_cmd_done_end(struct ata_channel *, struct ata_xfer *); 154 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 155 156 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 157 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 158 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 159 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 160 161 static void siisata_reinit_port(struct ata_channel *, int); 162 static void siisata_device_reset(struct ata_channel *); 163 static void siisata_activate_prb(struct siisata_channel *, int); 164 static void siisata_deactivate_prb(struct siisata_channel *, int); 165 static int siisata_dma_setup(struct ata_channel *, int, void *, size_t, int); 166 void siisata_channel_recover(struct ata_channel *, uint32_t); 167 168 #if NATAPIBUS > 0 169 void siisata_atapibus_attach(struct atabus_softc *); 170 void siisata_atapi_probe_device(struct atapibus_softc *, int); 171 void siisata_atapi_minphys(struct buf *); 172 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 173 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 174 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 175 void siisata_atapi_scsipi_request(struct scsipi_channel *, 176 scsipi_adapter_req_t, void *); 177 void siisata_atapi_kill_pending(struct scsipi_periph *); 178 #endif /* NATAPIBUS */ 179 180 const struct ata_bustype siisata_ata_bustype = { 181 SCSIPI_BUSTYPE_ATA, 182 siisata_ata_bio, 183 siisata_reset_drive, 184 siisata_reset_channel, 185 siisata_exec_command, 186 ata_get_params, 187 siisata_ata_addref, 188 siisata_ata_delref, 189 siisata_killpending 190 }; 191 192 #if NATAPIBUS > 0 193 static const struct scsipi_bustype siisata_atapi_bustype = { 194 SCSIPI_BUSTYPE_ATAPI, 195 atapi_scsipi_cmd, 196 atapi_interpret_sense, 197 atapi_print_addr, 198 siisata_atapi_kill_pending, 199 NULL, 200 }; 201 #endif /* NATAPIBUS */ 202 203 204 void 205 siisata_attach(struct siisata_softc *sc) 206 { 207 int i; 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 211 212 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 213 sc->sc_atac.atac_pio_cap = 4; 214 sc->sc_atac.atac_dma_cap = 2; 215 sc->sc_atac.atac_udma_cap = 6; 216 sc->sc_atac.atac_channels = sc->sc_chanarray; 217 sc->sc_atac.atac_probe = siisata_probe_drive; 218 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 219 sc->sc_atac.atac_set_modes = siisata_setup_channel; 220 #if NATAPIBUS > 0 221 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 222 #endif 223 224 /* come out of reset state */ 225 GRWRITE(sc, GR_GC, 0); 226 227 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 228 siisata_attach_port(sc, i); 229 } 230 231 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 232 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 233 return; 234 } 235 236 static void 237 siisata_disable_port_interrupt(struct ata_channel *chp) 238 { 239 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 240 241 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 242 } 243 244 static void 245 siisata_enable_port_interrupt(struct ata_channel *chp) 246 { 247 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 248 249 /* clear any interrupts */ 250 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 251 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 252 /* and enable CmdErrr+CmdCmpl interrupting */ 253 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 254 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 255 } 256 257 static void 258 siisata_init_port(struct siisata_softc *sc, int port) 259 { 260 struct siisata_channel *schp; 261 struct ata_channel *chp; 262 263 schp = &sc->sc_channels[port]; 264 chp = (struct ata_channel *)schp; 265 266 /* 267 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 268 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 269 */ 270 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 271 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 272 /* initialize port */ 273 siisata_reinit_port(chp, -1); 274 /* enable CmdErrr+CmdCmpl interrupting */ 275 siisata_enable_port_interrupt(chp); 276 /* enable port interrupt */ 277 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 278 } 279 280 static void 281 siisata_attach_port(struct siisata_softc *sc, int port) 282 { 283 int j; 284 int dmasize; 285 int error; 286 void *prbp; 287 struct siisata_channel *schp; 288 struct ata_channel *chp; 289 290 schp = &sc->sc_channels[port]; 291 chp = (struct ata_channel *)schp; 292 sc->sc_chanarray[port] = chp; 293 chp->ch_channel = port; 294 chp->ch_atac = &sc->sc_atac; 295 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 296 if (chp->ch_queue == NULL) { 297 aprint_error_dev(sc->sc_atac.atac_dev, 298 "port %d: can't allocate memory " 299 "for command queue\n", chp->ch_channel); 300 return; 301 } 302 303 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 304 305 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 306 __func__, dmasize), DEBUG_FUNCS); 307 308 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 309 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 310 if (error) { 311 aprint_error_dev(sc->sc_atac.atac_dev, 312 "unable to allocate PRB table memory, " 313 "error=%d\n", error); 314 return; 315 } 316 317 error = bus_dmamem_map(sc->sc_dmat, 318 &schp->sch_prb_seg, schp->sch_prb_nseg, 319 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 320 if (error) { 321 aprint_error_dev(sc->sc_atac.atac_dev, 322 "unable to map PRB table memory, " 323 "error=%d\n", error); 324 bus_dmamem_free(sc->sc_dmat, 325 &schp->sch_prb_seg, schp->sch_prb_nseg); 326 return; 327 } 328 329 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 330 BUS_DMA_NOWAIT, &schp->sch_prbd); 331 if (error) { 332 aprint_error_dev(sc->sc_atac.atac_dev, 333 "unable to create PRB table map, " 334 "error=%d\n", error); 335 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 336 bus_dmamem_free(sc->sc_dmat, 337 &schp->sch_prb_seg, schp->sch_prb_nseg); 338 return; 339 } 340 341 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 342 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 343 if (error) { 344 aprint_error_dev(sc->sc_atac.atac_dev, 345 "unable to load PRB table map, " 346 "error=%d\n", error); 347 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 348 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 349 bus_dmamem_free(sc->sc_dmat, 350 &schp->sch_prb_seg, schp->sch_prb_nseg); 351 return; 352 } 353 354 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 355 schp->sch_prb[j] = (struct siisata_prb *) 356 ((char *)prbp + SIISATA_CMD_SIZE * j); 357 schp->sch_bus_prb[j] = 358 schp->sch_prbd->dm_segs[0].ds_addr + 359 SIISATA_CMD_SIZE * j; 360 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 361 SIISATA_NSGE, MAXPHYS, 0, 362 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 363 &schp->sch_datad[j]); 364 if (error) { 365 aprint_error_dev(sc->sc_atac.atac_dev, 366 "couldn't create xfer DMA map, error=%d\n", 367 error); 368 return; 369 } 370 } 371 372 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 373 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 374 aprint_error_dev(sc->sc_atac.atac_dev, 375 "couldn't map port %d SStatus regs\n", 376 chp->ch_channel); 377 return; 378 } 379 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 380 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 381 aprint_error_dev(sc->sc_atac.atac_dev, 382 "couldn't map port %d SControl regs\n", 383 chp->ch_channel); 384 return; 385 } 386 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 387 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 388 aprint_error_dev(sc->sc_atac.atac_dev, 389 "couldn't map port %d SError regs\n", 390 chp->ch_channel); 391 return; 392 } 393 394 siisata_init_port(sc, port); 395 396 ata_channel_attach(chp); 397 398 return; 399 } 400 401 int 402 siisata_detach(struct siisata_softc *sc, int flags) 403 { 404 struct atac_softc *atac = &sc->sc_atac; 405 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 406 struct siisata_channel *schp; 407 struct ata_channel *chp; 408 int i, j, error; 409 410 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 411 schp = &sc->sc_channels[i]; 412 chp = sc->sc_chanarray[i]; 413 414 if (chp->atabus == NULL) 415 continue; 416 if ((error = config_detach(chp->atabus, flags)) != 0) 417 return error; 418 419 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 420 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 421 422 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 423 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 424 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 425 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 426 bus_dmamem_free(sc->sc_dmat, 427 &schp->sch_prb_seg, schp->sch_prb_nseg); 428 429 free(chp->ch_queue, M_DEVBUF); 430 chp->atabus = NULL; 431 432 ata_channel_detach(chp); 433 } 434 435 if (adapt->adapt_refcnt != 0) 436 return EBUSY; 437 438 /* leave the chip in reset */ 439 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 440 441 return 0; 442 } 443 444 void 445 siisata_resume(struct siisata_softc *sc) 446 { 447 int i; 448 449 /* come out of reset state */ 450 GRWRITE(sc, GR_GC, 0); 451 452 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 453 siisata_init_port(sc, i); 454 } 455 456 } 457 458 int 459 siisata_intr(void *v) 460 { 461 struct siisata_softc *sc = v; 462 uint32_t is; 463 int i, r = 0; 464 while ((is = GRREAD(sc, GR_GIS))) { 465 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 466 SIISATANAME(sc), __func__, is), DEBUG_INTR); 467 r = 1; 468 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 469 if (is & GR_GIS_PXIS(i)) 470 siisata_intr_port(&sc->sc_channels[i]); 471 } 472 return r; 473 } 474 475 static void 476 siisata_intr_port(struct siisata_channel *schp) 477 { 478 struct siisata_softc *sc = 479 (struct siisata_softc *)schp->ata_channel.ch_atac; 480 struct ata_channel *chp = &schp->ata_channel; 481 struct ata_xfer *xfer = NULL; 482 uint32_t pss, pis, tfd = 0; 483 bool recover = false; 484 485 /* get slot status, clearing completion interrupt */ 486 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 487 488 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x ", 489 SIISATANAME(sc), __func__, chp->ch_channel, pss), 490 DEBUG_INTR); 491 492 if (__predict_true((pss & PR_PSS_ATTENTION) == 0)) { 493 SIISATA_DEBUG_PRINT(("no attention"), DEBUG_INTR); 494 goto process; 495 } 496 497 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 498 499 SIISATA_DEBUG_PRINT(("pis 0x%x\n", pss), DEBUG_INTR); 500 501 if (pis & PR_PIS_CMDERRR) { 502 uint32_t ec; 503 504 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 505 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 506 507 /* emulate a CRC error by default */ 508 tfd = ATACH_ERR_ST(WDCE_CRC, WDCS_ERR); 509 510 if (ec <= PR_PCE_DATAFISERROR) { 511 if (ec == PR_PCE_DEVICEERROR 512 && (chp->ch_flags & ATACH_NCQ) == 0) { 513 xfer = ata_queue_get_active_xfer(chp); 514 515 /* read in specific information about error */ 516 uint32_t prbfis = bus_space_read_stream_4( 517 sc->sc_prt, sc->sc_prh, 518 PRSX(chp->ch_channel, xfer->c_slot, 519 PRSO_FIS)); 520 521 /* get status and error */ 522 int ntfd = satafis_rdh_parse(chp, 523 (uint8_t *)&prbfis); 524 525 if (ATACH_ST(ntfd) & WDCS_ERR) 526 tfd = ntfd; 527 } 528 529 /* 530 * We don't expect the recovery to trigger error, 531 * but handle this just in case. 532 */ 533 if (!schp->sch_recovering) 534 recover = true; 535 else { 536 aprint_error_dev(sc->sc_atac.atac_dev, 537 "error ec %x while recovering\n", ec); 538 539 /* Command will be marked as errored out */ 540 pss = 0; 541 } 542 } else { 543 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 544 " on channel %d (ctx 0x%x), resetting\n", 545 ec, chp->ch_channel, 546 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 547 548 /* okay, we have a "Fatal Error" */ 549 siisata_device_reset(chp); 550 } 551 } 552 553 /* clear some (ok, all) ints */ 554 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 555 556 if (__predict_false(recover)) 557 ata_channel_freeze(chp); 558 559 process: 560 if (xfer != NULL) { 561 xfer->c_intr(chp, xfer, tfd); 562 } else { 563 /* 564 * For NCQ, HBA halts processing when error is notified, 565 * and any further D2H FISes are ignored until the error 566 * condition is cleared. Hence if a command is inactive, 567 * it means it actually already finished successfully. 568 * Note: active slots can change as c_intr() callback 569 * can activate another command(s), so must only process 570 * commands active before we start processing. 571 */ 572 uint32_t aslots = schp->sch_active_slots; 573 574 for (int slot=0; slot < SIISATA_MAX_SLOTS; slot++) { 575 if ((aslots & __BIT(slot)) != 0 && 576 (pss & PR_PXSS(slot)) == 0) { 577 xfer = ata_queue_hwslot_to_xfer(chp, slot); 578 xfer->c_intr(chp, xfer, 0); 579 } 580 } 581 } 582 583 if (__predict_false(recover)) { 584 ata_channel_thaw(chp); 585 siisata_channel_recover(chp, tfd); 586 } 587 } 588 589 static void 590 siisata_hold(struct siisata_channel *schp) 591 { 592 schp->sch_hold_slots |= schp->sch_active_slots; 593 schp->sch_active_slots = 0; 594 } 595 596 static void 597 siisata_unhold(struct siisata_channel *schp) 598 { 599 schp->sch_active_slots = schp->sch_hold_slots; 600 schp->sch_hold_slots = 0; 601 } 602 603 /* Recover channel after transfer aborted */ 604 void 605 siisata_channel_recover(struct ata_channel *chp, uint32_t tfd) 606 { 607 struct siisata_channel *schp = (struct siisata_channel *)chp; 608 struct siisata_softc *sc = 609 (struct siisata_softc *)schp->ata_channel.ch_atac; 610 struct ata_drive_datas *drvp; 611 int drive, error; 612 uint8_t eslot, slot, st, err; 613 struct ata_xfer *xfer; 614 615 KASSERT(!schp->sch_recovering); 616 617 schp->sch_recovering = true; 618 619 if (chp->ch_ndrives > PMP_PORT_CTL) { 620 /* Get PM port number for the device in error */ 621 int pcr = PRREAD(sc, PRX(chp->ch_channel, PRO_PCR)); 622 drive = PRO_PCR_PMP(pcr); 623 } else 624 drive = 0; 625 626 drvp = &chp->ch_drive[drive]; 627 628 /* 629 * If BSY or DRQ bits are set, must execute COMRESET to return 630 * device to idle state. Otherwise, commands can be reissued 631 * after reinitalization of port. After that, need to execute 632 * READ LOG EXT for NCQ to unblock device processing if COMRESET 633 * was not done. 634 */ 635 if ((ATACH_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) 636 goto reset; 637 638 KASSERT(drive >= 0); 639 siisata_reinit_port(chp, drive); 640 641 siisata_hold(schp); 642 643 /* 644 * When running NCQ commands, READ LOG EXT is necessary to clear the 645 * error condition and unblock the device. 646 */ 647 error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err); 648 649 siisata_unhold(schp); 650 651 switch (error) { 652 case 0: 653 /* Error out the particular NCQ xfer, then requeue the others */ 654 if ((schp->sch_active_slots & (1 << eslot)) != 0) { 655 xfer = ata_queue_hwslot_to_xfer(chp, eslot); 656 xfer->c_intr(chp, xfer, ATACH_ERR_ST(err, st)); 657 } 658 break; 659 660 case EOPNOTSUPP: 661 /* 662 * Non-NCQ command error, just find the slot and end it with 663 * the error. 664 */ 665 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 666 if ((schp->sch_active_slots & (1 << slot)) != 0) { 667 xfer = ata_queue_hwslot_to_xfer(chp, slot); 668 if (xfer->c_drive != drive) 669 continue; 670 671 xfer->c_intr(chp, xfer, tfd); 672 } 673 } 674 break; 675 676 case EAGAIN: 677 /* 678 * Failed to get resources to run the recovery command, must 679 * reset the drive. This will also kill all still outstanding 680 * transfers. 681 */ 682 reset: 683 siisata_device_reset(chp); 684 goto out; 685 /* NOTREACHED */ 686 687 default: 688 /* 689 * The command to get the slot failed. Kill outstanding 690 * commands for the same drive only. No need to reset 691 * the drive, it's unblocked nevertheless. 692 */ 693 break; 694 } 695 696 /* Requeue the non-errorred commands */ 697 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 698 if (((schp->sch_active_slots >> slot) & 1) == 0) 699 continue; 700 701 xfer = ata_queue_hwslot_to_xfer(chp, slot); 702 if (xfer->c_drive != drive) 703 continue; 704 705 xfer->c_kill_xfer(chp, xfer, 706 (error == 0) ? KILL_REQUEUE : KILL_RESET); 707 } 708 709 out: 710 /* Drive unblocked, back to normal operation */ 711 schp->sch_recovering = false; 712 atastart(chp); 713 } 714 715 void 716 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 717 { 718 struct ata_channel *chp = drvp->chnl_softc; 719 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 720 struct siisata_channel *schp = (struct siisata_channel *)chp; 721 struct siisata_prb *prb; 722 struct ata_xfer *xfer; 723 uint32_t pss, pis; 724 int i; 725 bool timed_out; 726 727 siisata_reinit_port(chp, drvp->drive); 728 729 xfer = ata_get_xfer_ext(chp, C_RECOVERY, 0); 730 731 prb = schp->sch_prb[xfer->c_slot]; 732 memset(prb, 0, SIISATA_CMD_SIZE); 733 prb->prb_control = 734 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 735 KASSERT(drvp->drive <= PMP_PORT_CTL); 736 prb->prb_fis[rhd_c] = drvp->drive; 737 738 siisata_disable_port_interrupt(chp); 739 740 siisata_activate_prb(schp, xfer->c_slot); 741 742 timed_out = true; 743 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 744 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 745 if ((pss & PR_PXSS(xfer->c_slot)) == 0) { 746 timed_out = false; 747 break; 748 } 749 if (pss & PR_PSS_ATTENTION) 750 break; 751 ata_delay(10, "siiprb", flags); 752 } 753 754 siisata_deactivate_prb(schp, xfer->c_slot); 755 756 if ((pss & PR_PSS_ATTENTION) != 0) { 757 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 758 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 759 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 760 761 if (slot != xfer->c_slot) 762 device_printf(sc->sc_atac.atac_dev, "%s port %d " 763 "drive %d slot %d c_slot %d", __func__, 764 chp->ch_channel, drvp->drive, slot, xfer->c_slot); 765 766 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 767 PR_PIS_CMDERRR); 768 } 769 770 siisata_enable_port_interrupt(chp); 771 772 if (timed_out) { 773 /* timeout */ 774 siisata_device_reset(chp); /* XXX is this right? */ 775 if (sigp) 776 *sigp = 0xffffffff; 777 } else { 778 /* read the signature out of the FIS */ 779 if (sigp) { 780 *sigp = 0; 781 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 782 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 783 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 784 PRSO_FIS+0xc)) & 0xff; 785 } 786 } 787 788 ata_free_xfer(chp, xfer); 789 790 return; 791 } 792 793 void 794 siisata_reset_channel(struct ata_channel *chp, int flags) 795 { 796 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 797 struct siisata_channel *schp = (struct siisata_channel *)chp; 798 799 SIISATA_DEBUG_PRINT(("%s: %s channel %d\n", SIISATANAME(sc), __func__, 800 chp->ch_channel), DEBUG_FUNCS); 801 802 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 803 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 804 aprint_error("%s port %d: reset failed\n", 805 SIISATANAME(sc), chp->ch_channel); 806 /* XXX and then ? */ 807 } 808 809 siisata_device_reset(chp); 810 811 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 812 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 813 814 return; 815 } 816 817 int 818 siisata_ata_addref(struct ata_drive_datas *drvp) 819 { 820 return 0; 821 } 822 823 void 824 siisata_ata_delref(struct ata_drive_datas *drvp) 825 { 826 return; 827 } 828 829 void 830 siisata_killpending(struct ata_drive_datas *drvp) 831 { 832 return; 833 } 834 835 void 836 siisata_probe_drive(struct ata_channel *chp) 837 { 838 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 839 struct siisata_channel *schp = (struct siisata_channel *)chp; 840 int i; 841 uint32_t sig; 842 struct siisata_prb *prb; 843 bool timed_out; 844 struct ata_xfer *xfer; 845 846 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 847 __func__, chp->ch_channel), DEBUG_FUNCS); 848 849 xfer = ata_get_xfer_ext(chp, 0, 0); 850 if (xfer == NULL) { 851 aprint_error_dev(sc->sc_atac.atac_dev, 852 "failed to get xfer port %d\n", 853 chp->ch_channel); 854 return; 855 } 856 857 /* 858 * disable port interrupt as we're polling for PHY up and 859 * prb completion 860 */ 861 siisata_disable_port_interrupt(chp); 862 863 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 864 schp->sch_sstatus, AT_WAIT)) { 865 case SStatus_DET_DEV: 866 /* clear any interrupts */ 867 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 868 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 869 870 /* wait for ready */ 871 timed_out = 1; 872 for (i = 0; i < ATA_DELAY / 10; i++) { 873 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & 874 PR_PS_PORT_READY) { 875 timed_out = 0; 876 break; 877 } 878 879 ata_delay(10, "siiprbrd", AT_WAIT); 880 } 881 if (timed_out) { 882 aprint_error_dev(sc->sc_atac.atac_dev, 883 "timed out waiting for PORT_READY on port %d, " 884 "reinitializing\n", chp->ch_channel); 885 siisata_reinit_port(chp, -1); 886 } 887 888 prb = schp->sch_prb[xfer->c_slot]; 889 memset(prb, 0, SIISATA_CMD_SIZE); 890 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 891 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 892 893 siisata_activate_prb(schp, xfer->c_slot); 894 895 timed_out = 1; 896 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 897 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 898 PR_PXSS(xfer->c_slot)) == 0) { 899 /* prb completed */ 900 timed_out = 0; 901 break; 902 } 903 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 904 PR_PIS_CMDERRR) { 905 /* we got an error; handle as timeout */ 906 break; 907 } 908 909 ata_delay(10, "siiprb", AT_WAIT); 910 } 911 912 siisata_deactivate_prb(schp, xfer->c_slot); 913 914 if (timed_out) { 915 aprint_error_dev(sc->sc_atac.atac_dev, 916 "SOFT_RESET failed on port %d (error %d PSS 0x%x PIS 0x%x), " 917 "resetting\n", chp->ch_channel, 918 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 919 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)), 920 PRREAD(sc, PRX(chp->ch_channel, PRO_PIS))); 921 siisata_reinit_port(chp, -1); 922 break; 923 } 924 925 /* read the signature out of the FIS */ 926 sig = 0; 927 sig |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 928 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 929 sig |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 930 PRSO_FIS+0xc)) & 0xff; 931 932 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 933 __func__, sig), DEBUG_PROBE); 934 935 if (sig == 0x96690101) 936 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 937 PR_PC_PMP_ENABLE); 938 sata_interpret_sig(chp, 0, sig); 939 break; 940 default: 941 break; 942 } 943 944 siisata_enable_port_interrupt(chp); 945 946 ata_free_xfer(chp, xfer); 947 948 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 949 __func__, chp->ch_channel), DEBUG_PROBE); 950 return; 951 } 952 953 void 954 siisata_setup_channel(struct ata_channel *chp) 955 { 956 return; 957 } 958 959 int 960 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 961 { 962 struct ata_channel *chp = drvp->chnl_softc; 963 struct ata_command *ata_c = &xfer->c_ata_c; 964 int ret; 965 int s; 966 967 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 968 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 969 DEBUG_FUNCS); 970 971 if (ata_c->flags & AT_POLL) 972 xfer->c_flags |= C_POLL; 973 if (ata_c->flags & AT_WAIT) 974 xfer->c_flags |= C_WAIT; 975 xfer->c_drive = drvp->drive; 976 xfer->c_databuf = ata_c->data; 977 xfer->c_bcount = ata_c->bcount; 978 xfer->c_start = siisata_cmd_start; 979 xfer->c_intr = siisata_cmd_complete; 980 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 981 s = splbio(); 982 ata_exec_xfer(chp, xfer); 983 #ifdef DIAGNOSTIC 984 if ((ata_c->flags & AT_POLL) != 0 && 985 (ata_c->flags & AT_DONE) == 0) 986 panic("%s: polled command not done", __func__); 987 #endif 988 if (ata_c->flags & AT_DONE) { 989 ret = ATACMD_COMPLETE; 990 } else { 991 if (ata_c->flags & AT_WAIT) { 992 while ((ata_c->flags & AT_DONE) == 0) { 993 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 994 SIISATANAME( 995 (struct siisata_softc *)chp->ch_atac), 996 __func__), DEBUG_FUNCS); 997 tsleep(ata_c, PRIBIO, "siicmd", 0); 998 } 999 ret = ATACMD_COMPLETE; 1000 } else { 1001 ret = ATACMD_QUEUED; 1002 } 1003 } 1004 splx(s); 1005 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 1006 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1007 DEBUG_FUNCS); 1008 return ret; 1009 } 1010 1011 void 1012 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1013 { 1014 struct siisata_channel *schp = (struct siisata_channel *)chp; 1015 struct ata_command *ata_c = &xfer->c_ata_c; 1016 struct siisata_prb *prb; 1017 int i; 1018 1019 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 1020 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1021 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 1022 DEBUG_FUNCS|DEBUG_XFERS); 1023 1024 prb = schp->sch_prb[xfer->c_slot]; 1025 memset(prb, 0, SIISATA_CMD_SIZE); 1026 1027 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 1028 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1029 prb->prb_fis[rhd_c] |= xfer->c_drive; 1030 1031 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 1032 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 1033 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 1034 } 1035 1036 if (siisata_dma_setup(chp, xfer->c_slot, 1037 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 1038 ata_c->bcount, 1039 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1040 ata_c->flags |= AT_DF; 1041 siisata_cmd_complete(chp, xfer, 0); 1042 return; 1043 } 1044 1045 if (xfer->c_flags & C_POLL) { 1046 /* polled command, disable interrupts */ 1047 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1048 siisata_disable_port_interrupt(chp); 1049 } 1050 1051 /* go for it */ 1052 siisata_activate_prb(schp, xfer->c_slot); 1053 1054 if ((ata_c->flags & AT_POLL) == 0) { 1055 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 1056 ata_timeout, xfer); 1057 goto out; 1058 } 1059 1060 /* 1061 * polled command 1062 */ 1063 for (i = 0; i < ata_c->timeout * 10; i++) { 1064 if (ata_c->flags & AT_DONE) 1065 break; 1066 siisata_intr_port(schp); 1067 DELAY(100); 1068 } 1069 1070 if ((ata_c->flags & AT_DONE) == 0) { 1071 ata_timeout(xfer); 1072 } 1073 1074 /* reenable interrupts */ 1075 siisata_enable_port_interrupt(chp); 1076 out: 1077 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1078 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1079 DEBUG_FUNCS); 1080 return; 1081 } 1082 1083 void 1084 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1085 int reason) 1086 { 1087 struct ata_command *ata_c = &xfer->c_ata_c; 1088 struct siisata_channel *schp = (struct siisata_channel *)chp; 1089 bool deactivate = true; 1090 1091 switch (reason) { 1092 case KILL_GONE_INACTIVE: 1093 deactivate = false; 1094 /* FALLTHROUGH */ 1095 case KILL_GONE: 1096 ata_c->flags |= AT_GONE; 1097 break; 1098 case KILL_RESET: 1099 ata_c->flags |= AT_RESET; 1100 break; 1101 case KILL_REQUEUE: 1102 panic("%s: not supposed to be requeued\n", __func__); 1103 break; 1104 default: 1105 panic("%s: port %d: unknown reason %d", 1106 __func__, chp->ch_channel, reason); 1107 } 1108 1109 if (deactivate) { 1110 siisata_deactivate_prb(schp, xfer->c_slot); 1111 ata_deactivate_xfer(chp, xfer); 1112 } 1113 1114 siisata_cmd_done_end(chp, xfer); 1115 } 1116 1117 int 1118 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1119 { 1120 struct siisata_channel *schp = (struct siisata_channel *)chp; 1121 struct ata_command *ata_c = &xfer->c_ata_c; 1122 #ifdef SIISATA_DEBUG 1123 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1124 #endif 1125 1126 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1127 SIISATANAME(sc), __func__, 1128 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1129 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1130 DEBUG_FUNCS|DEBUG_XFERS); 1131 1132 if (ata_waitdrain_xfer_check(chp, xfer)) 1133 return 0; 1134 1135 siisata_deactivate_prb(schp, xfer->c_slot); 1136 ata_deactivate_xfer(chp, xfer); 1137 1138 if (xfer->c_flags & C_TIMEOU) 1139 ata_c->flags |= AT_TIMEOU; 1140 1141 if (ATACH_ST(tfd) & WDCS_BSY) { 1142 ata_c->flags |= AT_TIMEOU; 1143 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1144 ata_c->r_error = ATACH_ERR(tfd); 1145 ata_c->flags |= AT_ERROR; 1146 } 1147 1148 siisata_cmd_done(chp, xfer, tfd); 1149 1150 return 0; 1151 } 1152 1153 void 1154 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1155 { 1156 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1157 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1158 struct siisata_channel *schp = (struct siisata_channel *)chp; 1159 struct ata_command *ata_c = &xfer->c_ata_c; 1160 uint16_t *idwordbuf; 1161 int i; 1162 1163 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1164 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1165 1166 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1167 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1168 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1169 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1170 BUS_DMASYNC_POSTWRITE); 1171 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1172 } 1173 1174 if (ata_c->flags & AT_READREG) { 1175 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1176 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1177 fis, __arraycount(fis)); 1178 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1179 } 1180 1181 /* correct the endianess of IDENTIFY data */ 1182 if (ata_c->r_command == WDCC_IDENTIFY || 1183 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1184 idwordbuf = xfer->c_databuf; 1185 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1186 idwordbuf[i] = le16toh(idwordbuf[i]); 1187 } 1188 } 1189 1190 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1191 ata_c->flags |= AT_XFDONE; 1192 1193 siisata_cmd_done_end(chp, xfer); 1194 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1195 atastart(chp); 1196 } 1197 1198 static void 1199 siisata_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1200 { 1201 struct ata_command *ata_c = &xfer->c_ata_c; 1202 1203 ata_c->flags |= AT_DONE; 1204 1205 if (ata_c->flags & AT_WAIT) 1206 wakeup(ata_c); 1207 return; 1208 } 1209 1210 int 1211 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1212 { 1213 struct ata_channel *chp = drvp->chnl_softc; 1214 struct ata_bio *ata_bio = &xfer->c_bio; 1215 1216 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1217 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1218 DEBUG_FUNCS); 1219 1220 if (xfer == NULL) 1221 return ATACMD_TRY_AGAIN; 1222 if (ata_bio->flags & ATA_POLL) 1223 xfer->c_flags |= C_POLL; 1224 xfer->c_drive = drvp->drive; 1225 xfer->c_databuf = ata_bio->databuf; 1226 xfer->c_bcount = ata_bio->bcount; 1227 xfer->c_start = siisata_bio_start; 1228 xfer->c_intr = siisata_bio_complete; 1229 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1230 ata_exec_xfer(chp, xfer); 1231 return (ata_bio->flags & ATA_ITSDONE) ? 1232 ATACMD_COMPLETE : ATACMD_QUEUED; 1233 } 1234 1235 void 1236 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1237 { 1238 struct siisata_channel *schp = (struct siisata_channel *)chp; 1239 struct siisata_prb *prb; 1240 struct ata_bio *ata_bio = &xfer->c_bio; 1241 int i; 1242 1243 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1244 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1245 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1246 1247 prb = schp->sch_prb[xfer->c_slot]; 1248 memset(prb, 0, SIISATA_CMD_SIZE); 1249 1250 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1251 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1252 prb->prb_fis[rhd_c] |= xfer->c_drive; 1253 1254 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1255 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1256 ata_bio->error = ERR_DMA; 1257 ata_bio->r_error = 0; 1258 siisata_bio_complete(chp, xfer, 0); 1259 return; 1260 } 1261 1262 if (xfer->c_flags & C_POLL) { 1263 /* polled command, disable interrupts */ 1264 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1265 siisata_disable_port_interrupt(chp); 1266 } 1267 1268 siisata_activate_prb(schp, xfer->c_slot); 1269 1270 if ((ata_bio->flags & ATA_POLL) == 0) { 1271 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1272 ata_timeout, xfer); 1273 goto out; 1274 } 1275 1276 /* 1277 * polled command 1278 */ 1279 for (i = 0; i < ATA_DELAY * 10; i++) { 1280 if (ata_bio->flags & ATA_ITSDONE) 1281 break; 1282 siisata_intr_port(schp); 1283 DELAY(100); 1284 } 1285 1286 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1287 ata_timeout(xfer); 1288 } 1289 1290 siisata_enable_port_interrupt(chp); 1291 out: 1292 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1293 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1294 DEBUG_FUNCS); 1295 return; 1296 } 1297 1298 void 1299 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1300 int reason) 1301 { 1302 struct siisata_channel *schp = (struct siisata_channel *)chp; 1303 struct ata_bio *ata_bio = &xfer->c_bio; 1304 int drive = xfer->c_drive; 1305 bool deactivate = true; 1306 1307 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1308 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1309 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1310 1311 ata_bio->flags |= ATA_ITSDONE; 1312 switch (reason) { 1313 case KILL_GONE_INACTIVE: 1314 deactivate = false; 1315 /* FALLTHROUGH */ 1316 case KILL_GONE: 1317 ata_bio->error = ERR_NODEV; 1318 break; 1319 case KILL_RESET: 1320 ata_bio->error = ERR_RESET; 1321 break; 1322 case KILL_REQUEUE: 1323 ata_bio->error = REQUEUE; 1324 break; 1325 default: 1326 panic("%s: port %d: unknown reason %d", 1327 __func__, chp->ch_channel, reason); 1328 } 1329 ata_bio->r_error = WDCE_ABRT; 1330 1331 if (deactivate) { 1332 siisata_deactivate_prb(schp, xfer->c_slot); 1333 ata_deactivate_xfer(chp, xfer); 1334 } 1335 1336 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1337 } 1338 1339 int 1340 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1341 { 1342 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1343 struct siisata_channel *schp = (struct siisata_channel *)chp; 1344 struct ata_bio *ata_bio = &xfer->c_bio; 1345 int drive = xfer->c_drive; 1346 1347 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d tfd %x\n", 1348 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1349 chp->ch_channel, xfer->c_slot, xfer->c_drive, tfd), DEBUG_FUNCS); 1350 1351 if (ata_waitdrain_xfer_check(chp, xfer)) 1352 return 0; 1353 1354 siisata_deactivate_prb(schp, xfer->c_slot); 1355 ata_deactivate_xfer(chp, xfer); 1356 1357 if (xfer->c_flags & C_TIMEOU) { 1358 ata_bio->error = TIMEOUT; 1359 } 1360 1361 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1362 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1363 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1364 BUS_DMASYNC_POSTWRITE); 1365 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1366 1367 ata_bio->flags |= ATA_ITSDONE; 1368 if (ATACH_ST(tfd) & WDCS_DWF) { 1369 ata_bio->error = ERR_DF; 1370 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1371 ata_bio->error = ERROR; 1372 ata_bio->r_error = ATACH_ERR(tfd); 1373 } else if (ATACH_ST(tfd) & WDCS_CORR) 1374 ata_bio->flags |= ATA_CORR; 1375 1376 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1377 ata_bio->bcount), DEBUG_XFERS); 1378 if (ata_bio->error == NOERROR) { 1379 if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ) 1380 ata_bio->bcount -= 1381 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1382 else 1383 ata_bio->bcount = 0; 1384 } 1385 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1386 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1387 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1388 atastart(chp); 1389 return 0; 1390 } 1391 1392 static int 1393 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1394 size_t count, int op) 1395 { 1396 1397 int error, seg; 1398 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1399 struct siisata_channel *schp = (struct siisata_channel *)chp; 1400 1401 struct siisata_prb *prbp; 1402 1403 prbp = schp->sch_prb[slot]; 1404 1405 if (data == NULL) { 1406 goto end; 1407 } 1408 1409 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1410 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1411 if (error) { 1412 aprint_error("%s port %d: " 1413 "failed to load xfer in slot %d: error %d\n", 1414 SIISATANAME(sc), chp->ch_channel, slot, error); 1415 return error; 1416 } 1417 1418 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1419 schp->sch_datad[slot]->dm_mapsize, 1420 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1421 1422 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1423 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1424 DEBUG_FUNCS | DEBUG_DEBUG); 1425 1426 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1427 prbp->prb_sge[seg].sge_da = 1428 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1429 prbp->prb_sge[seg].sge_dc = 1430 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1431 prbp->prb_sge[seg].sge_flags = htole32(0); 1432 } 1433 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1434 end: 1435 return 0; 1436 } 1437 1438 static void 1439 siisata_activate_prb(struct siisata_channel *schp, int slot) 1440 { 1441 struct siisata_softc *sc; 1442 bus_size_t offset; 1443 uint64_t pprb; 1444 1445 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1446 1447 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) == 0, 1448 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1449 1450 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1451 /* keep track of what's going on */ 1452 schp->sch_active_slots |= __BIT(slot); 1453 1454 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1455 1456 pprb = schp->sch_bus_prb[slot]; 1457 1458 PRWRITE(sc, offset + 0, pprb >> 0); 1459 PRWRITE(sc, offset + 4, pprb >> 32); 1460 } 1461 1462 static void 1463 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1464 { 1465 struct siisata_softc *sc; 1466 1467 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1468 1469 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1470 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1471 slot); 1472 1473 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1474 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1475 } 1476 1477 static void 1478 siisata_reinit_port(struct ata_channel *chp, int drive) 1479 { 1480 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1481 int ps; 1482 1483 1484 if (chp->ch_ndrives > 1) { 1485 /* 1486 * Proper recovery would SET this bit, which makes it 1487 * not possible to submit new commands and resume execution 1488 * on non-errored drives, then wait for those commands, 1489 * to finish, and only then clear the bit and reset the state. 1490 * For now this is okay, since we never queue commands for 1491 * more than one drive. 1492 * XXX FIS-based switching 1493 */ 1494 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_RESUME); 1495 1496 for (int i = 0; i < chp->ch_ndrives; i++) { 1497 if (drive >= 0 && i != drive) 1498 continue; 1499 1500 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPSTS(i)), 0); 1501 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPQACT(i)), 0); 1502 } 1503 } 1504 1505 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1506 for (int i = 0; i < ATA_DELAY * 100; i++) { 1507 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1508 if ((ps & PR_PS_PORT_READY) != 0) 1509 break; 1510 1511 DELAY(10); 1512 } 1513 if ((ps & PR_PS_PORT_READY) == 0) { 1514 printf("%s: timeout waiting for port to be ready\n", __func__); 1515 siisata_reset_channel(chp, AT_POLL); 1516 } 1517 1518 if (chp->ch_ndrives > 1) 1519 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1520 } 1521 1522 static void 1523 siisata_device_reset(struct ata_channel *chp) 1524 { 1525 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1526 int ps; 1527 1528 /* 1529 * This is always called after siisata_reinit_port(), so don't 1530 * need to deal with RESUME and clearing device error state. 1531 */ 1532 1533 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1534 1535 for (int i = 0; i < ATA_DELAY * 100; i++) { 1536 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1537 if ((ps & PR_PS_PORT_READY) != 0) 1538 break; 1539 1540 DELAY(10); 1541 } 1542 if ((ps & PR_PS_PORT_READY) == 0) { 1543 printf("%s: timeout waiting for port to be ready\n", __func__); 1544 siisata_reset_channel(chp, AT_POLL); 1545 } 1546 1547 ata_kill_active(chp, KILL_RESET, 0); 1548 } 1549 1550 1551 #if NATAPIBUS > 0 1552 void 1553 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1554 { 1555 struct ata_channel *chp = ata_sc->sc_chan; 1556 struct atac_softc *atac = chp->ch_atac; 1557 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1558 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1559 1560 /* 1561 * Fill in the scsipi_adapter. 1562 */ 1563 adapt->adapt_dev = atac->atac_dev; 1564 adapt->adapt_nchannels = atac->atac_nchannels; 1565 adapt->adapt_request = siisata_atapi_scsipi_request; 1566 adapt->adapt_minphys = siisata_atapi_minphys; 1567 atac->atac_atapi_adapter.atapi_probe_device = 1568 siisata_atapi_probe_device; 1569 1570 /* 1571 * Fill in the scsipi_channel. 1572 */ 1573 memset(chan, 0, sizeof(*chan)); 1574 chan->chan_adapter = adapt; 1575 chan->chan_bustype = &siisata_atapi_bustype; 1576 chan->chan_channel = chp->ch_channel; 1577 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1578 chan->chan_openings = 1; 1579 chan->chan_max_periph = 1; 1580 chan->chan_ntargets = 1; 1581 chan->chan_nluns = 1; 1582 1583 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1584 atapiprint); 1585 } 1586 1587 void 1588 siisata_atapi_minphys(struct buf *bp) 1589 { 1590 if (bp->b_bcount > MAXPHYS) 1591 bp->b_bcount = MAXPHYS; 1592 minphys(bp); 1593 } 1594 1595 /* 1596 * Kill off all pending xfers for a periph. 1597 * 1598 * Must be called at splbio(). 1599 */ 1600 void 1601 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1602 { 1603 struct atac_softc *atac = 1604 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1605 struct ata_channel *chp = 1606 atac->atac_channels[periph->periph_channel->chan_channel]; 1607 1608 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1609 } 1610 1611 void 1612 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1613 int reason) 1614 { 1615 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1616 struct siisata_channel *schp = (struct siisata_channel *)chp; 1617 bool deactivate = true; 1618 1619 /* remove this command from xfer queue */ 1620 switch (reason) { 1621 case KILL_GONE_INACTIVE: 1622 deactivate = false; 1623 /* FALLTHROUGH */ 1624 case KILL_GONE: 1625 sc_xfer->error = XS_DRIVER_STUFFUP; 1626 break; 1627 case KILL_RESET: 1628 sc_xfer->error = XS_RESET; 1629 break; 1630 case KILL_REQUEUE: 1631 sc_xfer->error = XS_REQUEUE; 1632 break; 1633 default: 1634 panic("%s: port %d: unknown reason %d", 1635 __func__, chp->ch_channel, reason); 1636 } 1637 1638 if (deactivate) { 1639 siisata_deactivate_prb(schp, xfer->c_slot); 1640 ata_deactivate_xfer(chp, xfer); 1641 } 1642 1643 ata_free_xfer(chp, xfer); 1644 scsipi_done(sc_xfer); 1645 } 1646 1647 void 1648 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1649 { 1650 struct scsipi_channel *chan = sc->sc_channel; 1651 struct scsipi_periph *periph; 1652 struct ataparams ids; 1653 struct ataparams *id = &ids; 1654 struct siisata_softc *siic = 1655 device_private(chan->chan_adapter->adapt_dev); 1656 struct atac_softc *atac = &siic->sc_atac; 1657 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1658 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1659 struct scsipibus_attach_args sa; 1660 char serial_number[21], model[41], firmware_revision[9]; 1661 int s; 1662 1663 /* skip if already attached */ 1664 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1665 return; 1666 1667 /* if no ATAPI device detected at attach time, skip */ 1668 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1669 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1670 target), DEBUG_PROBE); 1671 return; 1672 } 1673 1674 /* Some ATAPI devices need a bit more time after software reset. */ 1675 DELAY(5000); 1676 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1677 #ifdef ATAPI_DEBUG_PROBE 1678 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1679 device_xname(sc->sc_dev), target, 1680 id->atap_config & ATAPI_CFG_CMD_MASK, 1681 id->atap_config & ATAPI_CFG_DRQ_MASK); 1682 #endif 1683 periph = scsipi_alloc_periph(M_NOWAIT); 1684 if (periph == NULL) { 1685 aprint_error_dev(sc->sc_dev, 1686 "%s: unable to allocate periph for " 1687 "channel %d drive %d\n", __func__, 1688 chp->ch_channel, target); 1689 return; 1690 } 1691 periph->periph_dev = NULL; 1692 periph->periph_channel = chan; 1693 periph->periph_switch = &atapi_probe_periphsw; 1694 periph->periph_target = target; 1695 periph->periph_lun = 0; 1696 periph->periph_quirks = PQUIRK_ONLYBIG; 1697 1698 #ifdef SCSIPI_DEBUG 1699 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1700 SCSIPI_DEBUG_TARGET == target) 1701 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1702 #endif 1703 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1704 if (id->atap_config & ATAPI_CFG_REMOV) 1705 periph->periph_flags |= PERIPH_REMOVABLE; 1706 sa.sa_periph = periph; 1707 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1708 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1709 T_REMOV : T_FIXED; 1710 strnvisx(model, sizeof(model), id->atap_model, 40, 1711 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1712 strnvisx(serial_number, sizeof(serial_number), 1713 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1714 strnvisx(firmware_revision, sizeof(firmware_revision), 1715 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1716 sa.sa_inqbuf.vendor = model; 1717 sa.sa_inqbuf.product = serial_number; 1718 sa.sa_inqbuf.revision = firmware_revision; 1719 1720 /* 1721 * Determine the operating mode capabilities of the device. 1722 */ 1723 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1724 == ATAPI_CFG_CMD_16) { 1725 periph->periph_cap |= PERIPH_CAP_CMD16; 1726 1727 /* configure port for packet length */ 1728 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1729 PR_PC_PACKET_LENGTH); 1730 } else { 1731 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1732 PR_PC_PACKET_LENGTH); 1733 } 1734 1735 /* XXX This is gross. */ 1736 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1737 1738 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1739 1740 if (drvp->drv_softc) 1741 ata_probe_caps(drvp); 1742 else { 1743 s = splbio(); 1744 drvp->drive_type &= ATA_DRIVET_NONE; 1745 splx(s); 1746 } 1747 } else { 1748 s = splbio(); 1749 drvp->drive_type &= ATA_DRIVET_NONE; 1750 splx(s); 1751 } 1752 } 1753 1754 void 1755 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1756 scsipi_adapter_req_t req, void *arg) 1757 { 1758 struct scsipi_adapter *adapt = chan->chan_adapter; 1759 struct scsipi_periph *periph; 1760 struct scsipi_xfer *sc_xfer; 1761 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1762 struct atac_softc *atac = &sc->sc_atac; 1763 struct ata_xfer *xfer; 1764 int channel = chan->chan_channel; 1765 int drive, s; 1766 1767 switch (req) { 1768 case ADAPTER_REQ_RUN_XFER: 1769 sc_xfer = arg; 1770 periph = sc_xfer->xs_periph; 1771 drive = periph->periph_target; 1772 1773 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1774 device_xname(atac->atac_dev), channel, drive), 1775 DEBUG_XFERS); 1776 1777 if (!device_is_active(atac->atac_dev)) { 1778 sc_xfer->error = XS_DRIVER_STUFFUP; 1779 scsipi_done(sc_xfer); 1780 return; 1781 } 1782 xfer = ata_get_xfer_ext(atac->atac_channels[channel], 0, 0); 1783 if (xfer == NULL) { 1784 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1785 scsipi_done(sc_xfer); 1786 return; 1787 } 1788 1789 if (sc_xfer->xs_control & XS_CTL_POLL) 1790 xfer->c_flags |= C_POLL; 1791 xfer->c_drive = drive; 1792 xfer->c_flags |= C_ATAPI; 1793 xfer->c_scsipi = sc_xfer; 1794 xfer->c_databuf = sc_xfer->data; 1795 xfer->c_bcount = sc_xfer->datalen; 1796 xfer->c_start = siisata_atapi_start; 1797 xfer->c_intr = siisata_atapi_complete; 1798 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1799 xfer->c_dscpoll = 0; 1800 s = splbio(); 1801 ata_exec_xfer(atac->atac_channels[channel], xfer); 1802 #ifdef DIAGNOSTIC 1803 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1804 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1805 panic("%s: polled command not done", __func__); 1806 #endif 1807 splx(s); 1808 return; 1809 1810 default: 1811 /* Not supported, nothing to do. */ 1812 ; 1813 } 1814 } 1815 1816 void 1817 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1818 { 1819 struct siisata_channel *schp = (struct siisata_channel *)chp; 1820 struct siisata_prb *prbp; 1821 1822 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1823 int i; 1824 1825 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1826 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1827 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1828 DEBUG_XFERS); 1829 1830 prbp = schp->sch_prb[xfer->c_slot]; 1831 memset(prbp, 0, SIISATA_CMD_SIZE); 1832 1833 /* fill in direction for ATAPI command */ 1834 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1835 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1836 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1837 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1838 1839 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1840 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1841 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1842 1843 /* copy over ATAPI command */ 1844 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1845 1846 if (siisata_dma_setup(chp, xfer->c_slot, 1847 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1848 xfer->c_databuf : NULL, 1849 xfer->c_bcount, 1850 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1851 BUS_DMA_READ : BUS_DMA_WRITE) 1852 ) 1853 panic("%s", __func__); 1854 1855 if (xfer->c_flags & C_POLL) { 1856 /* polled command, disable interrupts */ 1857 prbp->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1858 siisata_disable_port_interrupt(chp); 1859 } 1860 1861 siisata_activate_prb(schp, xfer->c_slot); 1862 1863 if ((xfer->c_flags & C_POLL) == 0) { 1864 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1865 ata_timeout, xfer); 1866 goto out; 1867 } 1868 1869 /* 1870 * polled command 1871 */ 1872 for (i = 0; i < ATA_DELAY * 10; i++) { 1873 if (sc_xfer->xs_status & XS_STS_DONE) 1874 break; 1875 siisata_intr_port(schp); 1876 DELAY(100); 1877 } 1878 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1879 ata_timeout(xfer); 1880 } 1881 /* reenable interrupts */ 1882 siisata_enable_port_interrupt(chp); 1883 out: 1884 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1885 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1886 DEBUG_FUNCS); 1887 return; 1888 } 1889 1890 int 1891 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1892 int tfd) 1893 { 1894 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1895 struct siisata_channel *schp = (struct siisata_channel *)chp; 1896 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1897 1898 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1899 DEBUG_INTR); 1900 1901 if (ata_waitdrain_xfer_check(chp, xfer)) 1902 return 0; 1903 1904 /* this command is not active any more */ 1905 siisata_deactivate_prb(schp, xfer->c_slot); 1906 ata_deactivate_xfer(chp, xfer); 1907 1908 if (xfer->c_flags & C_TIMEOU) { 1909 sc_xfer->error = XS_TIMEOUT; 1910 } else if ((ATACH_ST(tfd) & WDCS_ERR) == 0) { 1911 sc_xfer->error = XS_NOERROR; 1912 } 1913 1914 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1915 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1916 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1917 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1918 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1919 1920 sc_xfer->resid = sc_xfer->datalen; 1921 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1922 PRSO_RTC)); 1923 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1924 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1925 if ((ATACH_ST(tfd) & WDCS_ERR) && 1926 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1927 sc_xfer->resid == sc_xfer->datalen)) { 1928 sc_xfer->error = XS_SHORTSENSE; 1929 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1930 if ((sc_xfer->xs_periph->periph_quirks & 1931 PQUIRK_NOSENSE) == 0) { 1932 /* request sense */ 1933 sc_xfer->error = XS_BUSY; 1934 sc_xfer->status = SCSI_CHECK; 1935 } 1936 } 1937 ata_free_xfer(chp, xfer); 1938 scsipi_done(sc_xfer); 1939 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1940 atastart(chp); 1941 return 0; 1942 } 1943 1944 #endif /* NATAPIBUS */ 1945
Indexes created Mon Oct 20 11:09:49 GMT 2025