siisata.c revision 1.30.4.38
1 /* $NetBSD: siisata.c,v 1.30.4.38 2017/09/19 21:06:25 jdolecek Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.30.4.38 2017/09/19 21:06:25 jdolecek Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define WDC_RESET_WAIT 31000 /* 31s for drive reset */ 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #if _BYTE_ORDER == _LITTLE_ENDIAN 116 #define bus_space_read_stream_4 bus_space_read_4 117 #define bus_space_read_region_stream_4 bus_space_read_region_4 118 #else 119 static inline uint32_t 120 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 121 { 122 return htole32(bus_space_read_4(t, h, o)); 123 } 124 125 static inline void 126 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 127 bus_size_t o, uint32_t *p, bus_size_t c) 128 { 129 bus_space_read_region_4(t, h, o, p, c); 130 for (bus_size_t i = 0; i < c; i++) { 131 p[i] = htole32(p[i]); 132 } 133 } 134 #endif 135 #endif 136 137 static void siisata_attach_port(struct siisata_softc *, int); 138 static void siisata_intr_port(struct siisata_channel *); 139 140 void siisata_probe_drive(struct ata_channel *); 141 void siisata_setup_channel(struct ata_channel *); 142 143 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 144 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 145 void siisata_reset_channel(struct ata_channel *, int); 146 int siisata_ata_addref(struct ata_drive_datas *); 147 void siisata_ata_delref(struct ata_drive_datas *); 148 void siisata_killpending(struct ata_drive_datas *); 149 150 int siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 151 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_cmd_poll(struct ata_channel *, struct ata_xfer *); 153 void siisata_cmd_abort(struct ata_channel *, struct ata_xfer *); 154 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 155 static void siisata_cmd_done_end(struct ata_channel *, struct ata_xfer *); 156 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 158 int siisata_bio_start(struct ata_channel *, struct ata_xfer *); 159 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 160 void siisata_bio_poll(struct ata_channel *, struct ata_xfer *); 161 void siisata_bio_abort(struct ata_channel *, struct ata_xfer *); 162 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 163 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 164 165 static void siisata_reinit_port(struct ata_channel *, int); 166 static void siisata_device_reset(struct ata_channel *); 167 static void siisata_activate_prb(struct siisata_channel *, int); 168 static void siisata_deactivate_prb(struct siisata_channel *, int); 169 static int siisata_dma_setup(struct ata_channel *, int, void *, size_t, int); 170 void siisata_channel_recover(struct ata_channel *, uint32_t); 171 172 #if NATAPIBUS > 0 173 void siisata_atapibus_attach(struct atabus_softc *); 174 void siisata_atapi_probe_device(struct atapibus_softc *, int); 175 void siisata_atapi_minphys(struct buf *); 176 int siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 177 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 178 void siisata_atapi_poll(struct ata_channel *, struct ata_xfer *); 179 void siisata_atapi_abort(struct ata_channel *, struct ata_xfer *); 180 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 181 void siisata_atapi_scsipi_request(struct scsipi_channel *, 182 scsipi_adapter_req_t, void *); 183 void siisata_atapi_kill_pending(struct scsipi_periph *); 184 #endif /* NATAPIBUS */ 185 186 const struct ata_bustype siisata_ata_bustype = { 187 SCSIPI_BUSTYPE_ATA, 188 siisata_ata_bio, 189 siisata_reset_drive, 190 siisata_reset_channel, 191 siisata_exec_command, 192 ata_get_params, 193 siisata_ata_addref, 194 siisata_ata_delref, 195 siisata_killpending 196 }; 197 198 #if NATAPIBUS > 0 199 static const struct scsipi_bustype siisata_atapi_bustype = { 200 SCSIPI_BUSTYPE_ATAPI, 201 atapi_scsipi_cmd, 202 atapi_interpret_sense, 203 atapi_print_addr, 204 siisata_atapi_kill_pending, 205 NULL, 206 }; 207 #endif /* NATAPIBUS */ 208 209 210 void 211 siisata_attach(struct siisata_softc *sc) 212 { 213 int i; 214 215 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 216 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 217 218 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 219 sc->sc_atac.atac_pio_cap = 4; 220 sc->sc_atac.atac_dma_cap = 2; 221 sc->sc_atac.atac_udma_cap = 6; 222 sc->sc_atac.atac_channels = sc->sc_chanarray; 223 sc->sc_atac.atac_probe = siisata_probe_drive; 224 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 225 sc->sc_atac.atac_set_modes = siisata_setup_channel; 226 #if NATAPIBUS > 0 227 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 228 #endif 229 230 /* come out of reset state */ 231 GRWRITE(sc, GR_GC, 0); 232 233 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 234 siisata_attach_port(sc, i); 235 } 236 237 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 238 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 239 return; 240 } 241 242 static void 243 siisata_disable_port_interrupt(struct ata_channel *chp) 244 { 245 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 246 247 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 248 } 249 250 static void 251 siisata_enable_port_interrupt(struct ata_channel *chp) 252 { 253 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 254 255 /* clear any interrupts */ 256 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 257 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 258 /* and enable CmdErrr+CmdCmpl interrupting */ 259 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 260 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 261 } 262 263 static void 264 siisata_init_port(struct siisata_softc *sc, int port) 265 { 266 struct siisata_channel *schp; 267 struct ata_channel *chp; 268 269 schp = &sc->sc_channels[port]; 270 chp = (struct ata_channel *)schp; 271 272 /* 273 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 274 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 275 */ 276 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 277 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 278 /* initialize port */ 279 siisata_reinit_port(chp, -1); 280 /* enable CmdErrr+CmdCmpl interrupting */ 281 siisata_enable_port_interrupt(chp); 282 /* enable port interrupt */ 283 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 284 } 285 286 static void 287 siisata_attach_port(struct siisata_softc *sc, int port) 288 { 289 int j; 290 int dmasize; 291 int error; 292 void *prbp; 293 struct siisata_channel *schp; 294 struct ata_channel *chp; 295 296 schp = &sc->sc_channels[port]; 297 chp = (struct ata_channel *)schp; 298 sc->sc_chanarray[port] = chp; 299 chp->ch_channel = port; 300 chp->ch_atac = &sc->sc_atac; 301 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 302 if (chp->ch_queue == NULL) { 303 aprint_error_dev(sc->sc_atac.atac_dev, 304 "port %d: can't allocate memory " 305 "for command queue\n", chp->ch_channel); 306 return; 307 } 308 309 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 310 311 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 312 __func__, dmasize), DEBUG_FUNCS); 313 314 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 315 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 316 if (error) { 317 aprint_error_dev(sc->sc_atac.atac_dev, 318 "unable to allocate PRB table memory, " 319 "error=%d\n", error); 320 return; 321 } 322 323 error = bus_dmamem_map(sc->sc_dmat, 324 &schp->sch_prb_seg, schp->sch_prb_nseg, 325 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 326 if (error) { 327 aprint_error_dev(sc->sc_atac.atac_dev, 328 "unable to map PRB table memory, " 329 "error=%d\n", error); 330 bus_dmamem_free(sc->sc_dmat, 331 &schp->sch_prb_seg, schp->sch_prb_nseg); 332 return; 333 } 334 335 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 336 BUS_DMA_NOWAIT, &schp->sch_prbd); 337 if (error) { 338 aprint_error_dev(sc->sc_atac.atac_dev, 339 "unable to create PRB table map, " 340 "error=%d\n", error); 341 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 342 bus_dmamem_free(sc->sc_dmat, 343 &schp->sch_prb_seg, schp->sch_prb_nseg); 344 return; 345 } 346 347 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 348 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 349 if (error) { 350 aprint_error_dev(sc->sc_atac.atac_dev, 351 "unable to load PRB table map, " 352 "error=%d\n", error); 353 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 354 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 355 bus_dmamem_free(sc->sc_dmat, 356 &schp->sch_prb_seg, schp->sch_prb_nseg); 357 return; 358 } 359 360 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 361 schp->sch_prb[j] = (struct siisata_prb *) 362 ((char *)prbp + SIISATA_CMD_SIZE * j); 363 schp->sch_bus_prb[j] = 364 schp->sch_prbd->dm_segs[0].ds_addr + 365 SIISATA_CMD_SIZE * j; 366 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 367 SIISATA_NSGE, MAXPHYS, 0, 368 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 369 &schp->sch_datad[j]); 370 if (error) { 371 aprint_error_dev(sc->sc_atac.atac_dev, 372 "couldn't create xfer DMA map, error=%d\n", 373 error); 374 return; 375 } 376 } 377 378 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 379 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 380 aprint_error_dev(sc->sc_atac.atac_dev, 381 "couldn't map port %d SStatus regs\n", 382 chp->ch_channel); 383 return; 384 } 385 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 386 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 387 aprint_error_dev(sc->sc_atac.atac_dev, 388 "couldn't map port %d SControl regs\n", 389 chp->ch_channel); 390 return; 391 } 392 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 393 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 394 aprint_error_dev(sc->sc_atac.atac_dev, 395 "couldn't map port %d SError regs\n", 396 chp->ch_channel); 397 return; 398 } 399 400 siisata_init_port(sc, port); 401 402 ata_channel_attach(chp); 403 404 return; 405 } 406 407 int 408 siisata_detach(struct siisata_softc *sc, int flags) 409 { 410 struct atac_softc *atac = &sc->sc_atac; 411 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 412 struct siisata_channel *schp; 413 struct ata_channel *chp; 414 int i, j, error; 415 416 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 417 schp = &sc->sc_channels[i]; 418 chp = sc->sc_chanarray[i]; 419 420 if (chp->atabus == NULL) 421 continue; 422 if ((error = config_detach(chp->atabus, flags)) != 0) 423 return error; 424 425 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 426 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 427 428 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 429 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 430 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 431 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 432 bus_dmamem_free(sc->sc_dmat, 433 &schp->sch_prb_seg, schp->sch_prb_nseg); 434 435 ata_queue_free(chp->ch_queue); 436 chp->ch_queue = NULL; 437 chp->atabus = NULL; 438 439 ata_channel_detach(chp); 440 } 441 442 if (adapt->adapt_refcnt != 0) 443 return EBUSY; 444 445 /* leave the chip in reset */ 446 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 447 448 return 0; 449 } 450 451 void 452 siisata_resume(struct siisata_softc *sc) 453 { 454 int i; 455 456 /* come out of reset state */ 457 GRWRITE(sc, GR_GC, 0); 458 459 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 460 siisata_init_port(sc, i); 461 } 462 463 } 464 465 int 466 siisata_intr(void *v) 467 { 468 struct siisata_softc *sc = v; 469 uint32_t is; 470 int i, r = 0; 471 while ((is = GRREAD(sc, GR_GIS))) { 472 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 473 SIISATANAME(sc), __func__, is), DEBUG_INTR); 474 r = 1; 475 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 476 if (is & GR_GIS_PXIS(i)) 477 siisata_intr_port(&sc->sc_channels[i]); 478 } 479 return r; 480 } 481 482 static void 483 siisata_intr_port(struct siisata_channel *schp) 484 { 485 struct siisata_softc *sc = 486 (struct siisata_softc *)schp->ata_channel.ch_atac; 487 struct ata_channel *chp = &schp->ata_channel; 488 struct ata_xfer *xfer = NULL; 489 uint32_t pss, pis, tfd = 0; 490 bool recover = false; 491 492 /* get slot status, clearing completion interrupt */ 493 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 494 495 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x ", 496 SIISATANAME(sc), __func__, chp->ch_channel, pss), 497 DEBUG_INTR); 498 499 if (__predict_true((pss & PR_PSS_ATTENTION) == 0)) { 500 SIISATA_DEBUG_PRINT(("no attention"), DEBUG_INTR); 501 goto process; 502 } 503 504 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 505 506 SIISATA_DEBUG_PRINT(("pis 0x%x\n", pss), DEBUG_INTR); 507 508 if (pis & PR_PIS_CMDERRR) { 509 uint32_t ec; 510 511 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 512 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 513 514 /* emulate a CRC error by default */ 515 tfd = ATACH_ERR_ST(WDCE_CRC, WDCS_ERR); 516 517 if (ec <= PR_PCE_DATAFISERROR) { 518 if (ec == PR_PCE_DEVICEERROR 519 && (chp->ch_flags & ATACH_NCQ) == 0) { 520 xfer = ata_queue_get_active_xfer(chp); 521 522 /* read in specific information about error */ 523 uint32_t prbfis = bus_space_read_stream_4( 524 sc->sc_prt, sc->sc_prh, 525 PRSX(chp->ch_channel, xfer->c_slot, 526 PRSO_FIS)); 527 528 /* get status and error */ 529 int ntfd = satafis_rdh_parse(chp, 530 (uint8_t *)&prbfis); 531 532 if (ATACH_ST(ntfd) & WDCS_ERR) 533 tfd = ntfd; 534 } 535 536 /* 537 * We don't expect the recovery to trigger error, 538 * but handle this just in case. 539 */ 540 if (!schp->sch_recovering) 541 recover = true; 542 else { 543 aprint_error_dev(sc->sc_atac.atac_dev, 544 "error ec %x while recovering\n", ec); 545 546 /* Command will be marked as errored out */ 547 pss = 0; 548 } 549 } else { 550 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 551 " on channel %d (ctx 0x%x), resetting\n", 552 ec, chp->ch_channel, 553 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 554 555 /* okay, we have a "Fatal Error" */ 556 siisata_device_reset(chp); 557 } 558 } 559 560 /* clear some (ok, all) ints */ 561 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 562 563 if (__predict_false(recover)) 564 ata_channel_freeze(chp); 565 566 process: 567 if (xfer != NULL) { 568 xfer->c_intr(chp, xfer, tfd); 569 } else { 570 /* 571 * For NCQ, HBA halts processing when error is notified, 572 * and any further D2H FISes are ignored until the error 573 * condition is cleared. Hence if a command is inactive, 574 * it means it actually already finished successfully. 575 * Note: active slots can change as c_intr() callback 576 * can activate another command(s), so must only process 577 * commands active before we start processing. 578 */ 579 uint32_t aslots = schp->sch_active_slots; 580 581 for (int slot=0; slot < SIISATA_MAX_SLOTS; slot++) { 582 if ((aslots & __BIT(slot)) != 0 && 583 (pss & PR_PXSS(slot)) == 0) { 584 xfer = ata_queue_hwslot_to_xfer(chp, slot); 585 xfer->c_intr(chp, xfer, 0); 586 } 587 } 588 } 589 590 if (__predict_false(recover)) { 591 ata_channel_thaw(chp); 592 siisata_channel_recover(chp, tfd); 593 } 594 } 595 596 static void 597 siisata_hold(struct siisata_channel *schp) 598 { 599 schp->sch_hold_slots |= schp->sch_active_slots; 600 schp->sch_active_slots = 0; 601 } 602 603 static void 604 siisata_unhold(struct siisata_channel *schp) 605 { 606 schp->sch_active_slots = schp->sch_hold_slots; 607 schp->sch_hold_slots = 0; 608 } 609 610 /* Recover channel after transfer aborted */ 611 void 612 siisata_channel_recover(struct ata_channel *chp, uint32_t tfd) 613 { 614 struct siisata_channel *schp = (struct siisata_channel *)chp; 615 struct siisata_softc *sc = 616 (struct siisata_softc *)schp->ata_channel.ch_atac; 617 struct ata_drive_datas *drvp; 618 int drive, error; 619 uint8_t eslot, slot, st, err; 620 struct ata_xfer *xfer; 621 622 KASSERT(!schp->sch_recovering); 623 624 schp->sch_recovering = true; 625 626 if (chp->ch_ndrives > PMP_PORT_CTL) { 627 /* Get PM port number for the device in error */ 628 int pcr = PRREAD(sc, PRX(chp->ch_channel, PRO_PCR)); 629 drive = PRO_PCR_PMP(pcr); 630 } else 631 drive = 0; 632 633 drvp = &chp->ch_drive[drive]; 634 635 /* 636 * If BSY or DRQ bits are set, must execute COMRESET to return 637 * device to idle state. Otherwise, commands can be reissued 638 * after reinitalization of port. After that, need to execute 639 * READ LOG EXT for NCQ to unblock device processing if COMRESET 640 * was not done. 641 */ 642 if ((ATACH_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) 643 goto reset; 644 645 KASSERT(drive >= 0); 646 siisata_reinit_port(chp, drive); 647 648 siisata_hold(schp); 649 650 /* 651 * When running NCQ commands, READ LOG EXT is necessary to clear the 652 * error condition and unblock the device. 653 */ 654 error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err); 655 656 siisata_unhold(schp); 657 658 switch (error) { 659 case 0: 660 /* Error out the particular NCQ xfer, then requeue the others */ 661 if ((schp->sch_active_slots & (1 << eslot)) != 0) { 662 xfer = ata_queue_hwslot_to_xfer(chp, eslot); 663 xfer->c_flags |= C_RECOVERED; 664 xfer->c_intr(chp, xfer, ATACH_ERR_ST(err, st)); 665 } 666 break; 667 668 case EOPNOTSUPP: 669 /* 670 * Non-NCQ command error, just find the slot and end it with 671 * the error. 672 */ 673 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 674 if ((schp->sch_active_slots & (1 << slot)) != 0) { 675 xfer = ata_queue_hwslot_to_xfer(chp, slot); 676 if (xfer->c_drive != drive) 677 continue; 678 679 xfer->c_intr(chp, xfer, tfd); 680 } 681 } 682 break; 683 684 case EAGAIN: 685 /* 686 * Failed to get resources to run the recovery command, must 687 * reset the drive. This will also kill all still outstanding 688 * transfers. 689 */ 690 reset: 691 siisata_device_reset(chp); 692 goto out; 693 /* NOTREACHED */ 694 695 default: 696 /* 697 * The command to get the slot failed. Kill outstanding 698 * commands for the same drive only. No need to reset 699 * the drive, it's unblocked nevertheless. 700 */ 701 break; 702 } 703 704 /* Requeue the non-errorred commands */ 705 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 706 if (((schp->sch_active_slots >> slot) & 1) == 0) 707 continue; 708 709 xfer = ata_queue_hwslot_to_xfer(chp, slot); 710 if (xfer->c_drive != drive) 711 continue; 712 713 xfer->c_kill_xfer(chp, xfer, 714 (error == 0) ? KILL_REQUEUE : KILL_RESET); 715 } 716 717 out: 718 /* Drive unblocked, back to normal operation */ 719 schp->sch_recovering = false; 720 atastart(chp); 721 } 722 723 void 724 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 725 { 726 struct ata_channel *chp = drvp->chnl_softc; 727 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 728 struct siisata_channel *schp = (struct siisata_channel *)chp; 729 struct siisata_prb *prb; 730 struct ata_xfer *xfer; 731 uint32_t pss, pis; 732 int i; 733 bool timed_out; 734 735 siisata_reinit_port(chp, drvp->drive); 736 737 xfer = ata_get_xfer_ext(chp, C_RECOVERY, 0); 738 739 prb = schp->sch_prb[xfer->c_slot]; 740 memset(prb, 0, SIISATA_CMD_SIZE); 741 prb->prb_control = 742 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 743 KASSERT(drvp->drive <= PMP_PORT_CTL); 744 prb->prb_fis[rhd_c] = drvp->drive; 745 746 ata_channel_lock(chp); 747 748 siisata_disable_port_interrupt(chp); 749 750 siisata_activate_prb(schp, xfer->c_slot); 751 752 timed_out = true; 753 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 754 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 755 if ((pss & PR_PXSS(xfer->c_slot)) == 0) { 756 timed_out = false; 757 break; 758 } 759 if (pss & PR_PSS_ATTENTION) 760 break; 761 ata_delay(chp, 10, "siiprb", flags); 762 } 763 764 siisata_deactivate_prb(schp, xfer->c_slot); 765 766 if ((pss & PR_PSS_ATTENTION) != 0) { 767 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 768 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 769 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 770 771 if (slot != xfer->c_slot) 772 device_printf(sc->sc_atac.atac_dev, "%s port %d " 773 "drive %d slot %d c_slot %d", __func__, 774 chp->ch_channel, drvp->drive, slot, xfer->c_slot); 775 776 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 777 PR_PIS_CMDERRR); 778 } 779 780 siisata_enable_port_interrupt(chp); 781 782 ata_channel_unlock(chp); 783 784 if (timed_out) { 785 /* timeout */ 786 siisata_device_reset(chp); /* XXX is this right? */ 787 if (sigp) 788 *sigp = 0xffffffff; 789 } else { 790 /* read the signature out of the FIS */ 791 if (sigp) { 792 *sigp = 0; 793 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 794 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 795 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 796 PRSO_FIS+0xc)) & 0xff; 797 } 798 } 799 800 ata_free_xfer(chp, xfer); 801 802 return; 803 } 804 805 void 806 siisata_reset_channel(struct ata_channel *chp, int flags) 807 { 808 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 809 struct siisata_channel *schp = (struct siisata_channel *)chp; 810 811 SIISATA_DEBUG_PRINT(("%s: %s channel %d\n", SIISATANAME(sc), __func__, 812 chp->ch_channel), DEBUG_FUNCS); 813 814 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 815 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 816 aprint_error("%s port %d: reset failed\n", 817 SIISATANAME(sc), chp->ch_channel); 818 /* XXX and then ? */ 819 } 820 821 siisata_device_reset(chp); 822 823 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 824 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 825 826 return; 827 } 828 829 int 830 siisata_ata_addref(struct ata_drive_datas *drvp) 831 { 832 return 0; 833 } 834 835 void 836 siisata_ata_delref(struct ata_drive_datas *drvp) 837 { 838 return; 839 } 840 841 void 842 siisata_killpending(struct ata_drive_datas *drvp) 843 { 844 return; 845 } 846 847 void 848 siisata_probe_drive(struct ata_channel *chp) 849 { 850 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 851 struct siisata_channel *schp = (struct siisata_channel *)chp; 852 int i; 853 uint32_t sig; 854 struct siisata_prb *prb; 855 bool timed_out; 856 struct ata_xfer *xfer; 857 858 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 859 __func__, chp->ch_channel), DEBUG_FUNCS); 860 861 xfer = ata_get_xfer_ext(chp, 0, 0); 862 if (xfer == NULL) { 863 aprint_error_dev(sc->sc_atac.atac_dev, 864 "%s: failed to get xfer port %d\n", 865 __func__, chp->ch_channel); 866 return; 867 } 868 869 ata_channel_lock(chp); 870 871 /* 872 * disable port interrupt as we're polling for PHY up and 873 * prb completion 874 */ 875 siisata_disable_port_interrupt(chp); 876 877 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 878 schp->sch_sstatus, AT_WAIT)) { 879 case SStatus_DET_DEV: 880 /* clear any interrupts */ 881 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 882 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 883 884 /* wait for ready */ 885 timed_out = 1; 886 for (i = 0; i < ATA_DELAY / 10; i++) { 887 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & 888 PR_PS_PORT_READY) { 889 timed_out = 0; 890 break; 891 } 892 893 ata_delay(chp, 10, "siiprbrd", AT_WAIT); 894 } 895 if (timed_out) { 896 aprint_error_dev(sc->sc_atac.atac_dev, 897 "timed out waiting for PORT_READY on port %d, " 898 "reinitializing\n", chp->ch_channel); 899 siisata_reinit_port(chp, -1); 900 } 901 902 prb = schp->sch_prb[xfer->c_slot]; 903 memset(prb, 0, SIISATA_CMD_SIZE); 904 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 905 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 906 907 siisata_activate_prb(schp, xfer->c_slot); 908 909 timed_out = 1; 910 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 911 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 912 PR_PXSS(xfer->c_slot)) == 0) { 913 /* prb completed */ 914 timed_out = 0; 915 break; 916 } 917 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 918 PR_PIS_CMDERRR) { 919 /* we got an error; handle as timeout */ 920 break; 921 } 922 923 ata_delay(chp, 10, "siiprb", AT_WAIT); 924 } 925 926 siisata_deactivate_prb(schp, xfer->c_slot); 927 928 if (timed_out) { 929 aprint_error_dev(sc->sc_atac.atac_dev, 930 "SOFT_RESET failed on port %d (error %d PSS 0x%x PIS 0x%x), " 931 "resetting\n", chp->ch_channel, 932 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 933 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)), 934 PRREAD(sc, PRX(chp->ch_channel, PRO_PIS))); 935 siisata_reinit_port(chp, -1); 936 break; 937 } 938 939 /* read the signature out of the FIS */ 940 sig = 0; 941 sig |= (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 942 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 943 sig |= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 944 PRSO_FIS+0xc)) & 0xff; 945 946 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 947 __func__, sig), DEBUG_PROBE); 948 949 if (sig == 0x96690101) 950 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 951 PR_PC_PMP_ENABLE); 952 sata_interpret_sig(chp, 0, sig); 953 break; 954 default: 955 break; 956 } 957 958 siisata_enable_port_interrupt(chp); 959 960 ata_channel_unlock(chp); 961 962 ata_free_xfer(chp, xfer); 963 964 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 965 __func__, chp->ch_channel), DEBUG_PROBE); 966 return; 967 } 968 969 void 970 siisata_setup_channel(struct ata_channel *chp) 971 { 972 return; 973 } 974 975 int 976 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 977 { 978 struct ata_channel *chp = drvp->chnl_softc; 979 struct ata_command *ata_c = &xfer->c_ata_c; 980 int ret; 981 int s; 982 983 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 984 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 985 DEBUG_FUNCS); 986 987 if (ata_c->flags & AT_POLL) 988 xfer->c_flags |= C_POLL; 989 if (ata_c->flags & AT_WAIT) 990 xfer->c_flags |= C_WAIT; 991 xfer->c_drive = drvp->drive; 992 xfer->c_databuf = ata_c->data; 993 xfer->c_bcount = ata_c->bcount; 994 xfer->c_start = siisata_cmd_start; 995 xfer->c_intr = siisata_cmd_complete; 996 xfer->c_poll = siisata_cmd_poll; 997 xfer->c_abort = siisata_cmd_abort; 998 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 999 s = splbio(); 1000 ata_exec_xfer(chp, xfer); 1001 #ifdef DIAGNOSTIC 1002 if ((ata_c->flags & AT_POLL) != 0 && 1003 (ata_c->flags & AT_DONE) == 0) 1004 panic("%s: polled command not done", __func__); 1005 #endif 1006 if (ata_c->flags & AT_DONE) { 1007 ret = ATACMD_COMPLETE; 1008 } else { 1009 if (ata_c->flags & AT_WAIT) { 1010 ata_channel_lock(chp); 1011 if ((ata_c->flags & AT_DONE) == 0) { 1012 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 1013 SIISATANAME( 1014 (struct siisata_softc *)chp->ch_atac), 1015 __func__), DEBUG_FUNCS); 1016 ata_wait_xfer(chp, xfer); 1017 KASSERT((ata_c->flags & AT_DONE) != 0); 1018 } 1019 ata_channel_unlock(chp); 1020 ret = ATACMD_COMPLETE; 1021 } else { 1022 ret = ATACMD_QUEUED; 1023 } 1024 } 1025 splx(s); 1026 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 1027 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1028 DEBUG_FUNCS); 1029 return ret; 1030 } 1031 1032 int 1033 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1034 { 1035 struct siisata_channel *schp = (struct siisata_channel *)chp; 1036 struct ata_command *ata_c = &xfer->c_ata_c; 1037 struct siisata_prb *prb; 1038 1039 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 1040 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1041 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 1042 DEBUG_FUNCS|DEBUG_XFERS); 1043 1044 ata_channel_lock_owned(chp); 1045 1046 prb = schp->sch_prb[xfer->c_slot]; 1047 memset(prb, 0, SIISATA_CMD_SIZE); 1048 1049 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 1050 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1051 prb->prb_fis[rhd_c] |= xfer->c_drive; 1052 1053 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 1054 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 1055 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 1056 } 1057 1058 if (siisata_dma_setup(chp, xfer->c_slot, 1059 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 1060 ata_c->bcount, 1061 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1062 ata_c->flags |= AT_DF; 1063 return ATASTART_ABORT; 1064 } 1065 1066 if (xfer->c_flags & C_POLL) { 1067 /* polled command, disable interrupts */ 1068 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1069 siisata_disable_port_interrupt(chp); 1070 } 1071 1072 /* go for it */ 1073 siisata_activate_prb(schp, xfer->c_slot); 1074 1075 if ((ata_c->flags & AT_POLL) == 0) { 1076 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 1077 ata_timeout, xfer); 1078 return ATASTART_STARTED; 1079 } else 1080 return ATASTART_POLL; 1081 } 1082 1083 void 1084 siisata_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1085 { 1086 struct siisata_channel *schp = (struct siisata_channel *)chp; 1087 1088 /* 1089 * polled command 1090 */ 1091 for (int i = 0; i < xfer->c_ata_c.timeout * 10; i++) { 1092 if (xfer->c_ata_c.flags & AT_DONE) 1093 break; 1094 siisata_intr_port(schp); 1095 DELAY(100); 1096 } 1097 1098 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1099 ata_timeout(xfer); 1100 } 1101 1102 /* reenable interrupts */ 1103 siisata_enable_port_interrupt(chp); 1104 1105 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1106 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1107 DEBUG_FUNCS); 1108 } 1109 1110 void 1111 siisata_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1112 { 1113 siisata_cmd_complete(chp, xfer, 0); 1114 } 1115 1116 void 1117 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1118 int reason) 1119 { 1120 struct ata_command *ata_c = &xfer->c_ata_c; 1121 struct siisata_channel *schp = (struct siisata_channel *)chp; 1122 bool deactivate = true; 1123 1124 switch (reason) { 1125 case KILL_GONE_INACTIVE: 1126 deactivate = false; 1127 /* FALLTHROUGH */ 1128 case KILL_GONE: 1129 ata_c->flags |= AT_GONE; 1130 break; 1131 case KILL_RESET: 1132 ata_c->flags |= AT_RESET; 1133 break; 1134 case KILL_REQUEUE: 1135 panic("%s: not supposed to be requeued\n", __func__); 1136 break; 1137 default: 1138 panic("%s: port %d: unknown reason %d", 1139 __func__, chp->ch_channel, reason); 1140 } 1141 1142 if (deactivate) { 1143 siisata_deactivate_prb(schp, xfer->c_slot); 1144 ata_deactivate_xfer(chp, xfer); 1145 } 1146 1147 siisata_cmd_done_end(chp, xfer); 1148 } 1149 1150 int 1151 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1152 { 1153 struct siisata_channel *schp = (struct siisata_channel *)chp; 1154 struct ata_command *ata_c = &xfer->c_ata_c; 1155 #ifdef SIISATA_DEBUG 1156 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1157 #endif 1158 1159 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1160 SIISATANAME(sc), __func__, 1161 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1162 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1163 DEBUG_FUNCS|DEBUG_XFERS); 1164 1165 if (ata_waitdrain_xfer_check(chp, xfer)) 1166 return 0; 1167 1168 siisata_deactivate_prb(schp, xfer->c_slot); 1169 ata_deactivate_xfer(chp, xfer); 1170 1171 if (xfer->c_flags & C_TIMEOU) 1172 ata_c->flags |= AT_TIMEOU; 1173 1174 if (ATACH_ST(tfd) & WDCS_BSY) { 1175 ata_c->flags |= AT_TIMEOU; 1176 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1177 ata_c->r_error = ATACH_ERR(tfd); 1178 ata_c->flags |= AT_ERROR; 1179 } 1180 1181 siisata_cmd_done(chp, xfer, tfd); 1182 1183 return 0; 1184 } 1185 1186 void 1187 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1188 { 1189 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1190 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1191 struct siisata_channel *schp = (struct siisata_channel *)chp; 1192 struct ata_command *ata_c = &xfer->c_ata_c; 1193 uint16_t *idwordbuf; 1194 int i; 1195 1196 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1197 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1198 1199 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1200 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1201 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1202 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1203 BUS_DMASYNC_POSTWRITE); 1204 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1205 } 1206 1207 if (ata_c->flags & AT_READREG) { 1208 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1209 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1210 fis, __arraycount(fis)); 1211 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1212 } 1213 1214 /* correct the endianess of IDENTIFY data */ 1215 if (ata_c->r_command == WDCC_IDENTIFY || 1216 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1217 idwordbuf = xfer->c_databuf; 1218 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1219 idwordbuf[i] = le16toh(idwordbuf[i]); 1220 } 1221 } 1222 1223 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1224 ata_c->flags |= AT_XFDONE; 1225 1226 siisata_cmd_done_end(chp, xfer); 1227 } 1228 1229 static void 1230 siisata_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1231 { 1232 struct ata_command *ata_c = &xfer->c_ata_c; 1233 1234 ata_channel_lock(chp); 1235 1236 ata_c->flags |= AT_DONE; 1237 1238 if (ata_c->flags & AT_WAIT) 1239 ata_wake_xfer(chp, xfer); 1240 1241 ata_channel_unlock(chp); 1242 return; 1243 } 1244 1245 int 1246 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1247 { 1248 struct ata_channel *chp = drvp->chnl_softc; 1249 struct ata_bio *ata_bio = &xfer->c_bio; 1250 1251 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1252 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1253 DEBUG_FUNCS); 1254 1255 if (xfer == NULL) 1256 return ATACMD_TRY_AGAIN; 1257 if (ata_bio->flags & ATA_POLL) 1258 xfer->c_flags |= C_POLL; 1259 xfer->c_drive = drvp->drive; 1260 xfer->c_databuf = ata_bio->databuf; 1261 xfer->c_bcount = ata_bio->bcount; 1262 xfer->c_start = siisata_bio_start; 1263 xfer->c_intr = siisata_bio_complete; 1264 xfer->c_poll = siisata_bio_poll; 1265 xfer->c_abort = siisata_bio_abort; 1266 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1267 ata_exec_xfer(chp, xfer); 1268 return (ata_bio->flags & ATA_ITSDONE) ? 1269 ATACMD_COMPLETE : ATACMD_QUEUED; 1270 } 1271 1272 int 1273 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1274 { 1275 struct siisata_channel *schp = (struct siisata_channel *)chp; 1276 struct siisata_prb *prb; 1277 struct ata_bio *ata_bio = &xfer->c_bio; 1278 1279 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1280 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1281 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1282 1283 ata_channel_lock_owned(chp); 1284 1285 prb = schp->sch_prb[xfer->c_slot]; 1286 memset(prb, 0, SIISATA_CMD_SIZE); 1287 1288 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1289 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1290 prb->prb_fis[rhd_c] |= xfer->c_drive; 1291 1292 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1293 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1294 ata_bio->error = ERR_DMA; 1295 ata_bio->r_error = 0; 1296 return ATASTART_ABORT; 1297 } 1298 1299 if (xfer->c_flags & C_POLL) { 1300 /* polled command, disable interrupts */ 1301 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1302 siisata_disable_port_interrupt(chp); 1303 } 1304 1305 siisata_activate_prb(schp, xfer->c_slot); 1306 1307 if ((ata_bio->flags & ATA_POLL) == 0) { 1308 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1309 ata_timeout, xfer); 1310 return ATASTART_STARTED; 1311 } else 1312 return ATASTART_POLL; 1313 } 1314 1315 void 1316 siisata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1317 { 1318 struct siisata_channel *schp = (struct siisata_channel *)chp; 1319 1320 /* 1321 * polled command 1322 */ 1323 for (int i = 0; i < ATA_DELAY * 10; i++) { 1324 if (xfer->c_bio.flags & ATA_ITSDONE) 1325 break; 1326 siisata_intr_port(schp); 1327 DELAY(100); 1328 } 1329 1330 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1331 ata_timeout(xfer); 1332 } 1333 1334 siisata_enable_port_interrupt(chp); 1335 1336 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1337 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1338 DEBUG_FUNCS); 1339 } 1340 1341 void 1342 siisata_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1343 { 1344 siisata_cmd_complete(chp, xfer, 0); 1345 } 1346 1347 void 1348 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1349 int reason) 1350 { 1351 struct siisata_channel *schp = (struct siisata_channel *)chp; 1352 struct ata_bio *ata_bio = &xfer->c_bio; 1353 int drive = xfer->c_drive; 1354 bool deactivate = true; 1355 1356 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1357 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1358 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1359 1360 ata_bio->flags |= ATA_ITSDONE; 1361 switch (reason) { 1362 case KILL_GONE_INACTIVE: 1363 deactivate = false; 1364 /* FALLTHROUGH */ 1365 case KILL_GONE: 1366 ata_bio->error = ERR_NODEV; 1367 break; 1368 case KILL_RESET: 1369 ata_bio->error = ERR_RESET; 1370 break; 1371 case KILL_REQUEUE: 1372 ata_bio->error = REQUEUE; 1373 break; 1374 default: 1375 panic("%s: port %d: unknown reason %d", 1376 __func__, chp->ch_channel, reason); 1377 } 1378 ata_bio->r_error = WDCE_ABRT; 1379 1380 if (deactivate) { 1381 siisata_deactivate_prb(schp, xfer->c_slot); 1382 ata_deactivate_xfer(chp, xfer); 1383 } 1384 1385 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1386 } 1387 1388 int 1389 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1390 { 1391 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1392 struct siisata_channel *schp = (struct siisata_channel *)chp; 1393 struct ata_bio *ata_bio = &xfer->c_bio; 1394 int drive = xfer->c_drive; 1395 1396 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d tfd %x\n", 1397 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1398 chp->ch_channel, xfer->c_slot, xfer->c_drive, tfd), DEBUG_FUNCS); 1399 1400 if (ata_waitdrain_xfer_check(chp, xfer)) 1401 return 0; 1402 1403 siisata_deactivate_prb(schp, xfer->c_slot); 1404 ata_deactivate_xfer(chp, xfer); 1405 1406 if (xfer->c_flags & C_TIMEOU) { 1407 ata_bio->error = TIMEOUT; 1408 } 1409 1410 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1411 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1412 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1413 BUS_DMASYNC_POSTWRITE); 1414 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1415 1416 ata_bio->flags |= ATA_ITSDONE; 1417 if (ATACH_ST(tfd) & WDCS_DWF) { 1418 ata_bio->error = ERR_DF; 1419 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1420 ata_bio->error = ERROR; 1421 ata_bio->r_error = ATACH_ERR(tfd); 1422 } else if (ATACH_ST(tfd) & WDCS_CORR) 1423 ata_bio->flags |= ATA_CORR; 1424 1425 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1426 ata_bio->bcount), DEBUG_XFERS); 1427 if (ata_bio->error == NOERROR) { 1428 if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ) 1429 ata_bio->bcount -= 1430 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1431 else 1432 ata_bio->bcount = 0; 1433 } 1434 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1435 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1436 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1437 atastart(chp); 1438 return 0; 1439 } 1440 1441 static int 1442 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1443 size_t count, int op) 1444 { 1445 1446 int error, seg; 1447 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1448 struct siisata_channel *schp = (struct siisata_channel *)chp; 1449 1450 struct siisata_prb *prbp; 1451 1452 prbp = schp->sch_prb[slot]; 1453 1454 if (data == NULL) { 1455 goto end; 1456 } 1457 1458 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1459 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1460 if (error) { 1461 aprint_error("%s port %d: " 1462 "failed to load xfer in slot %d: error %d\n", 1463 SIISATANAME(sc), chp->ch_channel, slot, error); 1464 return error; 1465 } 1466 1467 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1468 schp->sch_datad[slot]->dm_mapsize, 1469 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1470 1471 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1472 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1473 DEBUG_FUNCS | DEBUG_DEBUG); 1474 1475 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1476 prbp->prb_sge[seg].sge_da = 1477 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1478 prbp->prb_sge[seg].sge_dc = 1479 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1480 prbp->prb_sge[seg].sge_flags = htole32(0); 1481 } 1482 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1483 end: 1484 return 0; 1485 } 1486 1487 static void 1488 siisata_activate_prb(struct siisata_channel *schp, int slot) 1489 { 1490 struct siisata_softc *sc; 1491 bus_size_t offset; 1492 uint64_t pprb; 1493 1494 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1495 1496 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) == 0, 1497 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1498 1499 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1500 /* keep track of what's going on */ 1501 schp->sch_active_slots |= __BIT(slot); 1502 1503 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1504 1505 pprb = schp->sch_bus_prb[slot]; 1506 1507 PRWRITE(sc, offset + 0, pprb >> 0); 1508 PRWRITE(sc, offset + 4, pprb >> 32); 1509 } 1510 1511 static void 1512 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1513 { 1514 struct siisata_softc *sc; 1515 1516 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1517 1518 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1519 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1520 slot); 1521 1522 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1523 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1524 } 1525 1526 static void 1527 siisata_reinit_port(struct ata_channel *chp, int drive) 1528 { 1529 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1530 int ps; 1531 1532 1533 if (chp->ch_ndrives > 1) { 1534 /* 1535 * Proper recovery would SET this bit, which makes it 1536 * not possible to submit new commands and resume execution 1537 * on non-errored drives, then wait for those commands, 1538 * to finish, and only then clear the bit and reset the state. 1539 * For now this is okay, since we never queue commands for 1540 * more than one drive. 1541 * XXX FIS-based switching 1542 */ 1543 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_RESUME); 1544 1545 for (int i = 0; i < chp->ch_ndrives; i++) { 1546 if (drive >= 0 && i != drive) 1547 continue; 1548 1549 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPSTS(i)), 0); 1550 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPQACT(i)), 0); 1551 } 1552 } 1553 1554 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1555 for (int i = 0; i < ATA_DELAY * 100; i++) { 1556 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1557 if ((ps & PR_PS_PORT_READY) != 0) 1558 break; 1559 1560 DELAY(10); 1561 } 1562 if ((ps & PR_PS_PORT_READY) == 0) { 1563 printf("%s: timeout waiting for port to be ready\n", __func__); 1564 siisata_reset_channel(chp, AT_POLL); 1565 } 1566 1567 if (chp->ch_ndrives > 1) 1568 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1569 } 1570 1571 static void 1572 siisata_device_reset(struct ata_channel *chp) 1573 { 1574 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1575 int ps; 1576 1577 /* 1578 * This is always called after siisata_reinit_port(), so don't 1579 * need to deal with RESUME and clearing device error state. 1580 */ 1581 1582 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1583 1584 for (int i = 0; i < ATA_DELAY * 100; i++) { 1585 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1586 if ((ps & PR_PS_PORT_READY) != 0) 1587 break; 1588 1589 DELAY(10); 1590 } 1591 if ((ps & PR_PS_PORT_READY) == 0) { 1592 printf("%s: timeout waiting for port to be ready\n", __func__); 1593 siisata_reset_channel(chp, AT_POLL); 1594 } 1595 1596 ata_kill_active(chp, KILL_RESET, 0); 1597 } 1598 1599 1600 #if NATAPIBUS > 0 1601 void 1602 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1603 { 1604 struct ata_channel *chp = ata_sc->sc_chan; 1605 struct atac_softc *atac = chp->ch_atac; 1606 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1607 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1608 1609 /* 1610 * Fill in the scsipi_adapter. 1611 */ 1612 adapt->adapt_dev = atac->atac_dev; 1613 adapt->adapt_nchannels = atac->atac_nchannels; 1614 adapt->adapt_request = siisata_atapi_scsipi_request; 1615 adapt->adapt_minphys = siisata_atapi_minphys; 1616 atac->atac_atapi_adapter.atapi_probe_device = 1617 siisata_atapi_probe_device; 1618 1619 /* 1620 * Fill in the scsipi_channel. 1621 */ 1622 memset(chan, 0, sizeof(*chan)); 1623 chan->chan_adapter = adapt; 1624 chan->chan_bustype = &siisata_atapi_bustype; 1625 chan->chan_channel = chp->ch_channel; 1626 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1627 chan->chan_openings = 1; 1628 chan->chan_max_periph = 1; 1629 chan->chan_ntargets = 1; 1630 chan->chan_nluns = 1; 1631 1632 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1633 atapiprint); 1634 } 1635 1636 void 1637 siisata_atapi_minphys(struct buf *bp) 1638 { 1639 if (bp->b_bcount > MAXPHYS) 1640 bp->b_bcount = MAXPHYS; 1641 minphys(bp); 1642 } 1643 1644 /* 1645 * Kill off all pending xfers for a periph. 1646 * 1647 * Must be called at splbio(). 1648 */ 1649 void 1650 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1651 { 1652 struct atac_softc *atac = 1653 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1654 struct ata_channel *chp = 1655 atac->atac_channels[periph->periph_channel->chan_channel]; 1656 1657 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1658 } 1659 1660 void 1661 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1662 int reason) 1663 { 1664 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1665 struct siisata_channel *schp = (struct siisata_channel *)chp; 1666 bool deactivate = true; 1667 1668 /* remove this command from xfer queue */ 1669 switch (reason) { 1670 case KILL_GONE_INACTIVE: 1671 deactivate = false; 1672 /* FALLTHROUGH */ 1673 case KILL_GONE: 1674 sc_xfer->error = XS_DRIVER_STUFFUP; 1675 break; 1676 case KILL_RESET: 1677 sc_xfer->error = XS_RESET; 1678 break; 1679 case KILL_REQUEUE: 1680 sc_xfer->error = XS_REQUEUE; 1681 break; 1682 default: 1683 panic("%s: port %d: unknown reason %d", 1684 __func__, chp->ch_channel, reason); 1685 } 1686 1687 if (deactivate) { 1688 siisata_deactivate_prb(schp, xfer->c_slot); 1689 ata_deactivate_xfer(chp, xfer); 1690 } 1691 1692 ata_free_xfer(chp, xfer); 1693 scsipi_done(sc_xfer); 1694 } 1695 1696 void 1697 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1698 { 1699 struct scsipi_channel *chan = sc->sc_channel; 1700 struct scsipi_periph *periph; 1701 struct ataparams ids; 1702 struct ataparams *id = &ids; 1703 struct siisata_softc *siic = 1704 device_private(chan->chan_adapter->adapt_dev); 1705 struct atac_softc *atac = &siic->sc_atac; 1706 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1707 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1708 struct scsipibus_attach_args sa; 1709 char serial_number[21], model[41], firmware_revision[9]; 1710 int s; 1711 1712 /* skip if already attached */ 1713 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1714 return; 1715 1716 /* if no ATAPI device detected at attach time, skip */ 1717 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1718 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1719 target), DEBUG_PROBE); 1720 return; 1721 } 1722 1723 /* Some ATAPI devices need a bit more time after software reset. */ 1724 DELAY(5000); 1725 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1726 #ifdef ATAPI_DEBUG_PROBE 1727 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1728 device_xname(sc->sc_dev), target, 1729 id->atap_config & ATAPI_CFG_CMD_MASK, 1730 id->atap_config & ATAPI_CFG_DRQ_MASK); 1731 #endif 1732 periph = scsipi_alloc_periph(M_NOWAIT); 1733 if (periph == NULL) { 1734 aprint_error_dev(sc->sc_dev, 1735 "%s: unable to allocate periph for " 1736 "channel %d drive %d\n", __func__, 1737 chp->ch_channel, target); 1738 return; 1739 } 1740 periph->periph_dev = NULL; 1741 periph->periph_channel = chan; 1742 periph->periph_switch = &atapi_probe_periphsw; 1743 periph->periph_target = target; 1744 periph->periph_lun = 0; 1745 periph->periph_quirks = PQUIRK_ONLYBIG; 1746 1747 #ifdef SCSIPI_DEBUG 1748 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1749 SCSIPI_DEBUG_TARGET == target) 1750 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1751 #endif 1752 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1753 if (id->atap_config & ATAPI_CFG_REMOV) 1754 periph->periph_flags |= PERIPH_REMOVABLE; 1755 sa.sa_periph = periph; 1756 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1757 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1758 T_REMOV : T_FIXED; 1759 strnvisx(model, sizeof(model), id->atap_model, 40, 1760 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1761 strnvisx(serial_number, sizeof(serial_number), 1762 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1763 strnvisx(firmware_revision, sizeof(firmware_revision), 1764 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1765 sa.sa_inqbuf.vendor = model; 1766 sa.sa_inqbuf.product = serial_number; 1767 sa.sa_inqbuf.revision = firmware_revision; 1768 1769 /* 1770 * Determine the operating mode capabilities of the device. 1771 */ 1772 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1773 == ATAPI_CFG_CMD_16) { 1774 periph->periph_cap |= PERIPH_CAP_CMD16; 1775 1776 /* configure port for packet length */ 1777 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1778 PR_PC_PACKET_LENGTH); 1779 } else { 1780 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1781 PR_PC_PACKET_LENGTH); 1782 } 1783 1784 /* XXX This is gross. */ 1785 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1786 1787 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1788 1789 if (drvp->drv_softc) 1790 ata_probe_caps(drvp); 1791 else { 1792 s = splbio(); 1793 drvp->drive_type &= ATA_DRIVET_NONE; 1794 splx(s); 1795 } 1796 } else { 1797 s = splbio(); 1798 drvp->drive_type &= ATA_DRIVET_NONE; 1799 splx(s); 1800 } 1801 } 1802 1803 void 1804 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1805 scsipi_adapter_req_t req, void *arg) 1806 { 1807 struct scsipi_adapter *adapt = chan->chan_adapter; 1808 struct scsipi_periph *periph; 1809 struct scsipi_xfer *sc_xfer; 1810 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1811 struct atac_softc *atac = &sc->sc_atac; 1812 struct ata_xfer *xfer; 1813 int channel = chan->chan_channel; 1814 int drive, s; 1815 1816 switch (req) { 1817 case ADAPTER_REQ_RUN_XFER: 1818 sc_xfer = arg; 1819 periph = sc_xfer->xs_periph; 1820 drive = periph->periph_target; 1821 1822 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1823 device_xname(atac->atac_dev), channel, drive), 1824 DEBUG_XFERS); 1825 1826 if (!device_is_active(atac->atac_dev)) { 1827 sc_xfer->error = XS_DRIVER_STUFFUP; 1828 scsipi_done(sc_xfer); 1829 return; 1830 } 1831 xfer = ata_get_xfer_ext(atac->atac_channels[channel], 0, 0); 1832 if (xfer == NULL) { 1833 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1834 scsipi_done(sc_xfer); 1835 return; 1836 } 1837 1838 if (sc_xfer->xs_control & XS_CTL_POLL) 1839 xfer->c_flags |= C_POLL; 1840 xfer->c_drive = drive; 1841 xfer->c_flags |= C_ATAPI; 1842 xfer->c_scsipi = sc_xfer; 1843 xfer->c_databuf = sc_xfer->data; 1844 xfer->c_bcount = sc_xfer->datalen; 1845 xfer->c_start = siisata_atapi_start; 1846 xfer->c_intr = siisata_atapi_complete; 1847 xfer->c_poll = siisata_atapi_poll; 1848 xfer->c_abort = siisata_atapi_abort; 1849 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1850 xfer->c_dscpoll = 0; 1851 s = splbio(); 1852 ata_exec_xfer(atac->atac_channels[channel], xfer); 1853 #ifdef DIAGNOSTIC 1854 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1855 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1856 panic("%s: polled command not done", __func__); 1857 #endif 1858 splx(s); 1859 return; 1860 1861 default: 1862 /* Not supported, nothing to do. */ 1863 ; 1864 } 1865 } 1866 1867 int 1868 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1869 { 1870 struct siisata_channel *schp = (struct siisata_channel *)chp; 1871 struct siisata_prb *prbp; 1872 1873 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1874 1875 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1876 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1877 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1878 DEBUG_XFERS); 1879 1880 ata_channel_lock_owned(chp); 1881 1882 prbp = schp->sch_prb[xfer->c_slot]; 1883 memset(prbp, 0, SIISATA_CMD_SIZE); 1884 1885 /* fill in direction for ATAPI command */ 1886 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1887 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1888 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1889 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1890 1891 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1892 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1893 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1894 1895 /* copy over ATAPI command */ 1896 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1897 1898 if (siisata_dma_setup(chp, xfer->c_slot, 1899 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1900 xfer->c_databuf : NULL, 1901 xfer->c_bcount, 1902 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1903 BUS_DMA_READ : BUS_DMA_WRITE) 1904 ) { 1905 sc_xfer->error = XS_DRIVER_STUFFUP; 1906 return ATASTART_ABORT; 1907 } 1908 1909 if (xfer->c_flags & C_POLL) { 1910 /* polled command, disable interrupts */ 1911 prbp->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1912 siisata_disable_port_interrupt(chp); 1913 } 1914 1915 siisata_activate_prb(schp, xfer->c_slot); 1916 1917 if ((xfer->c_flags & C_POLL) == 0) { 1918 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1919 ata_timeout, xfer); 1920 return ATASTART_STARTED; 1921 } else 1922 return ATASTART_POLL; 1923 } 1924 1925 void 1926 siisata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1927 { 1928 struct siisata_channel *schp = (struct siisata_channel *)chp; 1929 1930 /* 1931 * polled command 1932 */ 1933 for (int i = 0; i < ATA_DELAY * 10; i++) { 1934 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1935 break; 1936 siisata_intr_port(schp); 1937 DELAY(100); 1938 } 1939 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1940 ata_timeout(xfer); 1941 } 1942 /* reenable interrupts */ 1943 siisata_enable_port_interrupt(chp); 1944 1945 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1946 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1947 DEBUG_FUNCS); 1948 } 1949 1950 void 1951 siisata_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1952 { 1953 siisata_atapi_complete(chp, xfer, 0); 1954 } 1955 1956 int 1957 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1958 int tfd) 1959 { 1960 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1961 struct siisata_channel *schp = (struct siisata_channel *)chp; 1962 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1963 1964 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1965 DEBUG_INTR); 1966 1967 if (ata_waitdrain_xfer_check(chp, xfer)) 1968 return 0; 1969 1970 /* this command is not active any more */ 1971 siisata_deactivate_prb(schp, xfer->c_slot); 1972 ata_deactivate_xfer(chp, xfer); 1973 1974 if (xfer->c_flags & C_TIMEOU) { 1975 sc_xfer->error = XS_TIMEOUT; 1976 } 1977 1978 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1979 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1980 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1981 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1982 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1983 1984 sc_xfer->resid = sc_xfer->datalen; 1985 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1986 PRSO_RTC)); 1987 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1988 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1989 if ((ATACH_ST(tfd) & WDCS_ERR) && 1990 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1991 sc_xfer->resid == sc_xfer->datalen)) { 1992 sc_xfer->error = XS_SHORTSENSE; 1993 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1994 if ((sc_xfer->xs_periph->periph_quirks & 1995 PQUIRK_NOSENSE) == 0) { 1996 /* request sense */ 1997 sc_xfer->error = XS_BUSY; 1998 sc_xfer->status = SCSI_CHECK; 1999 } 2000 } 2001 ata_free_xfer(chp, xfer); 2002 scsipi_done(sc_xfer); 2003 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 2004 atastart(chp); 2005 return 0; 2006 } 2007 2008 #endif /* NATAPIBUS */ 2009
Indexes created Mon Oct 20 16:09:52 GMT 2025