siisata.c revision 1.30.4.6
1 /* $NetBSD: siisata.c,v 1.30.4.6 2017/04/22 13:19:28 jakllsch Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.30.4.6 2017/04/22 13:19:28 jakllsch Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 113 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 114 #if _BYTE_ORDER == _LITTLE_ENDIAN 115 #define bus_space_read_stream_4 bus_space_read_4 116 #define bus_space_read_region_stream_4 bus_space_read_region_4 117 #else 118 static inline uint32_t 119 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 120 { 121 return htole32(bus_space_read_4(t, h, o)); 122 } 123 124 static inline void 125 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o, uint32_t *p, bus_size_t c) 126 { 127 bus_space_read_region_4(t, h, o, p, c); 128 for (bus_size_t i = 0; i < c; i++) { 129 p[i] = htole32(p[i]); 130 } 131 } 132 #endif 133 #endif 134 135 static void siisata_attach_port(struct siisata_softc *, int); 136 static void siisata_intr_port(struct siisata_channel *); 137 138 void siisata_probe_drive(struct ata_channel *); 139 void siisata_setup_channel(struct ata_channel *); 140 141 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 142 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 143 void siisata_reset_channel(struct ata_channel *, int); 144 int siisata_ata_addref(struct ata_drive_datas *); 145 void siisata_ata_delref(struct ata_drive_datas *); 146 void siisata_killpending(struct ata_drive_datas *); 147 148 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 149 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 150 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 151 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 152 153 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 154 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 155 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 156 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 157 158 void siisata_timeout(void *); 159 160 static void siisata_reinit_port(struct ata_channel *); 161 static void siisata_device_reset(struct ata_channel *); 162 static void siisata_activate_prb(struct siisata_channel *, int); 163 static void siisata_deactivate_prb(struct siisata_channel *, int); 164 static int siisata_dma_setup(struct ata_channel *chp, int slot, 165 void *data, size_t, int); 166 167 #if NATAPIBUS > 0 168 void siisata_atapibus_attach(struct atabus_softc *); 169 void siisata_atapi_probe_device(struct atapibus_softc *, int); 170 void siisata_atapi_minphys(struct buf *); 171 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 172 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 173 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 174 void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 175 void siisata_atapi_scsipi_request(struct scsipi_channel *, 176 scsipi_adapter_req_t, void *); 177 void siisata_atapi_kill_pending(struct scsipi_periph *); 178 #endif /* NATAPIBUS */ 179 180 const struct ata_bustype siisata_ata_bustype = { 181 SCSIPI_BUSTYPE_ATA, 182 siisata_ata_bio, 183 siisata_reset_drive, 184 siisata_reset_channel, 185 siisata_exec_command, 186 ata_get_params, 187 siisata_ata_addref, 188 siisata_ata_delref, 189 siisata_killpending 190 }; 191 192 #if NATAPIBUS > 0 193 static const struct scsipi_bustype siisata_atapi_bustype = { 194 SCSIPI_BUSTYPE_ATAPI, 195 atapi_scsipi_cmd, 196 atapi_interpret_sense, 197 atapi_print_addr, 198 siisata_atapi_kill_pending, 199 NULL, 200 }; 201 #endif /* NATAPIBUS */ 202 203 204 void 205 siisata_attach(struct siisata_softc *sc) 206 { 207 int i; 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 211 212 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 213 sc->sc_atac.atac_pio_cap = 4; 214 sc->sc_atac.atac_dma_cap = 2; 215 sc->sc_atac.atac_udma_cap = 6; 216 sc->sc_atac.atac_channels = sc->sc_chanarray; 217 sc->sc_atac.atac_probe = siisata_probe_drive; 218 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 219 sc->sc_atac.atac_set_modes = siisata_setup_channel; 220 #if NATAPIBUS > 0 221 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 222 #endif 223 224 /* come out of reset state */ 225 GRWRITE(sc, GR_GC, 0); 226 227 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 228 siisata_attach_port(sc, i); 229 } 230 231 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 232 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 233 DEBUG_FUNCS); 234 return; 235 } 236 237 static void 238 siisata_disable_port_interrupt(struct ata_channel *chp) 239 { 240 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 241 242 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 243 } 244 245 static void 246 siisata_enable_port_interrupt(struct ata_channel *chp) 247 { 248 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 249 250 /* clear any interrupts */ 251 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 252 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 253 /* and enable CmdErrr+CmdCmpl interrupting */ 254 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 255 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 256 } 257 258 static void 259 siisata_init_port(struct siisata_softc *sc, int port) 260 { 261 struct siisata_channel *schp; 262 struct ata_channel *chp; 263 264 schp = &sc->sc_channels[port]; 265 chp = (struct ata_channel *)schp; 266 267 /* come out of reset, 64-bit activation */ 268 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 269 PR_PC_32BA | PR_PC_PORT_RESET); 270 /* initialize port */ 271 siisata_reinit_port(chp); 272 /* enable CmdErrr+CmdCmpl interrupting */ 273 siisata_enable_port_interrupt(chp); 274 /* enable port interrupt */ 275 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 276 } 277 278 static void 279 siisata_attach_port(struct siisata_softc *sc, int port) 280 { 281 int j; 282 int dmasize; 283 int error; 284 void *prbp; 285 struct siisata_channel *schp; 286 struct ata_channel *chp; 287 288 schp = &sc->sc_channels[port]; 289 chp = (struct ata_channel *)schp; 290 sc->sc_chanarray[port] = chp; 291 chp->ch_channel = port; 292 chp->ch_atac = &sc->sc_atac; 293 chp->ch_queue = ata_queue_alloc(1); // XXX 294 if (chp->ch_queue == NULL) { 295 aprint_error_dev(sc->sc_atac.atac_dev, 296 "port %d: can't allocate memory " 297 "for command queue\n", chp->ch_channel); 298 return; 299 } 300 301 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 302 303 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 304 __func__, dmasize), DEBUG_FUNCS); 305 306 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 307 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 308 if (error) { 309 aprint_error_dev(sc->sc_atac.atac_dev, 310 "unable to allocate PRB table memory, " 311 "error=%d\n", error); 312 return; 313 } 314 315 error = bus_dmamem_map(sc->sc_dmat, 316 &schp->sch_prb_seg, schp->sch_prb_nseg, 317 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 318 if (error) { 319 aprint_error_dev(sc->sc_atac.atac_dev, 320 "unable to map PRB table memory, " 321 "error=%d\n", error); 322 bus_dmamem_free(sc->sc_dmat, 323 &schp->sch_prb_seg, schp->sch_prb_nseg); 324 return; 325 } 326 327 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 328 BUS_DMA_NOWAIT, &schp->sch_prbd); 329 if (error) { 330 aprint_error_dev(sc->sc_atac.atac_dev, 331 "unable to create PRB table map, " 332 "error=%d\n", error); 333 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 334 bus_dmamem_free(sc->sc_dmat, 335 &schp->sch_prb_seg, schp->sch_prb_nseg); 336 return; 337 } 338 339 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 340 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 341 if (error) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "unable to load PRB table map, " 344 "error=%d\n", error); 345 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 346 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 347 bus_dmamem_free(sc->sc_dmat, 348 &schp->sch_prb_seg, schp->sch_prb_nseg); 349 return; 350 } 351 352 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 353 schp->sch_prb[j] = (struct siisata_prb *) 354 ((char *)prbp + SIISATA_CMD_SIZE * j); 355 schp->sch_bus_prb[j] = 356 schp->sch_prbd->dm_segs[0].ds_addr + 357 SIISATA_CMD_SIZE * j; 358 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 359 SIISATA_NSGE, MAXPHYS, 0, 360 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 361 &schp->sch_datad[j]); 362 if (error) { 363 aprint_error_dev(sc->sc_atac.atac_dev, 364 "couldn't create xfer DMA map, error=%d\n", 365 error); 366 return; 367 } 368 } 369 370 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 371 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 372 aprint_error_dev(sc->sc_atac.atac_dev, 373 "couldn't map port %d SStatus regs\n", 374 chp->ch_channel); 375 return; 376 } 377 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 378 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 379 aprint_error_dev(sc->sc_atac.atac_dev, 380 "couldn't map port %d SControl regs\n", 381 chp->ch_channel); 382 return; 383 } 384 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 385 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 386 aprint_error_dev(sc->sc_atac.atac_dev, 387 "couldn't map port %d SError regs\n", 388 chp->ch_channel); 389 return; 390 } 391 392 siisata_init_port(sc, port); 393 394 ata_channel_attach(chp); 395 396 return; 397 } 398 399 int 400 siisata_detach(struct siisata_softc *sc, int flags) 401 { 402 struct atac_softc *atac = &sc->sc_atac; 403 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 404 struct siisata_channel *schp; 405 struct ata_channel *chp; 406 int i, j, error; 407 408 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 409 schp = &sc->sc_channels[i]; 410 chp = sc->sc_chanarray[i]; 411 412 if (chp->atabus == NULL) 413 continue; 414 if ((error = config_detach(chp->atabus, flags)) != 0) 415 return error; 416 417 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 418 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 419 420 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 421 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 422 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 423 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 424 bus_dmamem_free(sc->sc_dmat, 425 &schp->sch_prb_seg, schp->sch_prb_nseg); 426 427 free(chp->ch_queue, M_DEVBUF); 428 chp->atabus = NULL; 429 } 430 431 if (adapt->adapt_refcnt != 0) 432 return EBUSY; 433 434 /* leave the chip in reset */ 435 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 436 437 return 0; 438 } 439 440 void 441 siisata_resume(struct siisata_softc *sc) 442 { 443 int i; 444 445 /* come out of reset state */ 446 GRWRITE(sc, GR_GC, 0); 447 448 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 449 siisata_init_port(sc, i); 450 } 451 452 } 453 454 int 455 siisata_intr(void *v) 456 { 457 struct siisata_softc *sc = v; 458 uint32_t is; 459 int i, r = 0; 460 while ((is = GRREAD(sc, GR_GIS))) { 461 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 462 SIISATANAME(sc), __func__, is), DEBUG_INTR); 463 r = 1; 464 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 465 if (is & GR_GIS_PXIS(i)) 466 siisata_intr_port(&sc->sc_channels[i]); 467 } 468 return r; 469 } 470 471 static void 472 siisata_intr_port(struct siisata_channel *schp) 473 { 474 struct siisata_softc *sc; 475 struct ata_channel *chp; 476 struct ata_xfer *xfer; 477 int slot; 478 uint32_t pss, pis; 479 uint32_t prbfis; 480 481 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 482 chp = &schp->ata_channel; 483 xfer = ata_queue_hwslot_to_xfer(chp->ch_queue, 0); /* XXX slot */ 484 slot = SIISATA_NON_NCQ_SLOT; 485 486 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 487 488 SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x ", 489 SIISATANAME(sc), __func__, chp->ch_channel, pis), DEBUG_INTR); 490 491 if (pis & PR_PIS_CMDCMPL) { 492 /* get slot status, clearing completion interrupt */ 493 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 494 SIISATA_DEBUG_PRINT(("pss 0x%x\n", pss), DEBUG_INTR); 495 /* is this expected? */ 496 /* XXX improve */ 497 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 498 aprint_error( "%s: unexpected command " 499 "completion on port %d\n", 500 SIISATANAME(sc), chp->ch_channel); 501 return; 502 } 503 if ((~pss & __BIT(slot)) == 0) { 504 aprint_error( "%s: unknown slot " 505 "completion on port %d, pss 0x%x\n", 506 SIISATANAME(sc), chp->ch_channel, pss); 507 return; 508 } 509 } else if (pis & PR_PIS_CMDERRR) { 510 uint32_t ec; 511 512 /* emulate a CRC error by default */ 513 chp->ch_status = WDCS_ERR; 514 chp->ch_error = WDCE_CRC; 515 516 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 517 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 518 if (ec <= PR_PCE_DATAFISERROR) { 519 if (ec == PR_PCE_DEVICEERROR && xfer != NULL) { 520 /* read in specific information about error */ 521 prbfis = bus_space_read_stream_4( 522 sc->sc_prt, sc->sc_prh, 523 PRSX(chp->ch_channel, slot, PRSO_FIS)); 524 /* set ch_status and ch_error */ 525 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 526 } 527 siisata_reinit_port(chp); 528 } else { 529 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 530 " on channel %d (ctx 0x%x), resetting\n", 531 ec, chp->ch_channel, 532 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 533 /* okay, we have a "Fatal Error" */ 534 siisata_device_reset(chp); 535 } 536 } 537 538 /* clear some (ok, all) ints */ 539 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 540 if (xfer && xfer->c_intr) 541 xfer->c_intr(chp, xfer, 0); 542 543 return; 544 } 545 546 void 547 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 548 { 549 struct ata_channel *chp = drvp->chnl_softc; 550 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 551 struct siisata_channel *schp = (struct siisata_channel *)chp; 552 struct siisata_prb *prb; 553 int slot = SIISATA_NON_NCQ_SLOT; 554 int i; 555 556 /* wait for ready */ 557 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 558 DELAY(10); 559 560 prb = schp->sch_prb[slot]; 561 memset(prb, 0, sizeof(struct siisata_prb)); 562 prb->prb_control = 563 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 564 KASSERT(drvp->drive <= PMP_PORT_CTL); 565 prb->prb_fis[rhd_c] = drvp->drive; 566 567 siisata_activate_prb(schp, slot); 568 569 for(i = 0; i < 3100; i++) { 570 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 571 PR_PXSS(slot)) == 0) 572 break; 573 if (flags & AT_WAIT) 574 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 575 else 576 DELAY(10000); 577 } 578 579 siisata_deactivate_prb(schp, slot); 580 if (i == 3100) { 581 /* timeout */ 582 siisata_device_reset(chp); 583 if (sigp) 584 *sigp = 0xffffffff; 585 } else { 586 /* read the signature out of the FIS */ 587 if (sigp) { 588 *sigp = 0; 589 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 590 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 591 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, slot, 592 PRSO_FIS+0xc)) & 0xff; 593 } 594 } 595 596 #if 1 597 /* attempt to downgrade signaling in event of CRC error */ 598 /* XXX should be part of the MI (S)ATA subsystem */ 599 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 600 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 601 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 602 DELAY(10); 603 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 604 SControl_IPM_NONE | SControl_SPD_G1); 605 DELAY(10); 606 for (;;) { 607 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 608 & SStatus_DET_mask) == SStatus_DET_DEV) 609 break; 610 DELAY(10); 611 } 612 } 613 #endif 614 615 #if 1 616 chp->ch_status = 0; 617 chp->ch_error = 0; 618 #endif 619 return; 620 } 621 622 void 623 siisata_reset_channel(struct ata_channel *chp, int flags) 624 { 625 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 626 struct siisata_channel *schp = (struct siisata_channel *)chp; 627 struct ata_xfer *xfer; 628 629 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 630 DEBUG_FUNCS); 631 632 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 633 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 634 aprint_error("%s port %d: reset failed\n", 635 SIISATANAME(sc), chp->ch_channel); 636 /* XXX and then ? */ 637 } 638 /* wait for ready */ 639 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 640 DELAY(10); 641 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 642 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 643 if ((xfer = ata_queue_hwslot_to_xfer(chp->ch_queue, 0)) != NULL) { /* XXX slot */ 644 (*xfer->c_kill_xfer)(chp, xfer, KILL_RESET); 645 } 646 647 return; 648 } 649 650 int 651 siisata_ata_addref(struct ata_drive_datas *drvp) 652 { 653 return 0; 654 } 655 656 void 657 siisata_ata_delref(struct ata_drive_datas *drvp) 658 { 659 return; 660 } 661 662 void 663 siisata_killpending(struct ata_drive_datas *drvp) 664 { 665 return; 666 } 667 668 void 669 siisata_probe_drive(struct ata_channel *chp) 670 { 671 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 672 struct siisata_channel *schp = (struct siisata_channel *)chp; 673 int i; 674 uint32_t sig; 675 int slot = SIISATA_NON_NCQ_SLOT; 676 struct siisata_prb *prb; 677 bool timed_out; 678 679 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 680 __func__, chp->ch_channel), DEBUG_FUNCS); 681 682 /* 683 * disable port interrupt as we're polling for PHY up and 684 * prb completion 685 */ 686 siisata_disable_port_interrupt(chp); 687 688 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 689 schp->sch_sstatus, AT_WAIT)) { 690 case SStatus_DET_DEV: 691 /* clear any interrupts */ 692 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 693 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 694 /* wait for ready */ 695 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 696 & PR_PS_PORT_READY)) 697 DELAY(10); 698 prb = schp->sch_prb[slot]; 699 memset(prb, 0, sizeof(struct siisata_prb)); 700 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 701 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 702 703 siisata_activate_prb(schp, slot); 704 705 timed_out = 1; 706 for(i = 0; i < 3100; i++) { 707 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 708 PR_PXSS(slot)) == 0) { 709 /* prb completed */ 710 timed_out = 0; 711 break; 712 } 713 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 714 (PR_PIS_CMDERRR << 16)) { 715 /* we got an error; handle as timeout */ 716 break; 717 } 718 719 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 720 } 721 722 siisata_deactivate_prb(schp, slot); 723 if (timed_out) { 724 aprint_error_dev(sc->sc_atac.atac_dev, 725 "SOFT_RESET failed on port %d (error %d PSS 0x%x), " 726 "resetting\n", chp->ch_channel, 727 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 728 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); 729 siisata_reinit_port(chp); 730 break; 731 } 732 733 /* read the signature out of the FIS */ 734 sig = 0; 735 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 736 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 737 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 738 PRSO_FIS+0xc)) & 0xff; 739 740 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 741 __func__, sig), DEBUG_PROBE); 742 743 if (sig == 0x96690101) 744 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 745 PR_PC_PMP_ENABLE); 746 sata_interpret_sig(chp, 0, sig); 747 break; 748 default: 749 break; 750 } 751 752 siisata_enable_port_interrupt(chp); 753 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 754 __func__, chp->ch_channel), DEBUG_PROBE); 755 return; 756 } 757 758 void 759 siisata_setup_channel(struct ata_channel *chp) 760 { 761 return; 762 } 763 764 int 765 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 766 { 767 struct ata_channel *chp = drvp->chnl_softc; 768 struct ata_command *ata_c = &xfer->c_ata_c; 769 int ret; 770 int s; 771 772 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 773 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 774 DEBUG_FUNCS); 775 776 if (ata_c->flags & AT_POLL) 777 xfer->c_flags |= C_POLL; 778 if (ata_c->flags & AT_WAIT) 779 xfer->c_flags |= C_WAIT; 780 xfer->c_drive = drvp->drive; 781 xfer->c_databuf = ata_c->data; 782 xfer->c_bcount = ata_c->bcount; 783 xfer->c_start = siisata_cmd_start; 784 xfer->c_intr = siisata_cmd_complete; 785 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 786 s = splbio(); 787 ata_exec_xfer(chp, xfer); 788 #ifdef DIAGNOSTIC 789 if ((ata_c->flags & AT_POLL) != 0 && 790 (ata_c->flags & AT_DONE) == 0) 791 panic("%s: polled command not done", __func__); 792 #endif 793 if (ata_c->flags & AT_DONE) { 794 ret = ATACMD_COMPLETE; 795 } else { 796 if (ata_c->flags & AT_WAIT) { 797 while ((ata_c->flags & AT_DONE) == 0) { 798 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 799 SIISATANAME( 800 (struct siisata_softc *)chp->ch_atac), 801 __func__), DEBUG_FUNCS); 802 tsleep(ata_c, PRIBIO, "siicmd", 0); 803 } 804 ret = ATACMD_COMPLETE; 805 } else { 806 ret = ATACMD_QUEUED; 807 } 808 } 809 splx(s); 810 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 811 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 812 DEBUG_FUNCS); 813 return ret; 814 } 815 816 void 817 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 818 { 819 struct siisata_channel *schp = (struct siisata_channel *)chp; 820 struct ata_command *ata_c = &xfer->c_ata_c; 821 int slot = SIISATA_NON_NCQ_SLOT; 822 struct siisata_prb *prb; 823 int i; 824 825 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 826 SIISATANAME((struct siisata_softc *)chp->ch_atac), 827 __func__, chp->ch_channel, xfer->c_drive, 828 ata_c->r_command, slot), 829 DEBUG_FUNCS|DEBUG_XFERS); 830 831 chp->ch_status = 0; 832 chp->ch_error = 0; 833 834 prb = schp->sch_prb[slot]; 835 memset(prb, 0, sizeof(struct siisata_prb)); 836 837 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 838 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 839 prb->prb_fis[rhd_c] |= xfer->c_drive; 840 841 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 842 843 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 844 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 845 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 846 } 847 848 if (siisata_dma_setup(chp, slot, 849 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 850 ata_c->bcount, 851 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 852 ata_c->flags |= AT_DF; 853 siisata_cmd_complete(chp, xfer, 0); 854 return; 855 } 856 857 if (xfer->c_flags & C_POLL) { 858 /* polled command, disable interrupts */ 859 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 860 siisata_disable_port_interrupt(chp); 861 } 862 863 /* go for it */ 864 siisata_activate_prb(schp, slot); 865 866 if ((ata_c->flags & AT_POLL) == 0) { 867 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 868 callout_reset(&xfer->c_timo_callout, mstohz(ata_c->timeout), 869 siisata_timeout, xfer); 870 goto out; 871 } 872 873 /* 874 * polled command 875 */ 876 for (i = 0; i < ata_c->timeout / 10; i++) { 877 if (ata_c->flags & AT_DONE) 878 break; 879 siisata_intr_port(schp); 880 DELAY(1000); 881 } 882 883 if ((ata_c->flags & AT_DONE) == 0) { 884 siisata_timeout(xfer); 885 } 886 887 /* reenable interrupts */ 888 siisata_enable_port_interrupt(chp); 889 out: 890 SIISATA_DEBUG_PRINT( 891 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 892 return; 893 } 894 895 void 896 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 897 int reason) 898 { 899 int slot = SIISATA_NON_NCQ_SLOT; 900 901 struct ata_command *ata_c = &xfer->c_ata_c; 902 switch (reason) { 903 case KILL_GONE: 904 ata_c->flags |= AT_GONE; 905 break; 906 case KILL_RESET: 907 ata_c->flags |= AT_RESET; 908 break; 909 default: 910 panic("%s: port %d: unknown reason %d", 911 __func__, chp->ch_channel, reason); 912 } 913 siisata_cmd_done(chp, xfer, slot); 914 } 915 916 int 917 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 918 { 919 struct ata_command *ata_c = &xfer->c_ata_c; 920 #ifdef SIISATA_DEBUG 921 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 922 #endif 923 int slot = SIISATA_NON_NCQ_SLOT; 924 925 SIISATA_DEBUG_PRINT( 926 ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS|DEBUG_XFERS); 927 928 chp->ch_flags &= ~ATACH_IRQ_WAIT; 929 if (xfer->c_flags & C_TIMEOU) 930 ata_c->flags |= AT_TIMEOU; 931 else 932 callout_stop(&xfer->c_timo_callout); 933 934 if (chp->ch_status & WDCS_BSY) { 935 ata_c->flags |= AT_TIMEOU; 936 } else if (chp->ch_status & WDCS_ERR) { 937 ata_c->r_error = chp->ch_error; 938 ata_c->flags |= AT_ERROR; 939 } 940 941 ata_deactivate_xfer(chp, xfer); 942 943 if (!ata_waitdrain_xfer_check(chp, xfer)) { 944 siisata_cmd_done(chp, xfer, slot); 945 } 946 947 return 0; 948 } 949 950 void 951 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 952 { 953 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 954 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 955 struct siisata_channel *schp = (struct siisata_channel *)chp; 956 struct ata_command *ata_c = &xfer->c_ata_c; 957 uint16_t *idwordbuf; 958 int i; 959 960 SIISATA_DEBUG_PRINT( 961 ("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), __func__, 962 ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 963 964 siisata_deactivate_prb(schp, slot); 965 966 if (ata_c->flags & (AT_READ | AT_WRITE)) { 967 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 968 schp->sch_datad[slot]->dm_mapsize, 969 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 970 BUS_DMASYNC_POSTWRITE); 971 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 972 } 973 974 if (ata_c->flags & AT_READREG) { 975 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 976 PRSX(chp->ch_channel, slot, PRSO_FIS), 977 fis, __arraycount(fis)); 978 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 979 } 980 981 /* correct the endianess of IDENTIFY data */ 982 if (ata_c->r_command == WDCC_IDENTIFY || 983 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 984 idwordbuf = xfer->c_databuf; 985 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 986 idwordbuf[i] = le16toh(idwordbuf[i]); 987 } 988 } 989 990 ata_c->flags |= AT_DONE; 991 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 992 ata_c->flags |= AT_XFDONE; 993 994 if (ata_c->flags & AT_WAIT) 995 wakeup(ata_c); 996 else if (ata_c->callback) 997 ata_c->callback(ata_c->callback_arg); 998 atastart(chp); 999 return; 1000 } 1001 1002 int 1003 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1004 { 1005 struct ata_channel *chp = drvp->chnl_softc; 1006 struct ata_bio *ata_bio = &xfer->c_bio; 1007 1008 SIISATA_DEBUG_PRINT( ("%s: %s.\n", 1009 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1010 __func__), DEBUG_FUNCS); 1011 1012 if (xfer == NULL) 1013 return ATACMD_TRY_AGAIN; 1014 if (ata_bio->flags & ATA_POLL) 1015 xfer->c_flags |= C_POLL; 1016 xfer->c_drive = drvp->drive; 1017 xfer->c_databuf = ata_bio->databuf; 1018 xfer->c_bcount = ata_bio->bcount; 1019 xfer->c_start = siisata_bio_start; 1020 xfer->c_intr = siisata_bio_complete; 1021 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1022 ata_exec_xfer(chp, xfer); 1023 return (ata_bio->flags & ATA_ITSDONE) ? 1024 ATACMD_COMPLETE : ATACMD_QUEUED; 1025 } 1026 1027 void 1028 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1029 { 1030 struct siisata_channel *schp = (struct siisata_channel *)chp; 1031 struct siisata_prb *prb; 1032 struct ata_bio *ata_bio = &xfer->c_bio; 1033 int slot = SIISATA_NON_NCQ_SLOT; 1034 int i; 1035 1036 SIISATA_DEBUG_PRINT( 1037 ("%s: %s port %d, slot %d\n", 1038 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, chp->ch_channel, slot), 1039 DEBUG_FUNCS); 1040 1041 chp->ch_status = 0; 1042 chp->ch_error = 0; 1043 1044 prb = schp->sch_prb[slot]; 1045 memset(prb, 0, sizeof(struct siisata_prb)); 1046 1047 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1048 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1049 prb->prb_fis[rhd_c] |= xfer->c_drive; 1050 1051 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 1052 1053 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1054 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1055 ata_bio->error = ERR_DMA; 1056 ata_bio->r_error = 0; 1057 siisata_bio_complete(chp, xfer, slot); 1058 return; 1059 } 1060 1061 if (xfer->c_flags & C_POLL) { 1062 /* polled command, disable interrupts */ 1063 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1064 siisata_disable_port_interrupt(chp); 1065 } 1066 1067 siisata_activate_prb(schp, slot); 1068 1069 if ((ata_bio->flags & ATA_POLL) == 0) { 1070 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1071 callout_reset(&xfer->c_timo_callout, mstohz(ATA_DELAY), 1072 siisata_timeout, xfer); 1073 goto out; 1074 } 1075 1076 /* 1077 * polled command 1078 */ 1079 for (i = 0; i < ATA_DELAY / 10; i++) { 1080 if (ata_bio->flags & ATA_ITSDONE) 1081 break; 1082 siisata_intr_port(schp); 1083 DELAY(1000); 1084 } 1085 1086 siisata_enable_port_interrupt(chp); 1087 out: 1088 SIISATA_DEBUG_PRINT( 1089 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 1090 return; 1091 } 1092 1093 void 1094 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1095 int reason) 1096 { 1097 struct siisata_channel *schp = (struct siisata_channel *)chp; 1098 struct ata_bio *ata_bio = &xfer->c_bio; 1099 int drive = xfer->c_drive; 1100 int slot = SIISATA_NON_NCQ_SLOT; 1101 1102 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1103 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1104 __func__, chp->ch_channel), DEBUG_FUNCS); 1105 1106 siisata_deactivate_prb(schp, slot); 1107 1108 ata_bio->flags |= ATA_ITSDONE; 1109 switch (reason) { 1110 case KILL_GONE: 1111 ata_bio->error = ERR_NODEV; 1112 break; 1113 case KILL_RESET: 1114 ata_bio->error = ERR_RESET; 1115 break; 1116 default: 1117 panic("%s: port %d: unknown reason %d", 1118 __func__, chp->ch_channel, reason); 1119 } 1120 ata_bio->r_error = WDCE_ABRT; 1121 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1122 } 1123 1124 int 1125 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1126 { 1127 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1128 struct siisata_channel *schp = (struct siisata_channel *)chp; 1129 struct ata_bio *ata_bio = &xfer->c_bio; 1130 int drive = xfer->c_drive; 1131 int slot = SIISATA_NON_NCQ_SLOT; 1132 1133 schp->sch_active_slots &= ~__BIT(slot); 1134 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1135 if (xfer->c_flags & C_TIMEOU) { 1136 ata_bio->error = TIMEOUT; 1137 } else { 1138 callout_stop(&xfer->c_timo_callout); 1139 ata_bio->error = NOERROR; 1140 } 1141 1142 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1143 schp->sch_datad[slot]->dm_mapsize, 1144 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1145 BUS_DMASYNC_POSTWRITE); 1146 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1147 1148 ata_deactivate_xfer(chp, xfer); 1149 1150 if (ata_waitdrain_xfer_check(chp, xfer)) { 1151 return 0; 1152 } 1153 1154 ata_bio->flags |= ATA_ITSDONE; 1155 if (chp->ch_status & WDCS_DWF) { 1156 ata_bio->error = ERR_DF; 1157 } else if (chp->ch_status & WDCS_ERR) { 1158 ata_bio->error = ERROR; 1159 ata_bio->r_error = chp->ch_error; 1160 } else if (chp->ch_status & WDCS_CORR) 1161 ata_bio->flags |= ATA_CORR; 1162 1163 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), 1164 __func__, ata_bio->bcount), DEBUG_XFERS); 1165 if (ata_bio->error == NOERROR) { 1166 if (ata_bio->flags & ATA_READ) 1167 ata_bio->bcount -= 1168 PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1169 else 1170 ata_bio->bcount = 0; 1171 } 1172 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1173 if (ata_bio->flags & ATA_POLL) 1174 return 1; 1175 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1176 atastart(chp); 1177 return 0; 1178 } 1179 1180 void 1181 siisata_timeout(void *v) 1182 { 1183 struct ata_xfer *xfer = v; 1184 struct ata_channel *chp = xfer->c_chp; 1185 int s = splbio(); 1186 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1187 siisata_device_reset(chp); 1188 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1189 xfer->c_flags |= C_TIMEOU; 1190 xfer->c_intr(chp, xfer, 0); 1191 } 1192 splx(s); 1193 } 1194 1195 static int 1196 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1197 size_t count, int op) 1198 { 1199 1200 int error, seg; 1201 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1202 struct siisata_channel *schp = (struct siisata_channel *)chp; 1203 1204 struct siisata_prb *prbp; 1205 1206 prbp = schp->sch_prb[slot]; 1207 1208 if (data == NULL) { 1209 goto end; 1210 } 1211 1212 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1213 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1214 if (error) { 1215 aprint_error("%s port %d: " 1216 "failed to load xfer in slot %d: error %d\n", 1217 SIISATANAME(sc), chp->ch_channel, slot, error); 1218 return error; 1219 } 1220 1221 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1222 schp->sch_datad[slot]->dm_mapsize, 1223 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1224 1225 /* make sure it's clean */ 1226 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1227 1228 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1229 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1230 DEBUG_FUNCS | DEBUG_DEBUG); 1231 1232 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1233 prbp->prb_sge[seg].sge_da = 1234 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1235 prbp->prb_sge[seg].sge_dc = 1236 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1237 prbp->prb_sge[seg].sge_flags = htole32(0); 1238 } 1239 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1240 end: 1241 return 0; 1242 } 1243 1244 static void 1245 siisata_activate_prb(struct siisata_channel *schp, int slot) 1246 { 1247 struct siisata_softc *sc; 1248 bus_size_t offset; 1249 uint64_t pprb; 1250 1251 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1252 1253 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != __BIT(slot), 1254 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1255 1256 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1257 /* keep track of what's going on */ 1258 schp->sch_active_slots |= __BIT(slot); 1259 1260 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1261 1262 pprb = schp->sch_bus_prb[slot]; 1263 1264 PRWRITE(sc, offset + 0, pprb >> 0); 1265 PRWRITE(sc, offset + 4, pprb >> 32); 1266 } 1267 1268 static void 1269 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1270 { 1271 struct siisata_softc *sc; 1272 1273 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1274 1275 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1276 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1277 slot); 1278 1279 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1280 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1281 } 1282 1283 static void 1284 siisata_reinit_port(struct ata_channel *chp) 1285 { 1286 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1287 1288 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1289 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1290 DELAY(10); 1291 if (chp->ch_ndrives > 1) 1292 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1293 } 1294 1295 static void 1296 siisata_device_reset(struct ata_channel *chp) 1297 { 1298 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1299 1300 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1301 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1302 DELAY(10); 1303 } 1304 1305 1306 #if NATAPIBUS > 0 1307 void 1308 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1309 { 1310 struct ata_channel *chp = ata_sc->sc_chan; 1311 struct atac_softc *atac = chp->ch_atac; 1312 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1313 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1314 1315 /* 1316 * Fill in the scsipi_adapter. 1317 */ 1318 adapt->adapt_dev = atac->atac_dev; 1319 adapt->adapt_nchannels = atac->atac_nchannels; 1320 adapt->adapt_request = siisata_atapi_scsipi_request; 1321 adapt->adapt_minphys = siisata_atapi_minphys; 1322 atac->atac_atapi_adapter.atapi_probe_device = 1323 siisata_atapi_probe_device; 1324 1325 /* 1326 * Fill in the scsipi_channel. 1327 */ 1328 memset(chan, 0, sizeof(*chan)); 1329 chan->chan_adapter = adapt; 1330 chan->chan_bustype = &siisata_atapi_bustype; 1331 chan->chan_channel = chp->ch_channel; 1332 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1333 chan->chan_openings = 1; 1334 chan->chan_max_periph = 1; 1335 chan->chan_ntargets = 1; 1336 chan->chan_nluns = 1; 1337 1338 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1339 atapiprint); 1340 } 1341 1342 void 1343 siisata_atapi_minphys(struct buf *bp) 1344 { 1345 if (bp->b_bcount > MAXPHYS) 1346 bp->b_bcount = MAXPHYS; 1347 minphys(bp); 1348 } 1349 1350 /* 1351 * Kill off all pending xfers for a periph. 1352 * 1353 * Must be called at splbio(). 1354 */ 1355 void 1356 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1357 { 1358 struct atac_softc *atac = 1359 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1360 struct ata_channel *chp = 1361 atac->atac_channels[periph->periph_channel->chan_channel]; 1362 1363 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1364 } 1365 1366 void 1367 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1368 int reason) 1369 { 1370 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1371 1372 /* remove this command from xfer queue */ 1373 switch (reason) { 1374 case KILL_GONE: 1375 sc_xfer->error = XS_DRIVER_STUFFUP; 1376 break; 1377 case KILL_RESET: 1378 sc_xfer->error = XS_RESET; 1379 break; 1380 default: 1381 panic("%s: port %d: unknown reason %d", 1382 __func__, chp->ch_channel, reason); 1383 } 1384 ata_free_xfer(chp, xfer); 1385 scsipi_done(sc_xfer); 1386 } 1387 1388 void 1389 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1390 { 1391 struct scsipi_channel *chan = sc->sc_channel; 1392 struct scsipi_periph *periph; 1393 struct ataparams ids; 1394 struct ataparams *id = &ids; 1395 struct siisata_softc *siic = 1396 device_private(chan->chan_adapter->adapt_dev); 1397 struct atac_softc *atac = &siic->sc_atac; 1398 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1399 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1400 struct scsipibus_attach_args sa; 1401 char serial_number[21], model[41], firmware_revision[9]; 1402 int s; 1403 1404 /* skip if already attached */ 1405 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1406 return; 1407 1408 /* if no ATAPI device detected at attach time, skip */ 1409 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1410 SIISATA_DEBUG_PRINT(("%s: drive %d " 1411 "not present\n", __func__, target), DEBUG_PROBE); 1412 return; 1413 } 1414 1415 /* Some ATAPI devices need a bit more time after software reset. */ 1416 DELAY(5000); 1417 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1418 #ifdef ATAPI_DEBUG_PROBE 1419 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1420 device_xname(sc->sc_dev), target, 1421 id->atap_config & ATAPI_CFG_CMD_MASK, 1422 id->atap_config & ATAPI_CFG_DRQ_MASK); 1423 #endif 1424 periph = scsipi_alloc_periph(M_NOWAIT); 1425 if (periph == NULL) { 1426 aprint_error_dev(sc->sc_dev, 1427 "%s: unable to allocate periph for " 1428 "channel %d drive %d\n", __func__, 1429 chp->ch_channel, target); 1430 return; 1431 } 1432 periph->periph_dev = NULL; 1433 periph->periph_channel = chan; 1434 periph->periph_switch = &atapi_probe_periphsw; 1435 periph->periph_target = target; 1436 periph->periph_lun = 0; 1437 periph->periph_quirks = PQUIRK_ONLYBIG; 1438 1439 #ifdef SCSIPI_DEBUG 1440 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1441 SCSIPI_DEBUG_TARGET == target) 1442 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1443 #endif 1444 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1445 if (id->atap_config & ATAPI_CFG_REMOV) 1446 periph->periph_flags |= PERIPH_REMOVABLE; 1447 sa.sa_periph = periph; 1448 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1449 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1450 T_REMOV : T_FIXED; 1451 strnvisx(model, sizeof(model), id->atap_model, 40, 1452 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1453 strnvisx(serial_number, sizeof(serial_number), 1454 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1455 strnvisx(firmware_revision, sizeof(firmware_revision), 1456 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1457 sa.sa_inqbuf.vendor = model; 1458 sa.sa_inqbuf.product = serial_number; 1459 sa.sa_inqbuf.revision = firmware_revision; 1460 1461 /* 1462 * Determine the operating mode capabilities of the device. 1463 */ 1464 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1465 == ATAPI_CFG_CMD_16) { 1466 periph->periph_cap |= PERIPH_CAP_CMD16; 1467 1468 /* configure port for packet length */ 1469 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1470 PR_PC_PACKET_LENGTH); 1471 } else { 1472 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1473 PR_PC_PACKET_LENGTH); 1474 } 1475 1476 /* XXX This is gross. */ 1477 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1478 1479 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1480 1481 if (drvp->drv_softc) 1482 ata_probe_caps(drvp); 1483 else { 1484 s = splbio(); 1485 drvp->drive_type &= ATA_DRIVET_NONE; 1486 splx(s); 1487 } 1488 } else { 1489 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1490 "failed for drive %s:%d:%d: error 0x%x\n", 1491 __func__, SIISATANAME(siic), chp->ch_channel, target, 1492 chp->ch_error), DEBUG_PROBE); 1493 s = splbio(); 1494 drvp->drive_type &= ATA_DRIVET_NONE; 1495 splx(s); 1496 } 1497 } 1498 1499 void 1500 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1501 scsipi_adapter_req_t req, void *arg) 1502 { 1503 struct scsipi_adapter *adapt = chan->chan_adapter; 1504 struct scsipi_periph *periph; 1505 struct scsipi_xfer *sc_xfer; 1506 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1507 struct atac_softc *atac = &sc->sc_atac; 1508 struct ata_xfer *xfer; 1509 int channel = chan->chan_channel; 1510 int drive, s; 1511 1512 switch (req) { 1513 case ADAPTER_REQ_RUN_XFER: 1514 sc_xfer = arg; 1515 periph = sc_xfer->xs_periph; 1516 drive = periph->periph_target; 1517 1518 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1519 device_xname(atac->atac_dev), channel, drive), 1520 DEBUG_XFERS); 1521 1522 if (!device_is_active(atac->atac_dev)) { 1523 sc_xfer->error = XS_DRIVER_STUFFUP; 1524 scsipi_done(sc_xfer); 1525 return; 1526 } 1527 xfer = ata_get_xfer(atac->atac_channels[channel]); 1528 if (xfer == NULL) { 1529 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1530 scsipi_done(sc_xfer); 1531 return; 1532 } 1533 1534 if (sc_xfer->xs_control & XS_CTL_POLL) 1535 xfer->c_flags |= C_POLL; 1536 xfer->c_drive = drive; 1537 xfer->c_flags |= C_ATAPI; 1538 xfer->c_scsipi = sc_xfer; 1539 xfer->c_databuf = sc_xfer->data; 1540 xfer->c_bcount = sc_xfer->datalen; 1541 xfer->c_start = siisata_atapi_start; 1542 xfer->c_intr = siisata_atapi_complete; 1543 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1544 xfer->c_dscpoll = 0; 1545 s = splbio(); 1546 ata_exec_xfer(atac->atac_channels[channel], xfer); 1547 #ifdef DIAGNOSTIC 1548 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1549 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1550 panic("%s: polled command not done", __func__); 1551 #endif 1552 splx(s); 1553 return; 1554 1555 default: 1556 /* Not supported, nothing to do. */ 1557 ; 1558 } 1559 } 1560 1561 void 1562 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1563 { 1564 struct siisata_channel *schp = (struct siisata_channel *)chp; 1565 struct siisata_prb *prbp; 1566 1567 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1568 1569 int slot = SIISATA_NON_NCQ_SLOT; 1570 int i; 1571 1572 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1573 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1574 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1575 DEBUG_XFERS); 1576 1577 chp->ch_status = 0; 1578 chp->ch_error = 0; 1579 1580 prbp = schp->sch_prb[slot]; 1581 memset(prbp, 0, sizeof(struct siisata_prb)); 1582 1583 1584 /* fill in direction for ATAPI command */ 1585 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1586 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1587 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1588 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1589 1590 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1591 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1592 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1593 1594 /* copy over ATAPI command */ 1595 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1596 1597 if (siisata_dma_setup(chp, slot, 1598 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1599 xfer->c_databuf : NULL, 1600 xfer->c_bcount, 1601 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1602 BUS_DMA_READ : BUS_DMA_WRITE) 1603 ) 1604 panic("%s", __func__); 1605 1606 if (xfer->c_flags & C_POLL) { 1607 /* polled command, disable interrupts */ 1608 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1609 siisata_disable_port_interrupt(chp); 1610 } 1611 1612 siisata_activate_prb(schp, slot); 1613 1614 if ((xfer->c_flags & C_POLL) == 0) { 1615 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1616 callout_reset(&xfer->c_timo_callout, mstohz(sc_xfer->timeout), 1617 siisata_timeout, xfer); 1618 goto out; 1619 } 1620 1621 /* 1622 * polled command 1623 */ 1624 for (i = 0; i < ATA_DELAY / 10; i++) { 1625 if (sc_xfer->xs_status & XS_STS_DONE) 1626 break; 1627 siisata_intr_port(schp); 1628 DELAY(1000); 1629 } 1630 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1631 siisata_timeout(xfer); 1632 } 1633 /* reenable interrupts */ 1634 siisata_enable_port_interrupt(chp); 1635 out: 1636 SIISATA_DEBUG_PRINT( 1637 ("%s: %s: done\n", SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), DEBUG_FUNCS); 1638 return; 1639 } 1640 1641 int 1642 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1643 int slot) 1644 { 1645 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1646 struct siisata_channel *schp = (struct siisata_channel *)chp; 1647 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1648 1649 SIISATA_DEBUG_PRINT( 1650 ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1651 1652 /* this comamnd is not active any more */ 1653 schp->sch_active_slots &= ~__BIT(slot); 1654 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1655 if (xfer->c_flags & C_TIMEOU) { 1656 sc_xfer->error = XS_TIMEOUT; 1657 } else { 1658 callout_stop(&xfer->c_timo_callout); 1659 sc_xfer->error = XS_NOERROR; 1660 } 1661 1662 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1663 schp->sch_datad[slot]->dm_mapsize, 1664 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1665 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1666 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1667 1668 ata_deactivate_xfer(chp, xfer); 1669 1670 if (!ata_waitdrain_xfer_check(chp, xfer)) { 1671 sc_xfer->error = XS_DRIVER_STUFFUP; 1672 return 0; /* XXX verify */ 1673 } 1674 1675 ata_free_xfer(chp, xfer); 1676 sc_xfer->resid = sc_xfer->datalen; 1677 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1678 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1679 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1680 if ((chp->ch_status & WDCS_ERR) && 1681 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1682 sc_xfer->resid == sc_xfer->datalen)) { 1683 sc_xfer->error = XS_SHORTSENSE; 1684 sc_xfer->sense.atapi_sense = chp->ch_error; 1685 if ((sc_xfer->xs_periph->periph_quirks & 1686 PQUIRK_NOSENSE) == 0) { 1687 /* request sense */ 1688 sc_xfer->error = XS_BUSY; 1689 sc_xfer->status = SCSI_CHECK; 1690 } 1691 } 1692 scsipi_done(sc_xfer); 1693 atastart(chp); 1694 return 0; /* XXX verify */ 1695 } 1696 1697 #endif /* NATAPIBUS */ 1698
Indexes created Mon Oct 20 01:09:56 GMT 2025