siisata.c revision 1.32
1 /* $NetBSD: siisata.c,v 1.32 2017/04/24 13:19:50 jakllsch Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.32 2017/04/24 13:19:50 jakllsch Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/malloc.h> 86 #include <sys/param.h> 87 #include <sys/kernel.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 113 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 114 #if _BYTE_ORDER == _LITTLE_ENDIAN 115 #define bus_space_read_stream_4 bus_space_read_4 116 #define bus_space_read_region_stream_4 bus_space_read_region_4 117 #else 118 static inline uint32_t 119 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 120 { 121 return htole32(bus_space_read_4(t, h, o)); 122 } 123 124 static inline void 125 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 126 bus_size_t o, uint32_t *p, bus_size_t c) 127 { 128 bus_space_read_region_4(t, h, o, p, c); 129 for (bus_size_t i = 0; i < c; i++) { 130 p[i] = htole32(p[i]); 131 } 132 } 133 #endif 134 #endif 135 136 static void siisata_attach_port(struct siisata_softc *, int); 137 static void siisata_intr_port(struct siisata_channel *); 138 139 void siisata_probe_drive(struct ata_channel *); 140 void siisata_setup_channel(struct ata_channel *); 141 142 int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); 143 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 144 void siisata_reset_channel(struct ata_channel *, int); 145 int siisata_ata_addref(struct ata_drive_datas *); 146 void siisata_ata_delref(struct ata_drive_datas *); 147 void siisata_killpending(struct ata_drive_datas *); 148 149 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 150 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 151 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 153 154 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 155 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 156 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); 158 159 void siisata_timeout(void *); 160 161 static void siisata_reinit_port(struct ata_channel *); 162 static void siisata_device_reset(struct ata_channel *); 163 static void siisata_activate_prb(struct siisata_channel *, int); 164 static void siisata_deactivate_prb(struct siisata_channel *, int); 165 static int siisata_dma_setup(struct ata_channel *chp, int, void *, 166 size_t, int); 167 168 #if NATAPIBUS > 0 169 void siisata_atapibus_attach(struct atabus_softc *); 170 void siisata_atapi_probe_device(struct atapibus_softc *, int); 171 void siisata_atapi_minphys(struct buf *); 172 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 173 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 174 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 175 void siisata_atapi_scsipi_request(struct scsipi_channel *, 176 scsipi_adapter_req_t, void *); 177 void siisata_atapi_kill_pending(struct scsipi_periph *); 178 #endif /* NATAPIBUS */ 179 180 const struct ata_bustype siisata_ata_bustype = { 181 SCSIPI_BUSTYPE_ATA, 182 siisata_ata_bio, 183 siisata_reset_drive, 184 siisata_reset_channel, 185 siisata_exec_command, 186 ata_get_params, 187 siisata_ata_addref, 188 siisata_ata_delref, 189 siisata_killpending 190 }; 191 192 #if NATAPIBUS > 0 193 static const struct scsipi_bustype siisata_atapi_bustype = { 194 SCSIPI_BUSTYPE_ATAPI, 195 atapi_scsipi_cmd, 196 atapi_interpret_sense, 197 atapi_print_addr, 198 siisata_atapi_kill_pending, 199 NULL, 200 }; 201 #endif /* NATAPIBUS */ 202 203 204 void 205 siisata_attach(struct siisata_softc *sc) 206 { 207 int i; 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 211 212 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 213 sc->sc_atac.atac_pio_cap = 4; 214 sc->sc_atac.atac_dma_cap = 2; 215 sc->sc_atac.atac_udma_cap = 6; 216 sc->sc_atac.atac_channels = sc->sc_chanarray; 217 sc->sc_atac.atac_probe = siisata_probe_drive; 218 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 219 sc->sc_atac.atac_set_modes = siisata_setup_channel; 220 #if NATAPIBUS > 0 221 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 222 #endif 223 224 /* come out of reset state */ 225 GRWRITE(sc, GR_GC, 0); 226 227 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 228 siisata_attach_port(sc, i); 229 } 230 231 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 232 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 233 return; 234 } 235 236 static void 237 siisata_disable_port_interrupt(struct ata_channel *chp) 238 { 239 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 240 241 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 242 } 243 244 static void 245 siisata_enable_port_interrupt(struct ata_channel *chp) 246 { 247 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 248 249 /* clear any interrupts */ 250 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 251 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 252 /* and enable CmdErrr+CmdCmpl interrupting */ 253 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 254 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 255 } 256 257 static void 258 siisata_init_port(struct siisata_softc *sc, int port) 259 { 260 struct siisata_channel *schp; 261 struct ata_channel *chp; 262 263 schp = &sc->sc_channels[port]; 264 chp = (struct ata_channel *)schp; 265 266 /* come out of reset, 64-bit activation */ 267 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 268 PR_PC_32BA | PR_PC_PORT_RESET); 269 /* initialize port */ 270 siisata_reinit_port(chp); 271 /* enable CmdErrr+CmdCmpl interrupting */ 272 siisata_enable_port_interrupt(chp); 273 /* enable port interrupt */ 274 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 275 } 276 277 static void 278 siisata_attach_port(struct siisata_softc *sc, int port) 279 { 280 int j; 281 int dmasize; 282 int error; 283 void *prbp; 284 struct siisata_channel *schp; 285 struct ata_channel *chp; 286 287 schp = &sc->sc_channels[port]; 288 chp = (struct ata_channel *)schp; 289 sc->sc_chanarray[port] = chp; 290 chp->ch_channel = port; 291 chp->ch_atac = &sc->sc_atac; 292 chp->ch_queue = malloc(sizeof(struct ata_queue), 293 M_DEVBUF, M_NOWAIT|M_ZERO); 294 if (chp->ch_queue == NULL) { 295 aprint_error_dev(sc->sc_atac.atac_dev, 296 "port %d: can't allocate memory " 297 "for command queue\n", chp->ch_channel); 298 return; 299 } 300 301 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 302 303 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 304 __func__, dmasize), DEBUG_FUNCS); 305 306 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 307 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 308 if (error) { 309 aprint_error_dev(sc->sc_atac.atac_dev, 310 "unable to allocate PRB table memory, " 311 "error=%d\n", error); 312 return; 313 } 314 315 error = bus_dmamem_map(sc->sc_dmat, 316 &schp->sch_prb_seg, schp->sch_prb_nseg, 317 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 318 if (error) { 319 aprint_error_dev(sc->sc_atac.atac_dev, 320 "unable to map PRB table memory, " 321 "error=%d\n", error); 322 bus_dmamem_free(sc->sc_dmat, 323 &schp->sch_prb_seg, schp->sch_prb_nseg); 324 return; 325 } 326 327 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 328 BUS_DMA_NOWAIT, &schp->sch_prbd); 329 if (error) { 330 aprint_error_dev(sc->sc_atac.atac_dev, 331 "unable to create PRB table map, " 332 "error=%d\n", error); 333 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 334 bus_dmamem_free(sc->sc_dmat, 335 &schp->sch_prb_seg, schp->sch_prb_nseg); 336 return; 337 } 338 339 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 340 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 341 if (error) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "unable to load PRB table map, " 344 "error=%d\n", error); 345 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 346 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 347 bus_dmamem_free(sc->sc_dmat, 348 &schp->sch_prb_seg, schp->sch_prb_nseg); 349 return; 350 } 351 352 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 353 schp->sch_prb[j] = (struct siisata_prb *) 354 ((char *)prbp + SIISATA_CMD_SIZE * j); 355 schp->sch_bus_prb[j] = 356 schp->sch_prbd->dm_segs[0].ds_addr + 357 SIISATA_CMD_SIZE * j; 358 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 359 SIISATA_NSGE, MAXPHYS, 0, 360 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 361 &schp->sch_datad[j]); 362 if (error) { 363 aprint_error_dev(sc->sc_atac.atac_dev, 364 "couldn't create xfer DMA map, error=%d\n", 365 error); 366 return; 367 } 368 } 369 370 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 371 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 372 aprint_error_dev(sc->sc_atac.atac_dev, 373 "couldn't map port %d SStatus regs\n", 374 chp->ch_channel); 375 return; 376 } 377 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 378 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 379 aprint_error_dev(sc->sc_atac.atac_dev, 380 "couldn't map port %d SControl regs\n", 381 chp->ch_channel); 382 return; 383 } 384 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 385 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 386 aprint_error_dev(sc->sc_atac.atac_dev, 387 "couldn't map port %d SError regs\n", 388 chp->ch_channel); 389 return; 390 } 391 392 siisata_init_port(sc, port); 393 394 ata_channel_attach(chp); 395 396 return; 397 } 398 399 int 400 siisata_detach(struct siisata_softc *sc, int flags) 401 { 402 struct atac_softc *atac = &sc->sc_atac; 403 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 404 struct siisata_channel *schp; 405 struct ata_channel *chp; 406 int i, j, error; 407 408 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 409 schp = &sc->sc_channels[i]; 410 chp = sc->sc_chanarray[i]; 411 412 if (chp->atabus == NULL) 413 continue; 414 if ((error = config_detach(chp->atabus, flags)) != 0) 415 return error; 416 417 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 418 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 419 420 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 421 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 422 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 423 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 424 bus_dmamem_free(sc->sc_dmat, 425 &schp->sch_prb_seg, schp->sch_prb_nseg); 426 427 free(chp->ch_queue, M_DEVBUF); 428 chp->atabus = NULL; 429 } 430 431 if (adapt->adapt_refcnt != 0) 432 return EBUSY; 433 434 /* leave the chip in reset */ 435 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 436 437 return 0; 438 } 439 440 void 441 siisata_resume(struct siisata_softc *sc) 442 { 443 int i; 444 445 /* come out of reset state */ 446 GRWRITE(sc, GR_GC, 0); 447 448 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 449 siisata_init_port(sc, i); 450 } 451 452 } 453 454 int 455 siisata_intr(void *v) 456 { 457 struct siisata_softc *sc = v; 458 uint32_t is; 459 int i, r = 0; 460 while ((is = GRREAD(sc, GR_GIS))) { 461 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 462 SIISATANAME(sc), __func__, is), DEBUG_INTR); 463 r = 1; 464 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 465 if (is & GR_GIS_PXIS(i)) 466 siisata_intr_port(&sc->sc_channels[i]); 467 } 468 return r; 469 } 470 471 static void 472 siisata_intr_port(struct siisata_channel *schp) 473 { 474 struct siisata_softc *sc; 475 struct ata_channel *chp; 476 struct ata_xfer *xfer; 477 int slot; 478 uint32_t pss, pis; 479 uint32_t prbfis; 480 481 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 482 chp = &schp->ata_channel; 483 xfer = chp->ch_queue->active_xfer; 484 slot = SIISATA_NON_NCQ_SLOT; 485 486 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 487 488 SIISATA_DEBUG_PRINT(("%s: %s port %d, pis 0x%x ", SIISATANAME(sc), 489 __func__, chp->ch_channel, pis), DEBUG_INTR); 490 491 if (pis & PR_PIS_CMDCMPL) { 492 /* get slot status, clearing completion interrupt */ 493 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 494 SIISATA_DEBUG_PRINT(("pss 0x%x\n", pss), DEBUG_INTR); 495 /* is this expected? */ 496 /* XXX improve */ 497 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 498 aprint_error( "%s: unexpected command " 499 "completion on port %d\n", 500 SIISATANAME(sc), chp->ch_channel); 501 return; 502 } 503 if ((~pss & __BIT(slot)) == 0) { 504 aprint_error( "%s: unknown slot " 505 "completion on port %d, pss 0x%x\n", 506 SIISATANAME(sc), chp->ch_channel, pss); 507 return; 508 } 509 } else if (pis & PR_PIS_CMDERRR) { 510 uint32_t ec; 511 512 /* emulate a CRC error by default */ 513 chp->ch_status = WDCS_ERR; 514 chp->ch_error = WDCE_CRC; 515 516 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 517 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 518 if (ec <= PR_PCE_DATAFISERROR) { 519 if (ec == PR_PCE_DEVICEERROR && xfer != NULL) { 520 /* read in specific information about error */ 521 prbfis = bus_space_read_stream_4( 522 sc->sc_prt, sc->sc_prh, 523 PRSX(chp->ch_channel, slot, PRSO_FIS)); 524 /* set ch_status and ch_error */ 525 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 526 } 527 siisata_reinit_port(chp); 528 } else { 529 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 530 " on channel %d (ctx 0x%x), resetting\n", 531 ec, chp->ch_channel, 532 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 533 /* okay, we have a "Fatal Error" */ 534 siisata_device_reset(chp); 535 } 536 } 537 538 /* clear some (ok, all) ints */ 539 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 540 if (xfer && xfer->c_intr) 541 xfer->c_intr(chp, xfer, slot); 542 543 return; 544 } 545 546 void 547 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 548 { 549 struct ata_channel *chp = drvp->chnl_softc; 550 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 551 struct siisata_channel *schp = (struct siisata_channel *)chp; 552 struct siisata_prb *prb; 553 int slot = SIISATA_NON_NCQ_SLOT; 554 int i; 555 556 /* wait for ready */ 557 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 558 DELAY(10); 559 560 prb = schp->sch_prb[slot]; 561 memset(prb, 0, sizeof(struct siisata_prb)); 562 prb->prb_control = 563 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 564 KASSERT(drvp->drive <= PMP_PORT_CTL); 565 prb->prb_fis[rhd_c] = drvp->drive; 566 567 siisata_activate_prb(schp, slot); 568 569 for(i = 0; i < 3100; i++) { 570 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 571 PR_PXSS(slot)) == 0) 572 break; 573 if (flags & AT_WAIT) 574 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 575 else 576 DELAY(10000); 577 } 578 579 siisata_deactivate_prb(schp, slot); 580 if (i == 3100) { 581 /* timeout */ 582 siisata_device_reset(chp); 583 if (sigp) 584 *sigp = 0xffffffff; 585 } else { 586 /* read the signature out of the FIS */ 587 if (sigp) { 588 *sigp = 0; 589 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 590 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 591 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, slot, 592 PRSO_FIS+0xc)) & 0xff; 593 } 594 } 595 596 #if 1 597 /* attempt to downgrade signaling in event of CRC error */ 598 /* XXX should be part of the MI (S)ATA subsystem */ 599 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 600 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 601 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 602 DELAY(10); 603 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 604 SControl_IPM_NONE | SControl_SPD_G1); 605 DELAY(10); 606 for (;;) { 607 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 608 & SStatus_DET_mask) == SStatus_DET_DEV) 609 break; 610 DELAY(10); 611 } 612 } 613 #endif 614 615 #if 1 616 chp->ch_status = 0; 617 chp->ch_error = 0; 618 #endif 619 return; 620 } 621 622 void 623 siisata_reset_channel(struct ata_channel *chp, int flags) 624 { 625 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 626 struct siisata_channel *schp = (struct siisata_channel *)chp; 627 628 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 629 DEBUG_FUNCS); 630 631 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 632 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 633 aprint_error("%s port %d: reset failed\n", 634 SIISATANAME(sc), chp->ch_channel); 635 /* XXX and then ? */ 636 } 637 /* wait for ready */ 638 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 639 DELAY(10); 640 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 641 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 642 if (chp->ch_queue->active_xfer) { 643 chp->ch_queue->active_xfer->c_kill_xfer(chp, 644 chp->ch_queue->active_xfer, KILL_RESET); 645 } 646 647 return; 648 } 649 650 int 651 siisata_ata_addref(struct ata_drive_datas *drvp) 652 { 653 return 0; 654 } 655 656 void 657 siisata_ata_delref(struct ata_drive_datas *drvp) 658 { 659 return; 660 } 661 662 void 663 siisata_killpending(struct ata_drive_datas *drvp) 664 { 665 return; 666 } 667 668 void 669 siisata_probe_drive(struct ata_channel *chp) 670 { 671 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 672 struct siisata_channel *schp = (struct siisata_channel *)chp; 673 int i; 674 uint32_t sig; 675 int slot = SIISATA_NON_NCQ_SLOT; 676 struct siisata_prb *prb; 677 bool timed_out; 678 679 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 680 __func__, chp->ch_channel), DEBUG_FUNCS); 681 682 /* 683 * disable port interrupt as we're polling for PHY up and 684 * prb completion 685 */ 686 siisata_disable_port_interrupt(chp); 687 688 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 689 schp->sch_sstatus, AT_WAIT)) { 690 case SStatus_DET_DEV: 691 /* clear any interrupts */ 692 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 693 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 694 /* wait for ready */ 695 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 696 & PR_PS_PORT_READY)) 697 DELAY(10); 698 prb = schp->sch_prb[slot]; 699 memset(prb, 0, sizeof(struct siisata_prb)); 700 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 701 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 702 703 siisata_activate_prb(schp, slot); 704 705 timed_out = 1; 706 for(i = 0; i < 3100; i++) { 707 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 708 PR_PXSS(slot)) == 0) { 709 /* prb completed */ 710 timed_out = 0; 711 break; 712 } 713 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 714 (PR_PIS_CMDERRR << 16)) { 715 /* we got an error; handle as timeout */ 716 break; 717 } 718 719 tsleep(schp, PRIBIO, "siiprb", mstohz(10)); 720 } 721 722 siisata_deactivate_prb(schp, slot); 723 if (timed_out) { 724 aprint_error_dev(sc->sc_atac.atac_dev, 725 "SOFT_RESET failed on port %d (error %d PSS 0x%x), " 726 "resetting\n", chp->ch_channel, 727 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 728 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS))); 729 siisata_reinit_port(chp); 730 break; 731 } 732 733 /* read the signature out of the FIS */ 734 sig = 0; 735 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 736 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 737 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 738 PRSO_FIS+0xc)) & 0xff; 739 740 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 741 __func__, sig), DEBUG_PROBE); 742 743 if (sig == 0x96690101) 744 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 745 PR_PC_PMP_ENABLE); 746 sata_interpret_sig(chp, 0, sig); 747 break; 748 default: 749 break; 750 } 751 752 siisata_enable_port_interrupt(chp); 753 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 754 __func__, chp->ch_channel), DEBUG_PROBE); 755 return; 756 } 757 758 void 759 siisata_setup_channel(struct ata_channel *chp) 760 { 761 return; 762 } 763 764 int 765 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 766 { 767 struct ata_channel *chp = drvp->chnl_softc; 768 struct ata_xfer *xfer; 769 int ret; 770 int s; 771 772 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 773 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 774 DEBUG_FUNCS); 775 776 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? 777 ATAXF_CANSLEEP : ATAXF_NOSLEEP); 778 if (xfer == NULL) 779 return ATACMD_TRY_AGAIN; 780 if (ata_c->flags & AT_POLL) 781 xfer->c_flags |= C_POLL; 782 if (ata_c->flags & AT_WAIT) 783 xfer->c_flags |= C_WAIT; 784 xfer->c_drive = drvp->drive; 785 xfer->c_databuf = ata_c->data; 786 xfer->c_bcount = ata_c->bcount; 787 xfer->c_cmd = ata_c; 788 xfer->c_start = siisata_cmd_start; 789 xfer->c_intr = siisata_cmd_complete; 790 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 791 s = splbio(); 792 ata_exec_xfer(chp, xfer); 793 #ifdef DIAGNOSTIC 794 if ((ata_c->flags & AT_POLL) != 0 && 795 (ata_c->flags & AT_DONE) == 0) 796 panic("%s: polled command not done", __func__); 797 #endif 798 if (ata_c->flags & AT_DONE) { 799 ret = ATACMD_COMPLETE; 800 } else { 801 if (ata_c->flags & AT_WAIT) { 802 while ((ata_c->flags & AT_DONE) == 0) { 803 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 804 SIISATANAME( 805 (struct siisata_softc *)chp->ch_atac), 806 __func__), DEBUG_FUNCS); 807 tsleep(ata_c, PRIBIO, "siicmd", 0); 808 } 809 ret = ATACMD_COMPLETE; 810 } else { 811 ret = ATACMD_QUEUED; 812 } 813 } 814 splx(s); 815 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 816 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 817 DEBUG_FUNCS); 818 return ret; 819 } 820 821 void 822 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 823 { 824 struct siisata_channel *schp = (struct siisata_channel *)chp; 825 struct ata_command *ata_c = xfer->c_cmd; 826 int slot = SIISATA_NON_NCQ_SLOT; 827 struct siisata_prb *prb; 828 int i; 829 830 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 831 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 832 chp->ch_channel, xfer->c_drive, ata_c->r_command, slot), 833 DEBUG_FUNCS|DEBUG_XFERS); 834 835 chp->ch_status = 0; 836 chp->ch_error = 0; 837 838 prb = schp->sch_prb[slot]; 839 memset(prb, 0, sizeof(struct siisata_prb)); 840 841 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 842 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 843 prb->prb_fis[rhd_c] |= xfer->c_drive; 844 845 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 846 847 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 848 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 849 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 850 } 851 852 if (siisata_dma_setup(chp, slot, 853 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 854 ata_c->bcount, 855 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 856 ata_c->flags |= AT_DF; 857 siisata_cmd_complete(chp, xfer, slot); 858 return; 859 } 860 861 if (xfer->c_flags & C_POLL) { 862 /* polled command, disable interrupts */ 863 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 864 siisata_disable_port_interrupt(chp); 865 } 866 867 /* go for it */ 868 siisata_activate_prb(schp, slot); 869 870 if ((ata_c->flags & AT_POLL) == 0) { 871 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 872 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 873 siisata_timeout, chp); 874 goto out; 875 } 876 877 /* 878 * polled command 879 */ 880 for (i = 0; i < ata_c->timeout / 10; i++) { 881 if (ata_c->flags & AT_DONE) 882 break; 883 siisata_intr_port(schp); 884 DELAY(1000); 885 } 886 887 if ((ata_c->flags & AT_DONE) == 0) { 888 siisata_timeout(chp); 889 } 890 891 /* reenable interrupts */ 892 siisata_enable_port_interrupt(chp); 893 out: 894 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 895 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 896 DEBUG_FUNCS); 897 return; 898 } 899 900 void 901 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 902 int reason) 903 { 904 int slot = SIISATA_NON_NCQ_SLOT; 905 906 struct ata_command *ata_c = xfer->c_cmd; 907 switch (reason) { 908 case KILL_GONE: 909 ata_c->flags |= AT_GONE; 910 break; 911 case KILL_RESET: 912 ata_c->flags |= AT_RESET; 913 break; 914 default: 915 panic("%s: port %d: unknown reason %d", 916 __func__, chp->ch_channel, reason); 917 } 918 siisata_cmd_done(chp, xfer, slot); 919 } 920 921 int 922 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 923 { 924 struct ata_command *ata_c = xfer->c_cmd; 925 #ifdef SIISATA_DEBUG 926 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 927 #endif 928 929 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 930 DEBUG_FUNCS|DEBUG_XFERS); 931 932 chp->ch_flags &= ~ATACH_IRQ_WAIT; 933 if (xfer->c_flags & C_TIMEOU) 934 ata_c->flags |= AT_TIMEOU; 935 else 936 callout_stop(&chp->ch_callout); 937 938 if (chp->ch_status & WDCS_BSY) { 939 ata_c->flags |= AT_TIMEOU; 940 } else if (chp->ch_status & WDCS_ERR) { 941 ata_c->r_error = chp->ch_error; 942 ata_c->flags |= AT_ERROR; 943 } 944 945 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 946 siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); 947 chp->ch_drive[xfer->c_drive].drive_flags &= 948 ~ATA_DRIVE_WAITDRAIN; 949 wakeup(&chp->ch_queue->active_xfer); 950 return 0; 951 } else 952 siisata_cmd_done(chp, xfer, slot); 953 954 return 0; 955 } 956 957 void 958 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 959 { 960 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 961 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 962 struct siisata_channel *schp = (struct siisata_channel *)chp; 963 struct ata_command *ata_c = xfer->c_cmd; 964 uint16_t *idwordbuf; 965 int i; 966 967 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 968 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 969 970 siisata_deactivate_prb(schp, slot); 971 972 if (ata_c->flags & (AT_READ | AT_WRITE)) { 973 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 974 schp->sch_datad[slot]->dm_mapsize, 975 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 976 BUS_DMASYNC_POSTWRITE); 977 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 978 } 979 980 if (ata_c->flags & AT_READREG) { 981 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 982 PRSX(chp->ch_channel, slot, PRSO_FIS), 983 fis, __arraycount(fis)); 984 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 985 } 986 987 /* correct the endianess of IDENTIFY data */ 988 if (ata_c->r_command == WDCC_IDENTIFY || 989 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 990 idwordbuf = xfer->c_databuf; 991 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 992 idwordbuf[i] = le16toh(idwordbuf[i]); 993 } 994 } 995 996 ata_c->flags |= AT_DONE; 997 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 998 ata_c->flags |= AT_XFDONE; 999 1000 chp->ch_queue->active_xfer = NULL; 1001 ata_free_xfer(chp, xfer); 1002 if (ata_c->flags & AT_WAIT) 1003 wakeup(ata_c); 1004 else if (ata_c->callback) 1005 ata_c->callback(ata_c->callback_arg); 1006 atastart(chp); 1007 return; 1008 } 1009 1010 int 1011 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 1012 { 1013 struct ata_channel *chp = drvp->chnl_softc; 1014 struct ata_xfer *xfer; 1015 1016 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1017 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1018 DEBUG_FUNCS); 1019 1020 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1021 if (xfer == NULL) 1022 return ATACMD_TRY_AGAIN; 1023 if (ata_bio->flags & ATA_POLL) 1024 xfer->c_flags |= C_POLL; 1025 xfer->c_drive = drvp->drive; 1026 xfer->c_cmd = ata_bio; 1027 xfer->c_databuf = ata_bio->databuf; 1028 xfer->c_bcount = ata_bio->bcount; 1029 xfer->c_start = siisata_bio_start; 1030 xfer->c_intr = siisata_bio_complete; 1031 xfer->c_kill_xfer = siisata_bio_kill_xfer; 1032 ata_exec_xfer(chp, xfer); 1033 return (ata_bio->flags & ATA_ITSDONE) ? 1034 ATACMD_COMPLETE : ATACMD_QUEUED; 1035 } 1036 1037 void 1038 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1039 { 1040 struct siisata_channel *schp = (struct siisata_channel *)chp; 1041 struct siisata_prb *prb; 1042 struct ata_bio *ata_bio = xfer->c_cmd; 1043 int slot = SIISATA_NON_NCQ_SLOT; 1044 int i; 1045 1046 SIISATA_DEBUG_PRINT(("%s: %s port %d, slot %d\n", 1047 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1048 chp->ch_channel, slot), DEBUG_FUNCS); 1049 1050 chp->ch_status = 0; 1051 chp->ch_error = 0; 1052 1053 prb = schp->sch_prb[slot]; 1054 memset(prb, 0, sizeof(struct siisata_prb)); 1055 1056 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1057 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1058 prb->prb_fis[rhd_c] |= xfer->c_drive; 1059 1060 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 1061 1062 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 1063 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1064 ata_bio->error = ERR_DMA; 1065 ata_bio->r_error = 0; 1066 siisata_bio_complete(chp, xfer, slot); 1067 return; 1068 } 1069 1070 if (xfer->c_flags & C_POLL) { 1071 /* polled command, disable interrupts */ 1072 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1073 siisata_disable_port_interrupt(chp); 1074 } 1075 1076 siisata_activate_prb(schp, slot); 1077 1078 if ((ata_bio->flags & ATA_POLL) == 0) { 1079 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1080 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1081 siisata_timeout, chp); 1082 goto out; 1083 } 1084 1085 /* 1086 * polled command 1087 */ 1088 for (i = 0; i < ATA_DELAY / 10; i++) { 1089 if (ata_bio->flags & ATA_ITSDONE) 1090 break; 1091 siisata_intr_port(schp); 1092 DELAY(1000); 1093 } 1094 1095 siisata_enable_port_interrupt(chp); 1096 out: 1097 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1098 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1099 DEBUG_FUNCS); 1100 return; 1101 } 1102 1103 void 1104 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1105 int reason) 1106 { 1107 struct siisata_channel *schp = (struct siisata_channel *)chp; 1108 struct ata_bio *ata_bio = xfer->c_cmd; 1109 int drive = xfer->c_drive; 1110 int slot = SIISATA_NON_NCQ_SLOT; 1111 1112 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1113 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1114 chp->ch_channel), DEBUG_FUNCS); 1115 1116 siisata_deactivate_prb(schp, slot); 1117 1118 ata_free_xfer(chp, xfer); 1119 ata_bio->flags |= ATA_ITSDONE; 1120 switch (reason) { 1121 case KILL_GONE: 1122 ata_bio->error = ERR_NODEV; 1123 break; 1124 case KILL_RESET: 1125 ata_bio->error = ERR_RESET; 1126 break; 1127 default: 1128 panic("%s: port %d: unknown reason %d", 1129 __func__, chp->ch_channel, reason); 1130 } 1131 ata_bio->r_error = WDCE_ABRT; 1132 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1133 } 1134 1135 int 1136 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1137 { 1138 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1139 struct siisata_channel *schp = (struct siisata_channel *)chp; 1140 struct ata_bio *ata_bio = xfer->c_cmd; 1141 int drive = xfer->c_drive; 1142 1143 schp->sch_active_slots &= ~__BIT(slot); 1144 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1145 if (xfer->c_flags & C_TIMEOU) { 1146 ata_bio->error = TIMEOUT; 1147 } else { 1148 callout_stop(&chp->ch_callout); 1149 ata_bio->error = NOERROR; 1150 } 1151 1152 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1153 schp->sch_datad[slot]->dm_mapsize, 1154 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1155 BUS_DMASYNC_POSTWRITE); 1156 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1157 1158 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1159 siisata_bio_kill_xfer(chp, xfer, KILL_GONE); 1160 chp->ch_drive[xfer->c_drive].drive_flags &= 1161 ~ATA_DRIVE_WAITDRAIN; 1162 wakeup(&chp->ch_queue->active_xfer); 1163 return 0; 1164 } 1165 1166 chp->ch_queue->active_xfer = NULL; 1167 ata_free_xfer(chp, xfer); 1168 ata_bio->flags |= ATA_ITSDONE; 1169 if (chp->ch_status & WDCS_DWF) { 1170 ata_bio->error = ERR_DF; 1171 } else if (chp->ch_status & WDCS_ERR) { 1172 ata_bio->error = ERROR; 1173 ata_bio->r_error = chp->ch_error; 1174 } else if (chp->ch_status & WDCS_CORR) 1175 ata_bio->flags |= ATA_CORR; 1176 1177 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1178 ata_bio->bcount), DEBUG_XFERS); 1179 if (ata_bio->error == NOERROR) { 1180 if (ata_bio->flags & ATA_READ) 1181 ata_bio->bcount -= 1182 PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1183 else 1184 ata_bio->bcount = 0; 1185 } 1186 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1187 if (ata_bio->flags & ATA_POLL) 1188 return 1; 1189 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1190 atastart(chp); 1191 return 0; 1192 } 1193 1194 void 1195 siisata_timeout(void *v) 1196 { 1197 struct ata_channel *chp = (struct ata_channel *)v; 1198 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1199 int slot = SIISATA_NON_NCQ_SLOT; 1200 int s = splbio(); 1201 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1202 siisata_device_reset(chp); 1203 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1204 xfer->c_flags |= C_TIMEOU; 1205 xfer->c_intr(chp, xfer, slot); 1206 } 1207 splx(s); 1208 } 1209 1210 static int 1211 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1212 size_t count, int op) 1213 { 1214 1215 int error, seg; 1216 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1217 struct siisata_channel *schp = (struct siisata_channel *)chp; 1218 1219 struct siisata_prb *prbp; 1220 1221 prbp = schp->sch_prb[slot]; 1222 1223 if (data == NULL) { 1224 goto end; 1225 } 1226 1227 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1228 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1229 if (error) { 1230 aprint_error("%s port %d: " 1231 "failed to load xfer in slot %d: error %d\n", 1232 SIISATANAME(sc), chp->ch_channel, slot, error); 1233 return error; 1234 } 1235 1236 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1237 schp->sch_datad[slot]->dm_mapsize, 1238 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1239 1240 /* make sure it's clean */ 1241 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1242 1243 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1244 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1245 DEBUG_FUNCS | DEBUG_DEBUG); 1246 1247 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1248 prbp->prb_sge[seg].sge_da = 1249 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1250 prbp->prb_sge[seg].sge_dc = 1251 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1252 prbp->prb_sge[seg].sge_flags = htole32(0); 1253 } 1254 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1255 end: 1256 return 0; 1257 } 1258 1259 static void 1260 siisata_activate_prb(struct siisata_channel *schp, int slot) 1261 { 1262 struct siisata_softc *sc; 1263 bus_size_t offset; 1264 uint64_t pprb; 1265 1266 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1267 1268 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != __BIT(slot), 1269 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1270 1271 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1272 /* keep track of what's going on */ 1273 schp->sch_active_slots |= __BIT(slot); 1274 1275 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1276 1277 pprb = schp->sch_bus_prb[slot]; 1278 1279 PRWRITE(sc, offset + 0, pprb >> 0); 1280 PRWRITE(sc, offset + 4, pprb >> 32); 1281 } 1282 1283 static void 1284 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1285 { 1286 struct siisata_softc *sc; 1287 1288 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1289 1290 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1291 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1292 slot); 1293 1294 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1295 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1296 } 1297 1298 static void 1299 siisata_reinit_port(struct ata_channel *chp) 1300 { 1301 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1302 1303 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1304 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1305 DELAY(10); 1306 if (chp->ch_ndrives > 1) 1307 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1308 } 1309 1310 static void 1311 siisata_device_reset(struct ata_channel *chp) 1312 { 1313 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1314 1315 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1316 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1317 DELAY(10); 1318 } 1319 1320 1321 #if NATAPIBUS > 0 1322 void 1323 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1324 { 1325 struct ata_channel *chp = ata_sc->sc_chan; 1326 struct atac_softc *atac = chp->ch_atac; 1327 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1328 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1329 1330 /* 1331 * Fill in the scsipi_adapter. 1332 */ 1333 adapt->adapt_dev = atac->atac_dev; 1334 adapt->adapt_nchannels = atac->atac_nchannels; 1335 adapt->adapt_request = siisata_atapi_scsipi_request; 1336 adapt->adapt_minphys = siisata_atapi_minphys; 1337 atac->atac_atapi_adapter.atapi_probe_device = 1338 siisata_atapi_probe_device; 1339 1340 /* 1341 * Fill in the scsipi_channel. 1342 */ 1343 memset(chan, 0, sizeof(*chan)); 1344 chan->chan_adapter = adapt; 1345 chan->chan_bustype = &siisata_atapi_bustype; 1346 chan->chan_channel = chp->ch_channel; 1347 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1348 chan->chan_openings = 1; 1349 chan->chan_max_periph = 1; 1350 chan->chan_ntargets = 1; 1351 chan->chan_nluns = 1; 1352 1353 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1354 atapiprint); 1355 } 1356 1357 void 1358 siisata_atapi_minphys(struct buf *bp) 1359 { 1360 if (bp->b_bcount > MAXPHYS) 1361 bp->b_bcount = MAXPHYS; 1362 minphys(bp); 1363 } 1364 1365 /* 1366 * Kill off all pending xfers for a periph. 1367 * 1368 * Must be called at splbio(). 1369 */ 1370 void 1371 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1372 { 1373 struct atac_softc *atac = 1374 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1375 struct ata_channel *chp = 1376 atac->atac_channels[periph->periph_channel->chan_channel]; 1377 1378 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1379 } 1380 1381 void 1382 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1383 int reason) 1384 { 1385 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1386 1387 /* remove this command from xfer queue */ 1388 switch (reason) { 1389 case KILL_GONE: 1390 sc_xfer->error = XS_DRIVER_STUFFUP; 1391 break; 1392 case KILL_RESET: 1393 sc_xfer->error = XS_RESET; 1394 break; 1395 default: 1396 panic("%s: port %d: unknown reason %d", 1397 __func__, chp->ch_channel, reason); 1398 } 1399 ata_free_xfer(chp, xfer); 1400 scsipi_done(sc_xfer); 1401 } 1402 1403 void 1404 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1405 { 1406 struct scsipi_channel *chan = sc->sc_channel; 1407 struct scsipi_periph *periph; 1408 struct ataparams ids; 1409 struct ataparams *id = &ids; 1410 struct siisata_softc *siic = 1411 device_private(chan->chan_adapter->adapt_dev); 1412 struct atac_softc *atac = &siic->sc_atac; 1413 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1414 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1415 struct scsipibus_attach_args sa; 1416 char serial_number[21], model[41], firmware_revision[9]; 1417 int s; 1418 1419 /* skip if already attached */ 1420 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1421 return; 1422 1423 /* if no ATAPI device detected at attach time, skip */ 1424 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1425 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1426 target), DEBUG_PROBE); 1427 return; 1428 } 1429 1430 /* Some ATAPI devices need a bit more time after software reset. */ 1431 DELAY(5000); 1432 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1433 #ifdef ATAPI_DEBUG_PROBE 1434 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1435 device_xname(sc->sc_dev), target, 1436 id->atap_config & ATAPI_CFG_CMD_MASK, 1437 id->atap_config & ATAPI_CFG_DRQ_MASK); 1438 #endif 1439 periph = scsipi_alloc_periph(M_NOWAIT); 1440 if (periph == NULL) { 1441 aprint_error_dev(sc->sc_dev, 1442 "%s: unable to allocate periph for " 1443 "channel %d drive %d\n", __func__, 1444 chp->ch_channel, target); 1445 return; 1446 } 1447 periph->periph_dev = NULL; 1448 periph->periph_channel = chan; 1449 periph->periph_switch = &atapi_probe_periphsw; 1450 periph->periph_target = target; 1451 periph->periph_lun = 0; 1452 periph->periph_quirks = PQUIRK_ONLYBIG; 1453 1454 #ifdef SCSIPI_DEBUG 1455 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1456 SCSIPI_DEBUG_TARGET == target) 1457 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1458 #endif 1459 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1460 if (id->atap_config & ATAPI_CFG_REMOV) 1461 periph->periph_flags |= PERIPH_REMOVABLE; 1462 sa.sa_periph = periph; 1463 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1464 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1465 T_REMOV : T_FIXED; 1466 strnvisx(model, sizeof(model), id->atap_model, 40, 1467 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1468 strnvisx(serial_number, sizeof(serial_number), 1469 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1470 strnvisx(firmware_revision, sizeof(firmware_revision), 1471 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1472 sa.sa_inqbuf.vendor = model; 1473 sa.sa_inqbuf.product = serial_number; 1474 sa.sa_inqbuf.revision = firmware_revision; 1475 1476 /* 1477 * Determine the operating mode capabilities of the device. 1478 */ 1479 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1480 == ATAPI_CFG_CMD_16) { 1481 periph->periph_cap |= PERIPH_CAP_CMD16; 1482 1483 /* configure port for packet length */ 1484 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1485 PR_PC_PACKET_LENGTH); 1486 } else { 1487 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1488 PR_PC_PACKET_LENGTH); 1489 } 1490 1491 /* XXX This is gross. */ 1492 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1493 1494 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1495 1496 if (drvp->drv_softc) 1497 ata_probe_caps(drvp); 1498 else { 1499 s = splbio(); 1500 drvp->drive_type &= ATA_DRIVET_NONE; 1501 splx(s); 1502 } 1503 } else { 1504 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1505 "failed for drive %s:%d:%d: error 0x%x\n", 1506 __func__, SIISATANAME(siic), chp->ch_channel, target, 1507 chp->ch_error), DEBUG_PROBE); 1508 s = splbio(); 1509 drvp->drive_type &= ATA_DRIVET_NONE; 1510 splx(s); 1511 } 1512 } 1513 1514 void 1515 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1516 scsipi_adapter_req_t req, void *arg) 1517 { 1518 struct scsipi_adapter *adapt = chan->chan_adapter; 1519 struct scsipi_periph *periph; 1520 struct scsipi_xfer *sc_xfer; 1521 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1522 struct atac_softc *atac = &sc->sc_atac; 1523 struct ata_xfer *xfer; 1524 int channel = chan->chan_channel; 1525 int drive, s; 1526 1527 switch (req) { 1528 case ADAPTER_REQ_RUN_XFER: 1529 sc_xfer = arg; 1530 periph = sc_xfer->xs_periph; 1531 drive = periph->periph_target; 1532 1533 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1534 device_xname(atac->atac_dev), channel, drive), 1535 DEBUG_XFERS); 1536 1537 if (!device_is_active(atac->atac_dev)) { 1538 sc_xfer->error = XS_DRIVER_STUFFUP; 1539 scsipi_done(sc_xfer); 1540 return; 1541 } 1542 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1543 if (xfer == NULL) { 1544 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1545 scsipi_done(sc_xfer); 1546 return; 1547 } 1548 1549 if (sc_xfer->xs_control & XS_CTL_POLL) 1550 xfer->c_flags |= C_POLL; 1551 xfer->c_drive = drive; 1552 xfer->c_flags |= C_ATAPI; 1553 xfer->c_cmd = sc_xfer; 1554 xfer->c_databuf = sc_xfer->data; 1555 xfer->c_bcount = sc_xfer->datalen; 1556 xfer->c_start = siisata_atapi_start; 1557 xfer->c_intr = siisata_atapi_complete; 1558 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1559 xfer->c_dscpoll = 0; 1560 s = splbio(); 1561 ata_exec_xfer(atac->atac_channels[channel], xfer); 1562 #ifdef DIAGNOSTIC 1563 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1564 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1565 panic("%s: polled command not done", __func__); 1566 #endif 1567 splx(s); 1568 return; 1569 1570 default: 1571 /* Not supported, nothing to do. */ 1572 ; 1573 } 1574 } 1575 1576 void 1577 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1578 { 1579 struct siisata_channel *schp = (struct siisata_channel *)chp; 1580 struct siisata_prb *prbp; 1581 1582 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1583 1584 int slot = SIISATA_NON_NCQ_SLOT; 1585 int i; 1586 1587 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1588 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1589 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1590 DEBUG_XFERS); 1591 1592 chp->ch_status = 0; 1593 chp->ch_error = 0; 1594 1595 prbp = schp->sch_prb[slot]; 1596 memset(prbp, 0, sizeof(struct siisata_prb)); 1597 1598 1599 /* fill in direction for ATAPI command */ 1600 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1601 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1602 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1603 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1604 1605 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1606 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1607 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1608 1609 /* copy over ATAPI command */ 1610 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1611 1612 if (siisata_dma_setup(chp, slot, 1613 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1614 xfer->c_databuf : NULL, 1615 xfer->c_bcount, 1616 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1617 BUS_DMA_READ : BUS_DMA_WRITE) 1618 ) 1619 panic("%s", __func__); 1620 1621 if (xfer->c_flags & C_POLL) { 1622 /* polled command, disable interrupts */ 1623 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1624 siisata_disable_port_interrupt(chp); 1625 } 1626 1627 siisata_activate_prb(schp, slot); 1628 1629 if ((xfer->c_flags & C_POLL) == 0) { 1630 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1631 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1632 siisata_timeout, chp); 1633 goto out; 1634 } 1635 1636 /* 1637 * polled command 1638 */ 1639 for (i = 0; i < ATA_DELAY / 10; i++) { 1640 if (sc_xfer->xs_status & XS_STS_DONE) 1641 break; 1642 siisata_intr_port(schp); 1643 DELAY(1000); 1644 } 1645 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1646 siisata_timeout(chp); 1647 } 1648 /* reenable interrupts */ 1649 siisata_enable_port_interrupt(chp); 1650 out: 1651 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1652 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1653 DEBUG_FUNCS); 1654 return; 1655 } 1656 1657 int 1658 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1659 int slot) 1660 { 1661 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1662 struct siisata_channel *schp = (struct siisata_channel *)chp; 1663 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1664 1665 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1666 DEBUG_INTR); 1667 1668 /* this command is not active any more */ 1669 schp->sch_active_slots &= ~__BIT(slot); 1670 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1671 if (xfer->c_flags & C_TIMEOU) { 1672 sc_xfer->error = XS_TIMEOUT; 1673 } else { 1674 callout_stop(&chp->ch_callout); 1675 sc_xfer->error = XS_NOERROR; 1676 } 1677 1678 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1679 schp->sch_datad[slot]->dm_mapsize, 1680 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1681 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1682 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1683 1684 if (chp->ch_drive[xfer->c_drive].drive_flags & ATA_DRIVE_WAITDRAIN) { 1685 siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); 1686 chp->ch_drive[xfer->c_drive].drive_flags &= 1687 ~ATA_DRIVE_WAITDRAIN; 1688 wakeup(&chp->ch_queue->active_xfer); 1689 return 0; /* XXX verify */ 1690 } 1691 1692 chp->ch_queue->active_xfer = NULL; 1693 ata_free_xfer(chp, xfer); 1694 sc_xfer->resid = sc_xfer->datalen; 1695 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1696 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1697 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1698 if ((chp->ch_status & WDCS_ERR) && 1699 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1700 sc_xfer->resid == sc_xfer->datalen)) { 1701 sc_xfer->error = XS_SHORTSENSE; 1702 sc_xfer->sense.atapi_sense = chp->ch_error; 1703 if ((sc_xfer->xs_periph->periph_quirks & 1704 PQUIRK_NOSENSE) == 0) { 1705 /* request sense */ 1706 sc_xfer->error = XS_BUSY; 1707 sc_xfer->status = SCSI_CHECK; 1708 } 1709 } 1710 scsipi_done(sc_xfer); 1711 atastart(chp); 1712 return 0; /* XXX verify */ 1713 } 1714 1715 #endif /* NATAPIBUS */ 1716
Indexes created Fri Sep 26 20:09:58 GMT 2025