siisata.c revision 1.35.6.10
1 /* $NetBSD: siisata.c,v 1.35.6.10 2018/10/15 21:18:53 jdolecek Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.35.6.10 2018/10/15 21:18:53 jdolecek Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define WDC_RESET_WAIT 31000 /* 31s for drive reset */ 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #if _BYTE_ORDER == _LITTLE_ENDIAN 116 #define bus_space_read_stream_4 bus_space_read_4 117 #define bus_space_read_region_stream_4 bus_space_read_region_4 118 #else 119 static inline uint32_t 120 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 121 { 122 return htole32(bus_space_read_4(t, h, o)); 123 } 124 125 static inline void 126 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 127 bus_size_t o, uint32_t *p, bus_size_t c) 128 { 129 bus_space_read_region_4(t, h, o, p, c); 130 for (bus_size_t i = 0; i < c; i++) { 131 p[i] = htole32(p[i]); 132 } 133 } 134 #endif 135 #endif 136 137 static void siisata_attach_port(struct siisata_softc *, int); 138 static void siisata_intr_port(struct siisata_channel *); 139 140 void siisata_probe_drive(struct ata_channel *); 141 void siisata_setup_channel(struct ata_channel *); 142 143 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 144 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 145 void siisata_reset_channel(struct ata_channel *, int); 146 int siisata_ata_addref(struct ata_drive_datas *); 147 void siisata_ata_delref(struct ata_drive_datas *); 148 void siisata_killpending(struct ata_drive_datas *); 149 150 int siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 151 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_cmd_poll(struct ata_channel *, struct ata_xfer *); 153 void siisata_cmd_abort(struct ata_channel *, struct ata_xfer *); 154 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 155 static void siisata_cmd_done_end(struct ata_channel *, struct ata_xfer *); 156 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 158 int siisata_bio_start(struct ata_channel *, struct ata_xfer *); 159 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 160 void siisata_bio_poll(struct ata_channel *, struct ata_xfer *); 161 void siisata_bio_abort(struct ata_channel *, struct ata_xfer *); 162 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 163 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 164 165 static void siisata_reinit_port(struct ata_channel *, int); 166 static void siisata_device_reset(struct ata_channel *); 167 static void siisata_activate_prb(struct siisata_channel *, int); 168 static void siisata_deactivate_prb(struct siisata_channel *, int); 169 static int siisata_dma_setup(struct ata_channel *, int, void *, size_t, int); 170 static void siisata_channel_recover(struct ata_channel *, int, uint32_t); 171 172 #if NATAPIBUS > 0 173 void siisata_atapibus_attach(struct atabus_softc *); 174 void siisata_atapi_probe_device(struct atapibus_softc *, int); 175 void siisata_atapi_minphys(struct buf *); 176 int siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 177 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 178 void siisata_atapi_poll(struct ata_channel *, struct ata_xfer *); 179 void siisata_atapi_abort(struct ata_channel *, struct ata_xfer *); 180 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 181 void siisata_atapi_scsipi_request(struct scsipi_channel *, 182 scsipi_adapter_req_t, void *); 183 void siisata_atapi_kill_pending(struct scsipi_periph *); 184 #endif /* NATAPIBUS */ 185 186 const struct ata_bustype siisata_ata_bustype = { 187 SCSIPI_BUSTYPE_ATA, 188 siisata_ata_bio, 189 siisata_reset_drive, 190 siisata_reset_channel, 191 siisata_exec_command, 192 ata_get_params, 193 siisata_ata_addref, 194 siisata_ata_delref, 195 siisata_killpending, 196 siisata_channel_recover, 197 }; 198 199 #if NATAPIBUS > 0 200 static const struct scsipi_bustype siisata_atapi_bustype = { 201 SCSIPI_BUSTYPE_ATAPI, 202 atapi_scsipi_cmd, 203 atapi_interpret_sense, 204 atapi_print_addr, 205 siisata_atapi_kill_pending, 206 NULL, 207 }; 208 #endif /* NATAPIBUS */ 209 210 211 void 212 siisata_attach(struct siisata_softc *sc) 213 { 214 int i; 215 216 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 217 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 218 219 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 220 sc->sc_atac.atac_pio_cap = 4; 221 sc->sc_atac.atac_dma_cap = 2; 222 sc->sc_atac.atac_udma_cap = 6; 223 sc->sc_atac.atac_channels = sc->sc_chanarray; 224 sc->sc_atac.atac_probe = siisata_probe_drive; 225 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 226 sc->sc_atac.atac_set_modes = siisata_setup_channel; 227 #if NATAPIBUS > 0 228 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 229 #endif 230 231 /* come out of reset state */ 232 GRWRITE(sc, GR_GC, 0); 233 234 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 235 siisata_attach_port(sc, i); 236 } 237 238 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 239 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 240 return; 241 } 242 243 static void 244 siisata_disable_port_interrupt(struct ata_channel *chp) 245 { 246 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 247 248 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 249 } 250 251 static void 252 siisata_enable_port_interrupt(struct ata_channel *chp) 253 { 254 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 255 256 /* clear any interrupts */ 257 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 258 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 259 /* and enable CmdErrr+CmdCmpl interrupting */ 260 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 261 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 262 } 263 264 static void 265 siisata_init_port(struct siisata_softc *sc, int port) 266 { 267 struct siisata_channel *schp; 268 struct ata_channel *chp; 269 270 schp = &sc->sc_channels[port]; 271 chp = (struct ata_channel *)schp; 272 273 /* 274 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 275 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 276 */ 277 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 278 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 279 /* initialize port */ 280 siisata_reinit_port(chp, -1); 281 /* enable CmdErrr+CmdCmpl interrupting */ 282 siisata_enable_port_interrupt(chp); 283 /* enable port interrupt */ 284 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 285 } 286 287 static void 288 siisata_attach_port(struct siisata_softc *sc, int port) 289 { 290 int j; 291 int dmasize; 292 int error; 293 void *prbp; 294 struct siisata_channel *schp; 295 struct ata_channel *chp; 296 297 schp = &sc->sc_channels[port]; 298 chp = (struct ata_channel *)schp; 299 sc->sc_chanarray[port] = chp; 300 chp->ch_channel = port; 301 chp->ch_atac = &sc->sc_atac; 302 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 303 if (chp->ch_queue == NULL) { 304 aprint_error_dev(sc->sc_atac.atac_dev, 305 "port %d: can't allocate memory " 306 "for command queue\n", chp->ch_channel); 307 return; 308 } 309 310 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 311 312 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 313 __func__, dmasize), DEBUG_FUNCS); 314 315 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 316 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 317 if (error) { 318 aprint_error_dev(sc->sc_atac.atac_dev, 319 "unable to allocate PRB table memory, " 320 "error=%d\n", error); 321 return; 322 } 323 324 error = bus_dmamem_map(sc->sc_dmat, 325 &schp->sch_prb_seg, schp->sch_prb_nseg, 326 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 327 if (error) { 328 aprint_error_dev(sc->sc_atac.atac_dev, 329 "unable to map PRB table memory, " 330 "error=%d\n", error); 331 bus_dmamem_free(sc->sc_dmat, 332 &schp->sch_prb_seg, schp->sch_prb_nseg); 333 return; 334 } 335 336 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 337 BUS_DMA_NOWAIT, &schp->sch_prbd); 338 if (error) { 339 aprint_error_dev(sc->sc_atac.atac_dev, 340 "unable to create PRB table map, " 341 "error=%d\n", error); 342 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 343 bus_dmamem_free(sc->sc_dmat, 344 &schp->sch_prb_seg, schp->sch_prb_nseg); 345 return; 346 } 347 348 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 349 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 350 if (error) { 351 aprint_error_dev(sc->sc_atac.atac_dev, 352 "unable to load PRB table map, " 353 "error=%d\n", error); 354 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 355 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 356 bus_dmamem_free(sc->sc_dmat, 357 &schp->sch_prb_seg, schp->sch_prb_nseg); 358 return; 359 } 360 361 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 362 schp->sch_prb[j] = (struct siisata_prb *) 363 ((char *)prbp + SIISATA_CMD_SIZE * j); 364 schp->sch_bus_prb[j] = 365 schp->sch_prbd->dm_segs[0].ds_addr + 366 SIISATA_CMD_SIZE * j; 367 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 368 SIISATA_NSGE, MAXPHYS, 0, 369 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 370 &schp->sch_datad[j]); 371 if (error) { 372 aprint_error_dev(sc->sc_atac.atac_dev, 373 "couldn't create xfer DMA map, error=%d\n", 374 error); 375 return; 376 } 377 } 378 379 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 380 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 381 aprint_error_dev(sc->sc_atac.atac_dev, 382 "couldn't map port %d SStatus regs\n", 383 chp->ch_channel); 384 return; 385 } 386 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 387 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 388 aprint_error_dev(sc->sc_atac.atac_dev, 389 "couldn't map port %d SControl regs\n", 390 chp->ch_channel); 391 return; 392 } 393 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 394 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 395 aprint_error_dev(sc->sc_atac.atac_dev, 396 "couldn't map port %d SError regs\n", 397 chp->ch_channel); 398 return; 399 } 400 401 siisata_init_port(sc, port); 402 403 ata_channel_attach(chp); 404 405 return; 406 } 407 408 int 409 siisata_detach(struct siisata_softc *sc, int flags) 410 { 411 struct atac_softc *atac = &sc->sc_atac; 412 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 413 struct siisata_channel *schp; 414 struct ata_channel *chp; 415 int i, j, error; 416 417 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 418 schp = &sc->sc_channels[i]; 419 chp = sc->sc_chanarray[i]; 420 421 if (chp->atabus == NULL) 422 continue; 423 if ((error = config_detach(chp->atabus, flags)) != 0) 424 return error; 425 426 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 427 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 428 429 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 430 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 431 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 432 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 433 bus_dmamem_free(sc->sc_dmat, 434 &schp->sch_prb_seg, schp->sch_prb_nseg); 435 436 chp->atabus = NULL; 437 438 ata_channel_detach(chp); 439 } 440 441 if (adapt->adapt_refcnt != 0) 442 return EBUSY; 443 444 /* leave the chip in reset */ 445 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 446 447 return 0; 448 } 449 450 void 451 siisata_resume(struct siisata_softc *sc) 452 { 453 int i; 454 455 /* come out of reset state */ 456 GRWRITE(sc, GR_GC, 0); 457 458 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 459 siisata_init_port(sc, i); 460 } 461 462 } 463 464 int 465 siisata_intr(void *v) 466 { 467 struct siisata_softc *sc = v; 468 uint32_t is; 469 int i, r = 0; 470 while ((is = GRREAD(sc, GR_GIS))) { 471 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 472 SIISATANAME(sc), __func__, is), DEBUG_INTR); 473 r = 1; 474 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 475 if (is & GR_GIS_PXIS(i)) 476 siisata_intr_port(&sc->sc_channels[i]); 477 } 478 return r; 479 } 480 481 static void 482 siisata_intr_port(struct siisata_channel *schp) 483 { 484 struct siisata_softc *sc = 485 (struct siisata_softc *)schp->ata_channel.ch_atac; 486 struct ata_channel *chp = &schp->ata_channel; 487 struct ata_xfer *xfer = NULL; 488 uint32_t pss, pis, tfd = 0; 489 bool recover = false; 490 491 /* get slot status, clearing completion interrupt */ 492 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 493 494 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x ", 495 SIISATANAME(sc), __func__, chp->ch_channel, pss), 496 DEBUG_INTR); 497 498 if (__predict_true((pss & PR_PSS_ATTENTION) == 0)) { 499 SIISATA_DEBUG_PRINT(("no attention"), DEBUG_INTR); 500 goto process; 501 } 502 503 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 504 505 SIISATA_DEBUG_PRINT(("pis 0x%x\n", pss), DEBUG_INTR); 506 507 if (pis & PR_PIS_CMDERRR) { 508 uint32_t ec; 509 510 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 511 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 512 513 /* emulate a CRC error by default */ 514 tfd = ATACH_ERR_ST(WDCE_CRC, WDCS_ERR); 515 516 if (ec <= PR_PCE_DATAFISERROR) { 517 if (ec == PR_PCE_DEVICEERROR 518 && (chp->ch_flags & ATACH_NCQ) == 0) { 519 xfer = ata_queue_get_active_xfer(chp); 520 521 /* read in specific information about error */ 522 uint32_t prbfis = bus_space_read_stream_4( 523 sc->sc_prt, sc->sc_prh, 524 PRSX(chp->ch_channel, xfer->c_slot, 525 PRSO_FIS)); 526 527 /* get status and error */ 528 int ntfd = satafis_rdh_parse(chp, 529 (uint8_t *)&prbfis); 530 531 if (ATACH_ST(ntfd) & WDCS_ERR) 532 tfd = ntfd; 533 } 534 535 /* 536 * We don't expect the recovery to trigger error, 537 * but handle this just in case. 538 */ 539 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 540 recover = true; 541 else { 542 aprint_error_dev(sc->sc_atac.atac_dev, 543 "error ec %x while recovering\n", ec); 544 545 /* Command will be marked as errored out */ 546 pss = 0; 547 } 548 } else { 549 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 550 " on channel %d (ctx 0x%x), resetting\n", 551 ec, chp->ch_channel, 552 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 553 554 /* okay, we have a "Fatal Error" */ 555 siisata_device_reset(chp); 556 } 557 } 558 559 /* clear some (ok, all) ints */ 560 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 561 562 if (__predict_false(recover)) 563 ata_channel_freeze(chp); 564 565 process: 566 if (xfer != NULL) { 567 xfer->ops->c_intr(chp, xfer, tfd); 568 } else { 569 /* 570 * For NCQ, HBA halts processing when error is notified, 571 * and any further D2H FISes are ignored until the error 572 * condition is cleared. Hence if a command is inactive, 573 * it means it actually already finished successfully. 574 * Note: active slots can change as c_intr() callback 575 * can activate another command(s), so must only process 576 * commands active before we start processing. 577 */ 578 uint32_t aslots = ata_queue_active(chp); 579 580 for (int slot=0; slot < SIISATA_MAX_SLOTS; slot++) { 581 if ((aslots & __BIT(slot)) != 0 && 582 (pss & PR_PXSS(slot)) == 0) { 583 xfer = ata_queue_hwslot_to_xfer(chp, slot); 584 xfer->ops->c_intr(chp, xfer, 0); 585 } 586 } 587 } 588 589 if (__predict_false(recover)) { 590 ata_channel_lock(chp); 591 ata_channel_thaw_locked(chp); 592 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 593 ata_channel_unlock(chp); 594 } 595 } 596 597 /* Recover channel after transfer aborted */ 598 void 599 siisata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 600 { 601 struct siisata_channel *schp = (struct siisata_channel *)chp; 602 struct siisata_softc *sc = 603 (struct siisata_softc *)schp->ata_channel.ch_atac; 604 int drive; 605 606 ata_channel_lock_owned(chp); 607 608 if (chp->ch_ndrives > PMP_PORT_CTL) { 609 /* Get PM port number for the device in error */ 610 int pcr = PRREAD(sc, PRX(chp->ch_channel, PRO_PCR)); 611 drive = PRO_PCR_PMP(pcr); 612 } else 613 drive = 0; 614 615 /* 616 * If BSY or DRQ bits are set, must execute COMRESET to return 617 * device to idle state. Otherwise, commands can be reissued 618 * after reinitalization of port. After that, need to execute 619 * READ LOG EXT for NCQ to unblock device processing if COMRESET 620 * was not done. 621 */ 622 if ((ATACH_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 623 siisata_device_reset(chp); 624 goto out; 625 } 626 627 KASSERT(drive >= 0); 628 siisata_reinit_port(chp, drive); 629 630 ata_recovery_resume(chp, drive, tfd, flags); 631 632 out: 633 /* Drive unblocked, back to normal operation */ 634 return; 635 } 636 637 void 638 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 639 { 640 struct ata_channel *chp = drvp->chnl_softc; 641 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 642 struct siisata_channel *schp = (struct siisata_channel *)chp; 643 struct siisata_prb *prb; 644 uint8_t c_slot; 645 uint32_t pss, pis; 646 int i; 647 bool timed_out; 648 649 ata_channel_lock_owned(chp); 650 651 siisata_reinit_port(chp, drvp->drive); 652 653 /* get a slot for running the command on */ 654 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 655 panic("%s: %s: failed to get xfer for reset, port %d\n", 656 device_xname(sc->sc_atac.atac_dev), 657 __func__, chp->ch_channel); 658 /* NOTREACHED */ 659 } 660 661 prb = schp->sch_prb[c_slot]; 662 memset(prb, 0, SIISATA_CMD_SIZE); 663 prb->prb_control = 664 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 665 KASSERT(drvp->drive <= PMP_PORT_CTL); 666 prb->prb_fis[rhd_c] = drvp->drive; 667 668 siisata_disable_port_interrupt(chp); 669 670 siisata_activate_prb(schp, c_slot); 671 672 timed_out = true; 673 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 674 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 675 if ((pss & PR_PXSS(c_slot)) == 0) { 676 timed_out = false; 677 break; 678 } 679 if (pss & PR_PSS_ATTENTION) 680 break; 681 ata_delay(chp, 10, "siiprb", flags); 682 } 683 684 siisata_deactivate_prb(schp, c_slot); 685 686 if ((pss & PR_PSS_ATTENTION) != 0) { 687 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 688 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 689 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 690 691 if (slot != c_slot) 692 device_printf(sc->sc_atac.atac_dev, "%s port %d " 693 "drive %d slot %d c_slot %d", __func__, 694 chp->ch_channel, drvp->drive, slot, c_slot); 695 696 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 697 PR_PIS_CMDERRR); 698 } 699 700 siisata_enable_port_interrupt(chp); 701 702 if (timed_out) { 703 /* timeout */ 704 siisata_device_reset(chp); /* XXX is this right? */ 705 if (sigp) 706 *sigp = 0xffffffff; 707 } else { 708 /* read the signature out of the FIS */ 709 if (sigp) { 710 *sigp = 0; 711 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 712 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 713 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 714 PRSO_FIS+0xc)) & 0xff; 715 } 716 } 717 718 ata_queue_free_slot(chp, c_slot); 719 } 720 721 void 722 siisata_reset_channel(struct ata_channel *chp, int flags) 723 { 724 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 725 struct siisata_channel *schp = (struct siisata_channel *)chp; 726 727 SIISATA_DEBUG_PRINT(("%s: %s channel %d\n", SIISATANAME(sc), __func__, 728 chp->ch_channel), DEBUG_FUNCS); 729 730 ata_channel_lock_owned(chp); 731 732 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 733 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 734 aprint_error("%s port %d: reset failed\n", 735 SIISATANAME(sc), chp->ch_channel); 736 /* XXX and then ? */ 737 } 738 739 siisata_device_reset(chp); 740 741 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 742 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 743 744 return; 745 } 746 747 int 748 siisata_ata_addref(struct ata_drive_datas *drvp) 749 { 750 return 0; 751 } 752 753 void 754 siisata_ata_delref(struct ata_drive_datas *drvp) 755 { 756 return; 757 } 758 759 void 760 siisata_killpending(struct ata_drive_datas *drvp) 761 { 762 return; 763 } 764 765 void 766 siisata_probe_drive(struct ata_channel *chp) 767 { 768 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 769 struct siisata_channel *schp = (struct siisata_channel *)chp; 770 int i; 771 uint32_t sig; 772 struct siisata_prb *prb; 773 bool timed_out; 774 uint8_t c_slot; 775 776 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 777 __func__, chp->ch_channel), DEBUG_FUNCS); 778 779 ata_channel_lock(chp); 780 781 /* get a slot for running the command on */ 782 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 783 aprint_error_dev(sc->sc_atac.atac_dev, 784 "%s: failed to get xfer port %d\n", 785 __func__, chp->ch_channel); 786 ata_channel_unlock(chp); 787 return; 788 } 789 790 /* 791 * disable port interrupt as we're polling for PHY up and 792 * prb completion 793 */ 794 siisata_disable_port_interrupt(chp); 795 796 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 797 schp->sch_sstatus, AT_WAIT)) { 798 case SStatus_DET_DEV: 799 /* clear any interrupts */ 800 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 801 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 802 803 /* wait for ready */ 804 timed_out = 1; 805 for (i = 0; i < ATA_DELAY / 10; i++) { 806 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & 807 PR_PS_PORT_READY) { 808 timed_out = 0; 809 break; 810 } 811 812 ata_delay(chp, 10, "siiprbrd", AT_WAIT); 813 } 814 if (timed_out) { 815 aprint_error_dev(sc->sc_atac.atac_dev, 816 "timed out waiting for PORT_READY on port %d, " 817 "reinitializing\n", chp->ch_channel); 818 siisata_reinit_port(chp, -1); 819 } 820 821 prb = schp->sch_prb[c_slot]; 822 memset(prb, 0, SIISATA_CMD_SIZE); 823 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 824 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 825 826 siisata_activate_prb(schp, c_slot); 827 828 timed_out = 1; 829 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 830 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 831 PR_PXSS(c_slot)) == 0) { 832 /* prb completed */ 833 timed_out = 0; 834 break; 835 } 836 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 837 PR_PIS_CMDERRR) { 838 /* we got an error; handle as timeout */ 839 break; 840 } 841 842 ata_delay(chp, 10, "siiprb", AT_WAIT); 843 } 844 845 siisata_deactivate_prb(schp, c_slot); 846 847 if (timed_out) { 848 aprint_error_dev(sc->sc_atac.atac_dev, 849 "SOFT_RESET failed on port %d (error %d PSS 0x%x PIS 0x%x), " 850 "resetting\n", chp->ch_channel, 851 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 852 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)), 853 PRREAD(sc, PRX(chp->ch_channel, PRO_PIS))); 854 siisata_reinit_port(chp, -1); 855 break; 856 } 857 858 /* read the signature out of the FIS */ 859 sig = 0; 860 sig |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 861 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 862 sig |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 863 PRSO_FIS+0xc)) & 0xff; 864 865 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 866 __func__, sig), DEBUG_PROBE); 867 868 if (sig == 0x96690101) 869 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 870 PR_PC_PMP_ENABLE); 871 sata_interpret_sig(chp, 0, sig); 872 break; 873 default: 874 break; 875 } 876 877 siisata_enable_port_interrupt(chp); 878 879 ata_queue_free_slot(chp, c_slot); 880 881 ata_channel_unlock(chp); 882 883 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 884 __func__, chp->ch_channel), DEBUG_PROBE); 885 return; 886 } 887 888 void 889 siisata_setup_channel(struct ata_channel *chp) 890 { 891 return; 892 } 893 894 static const struct ata_xfer_ops siisata_cmd_xfer_ops = { 895 .c_start = siisata_cmd_start, 896 .c_intr = siisata_cmd_complete, 897 .c_poll = siisata_cmd_poll, 898 .c_abort = siisata_cmd_abort, 899 .c_kill_xfer = siisata_cmd_kill_xfer, 900 }; 901 902 int 903 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 904 { 905 struct ata_channel *chp = drvp->chnl_softc; 906 struct ata_command *ata_c = &xfer->c_ata_c; 907 int ret; 908 int s; 909 910 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 911 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 912 DEBUG_FUNCS); 913 914 if (ata_c->flags & AT_POLL) 915 xfer->c_flags |= C_POLL; 916 if (ata_c->flags & AT_WAIT) 917 xfer->c_flags |= C_WAIT; 918 xfer->c_drive = drvp->drive; 919 xfer->c_databuf = ata_c->data; 920 xfer->c_bcount = ata_c->bcount; 921 xfer->ops = &siisata_cmd_xfer_ops; 922 s = splbio(); 923 ata_exec_xfer(chp, xfer); 924 #ifdef DIAGNOSTIC 925 if ((ata_c->flags & AT_POLL) != 0 && 926 (ata_c->flags & AT_DONE) == 0) 927 panic("%s: polled command not done", __func__); 928 #endif 929 if (ata_c->flags & AT_DONE) { 930 ret = ATACMD_COMPLETE; 931 } else { 932 if (ata_c->flags & AT_WAIT) { 933 ata_wait_cmd(chp, xfer); 934 ret = ATACMD_COMPLETE; 935 } else { 936 ret = ATACMD_QUEUED; 937 } 938 } 939 splx(s); 940 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 941 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 942 DEBUG_FUNCS); 943 return ret; 944 } 945 946 int 947 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 948 { 949 struct siisata_channel *schp = (struct siisata_channel *)chp; 950 struct ata_command *ata_c = &xfer->c_ata_c; 951 struct siisata_prb *prb; 952 953 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 954 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 955 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 956 DEBUG_FUNCS|DEBUG_XFERS); 957 958 ata_channel_lock_owned(chp); 959 960 prb = schp->sch_prb[xfer->c_slot]; 961 memset(prb, 0, SIISATA_CMD_SIZE); 962 963 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 964 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 965 prb->prb_fis[rhd_c] |= xfer->c_drive; 966 967 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 968 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 969 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 970 } 971 972 if (siisata_dma_setup(chp, xfer->c_slot, 973 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 974 ata_c->bcount, 975 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 976 ata_c->flags |= AT_DF; 977 return ATASTART_ABORT; 978 } 979 980 if (xfer->c_flags & C_POLL) { 981 /* polled command, disable interrupts */ 982 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 983 siisata_disable_port_interrupt(chp); 984 } 985 986 /* go for it */ 987 siisata_activate_prb(schp, xfer->c_slot); 988 989 if ((ata_c->flags & AT_POLL) == 0) { 990 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 991 ata_timeout, chp); 992 return ATASTART_STARTED; 993 } else 994 return ATASTART_POLL; 995 } 996 997 void 998 siisata_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 999 { 1000 struct siisata_channel *schp = (struct siisata_channel *)chp; 1001 1002 /* 1003 * polled command 1004 */ 1005 for (int i = 0; i < xfer->c_ata_c.timeout * 10; i++) { 1006 if (xfer->c_ata_c.flags & AT_DONE) 1007 break; 1008 siisata_intr_port(schp); 1009 DELAY(100); 1010 } 1011 1012 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1013 ata_timeout(xfer); 1014 } 1015 1016 /* reenable interrupts */ 1017 siisata_enable_port_interrupt(chp); 1018 1019 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1020 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1021 DEBUG_FUNCS); 1022 } 1023 1024 void 1025 siisata_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1026 { 1027 siisata_cmd_complete(chp, xfer, 0); 1028 } 1029 1030 void 1031 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1032 int reason) 1033 { 1034 struct ata_command *ata_c = &xfer->c_ata_c; 1035 struct siisata_channel *schp = (struct siisata_channel *)chp; 1036 bool deactivate = true; 1037 1038 switch (reason) { 1039 case KILL_GONE_INACTIVE: 1040 deactivate = false; 1041 /* FALLTHROUGH */ 1042 case KILL_GONE: 1043 ata_c->flags |= AT_GONE; 1044 break; 1045 case KILL_RESET: 1046 ata_c->flags |= AT_RESET; 1047 break; 1048 case KILL_REQUEUE: 1049 panic("%s: not supposed to be requeued\n", __func__); 1050 break; 1051 default: 1052 panic("%s: port %d: unknown reason %d", 1053 __func__, chp->ch_channel, reason); 1054 } 1055 1056 siisata_cmd_done_end(chp, xfer); 1057 1058 if (deactivate) { 1059 siisata_deactivate_prb(schp, xfer->c_slot); 1060 ata_deactivate_xfer(chp, xfer); 1061 } 1062 } 1063 1064 int 1065 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1066 { 1067 struct siisata_channel *schp = (struct siisata_channel *)chp; 1068 struct ata_command *ata_c = &xfer->c_ata_c; 1069 #ifdef SIISATA_DEBUG 1070 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1071 #endif 1072 1073 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1074 SIISATANAME(sc), __func__, 1075 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1076 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1077 DEBUG_FUNCS|DEBUG_XFERS); 1078 1079 if (ata_waitdrain_xfer_check(chp, xfer)) 1080 return 0; 1081 1082 if (xfer->c_flags & C_TIMEOU) 1083 ata_c->flags |= AT_TIMEOU; 1084 1085 if (ATACH_ST(tfd) & WDCS_BSY) { 1086 ata_c->flags |= AT_TIMEOU; 1087 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1088 ata_c->r_error = ATACH_ERR(tfd); 1089 ata_c->flags |= AT_ERROR; 1090 } 1091 1092 siisata_cmd_done(chp, xfer, tfd); 1093 1094 siisata_deactivate_prb(schp, xfer->c_slot); 1095 ata_deactivate_xfer(chp, xfer); 1096 1097 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1098 atastart(chp); 1099 1100 return 0; 1101 } 1102 1103 void 1104 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1105 { 1106 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1107 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1108 struct siisata_channel *schp = (struct siisata_channel *)chp; 1109 struct ata_command *ata_c = &xfer->c_ata_c; 1110 uint16_t *idwordbuf; 1111 int i; 1112 1113 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1114 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1115 1116 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1117 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1118 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1119 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1120 BUS_DMASYNC_POSTWRITE); 1121 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1122 } 1123 1124 if (ata_c->flags & AT_READREG) { 1125 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1126 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1127 fis, __arraycount(fis)); 1128 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1129 } 1130 1131 /* correct the endianess of IDENTIFY data */ 1132 if (ata_c->r_command == WDCC_IDENTIFY || 1133 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1134 idwordbuf = xfer->c_databuf; 1135 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1136 idwordbuf[i] = le16toh(idwordbuf[i]); 1137 } 1138 } 1139 1140 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1141 ata_c->flags |= AT_XFDONE; 1142 1143 siisata_cmd_done_end(chp, xfer); 1144 } 1145 1146 static void 1147 siisata_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1148 { 1149 struct ata_command *ata_c = &xfer->c_ata_c; 1150 1151 ata_c->flags |= AT_DONE; 1152 } 1153 1154 static const struct ata_xfer_ops siisata_bio_xfer_ops = { 1155 .c_start = siisata_bio_start, 1156 .c_intr = siisata_bio_complete, 1157 .c_poll = siisata_bio_poll, 1158 .c_abort = siisata_bio_abort, 1159 .c_kill_xfer = siisata_bio_kill_xfer, 1160 }; 1161 1162 int 1163 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1164 { 1165 struct ata_channel *chp = drvp->chnl_softc; 1166 struct ata_bio *ata_bio = &xfer->c_bio; 1167 1168 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1169 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1170 DEBUG_FUNCS); 1171 1172 if (xfer == NULL) 1173 return ATACMD_TRY_AGAIN; 1174 if (ata_bio->flags & ATA_POLL) 1175 xfer->c_flags |= C_POLL; 1176 xfer->c_drive = drvp->drive; 1177 xfer->c_databuf = ata_bio->databuf; 1178 xfer->c_bcount = ata_bio->bcount; 1179 xfer->ops = &siisata_bio_xfer_ops; 1180 ata_exec_xfer(chp, xfer); 1181 return (ata_bio->flags & ATA_ITSDONE) ? 1182 ATACMD_COMPLETE : ATACMD_QUEUED; 1183 } 1184 1185 int 1186 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1187 { 1188 struct siisata_channel *schp = (struct siisata_channel *)chp; 1189 struct siisata_prb *prb; 1190 struct ata_bio *ata_bio = &xfer->c_bio; 1191 1192 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1193 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1194 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1195 1196 ata_channel_lock_owned(chp); 1197 1198 prb = schp->sch_prb[xfer->c_slot]; 1199 memset(prb, 0, SIISATA_CMD_SIZE); 1200 1201 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1202 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1203 prb->prb_fis[rhd_c] |= xfer->c_drive; 1204 1205 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1206 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1207 ata_bio->error = ERR_DMA; 1208 ata_bio->r_error = 0; 1209 return ATASTART_ABORT; 1210 } 1211 1212 if (xfer->c_flags & C_POLL) { 1213 /* polled command, disable interrupts */ 1214 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1215 siisata_disable_port_interrupt(chp); 1216 } 1217 1218 siisata_activate_prb(schp, xfer->c_slot); 1219 1220 if ((ata_bio->flags & ATA_POLL) == 0) { 1221 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1222 ata_timeout, chp); 1223 return ATASTART_STARTED; 1224 } else 1225 return ATASTART_POLL; 1226 } 1227 1228 void 1229 siisata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1230 { 1231 struct siisata_channel *schp = (struct siisata_channel *)chp; 1232 1233 /* 1234 * polled command 1235 */ 1236 for (int i = 0; i < ATA_DELAY * 10; i++) { 1237 if (xfer->c_bio.flags & ATA_ITSDONE) 1238 break; 1239 siisata_intr_port(schp); 1240 DELAY(100); 1241 } 1242 1243 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1244 ata_timeout(xfer); 1245 } 1246 1247 siisata_enable_port_interrupt(chp); 1248 1249 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1250 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1251 DEBUG_FUNCS); 1252 } 1253 1254 void 1255 siisata_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1256 { 1257 siisata_cmd_complete(chp, xfer, 0); 1258 } 1259 1260 void 1261 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1262 int reason) 1263 { 1264 struct siisata_channel *schp = (struct siisata_channel *)chp; 1265 struct ata_bio *ata_bio = &xfer->c_bio; 1266 int drive = xfer->c_drive; 1267 bool deactivate = true; 1268 1269 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1270 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1271 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1272 1273 ata_bio->flags |= ATA_ITSDONE; 1274 switch (reason) { 1275 case KILL_GONE_INACTIVE: 1276 deactivate = false; 1277 /* FALLTHROUGH */ 1278 case KILL_GONE: 1279 ata_bio->error = ERR_NODEV; 1280 break; 1281 case KILL_RESET: 1282 ata_bio->error = ERR_RESET; 1283 break; 1284 case KILL_REQUEUE: 1285 ata_bio->error = REQUEUE; 1286 break; 1287 default: 1288 panic("%s: port %d: unknown reason %d", 1289 __func__, chp->ch_channel, reason); 1290 } 1291 ata_bio->r_error = WDCE_ABRT; 1292 1293 if (deactivate) { 1294 siisata_deactivate_prb(schp, xfer->c_slot); 1295 ata_deactivate_xfer(chp, xfer); 1296 } 1297 1298 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1299 } 1300 1301 int 1302 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1303 { 1304 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1305 struct siisata_channel *schp = (struct siisata_channel *)chp; 1306 struct ata_bio *ata_bio = &xfer->c_bio; 1307 int drive = xfer->c_drive; 1308 1309 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d tfd %x\n", 1310 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1311 chp->ch_channel, xfer->c_slot, xfer->c_drive, tfd), DEBUG_FUNCS); 1312 1313 if (ata_waitdrain_xfer_check(chp, xfer)) 1314 return 0; 1315 1316 if (xfer->c_flags & C_TIMEOU) { 1317 ata_bio->error = TIMEOUT; 1318 } 1319 1320 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1321 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1322 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1323 BUS_DMASYNC_POSTWRITE); 1324 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1325 1326 ata_bio->flags |= ATA_ITSDONE; 1327 if (ATACH_ST(tfd) & WDCS_DWF) { 1328 ata_bio->error = ERR_DF; 1329 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1330 ata_bio->error = ERROR; 1331 ata_bio->r_error = ATACH_ERR(tfd); 1332 } else if (ATACH_ST(tfd) & WDCS_CORR) 1333 ata_bio->flags |= ATA_CORR; 1334 1335 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1336 ata_bio->bcount), DEBUG_XFERS); 1337 if (ata_bio->error == NOERROR) { 1338 if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ) 1339 ata_bio->bcount -= 1340 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1341 else 1342 ata_bio->bcount = 0; 1343 } 1344 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1345 1346 siisata_deactivate_prb(schp, xfer->c_slot); 1347 ata_deactivate_xfer(chp, xfer); 1348 1349 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1350 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1351 atastart(chp); 1352 return 0; 1353 } 1354 1355 static int 1356 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1357 size_t count, int op) 1358 { 1359 1360 int error, seg; 1361 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1362 struct siisata_channel *schp = (struct siisata_channel *)chp; 1363 1364 struct siisata_prb *prbp; 1365 1366 prbp = schp->sch_prb[slot]; 1367 1368 if (data == NULL) { 1369 goto end; 1370 } 1371 1372 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1373 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1374 if (error) { 1375 aprint_error("%s port %d: " 1376 "failed to load xfer in slot %d: error %d\n", 1377 SIISATANAME(sc), chp->ch_channel, slot, error); 1378 return error; 1379 } 1380 1381 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1382 schp->sch_datad[slot]->dm_mapsize, 1383 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1384 1385 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1386 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1387 DEBUG_FUNCS | DEBUG_DEBUG); 1388 1389 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1390 prbp->prb_sge[seg].sge_da = 1391 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1392 prbp->prb_sge[seg].sge_dc = 1393 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1394 prbp->prb_sge[seg].sge_flags = htole32(0); 1395 } 1396 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1397 end: 1398 return 0; 1399 } 1400 1401 static void 1402 siisata_activate_prb(struct siisata_channel *schp, int slot) 1403 { 1404 struct siisata_softc *sc; 1405 bus_size_t offset; 1406 uint64_t pprb; 1407 1408 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1409 1410 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1411 1412 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1413 1414 pprb = schp->sch_bus_prb[slot]; 1415 1416 PRWRITE(sc, offset + 0, pprb >> 0); 1417 PRWRITE(sc, offset + 4, pprb >> 32); 1418 } 1419 1420 static void 1421 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1422 { 1423 struct siisata_softc *sc; 1424 1425 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1426 1427 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1428 } 1429 1430 static void 1431 siisata_reinit_port(struct ata_channel *chp, int drive) 1432 { 1433 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1434 int ps; 1435 1436 1437 if (chp->ch_ndrives > 1) { 1438 /* 1439 * Proper recovery would SET this bit, which makes it 1440 * not possible to submit new commands and resume execution 1441 * on non-errored drives, then wait for those commands, 1442 * to finish, and only then clear the bit and reset the state. 1443 * For now this is okay, since we never queue commands for 1444 * more than one drive. 1445 * XXX FIS-based switching 1446 */ 1447 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_RESUME); 1448 1449 for (int i = 0; i < chp->ch_ndrives; i++) { 1450 if (drive >= 0 && i != drive) 1451 continue; 1452 1453 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPSTS(i)), 0); 1454 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPQACT(i)), 0); 1455 } 1456 } 1457 1458 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1459 for (int i = 0; i < ATA_DELAY * 100; i++) { 1460 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1461 if ((ps & PR_PS_PORT_READY) != 0) 1462 break; 1463 1464 DELAY(10); 1465 } 1466 if ((ps & PR_PS_PORT_READY) == 0) { 1467 printf("%s: timeout waiting for port to be ready\n", __func__); 1468 ata_channel_lock(chp); 1469 siisata_reset_channel(chp, AT_POLL); 1470 ata_channel_unlock(chp); 1471 } 1472 1473 if (chp->ch_ndrives > 1) 1474 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1475 } 1476 1477 static void 1478 siisata_device_reset(struct ata_channel *chp) 1479 { 1480 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1481 int ps; 1482 1483 ata_channel_lock_owned(chp); 1484 1485 /* 1486 * This is always called after siisata_reinit_port(), so don't 1487 * need to deal with RESUME and clearing device error state. 1488 */ 1489 1490 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1491 1492 for (int i = 0; i < ATA_DELAY * 100; i++) { 1493 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1494 if ((ps & PR_PS_PORT_READY) != 0) 1495 break; 1496 1497 DELAY(10); 1498 } 1499 if ((ps & PR_PS_PORT_READY) == 0) { 1500 printf("%s: timeout waiting for port to be ready\n", __func__); 1501 siisata_reset_channel(chp, AT_POLL); 1502 } 1503 1504 ata_kill_active(chp, KILL_RESET, 0); 1505 } 1506 1507 1508 #if NATAPIBUS > 0 1509 void 1510 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1511 { 1512 struct ata_channel *chp = ata_sc->sc_chan; 1513 struct atac_softc *atac = chp->ch_atac; 1514 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1515 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1516 1517 /* 1518 * Fill in the scsipi_adapter. 1519 */ 1520 adapt->adapt_dev = atac->atac_dev; 1521 adapt->adapt_nchannels = atac->atac_nchannels; 1522 adapt->adapt_request = siisata_atapi_scsipi_request; 1523 adapt->adapt_minphys = siisata_atapi_minphys; 1524 atac->atac_atapi_adapter.atapi_probe_device = 1525 siisata_atapi_probe_device; 1526 1527 /* 1528 * Fill in the scsipi_channel. 1529 */ 1530 memset(chan, 0, sizeof(*chan)); 1531 chan->chan_adapter = adapt; 1532 chan->chan_bustype = &siisata_atapi_bustype; 1533 chan->chan_channel = chp->ch_channel; 1534 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1535 chan->chan_openings = 1; 1536 chan->chan_max_periph = 1; 1537 chan->chan_ntargets = 1; 1538 chan->chan_nluns = 1; 1539 1540 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1541 atapiprint); 1542 } 1543 1544 void 1545 siisata_atapi_minphys(struct buf *bp) 1546 { 1547 if (bp->b_bcount > MAXPHYS) 1548 bp->b_bcount = MAXPHYS; 1549 minphys(bp); 1550 } 1551 1552 /* 1553 * Kill off all pending xfers for a periph. 1554 * 1555 * Must be called at splbio(). 1556 */ 1557 void 1558 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1559 { 1560 struct atac_softc *atac = 1561 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1562 struct ata_channel *chp = 1563 atac->atac_channels[periph->periph_channel->chan_channel]; 1564 1565 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1566 } 1567 1568 void 1569 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1570 int reason) 1571 { 1572 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1573 struct siisata_channel *schp = (struct siisata_channel *)chp; 1574 bool deactivate = true; 1575 1576 /* remove this command from xfer queue */ 1577 switch (reason) { 1578 case KILL_GONE_INACTIVE: 1579 deactivate = false; 1580 /* FALLTHROUGH */ 1581 case KILL_GONE: 1582 sc_xfer->error = XS_DRIVER_STUFFUP; 1583 break; 1584 case KILL_RESET: 1585 sc_xfer->error = XS_RESET; 1586 break; 1587 case KILL_REQUEUE: 1588 sc_xfer->error = XS_REQUEUE; 1589 break; 1590 default: 1591 panic("%s: port %d: unknown reason %d", 1592 __func__, chp->ch_channel, reason); 1593 } 1594 1595 if (deactivate) { 1596 siisata_deactivate_prb(schp, xfer->c_slot); 1597 ata_deactivate_xfer(chp, xfer); 1598 } 1599 1600 ata_free_xfer(chp, xfer); 1601 scsipi_done(sc_xfer); 1602 } 1603 1604 void 1605 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1606 { 1607 struct scsipi_channel *chan = sc->sc_channel; 1608 struct scsipi_periph *periph; 1609 struct ataparams ids; 1610 struct ataparams *id = &ids; 1611 struct siisata_softc *siic = 1612 device_private(chan->chan_adapter->adapt_dev); 1613 struct atac_softc *atac = &siic->sc_atac; 1614 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1615 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1616 struct scsipibus_attach_args sa; 1617 char serial_number[21], model[41], firmware_revision[9]; 1618 int s; 1619 1620 /* skip if already attached */ 1621 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1622 return; 1623 1624 /* if no ATAPI device detected at attach time, skip */ 1625 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1626 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1627 target), DEBUG_PROBE); 1628 return; 1629 } 1630 1631 /* Some ATAPI devices need a bit more time after software reset. */ 1632 DELAY(5000); 1633 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1634 #ifdef ATAPI_DEBUG_PROBE 1635 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1636 device_xname(sc->sc_dev), target, 1637 id->atap_config & ATAPI_CFG_CMD_MASK, 1638 id->atap_config & ATAPI_CFG_DRQ_MASK); 1639 #endif 1640 periph = scsipi_alloc_periph(M_NOWAIT); 1641 if (periph == NULL) { 1642 aprint_error_dev(sc->sc_dev, 1643 "%s: unable to allocate periph for " 1644 "channel %d drive %d\n", __func__, 1645 chp->ch_channel, target); 1646 return; 1647 } 1648 periph->periph_dev = NULL; 1649 periph->periph_channel = chan; 1650 periph->periph_switch = &atapi_probe_periphsw; 1651 periph->periph_target = target; 1652 periph->periph_lun = 0; 1653 periph->periph_quirks = PQUIRK_ONLYBIG; 1654 1655 #ifdef SCSIPI_DEBUG 1656 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1657 SCSIPI_DEBUG_TARGET == target) 1658 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1659 #endif 1660 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1661 if (id->atap_config & ATAPI_CFG_REMOV) 1662 periph->periph_flags |= PERIPH_REMOVABLE; 1663 sa.sa_periph = periph; 1664 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1665 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1666 T_REMOV : T_FIXED; 1667 strnvisx(model, sizeof(model), id->atap_model, 40, 1668 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1669 strnvisx(serial_number, sizeof(serial_number), 1670 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1671 strnvisx(firmware_revision, sizeof(firmware_revision), 1672 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1673 sa.sa_inqbuf.vendor = model; 1674 sa.sa_inqbuf.product = serial_number; 1675 sa.sa_inqbuf.revision = firmware_revision; 1676 1677 /* 1678 * Determine the operating mode capabilities of the device. 1679 */ 1680 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1681 == ATAPI_CFG_CMD_16) { 1682 periph->periph_cap |= PERIPH_CAP_CMD16; 1683 1684 /* configure port for packet length */ 1685 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1686 PR_PC_PACKET_LENGTH); 1687 } else { 1688 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1689 PR_PC_PACKET_LENGTH); 1690 } 1691 1692 /* XXX This is gross. */ 1693 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1694 1695 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1696 1697 if (drvp->drv_softc) 1698 ata_probe_caps(drvp); 1699 else { 1700 s = splbio(); 1701 drvp->drive_type &= ATA_DRIVET_NONE; 1702 splx(s); 1703 } 1704 } else { 1705 s = splbio(); 1706 drvp->drive_type &= ATA_DRIVET_NONE; 1707 splx(s); 1708 } 1709 } 1710 1711 static const struct ata_xfer_ops siisata_atapi_xfer_ops = { 1712 .c_start = siisata_atapi_start, 1713 .c_intr = siisata_atapi_complete, 1714 .c_poll = siisata_atapi_poll, 1715 .c_abort = siisata_atapi_abort, 1716 .c_kill_xfer = siisata_atapi_kill_xfer, 1717 }; 1718 1719 void 1720 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1721 scsipi_adapter_req_t req, void *arg) 1722 { 1723 struct scsipi_adapter *adapt = chan->chan_adapter; 1724 struct scsipi_periph *periph; 1725 struct scsipi_xfer *sc_xfer; 1726 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1727 struct atac_softc *atac = &sc->sc_atac; 1728 struct ata_xfer *xfer; 1729 int channel = chan->chan_channel; 1730 int drive, s; 1731 1732 switch (req) { 1733 case ADAPTER_REQ_RUN_XFER: 1734 sc_xfer = arg; 1735 periph = sc_xfer->xs_periph; 1736 drive = periph->periph_target; 1737 1738 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1739 device_xname(atac->atac_dev), channel, drive), 1740 DEBUG_XFERS); 1741 1742 if (!device_is_active(atac->atac_dev)) { 1743 sc_xfer->error = XS_DRIVER_STUFFUP; 1744 scsipi_done(sc_xfer); 1745 return; 1746 } 1747 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1748 if (xfer == NULL) { 1749 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1750 scsipi_done(sc_xfer); 1751 return; 1752 } 1753 1754 if (sc_xfer->xs_control & XS_CTL_POLL) 1755 xfer->c_flags |= C_POLL; 1756 xfer->c_drive = drive; 1757 xfer->c_flags |= C_ATAPI; 1758 xfer->c_databuf = sc_xfer->data; 1759 xfer->c_bcount = sc_xfer->datalen; 1760 xfer->ops = &siisata_atapi_xfer_ops; 1761 xfer->c_scsipi = sc_xfer; 1762 xfer->c_atapi.c_dscpoll = 0; 1763 s = splbio(); 1764 ata_exec_xfer(atac->atac_channels[channel], xfer); 1765 #ifdef DIAGNOSTIC 1766 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1767 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1768 panic("%s: polled command not done", __func__); 1769 #endif 1770 splx(s); 1771 return; 1772 1773 default: 1774 /* Not supported, nothing to do. */ 1775 ; 1776 } 1777 } 1778 1779 int 1780 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1781 { 1782 struct siisata_channel *schp = (struct siisata_channel *)chp; 1783 struct siisata_prb *prbp; 1784 1785 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1786 1787 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1788 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1789 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1790 DEBUG_XFERS); 1791 1792 ata_channel_lock_owned(chp); 1793 1794 prbp = schp->sch_prb[xfer->c_slot]; 1795 memset(prbp, 0, SIISATA_CMD_SIZE); 1796 1797 /* fill in direction for ATAPI command */ 1798 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1799 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1800 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1801 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1802 1803 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1804 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1805 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1806 1807 /* copy over ATAPI command */ 1808 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1809 1810 if (siisata_dma_setup(chp, xfer->c_slot, 1811 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1812 xfer->c_databuf : NULL, 1813 xfer->c_bcount, 1814 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1815 BUS_DMA_READ : BUS_DMA_WRITE) 1816 ) { 1817 sc_xfer->error = XS_DRIVER_STUFFUP; 1818 return ATASTART_ABORT; 1819 } 1820 1821 if (xfer->c_flags & C_POLL) { 1822 /* polled command, disable interrupts */ 1823 prbp->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1824 siisata_disable_port_interrupt(chp); 1825 } 1826 1827 siisata_activate_prb(schp, xfer->c_slot); 1828 1829 if ((xfer->c_flags & C_POLL) == 0) { 1830 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1831 ata_timeout, chp); 1832 return ATASTART_STARTED; 1833 } else 1834 return ATASTART_POLL; 1835 } 1836 1837 void 1838 siisata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1839 { 1840 struct siisata_channel *schp = (struct siisata_channel *)chp; 1841 1842 /* 1843 * polled command 1844 */ 1845 for (int i = 0; i < ATA_DELAY * 10; i++) { 1846 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1847 break; 1848 siisata_intr_port(schp); 1849 DELAY(100); 1850 } 1851 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1852 ata_timeout(xfer); 1853 } 1854 /* reenable interrupts */ 1855 siisata_enable_port_interrupt(chp); 1856 1857 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1858 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1859 DEBUG_FUNCS); 1860 } 1861 1862 void 1863 siisata_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1864 { 1865 siisata_atapi_complete(chp, xfer, 0); 1866 } 1867 1868 int 1869 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1870 int tfd) 1871 { 1872 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1873 struct siisata_channel *schp = (struct siisata_channel *)chp; 1874 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1875 1876 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1877 DEBUG_INTR); 1878 1879 if (ata_waitdrain_xfer_check(chp, xfer)) 1880 return 0; 1881 1882 if (xfer->c_flags & C_TIMEOU) { 1883 sc_xfer->error = XS_TIMEOUT; 1884 } 1885 1886 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1887 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1888 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1889 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1890 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1891 1892 sc_xfer->resid = sc_xfer->datalen; 1893 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1894 PRSO_RTC)); 1895 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1896 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1897 if ((ATACH_ST(tfd) & WDCS_ERR) && 1898 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1899 sc_xfer->resid == sc_xfer->datalen)) { 1900 sc_xfer->error = XS_SHORTSENSE; 1901 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1902 if ((sc_xfer->xs_periph->periph_quirks & 1903 PQUIRK_NOSENSE) == 0) { 1904 /* request sense */ 1905 sc_xfer->error = XS_BUSY; 1906 sc_xfer->status = SCSI_CHECK; 1907 } 1908 } 1909 1910 siisata_deactivate_prb(schp, xfer->c_slot); 1911 ata_deactivate_xfer(chp, xfer); 1912 1913 ata_free_xfer(chp, xfer); 1914 scsipi_done(sc_xfer); 1915 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1916 atastart(chp); 1917 return 0; 1918 } 1919 1920 #endif /* NATAPIBUS */ 1921
Indexes created Wed Oct 22 13:09:56 GMT 2025