siisata.c revision 1.35.6.11
1 /* $NetBSD: siisata.c,v 1.35.6.11 2018/10/21 18:13:14 jdolecek Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.35.6.11 2018/10/21 18:13:14 jdolecek Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define WDC_RESET_WAIT 31000 /* 31s for drive reset */ 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #if _BYTE_ORDER == _LITTLE_ENDIAN 116 #define bus_space_read_stream_4 bus_space_read_4 117 #define bus_space_read_region_stream_4 bus_space_read_region_4 118 #else 119 static inline uint32_t 120 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 121 { 122 return htole32(bus_space_read_4(t, h, o)); 123 } 124 125 static inline void 126 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 127 bus_size_t o, uint32_t *p, bus_size_t c) 128 { 129 bus_space_read_region_4(t, h, o, p, c); 130 for (bus_size_t i = 0; i < c; i++) { 131 p[i] = htole32(p[i]); 132 } 133 } 134 #endif 135 #endif 136 137 static void siisata_attach_port(struct siisata_softc *, int); 138 static void siisata_intr_port(struct siisata_channel *); 139 140 void siisata_probe_drive(struct ata_channel *); 141 void siisata_setup_channel(struct ata_channel *); 142 143 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 144 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 145 void siisata_reset_channel(struct ata_channel *, int); 146 int siisata_ata_addref(struct ata_drive_datas *); 147 void siisata_ata_delref(struct ata_drive_datas *); 148 void siisata_killpending(struct ata_drive_datas *); 149 150 int siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 151 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_cmd_poll(struct ata_channel *, struct ata_xfer *); 153 void siisata_cmd_abort(struct ata_channel *, struct ata_xfer *); 154 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 155 static void siisata_cmd_done_end(struct ata_channel *, struct ata_xfer *); 156 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 158 int siisata_bio_start(struct ata_channel *, struct ata_xfer *); 159 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 160 void siisata_bio_poll(struct ata_channel *, struct ata_xfer *); 161 void siisata_bio_abort(struct ata_channel *, struct ata_xfer *); 162 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 163 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 164 165 static int siisata_reinit_port(struct ata_channel *, int); 166 static void siisata_device_reset(struct ata_channel *); 167 static void siisata_activate_prb(struct siisata_channel *, int); 168 static void siisata_deactivate_prb(struct siisata_channel *, int); 169 static int siisata_dma_setup(struct ata_channel *, int, void *, size_t, int); 170 static void siisata_channel_recover(struct ata_channel *, int, uint32_t); 171 172 #if NATAPIBUS > 0 173 void siisata_atapibus_attach(struct atabus_softc *); 174 void siisata_atapi_probe_device(struct atapibus_softc *, int); 175 void siisata_atapi_minphys(struct buf *); 176 int siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 177 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 178 void siisata_atapi_poll(struct ata_channel *, struct ata_xfer *); 179 void siisata_atapi_abort(struct ata_channel *, struct ata_xfer *); 180 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 181 void siisata_atapi_scsipi_request(struct scsipi_channel *, 182 scsipi_adapter_req_t, void *); 183 void siisata_atapi_kill_pending(struct scsipi_periph *); 184 #endif /* NATAPIBUS */ 185 186 const struct ata_bustype siisata_ata_bustype = { 187 SCSIPI_BUSTYPE_ATA, 188 siisata_ata_bio, 189 siisata_reset_drive, 190 siisata_reset_channel, 191 siisata_exec_command, 192 ata_get_params, 193 siisata_ata_addref, 194 siisata_ata_delref, 195 siisata_killpending, 196 siisata_channel_recover, 197 }; 198 199 #if NATAPIBUS > 0 200 static const struct scsipi_bustype siisata_atapi_bustype = { 201 SCSIPI_BUSTYPE_ATAPI, 202 atapi_scsipi_cmd, 203 atapi_interpret_sense, 204 atapi_print_addr, 205 siisata_atapi_kill_pending, 206 NULL, 207 }; 208 #endif /* NATAPIBUS */ 209 210 211 void 212 siisata_attach(struct siisata_softc *sc) 213 { 214 int i; 215 216 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 217 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 218 219 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 220 sc->sc_atac.atac_pio_cap = 4; 221 sc->sc_atac.atac_dma_cap = 2; 222 sc->sc_atac.atac_udma_cap = 6; 223 sc->sc_atac.atac_channels = sc->sc_chanarray; 224 sc->sc_atac.atac_probe = siisata_probe_drive; 225 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 226 sc->sc_atac.atac_set_modes = siisata_setup_channel; 227 #if NATAPIBUS > 0 228 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 229 #endif 230 231 /* come out of reset state */ 232 GRWRITE(sc, GR_GC, 0); 233 234 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 235 siisata_attach_port(sc, i); 236 } 237 238 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 239 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 240 return; 241 } 242 243 static void 244 siisata_disable_port_interrupt(struct ata_channel *chp) 245 { 246 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 247 248 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 249 } 250 251 static void 252 siisata_enable_port_interrupt(struct ata_channel *chp) 253 { 254 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 255 256 /* clear any interrupts */ 257 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 258 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 259 /* and enable CmdErrr+CmdCmpl interrupting */ 260 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 261 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 262 } 263 264 static int 265 siisata_init_port(struct siisata_softc *sc, int port) 266 { 267 struct siisata_channel *schp; 268 struct ata_channel *chp; 269 int error; 270 271 schp = &sc->sc_channels[port]; 272 chp = (struct ata_channel *)schp; 273 274 /* 275 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 276 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 277 */ 278 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 279 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 280 /* initialize port */ 281 error = siisata_reinit_port(chp, -1); 282 /* enable CmdErrr+CmdCmpl interrupting */ 283 siisata_enable_port_interrupt(chp); 284 /* enable port interrupt */ 285 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 286 287 return error; 288 } 289 290 static void 291 siisata_attach_port(struct siisata_softc *sc, int port) 292 { 293 int j; 294 int dmasize; 295 int error; 296 void *prbp; 297 struct siisata_channel *schp; 298 struct ata_channel *chp; 299 300 schp = &sc->sc_channels[port]; 301 chp = (struct ata_channel *)schp; 302 sc->sc_chanarray[port] = chp; 303 chp->ch_channel = port; 304 chp->ch_atac = &sc->sc_atac; 305 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 306 if (chp->ch_queue == NULL) { 307 aprint_error_dev(sc->sc_atac.atac_dev, 308 "port %d: can't allocate memory " 309 "for command queue\n", chp->ch_channel); 310 return; 311 } 312 313 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 314 315 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 316 __func__, dmasize), DEBUG_FUNCS); 317 318 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 319 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 320 if (error) { 321 aprint_error_dev(sc->sc_atac.atac_dev, 322 "unable to allocate PRB table memory, " 323 "error=%d\n", error); 324 return; 325 } 326 327 error = bus_dmamem_map(sc->sc_dmat, 328 &schp->sch_prb_seg, schp->sch_prb_nseg, 329 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 330 if (error) { 331 aprint_error_dev(sc->sc_atac.atac_dev, 332 "unable to map PRB table memory, " 333 "error=%d\n", error); 334 bus_dmamem_free(sc->sc_dmat, 335 &schp->sch_prb_seg, schp->sch_prb_nseg); 336 return; 337 } 338 339 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 340 BUS_DMA_NOWAIT, &schp->sch_prbd); 341 if (error) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "unable to create PRB table map, " 344 "error=%d\n", error); 345 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 346 bus_dmamem_free(sc->sc_dmat, 347 &schp->sch_prb_seg, schp->sch_prb_nseg); 348 return; 349 } 350 351 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 352 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 353 if (error) { 354 aprint_error_dev(sc->sc_atac.atac_dev, 355 "unable to load PRB table map, " 356 "error=%d\n", error); 357 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 358 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 359 bus_dmamem_free(sc->sc_dmat, 360 &schp->sch_prb_seg, schp->sch_prb_nseg); 361 return; 362 } 363 364 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 365 schp->sch_prb[j] = (struct siisata_prb *) 366 ((char *)prbp + SIISATA_CMD_SIZE * j); 367 schp->sch_bus_prb[j] = 368 schp->sch_prbd->dm_segs[0].ds_addr + 369 SIISATA_CMD_SIZE * j; 370 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 371 SIISATA_NSGE, MAXPHYS, 0, 372 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 373 &schp->sch_datad[j]); 374 if (error) { 375 aprint_error_dev(sc->sc_atac.atac_dev, 376 "couldn't create xfer DMA map, error=%d\n", 377 error); 378 return; 379 } 380 } 381 382 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 383 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 384 aprint_error_dev(sc->sc_atac.atac_dev, 385 "couldn't map port %d SStatus regs\n", 386 chp->ch_channel); 387 return; 388 } 389 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 390 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 391 aprint_error_dev(sc->sc_atac.atac_dev, 392 "couldn't map port %d SControl regs\n", 393 chp->ch_channel); 394 return; 395 } 396 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 397 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 398 aprint_error_dev(sc->sc_atac.atac_dev, 399 "couldn't map port %d SError regs\n", 400 chp->ch_channel); 401 return; 402 } 403 404 (void)siisata_init_port(sc, port); 405 406 ata_channel_attach(chp); 407 408 return; 409 } 410 411 int 412 siisata_detach(struct siisata_softc *sc, int flags) 413 { 414 struct atac_softc *atac = &sc->sc_atac; 415 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 416 struct siisata_channel *schp; 417 struct ata_channel *chp; 418 int i, j, error; 419 420 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 421 schp = &sc->sc_channels[i]; 422 chp = sc->sc_chanarray[i]; 423 424 if (chp->atabus == NULL) 425 continue; 426 if ((error = config_detach(chp->atabus, flags)) != 0) 427 return error; 428 429 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 430 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 431 432 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 433 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 434 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 435 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 436 bus_dmamem_free(sc->sc_dmat, 437 &schp->sch_prb_seg, schp->sch_prb_nseg); 438 439 chp->atabus = NULL; 440 441 ata_channel_detach(chp); 442 } 443 444 if (adapt->adapt_refcnt != 0) 445 return EBUSY; 446 447 /* leave the chip in reset */ 448 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 449 450 return 0; 451 } 452 453 void 454 siisata_resume(struct siisata_softc *sc) 455 { 456 /* come out of reset state */ 457 GRWRITE(sc, GR_GC, 0); 458 459 for (int port = 0; port < sc->sc_atac.atac_nchannels; port++) { 460 int error; 461 462 error = siisata_init_port(sc, port); 463 if (error) { 464 struct siisata_channel *schp = &sc->sc_channels[port]; 465 struct ata_channel *chp = (struct ata_channel *)schp; 466 467 ata_channel_lock(chp); 468 siisata_reset_channel(chp, AT_POLL); 469 ata_channel_unlock(chp); 470 } 471 } 472 } 473 474 int 475 siisata_intr(void *v) 476 { 477 struct siisata_softc *sc = v; 478 uint32_t is; 479 int i, r = 0; 480 while ((is = GRREAD(sc, GR_GIS))) { 481 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 482 SIISATANAME(sc), __func__, is), DEBUG_INTR); 483 r = 1; 484 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 485 if (is & GR_GIS_PXIS(i)) 486 siisata_intr_port(&sc->sc_channels[i]); 487 } 488 return r; 489 } 490 491 static void 492 siisata_intr_port(struct siisata_channel *schp) 493 { 494 struct siisata_softc *sc = 495 (struct siisata_softc *)schp->ata_channel.ch_atac; 496 struct ata_channel *chp = &schp->ata_channel; 497 struct ata_xfer *xfer = NULL; 498 uint32_t pss, pis, tfd = 0; 499 bool recover = false; 500 501 /* get slot status, clearing completion interrupt */ 502 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 503 504 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x ", 505 SIISATANAME(sc), __func__, chp->ch_channel, pss), 506 DEBUG_INTR); 507 508 if (__predict_true((pss & PR_PSS_ATTENTION) == 0)) { 509 SIISATA_DEBUG_PRINT(("no attention"), DEBUG_INTR); 510 goto process; 511 } 512 513 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 514 515 SIISATA_DEBUG_PRINT(("pis 0x%x\n", pss), DEBUG_INTR); 516 517 if (pis & PR_PIS_CMDERRR) { 518 uint32_t ec; 519 520 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 521 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 522 523 /* emulate a CRC error by default */ 524 tfd = ATACH_ERR_ST(WDCE_CRC, WDCS_ERR); 525 526 if (ec <= PR_PCE_DATAFISERROR) { 527 if (ec == PR_PCE_DEVICEERROR 528 && (chp->ch_flags & ATACH_NCQ) == 0) { 529 xfer = ata_queue_get_active_xfer(chp); 530 531 /* read in specific information about error */ 532 uint32_t prbfis = bus_space_read_stream_4( 533 sc->sc_prt, sc->sc_prh, 534 PRSX(chp->ch_channel, xfer->c_slot, 535 PRSO_FIS)); 536 537 /* get status and error */ 538 int ntfd = satafis_rdh_parse(chp, 539 (uint8_t *)&prbfis); 540 541 if (ATACH_ST(ntfd) & WDCS_ERR) 542 tfd = ntfd; 543 } 544 545 /* 546 * We don't expect the recovery to trigger error, 547 * but handle this just in case. 548 */ 549 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 550 recover = true; 551 else { 552 aprint_error_dev(sc->sc_atac.atac_dev, 553 "error ec %x while recovering\n", ec); 554 555 /* Command will be marked as errored out */ 556 pss = 0; 557 } 558 } else { 559 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 560 " on channel %d (ctx 0x%x), resetting\n", 561 ec, chp->ch_channel, 562 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 563 564 /* okay, we have a "Fatal Error" */ 565 siisata_device_reset(chp); 566 } 567 } 568 569 /* clear some (ok, all) ints */ 570 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 571 572 if (__predict_false(recover)) 573 ata_channel_freeze(chp); 574 575 process: 576 if (xfer != NULL) { 577 xfer->ops->c_intr(chp, xfer, tfd); 578 } else { 579 /* 580 * For NCQ, HBA halts processing when error is notified, 581 * and any further D2H FISes are ignored until the error 582 * condition is cleared. Hence if a command is inactive, 583 * it means it actually already finished successfully. 584 * Note: active slots can change as c_intr() callback 585 * can activate another command(s), so must only process 586 * commands active before we start processing. 587 */ 588 uint32_t aslots = ata_queue_active(chp); 589 590 for (int slot=0; slot < SIISATA_MAX_SLOTS; slot++) { 591 if ((aslots & __BIT(slot)) != 0 && 592 (pss & PR_PXSS(slot)) == 0) { 593 xfer = ata_queue_hwslot_to_xfer(chp, slot); 594 xfer->ops->c_intr(chp, xfer, 0); 595 } 596 } 597 } 598 599 if (__predict_false(recover)) { 600 ata_channel_lock(chp); 601 ata_channel_thaw_locked(chp); 602 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 603 ata_channel_unlock(chp); 604 } 605 } 606 607 /* Recover channel after transfer aborted */ 608 void 609 siisata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 610 { 611 struct siisata_channel *schp = (struct siisata_channel *)chp; 612 struct siisata_softc *sc = 613 (struct siisata_softc *)schp->ata_channel.ch_atac; 614 int drive; 615 616 ata_channel_lock_owned(chp); 617 618 if (chp->ch_ndrives > PMP_PORT_CTL) { 619 /* Get PM port number for the device in error */ 620 int pcr = PRREAD(sc, PRX(chp->ch_channel, PRO_PCR)); 621 drive = PRO_PCR_PMP(pcr); 622 } else 623 drive = 0; 624 625 /* 626 * If BSY or DRQ bits are set, must execute COMRESET to return 627 * device to idle state. Otherwise, commands can be reissued 628 * after reinitalization of port. After that, need to execute 629 * READ LOG EXT for NCQ to unblock device processing if COMRESET 630 * was not done. 631 */ 632 if ((ATACH_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 633 siisata_device_reset(chp); 634 goto out; 635 } 636 637 KASSERT(drive >= 0); 638 (void)siisata_reinit_port(chp, drive); 639 640 ata_recovery_resume(chp, drive, tfd, flags); 641 642 out: 643 /* Drive unblocked, back to normal operation */ 644 return; 645 } 646 647 void 648 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 649 { 650 struct ata_channel *chp = drvp->chnl_softc; 651 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 652 struct siisata_channel *schp = (struct siisata_channel *)chp; 653 struct siisata_prb *prb; 654 uint8_t c_slot; 655 uint32_t pss, pis; 656 int i; 657 bool timed_out; 658 659 ata_channel_lock_owned(chp); 660 661 if (siisata_reinit_port(chp, drvp->drive)) 662 siisata_reset_channel(chp, flags); 663 664 /* get a slot for running the command on */ 665 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 666 panic("%s: %s: failed to get xfer for reset, port %d\n", 667 device_xname(sc->sc_atac.atac_dev), 668 __func__, chp->ch_channel); 669 /* NOTREACHED */ 670 } 671 672 prb = schp->sch_prb[c_slot]; 673 memset(prb, 0, SIISATA_CMD_SIZE); 674 prb->prb_control = 675 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 676 KASSERT(drvp->drive <= PMP_PORT_CTL); 677 prb->prb_fis[rhd_c] = drvp->drive; 678 679 siisata_disable_port_interrupt(chp); 680 681 siisata_activate_prb(schp, c_slot); 682 683 timed_out = true; 684 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 685 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 686 if ((pss & PR_PXSS(c_slot)) == 0) { 687 timed_out = false; 688 break; 689 } 690 if (pss & PR_PSS_ATTENTION) 691 break; 692 ata_delay(chp, 10, "siiprb", flags); 693 } 694 695 siisata_deactivate_prb(schp, c_slot); 696 697 if ((pss & PR_PSS_ATTENTION) != 0) { 698 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 699 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 700 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 701 702 if (slot != c_slot) 703 device_printf(sc->sc_atac.atac_dev, "%s port %d " 704 "drive %d slot %d c_slot %d", __func__, 705 chp->ch_channel, drvp->drive, slot, c_slot); 706 707 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 708 PR_PIS_CMDERRR); 709 } 710 711 siisata_enable_port_interrupt(chp); 712 713 if (timed_out) { 714 /* timeout */ 715 siisata_device_reset(chp); /* XXX is this right? */ 716 if (sigp) 717 *sigp = 0xffffffff; 718 } else { 719 /* read the signature out of the FIS */ 720 if (sigp) { 721 *sigp = 0; 722 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 723 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 724 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 725 PRSO_FIS+0xc)) & 0xff; 726 } 727 } 728 729 ata_queue_free_slot(chp, c_slot); 730 } 731 732 void 733 siisata_reset_channel(struct ata_channel *chp, int flags) 734 { 735 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 736 struct siisata_channel *schp = (struct siisata_channel *)chp; 737 738 SIISATA_DEBUG_PRINT(("%s: %s channel %d\n", SIISATANAME(sc), __func__, 739 chp->ch_channel), DEBUG_FUNCS); 740 741 ata_channel_lock_owned(chp); 742 743 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 744 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 745 aprint_error("%s port %d: reset failed\n", 746 SIISATANAME(sc), chp->ch_channel); 747 /* XXX and then ? */ 748 } 749 750 siisata_device_reset(chp); 751 752 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 753 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 754 755 return; 756 } 757 758 int 759 siisata_ata_addref(struct ata_drive_datas *drvp) 760 { 761 return 0; 762 } 763 764 void 765 siisata_ata_delref(struct ata_drive_datas *drvp) 766 { 767 return; 768 } 769 770 void 771 siisata_killpending(struct ata_drive_datas *drvp) 772 { 773 return; 774 } 775 776 void 777 siisata_probe_drive(struct ata_channel *chp) 778 { 779 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 780 struct siisata_channel *schp = (struct siisata_channel *)chp; 781 int i; 782 uint32_t sig; 783 struct siisata_prb *prb; 784 bool timed_out; 785 uint8_t c_slot; 786 787 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 788 __func__, chp->ch_channel), DEBUG_FUNCS); 789 790 ata_channel_lock(chp); 791 792 /* get a slot for running the command on */ 793 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 794 aprint_error_dev(sc->sc_atac.atac_dev, 795 "%s: failed to get xfer port %d\n", 796 __func__, chp->ch_channel); 797 ata_channel_unlock(chp); 798 return; 799 } 800 801 /* 802 * disable port interrupt as we're polling for PHY up and 803 * prb completion 804 */ 805 siisata_disable_port_interrupt(chp); 806 807 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 808 schp->sch_sstatus, AT_WAIT)) { 809 case SStatus_DET_DEV: 810 /* clear any interrupts */ 811 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 812 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 813 814 /* wait for ready */ 815 timed_out = 1; 816 for (i = 0; i < ATA_DELAY / 10; i++) { 817 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & 818 PR_PS_PORT_READY) { 819 timed_out = 0; 820 break; 821 } 822 823 ata_delay(chp, 10, "siiprbrd", AT_WAIT); 824 } 825 if (timed_out) { 826 aprint_error_dev(sc->sc_atac.atac_dev, 827 "timed out waiting for PORT_READY on port %d, " 828 "reinitializing\n", chp->ch_channel); 829 if (siisata_reinit_port(chp, -1)) 830 siisata_reset_channel(chp, AT_WAIT); 831 } 832 833 prb = schp->sch_prb[c_slot]; 834 memset(prb, 0, SIISATA_CMD_SIZE); 835 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 836 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 837 838 siisata_activate_prb(schp, c_slot); 839 840 timed_out = 1; 841 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 842 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 843 PR_PXSS(c_slot)) == 0) { 844 /* prb completed */ 845 timed_out = 0; 846 break; 847 } 848 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 849 PR_PIS_CMDERRR) { 850 /* we got an error; handle as timeout */ 851 break; 852 } 853 854 ata_delay(chp, 10, "siiprb", AT_WAIT); 855 } 856 857 siisata_deactivate_prb(schp, c_slot); 858 859 if (timed_out) { 860 aprint_error_dev(sc->sc_atac.atac_dev, 861 "SOFT_RESET failed on port %d (error %d PSS 0x%x PIS 0x%x), " 862 "resetting\n", chp->ch_channel, 863 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 864 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)), 865 PRREAD(sc, PRX(chp->ch_channel, PRO_PIS))); 866 if (siisata_reinit_port(chp, -1)) 867 siisata_reset_channel(chp, AT_WAIT); 868 break; 869 } 870 871 /* read the signature out of the FIS */ 872 sig = 0; 873 sig |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 874 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 875 sig |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 876 PRSO_FIS+0xc)) & 0xff; 877 878 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 879 __func__, sig), DEBUG_PROBE); 880 881 if (sig == 0x96690101) 882 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 883 PR_PC_PMP_ENABLE); 884 sata_interpret_sig(chp, 0, sig); 885 break; 886 default: 887 break; 888 } 889 890 siisata_enable_port_interrupt(chp); 891 892 ata_queue_free_slot(chp, c_slot); 893 894 ata_channel_unlock(chp); 895 896 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 897 __func__, chp->ch_channel), DEBUG_PROBE); 898 return; 899 } 900 901 void 902 siisata_setup_channel(struct ata_channel *chp) 903 { 904 return; 905 } 906 907 static const struct ata_xfer_ops siisata_cmd_xfer_ops = { 908 .c_start = siisata_cmd_start, 909 .c_intr = siisata_cmd_complete, 910 .c_poll = siisata_cmd_poll, 911 .c_abort = siisata_cmd_abort, 912 .c_kill_xfer = siisata_cmd_kill_xfer, 913 }; 914 915 int 916 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 917 { 918 struct ata_channel *chp = drvp->chnl_softc; 919 struct ata_command *ata_c = &xfer->c_ata_c; 920 int ret; 921 int s; 922 923 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 924 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 925 DEBUG_FUNCS); 926 927 if (ata_c->flags & AT_POLL) 928 xfer->c_flags |= C_POLL; 929 if (ata_c->flags & AT_WAIT) 930 xfer->c_flags |= C_WAIT; 931 xfer->c_drive = drvp->drive; 932 xfer->c_databuf = ata_c->data; 933 xfer->c_bcount = ata_c->bcount; 934 xfer->ops = &siisata_cmd_xfer_ops; 935 s = splbio(); 936 ata_exec_xfer(chp, xfer); 937 #ifdef DIAGNOSTIC 938 if ((ata_c->flags & AT_POLL) != 0 && 939 (ata_c->flags & AT_DONE) == 0) 940 panic("%s: polled command not done", __func__); 941 #endif 942 if (ata_c->flags & AT_DONE) { 943 ret = ATACMD_COMPLETE; 944 } else { 945 if (ata_c->flags & AT_WAIT) { 946 ata_wait_cmd(chp, xfer); 947 ret = ATACMD_COMPLETE; 948 } else { 949 ret = ATACMD_QUEUED; 950 } 951 } 952 splx(s); 953 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 954 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 955 DEBUG_FUNCS); 956 return ret; 957 } 958 959 int 960 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 961 { 962 struct siisata_channel *schp = (struct siisata_channel *)chp; 963 struct ata_command *ata_c = &xfer->c_ata_c; 964 struct siisata_prb *prb; 965 966 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 967 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 968 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 969 DEBUG_FUNCS|DEBUG_XFERS); 970 971 ata_channel_lock_owned(chp); 972 973 prb = schp->sch_prb[xfer->c_slot]; 974 memset(prb, 0, SIISATA_CMD_SIZE); 975 976 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 977 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 978 prb->prb_fis[rhd_c] |= xfer->c_drive; 979 980 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 981 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 982 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 983 } 984 985 if (siisata_dma_setup(chp, xfer->c_slot, 986 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 987 ata_c->bcount, 988 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 989 ata_c->flags |= AT_DF; 990 return ATASTART_ABORT; 991 } 992 993 if (xfer->c_flags & C_POLL) { 994 /* polled command, disable interrupts */ 995 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 996 siisata_disable_port_interrupt(chp); 997 } 998 999 /* go for it */ 1000 siisata_activate_prb(schp, xfer->c_slot); 1001 1002 if ((ata_c->flags & AT_POLL) == 0) { 1003 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1004 ata_timeout, chp); 1005 return ATASTART_STARTED; 1006 } else 1007 return ATASTART_POLL; 1008 } 1009 1010 void 1011 siisata_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1012 { 1013 struct siisata_channel *schp = (struct siisata_channel *)chp; 1014 1015 /* 1016 * polled command 1017 */ 1018 for (int i = 0; i < xfer->c_ata_c.timeout * 10; i++) { 1019 if (xfer->c_ata_c.flags & AT_DONE) 1020 break; 1021 siisata_intr_port(schp); 1022 DELAY(100); 1023 } 1024 1025 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1026 ata_timeout(xfer); 1027 } 1028 1029 /* reenable interrupts */ 1030 siisata_enable_port_interrupt(chp); 1031 1032 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1033 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1034 DEBUG_FUNCS); 1035 } 1036 1037 void 1038 siisata_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1039 { 1040 siisata_cmd_complete(chp, xfer, 0); 1041 } 1042 1043 void 1044 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1045 int reason) 1046 { 1047 struct ata_command *ata_c = &xfer->c_ata_c; 1048 struct siisata_channel *schp = (struct siisata_channel *)chp; 1049 bool deactivate = true; 1050 1051 switch (reason) { 1052 case KILL_GONE_INACTIVE: 1053 deactivate = false; 1054 /* FALLTHROUGH */ 1055 case KILL_GONE: 1056 ata_c->flags |= AT_GONE; 1057 break; 1058 case KILL_RESET: 1059 ata_c->flags |= AT_RESET; 1060 break; 1061 case KILL_REQUEUE: 1062 panic("%s: not supposed to be requeued\n", __func__); 1063 break; 1064 default: 1065 panic("%s: port %d: unknown reason %d", 1066 __func__, chp->ch_channel, reason); 1067 } 1068 1069 siisata_cmd_done_end(chp, xfer); 1070 1071 if (deactivate) { 1072 siisata_deactivate_prb(schp, xfer->c_slot); 1073 ata_deactivate_xfer(chp, xfer); 1074 } 1075 } 1076 1077 int 1078 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1079 { 1080 struct siisata_channel *schp = (struct siisata_channel *)chp; 1081 struct ata_command *ata_c = &xfer->c_ata_c; 1082 #ifdef SIISATA_DEBUG 1083 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1084 #endif 1085 1086 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1087 SIISATANAME(sc), __func__, 1088 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1089 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1090 DEBUG_FUNCS|DEBUG_XFERS); 1091 1092 if (ata_waitdrain_xfer_check(chp, xfer)) 1093 return 0; 1094 1095 if (xfer->c_flags & C_TIMEOU) 1096 ata_c->flags |= AT_TIMEOU; 1097 1098 if (ATACH_ST(tfd) & WDCS_BSY) { 1099 ata_c->flags |= AT_TIMEOU; 1100 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1101 ata_c->r_error = ATACH_ERR(tfd); 1102 ata_c->flags |= AT_ERROR; 1103 } 1104 1105 siisata_cmd_done(chp, xfer, tfd); 1106 1107 siisata_deactivate_prb(schp, xfer->c_slot); 1108 ata_deactivate_xfer(chp, xfer); 1109 1110 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1111 atastart(chp); 1112 1113 return 0; 1114 } 1115 1116 void 1117 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1118 { 1119 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1120 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1121 struct siisata_channel *schp = (struct siisata_channel *)chp; 1122 struct ata_command *ata_c = &xfer->c_ata_c; 1123 uint16_t *idwordbuf; 1124 int i; 1125 1126 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1127 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1128 1129 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1130 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1131 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1132 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1133 BUS_DMASYNC_POSTWRITE); 1134 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1135 } 1136 1137 if (ata_c->flags & AT_READREG) { 1138 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1139 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1140 fis, __arraycount(fis)); 1141 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1142 } 1143 1144 /* correct the endianess of IDENTIFY data */ 1145 if (ata_c->r_command == WDCC_IDENTIFY || 1146 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1147 idwordbuf = xfer->c_databuf; 1148 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1149 idwordbuf[i] = le16toh(idwordbuf[i]); 1150 } 1151 } 1152 1153 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1154 ata_c->flags |= AT_XFDONE; 1155 1156 siisata_cmd_done_end(chp, xfer); 1157 } 1158 1159 static void 1160 siisata_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1161 { 1162 struct ata_command *ata_c = &xfer->c_ata_c; 1163 1164 ata_c->flags |= AT_DONE; 1165 } 1166 1167 static const struct ata_xfer_ops siisata_bio_xfer_ops = { 1168 .c_start = siisata_bio_start, 1169 .c_intr = siisata_bio_complete, 1170 .c_poll = siisata_bio_poll, 1171 .c_abort = siisata_bio_abort, 1172 .c_kill_xfer = siisata_bio_kill_xfer, 1173 }; 1174 1175 int 1176 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1177 { 1178 struct ata_channel *chp = drvp->chnl_softc; 1179 struct ata_bio *ata_bio = &xfer->c_bio; 1180 1181 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1182 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1183 DEBUG_FUNCS); 1184 1185 if (xfer == NULL) 1186 return ATACMD_TRY_AGAIN; 1187 if (ata_bio->flags & ATA_POLL) 1188 xfer->c_flags |= C_POLL; 1189 xfer->c_drive = drvp->drive; 1190 xfer->c_databuf = ata_bio->databuf; 1191 xfer->c_bcount = ata_bio->bcount; 1192 xfer->ops = &siisata_bio_xfer_ops; 1193 ata_exec_xfer(chp, xfer); 1194 return (ata_bio->flags & ATA_ITSDONE) ? 1195 ATACMD_COMPLETE : ATACMD_QUEUED; 1196 } 1197 1198 int 1199 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1200 { 1201 struct siisata_channel *schp = (struct siisata_channel *)chp; 1202 struct siisata_prb *prb; 1203 struct ata_bio *ata_bio = &xfer->c_bio; 1204 1205 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1206 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1207 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1208 1209 ata_channel_lock_owned(chp); 1210 1211 prb = schp->sch_prb[xfer->c_slot]; 1212 memset(prb, 0, SIISATA_CMD_SIZE); 1213 1214 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1215 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1216 prb->prb_fis[rhd_c] |= xfer->c_drive; 1217 1218 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1219 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1220 ata_bio->error = ERR_DMA; 1221 ata_bio->r_error = 0; 1222 return ATASTART_ABORT; 1223 } 1224 1225 if (xfer->c_flags & C_POLL) { 1226 /* polled command, disable interrupts */ 1227 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1228 siisata_disable_port_interrupt(chp); 1229 } 1230 1231 siisata_activate_prb(schp, xfer->c_slot); 1232 1233 if ((ata_bio->flags & ATA_POLL) == 0) { 1234 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1235 ata_timeout, chp); 1236 return ATASTART_STARTED; 1237 } else 1238 return ATASTART_POLL; 1239 } 1240 1241 void 1242 siisata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1243 { 1244 struct siisata_channel *schp = (struct siisata_channel *)chp; 1245 1246 /* 1247 * polled command 1248 */ 1249 for (int i = 0; i < ATA_DELAY * 10; i++) { 1250 if (xfer->c_bio.flags & ATA_ITSDONE) 1251 break; 1252 siisata_intr_port(schp); 1253 DELAY(100); 1254 } 1255 1256 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1257 ata_timeout(xfer); 1258 } 1259 1260 siisata_enable_port_interrupt(chp); 1261 1262 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1263 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1264 DEBUG_FUNCS); 1265 } 1266 1267 void 1268 siisata_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1269 { 1270 siisata_cmd_complete(chp, xfer, 0); 1271 } 1272 1273 void 1274 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1275 int reason) 1276 { 1277 struct siisata_channel *schp = (struct siisata_channel *)chp; 1278 struct ata_bio *ata_bio = &xfer->c_bio; 1279 int drive = xfer->c_drive; 1280 bool deactivate = true; 1281 1282 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1283 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1284 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1285 1286 ata_bio->flags |= ATA_ITSDONE; 1287 switch (reason) { 1288 case KILL_GONE_INACTIVE: 1289 deactivate = false; 1290 /* FALLTHROUGH */ 1291 case KILL_GONE: 1292 ata_bio->error = ERR_NODEV; 1293 break; 1294 case KILL_RESET: 1295 ata_bio->error = ERR_RESET; 1296 break; 1297 case KILL_REQUEUE: 1298 ata_bio->error = REQUEUE; 1299 break; 1300 default: 1301 panic("%s: port %d: unknown reason %d", 1302 __func__, chp->ch_channel, reason); 1303 } 1304 ata_bio->r_error = WDCE_ABRT; 1305 1306 if (deactivate) { 1307 siisata_deactivate_prb(schp, xfer->c_slot); 1308 ata_deactivate_xfer(chp, xfer); 1309 } 1310 1311 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1312 } 1313 1314 int 1315 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1316 { 1317 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1318 struct siisata_channel *schp = (struct siisata_channel *)chp; 1319 struct ata_bio *ata_bio = &xfer->c_bio; 1320 int drive = xfer->c_drive; 1321 1322 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d tfd %x\n", 1323 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1324 chp->ch_channel, xfer->c_slot, xfer->c_drive, tfd), DEBUG_FUNCS); 1325 1326 if (ata_waitdrain_xfer_check(chp, xfer)) 1327 return 0; 1328 1329 if (xfer->c_flags & C_TIMEOU) { 1330 ata_bio->error = TIMEOUT; 1331 } 1332 1333 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1334 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1335 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1336 BUS_DMASYNC_POSTWRITE); 1337 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1338 1339 ata_bio->flags |= ATA_ITSDONE; 1340 if (ATACH_ST(tfd) & WDCS_DWF) { 1341 ata_bio->error = ERR_DF; 1342 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1343 ata_bio->error = ERROR; 1344 ata_bio->r_error = ATACH_ERR(tfd); 1345 } else if (ATACH_ST(tfd) & WDCS_CORR) 1346 ata_bio->flags |= ATA_CORR; 1347 1348 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1349 ata_bio->bcount), DEBUG_XFERS); 1350 if (ata_bio->error == NOERROR) { 1351 if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ) 1352 ata_bio->bcount -= 1353 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1354 else 1355 ata_bio->bcount = 0; 1356 } 1357 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1358 1359 siisata_deactivate_prb(schp, xfer->c_slot); 1360 ata_deactivate_xfer(chp, xfer); 1361 1362 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1363 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1364 atastart(chp); 1365 return 0; 1366 } 1367 1368 static int 1369 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1370 size_t count, int op) 1371 { 1372 1373 int error, seg; 1374 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1375 struct siisata_channel *schp = (struct siisata_channel *)chp; 1376 1377 struct siisata_prb *prbp; 1378 1379 prbp = schp->sch_prb[slot]; 1380 1381 if (data == NULL) { 1382 goto end; 1383 } 1384 1385 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1386 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1387 if (error) { 1388 aprint_error("%s port %d: " 1389 "failed to load xfer in slot %d: error %d\n", 1390 SIISATANAME(sc), chp->ch_channel, slot, error); 1391 return error; 1392 } 1393 1394 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1395 schp->sch_datad[slot]->dm_mapsize, 1396 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1397 1398 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1399 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1400 DEBUG_FUNCS | DEBUG_DEBUG); 1401 1402 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1403 prbp->prb_sge[seg].sge_da = 1404 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1405 prbp->prb_sge[seg].sge_dc = 1406 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1407 prbp->prb_sge[seg].sge_flags = htole32(0); 1408 } 1409 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1410 end: 1411 return 0; 1412 } 1413 1414 static void 1415 siisata_activate_prb(struct siisata_channel *schp, int slot) 1416 { 1417 struct siisata_softc *sc; 1418 bus_size_t offset; 1419 uint64_t pprb; 1420 1421 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1422 1423 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1424 1425 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1426 1427 pprb = schp->sch_bus_prb[slot]; 1428 1429 PRWRITE(sc, offset + 0, pprb >> 0); 1430 PRWRITE(sc, offset + 4, pprb >> 32); 1431 } 1432 1433 static void 1434 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1435 { 1436 struct siisata_softc *sc; 1437 1438 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1439 1440 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1441 } 1442 1443 static int 1444 siisata_reinit_port(struct ata_channel *chp, int drive) 1445 { 1446 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1447 int ps; 1448 int error = 0; 1449 1450 if (chp->ch_ndrives > 1) { 1451 /* 1452 * Proper recovery would SET this bit, which makes it 1453 * not possible to submit new commands and resume execution 1454 * on non-errored drives, then wait for those commands, 1455 * to finish, and only then clear the bit and reset the state. 1456 * For now this is okay, since we never queue commands for 1457 * more than one drive. 1458 * XXX FIS-based switching 1459 */ 1460 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_RESUME); 1461 1462 for (int i = 0; i < chp->ch_ndrives; i++) { 1463 if (drive >= 0 && i != drive) 1464 continue; 1465 1466 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPSTS(i)), 0); 1467 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPQACT(i)), 0); 1468 } 1469 } 1470 1471 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1472 for (int i = 0; i < ATA_DELAY * 100; i++) { 1473 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1474 if ((ps & PR_PS_PORT_READY) != 0) 1475 break; 1476 1477 DELAY(10); 1478 } 1479 if ((ps & PR_PS_PORT_READY) == 0) { 1480 printf("%s: timeout waiting for port to be ready\n", __func__); 1481 error = EBUSY; 1482 } 1483 1484 if (chp->ch_ndrives > 1) 1485 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1486 1487 return error; 1488 } 1489 1490 static void 1491 siisata_device_reset(struct ata_channel *chp) 1492 { 1493 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1494 int ps; 1495 1496 ata_channel_lock_owned(chp); 1497 1498 /* 1499 * This is always called after siisata_reinit_port(), so don't 1500 * need to deal with RESUME and clearing device error state. 1501 */ 1502 1503 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1504 1505 for (int i = 0; i < ATA_DELAY * 100; i++) { 1506 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1507 if ((ps & PR_PS_PORT_READY) != 0) 1508 break; 1509 1510 DELAY(10); 1511 } 1512 if ((ps & PR_PS_PORT_READY) == 0) { 1513 printf("%s: timeout waiting for port to be ready\n", __func__); 1514 siisata_reset_channel(chp, AT_POLL); 1515 } 1516 1517 ata_kill_active(chp, KILL_RESET, 0); 1518 } 1519 1520 1521 #if NATAPIBUS > 0 1522 void 1523 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1524 { 1525 struct ata_channel *chp = ata_sc->sc_chan; 1526 struct atac_softc *atac = chp->ch_atac; 1527 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1528 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1529 1530 /* 1531 * Fill in the scsipi_adapter. 1532 */ 1533 adapt->adapt_dev = atac->atac_dev; 1534 adapt->adapt_nchannels = atac->atac_nchannels; 1535 adapt->adapt_request = siisata_atapi_scsipi_request; 1536 adapt->adapt_minphys = siisata_atapi_minphys; 1537 atac->atac_atapi_adapter.atapi_probe_device = 1538 siisata_atapi_probe_device; 1539 1540 /* 1541 * Fill in the scsipi_channel. 1542 */ 1543 memset(chan, 0, sizeof(*chan)); 1544 chan->chan_adapter = adapt; 1545 chan->chan_bustype = &siisata_atapi_bustype; 1546 chan->chan_channel = chp->ch_channel; 1547 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1548 chan->chan_openings = 1; 1549 chan->chan_max_periph = 1; 1550 chan->chan_ntargets = 1; 1551 chan->chan_nluns = 1; 1552 1553 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1554 atapiprint); 1555 } 1556 1557 void 1558 siisata_atapi_minphys(struct buf *bp) 1559 { 1560 if (bp->b_bcount > MAXPHYS) 1561 bp->b_bcount = MAXPHYS; 1562 minphys(bp); 1563 } 1564 1565 /* 1566 * Kill off all pending xfers for a periph. 1567 * 1568 * Must be called at splbio(). 1569 */ 1570 void 1571 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1572 { 1573 struct atac_softc *atac = 1574 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1575 struct ata_channel *chp = 1576 atac->atac_channels[periph->periph_channel->chan_channel]; 1577 1578 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1579 } 1580 1581 void 1582 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1583 int reason) 1584 { 1585 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1586 struct siisata_channel *schp = (struct siisata_channel *)chp; 1587 bool deactivate = true; 1588 1589 /* remove this command from xfer queue */ 1590 switch (reason) { 1591 case KILL_GONE_INACTIVE: 1592 deactivate = false; 1593 /* FALLTHROUGH */ 1594 case KILL_GONE: 1595 sc_xfer->error = XS_DRIVER_STUFFUP; 1596 break; 1597 case KILL_RESET: 1598 sc_xfer->error = XS_RESET; 1599 break; 1600 case KILL_REQUEUE: 1601 sc_xfer->error = XS_REQUEUE; 1602 break; 1603 default: 1604 panic("%s: port %d: unknown reason %d", 1605 __func__, chp->ch_channel, reason); 1606 } 1607 1608 if (deactivate) { 1609 siisata_deactivate_prb(schp, xfer->c_slot); 1610 ata_deactivate_xfer(chp, xfer); 1611 } 1612 1613 ata_free_xfer(chp, xfer); 1614 scsipi_done(sc_xfer); 1615 } 1616 1617 void 1618 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1619 { 1620 struct scsipi_channel *chan = sc->sc_channel; 1621 struct scsipi_periph *periph; 1622 struct ataparams ids; 1623 struct ataparams *id = &ids; 1624 struct siisata_softc *siic = 1625 device_private(chan->chan_adapter->adapt_dev); 1626 struct atac_softc *atac = &siic->sc_atac; 1627 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1628 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1629 struct scsipibus_attach_args sa; 1630 char serial_number[21], model[41], firmware_revision[9]; 1631 int s; 1632 1633 /* skip if already attached */ 1634 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1635 return; 1636 1637 /* if no ATAPI device detected at attach time, skip */ 1638 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1639 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1640 target), DEBUG_PROBE); 1641 return; 1642 } 1643 1644 /* Some ATAPI devices need a bit more time after software reset. */ 1645 DELAY(5000); 1646 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1647 #ifdef ATAPI_DEBUG_PROBE 1648 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1649 device_xname(sc->sc_dev), target, 1650 id->atap_config & ATAPI_CFG_CMD_MASK, 1651 id->atap_config & ATAPI_CFG_DRQ_MASK); 1652 #endif 1653 periph = scsipi_alloc_periph(M_NOWAIT); 1654 if (periph == NULL) { 1655 aprint_error_dev(sc->sc_dev, 1656 "%s: unable to allocate periph for " 1657 "channel %d drive %d\n", __func__, 1658 chp->ch_channel, target); 1659 return; 1660 } 1661 periph->periph_dev = NULL; 1662 periph->periph_channel = chan; 1663 periph->periph_switch = &atapi_probe_periphsw; 1664 periph->periph_target = target; 1665 periph->periph_lun = 0; 1666 periph->periph_quirks = PQUIRK_ONLYBIG; 1667 1668 #ifdef SCSIPI_DEBUG 1669 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1670 SCSIPI_DEBUG_TARGET == target) 1671 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1672 #endif 1673 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1674 if (id->atap_config & ATAPI_CFG_REMOV) 1675 periph->periph_flags |= PERIPH_REMOVABLE; 1676 sa.sa_periph = periph; 1677 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1678 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1679 T_REMOV : T_FIXED; 1680 strnvisx(model, sizeof(model), id->atap_model, 40, 1681 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1682 strnvisx(serial_number, sizeof(serial_number), 1683 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1684 strnvisx(firmware_revision, sizeof(firmware_revision), 1685 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1686 sa.sa_inqbuf.vendor = model; 1687 sa.sa_inqbuf.product = serial_number; 1688 sa.sa_inqbuf.revision = firmware_revision; 1689 1690 /* 1691 * Determine the operating mode capabilities of the device. 1692 */ 1693 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1694 == ATAPI_CFG_CMD_16) { 1695 periph->periph_cap |= PERIPH_CAP_CMD16; 1696 1697 /* configure port for packet length */ 1698 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1699 PR_PC_PACKET_LENGTH); 1700 } else { 1701 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1702 PR_PC_PACKET_LENGTH); 1703 } 1704 1705 /* XXX This is gross. */ 1706 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1707 1708 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1709 1710 if (drvp->drv_softc) 1711 ata_probe_caps(drvp); 1712 else { 1713 s = splbio(); 1714 drvp->drive_type &= ATA_DRIVET_NONE; 1715 splx(s); 1716 } 1717 } else { 1718 s = splbio(); 1719 drvp->drive_type &= ATA_DRIVET_NONE; 1720 splx(s); 1721 } 1722 } 1723 1724 static const struct ata_xfer_ops siisata_atapi_xfer_ops = { 1725 .c_start = siisata_atapi_start, 1726 .c_intr = siisata_atapi_complete, 1727 .c_poll = siisata_atapi_poll, 1728 .c_abort = siisata_atapi_abort, 1729 .c_kill_xfer = siisata_atapi_kill_xfer, 1730 }; 1731 1732 void 1733 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1734 scsipi_adapter_req_t req, void *arg) 1735 { 1736 struct scsipi_adapter *adapt = chan->chan_adapter; 1737 struct scsipi_periph *periph; 1738 struct scsipi_xfer *sc_xfer; 1739 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1740 struct atac_softc *atac = &sc->sc_atac; 1741 struct ata_xfer *xfer; 1742 int channel = chan->chan_channel; 1743 int drive, s; 1744 1745 switch (req) { 1746 case ADAPTER_REQ_RUN_XFER: 1747 sc_xfer = arg; 1748 periph = sc_xfer->xs_periph; 1749 drive = periph->periph_target; 1750 1751 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1752 device_xname(atac->atac_dev), channel, drive), 1753 DEBUG_XFERS); 1754 1755 if (!device_is_active(atac->atac_dev)) { 1756 sc_xfer->error = XS_DRIVER_STUFFUP; 1757 scsipi_done(sc_xfer); 1758 return; 1759 } 1760 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1761 if (xfer == NULL) { 1762 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1763 scsipi_done(sc_xfer); 1764 return; 1765 } 1766 1767 if (sc_xfer->xs_control & XS_CTL_POLL) 1768 xfer->c_flags |= C_POLL; 1769 xfer->c_drive = drive; 1770 xfer->c_flags |= C_ATAPI; 1771 xfer->c_databuf = sc_xfer->data; 1772 xfer->c_bcount = sc_xfer->datalen; 1773 xfer->ops = &siisata_atapi_xfer_ops; 1774 xfer->c_scsipi = sc_xfer; 1775 xfer->c_atapi.c_dscpoll = 0; 1776 s = splbio(); 1777 ata_exec_xfer(atac->atac_channels[channel], xfer); 1778 #ifdef DIAGNOSTIC 1779 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1780 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1781 panic("%s: polled command not done", __func__); 1782 #endif 1783 splx(s); 1784 return; 1785 1786 default: 1787 /* Not supported, nothing to do. */ 1788 ; 1789 } 1790 } 1791 1792 int 1793 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1794 { 1795 struct siisata_channel *schp = (struct siisata_channel *)chp; 1796 struct siisata_prb *prbp; 1797 1798 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1799 1800 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1801 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1802 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1803 DEBUG_XFERS); 1804 1805 ata_channel_lock_owned(chp); 1806 1807 prbp = schp->sch_prb[xfer->c_slot]; 1808 memset(prbp, 0, SIISATA_CMD_SIZE); 1809 1810 /* fill in direction for ATAPI command */ 1811 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1812 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1813 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1814 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1815 1816 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1817 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1818 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1819 1820 /* copy over ATAPI command */ 1821 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1822 1823 if (siisata_dma_setup(chp, xfer->c_slot, 1824 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1825 xfer->c_databuf : NULL, 1826 xfer->c_bcount, 1827 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1828 BUS_DMA_READ : BUS_DMA_WRITE) 1829 ) { 1830 sc_xfer->error = XS_DRIVER_STUFFUP; 1831 return ATASTART_ABORT; 1832 } 1833 1834 if (xfer->c_flags & C_POLL) { 1835 /* polled command, disable interrupts */ 1836 prbp->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1837 siisata_disable_port_interrupt(chp); 1838 } 1839 1840 siisata_activate_prb(schp, xfer->c_slot); 1841 1842 if ((xfer->c_flags & C_POLL) == 0) { 1843 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1844 ata_timeout, chp); 1845 return ATASTART_STARTED; 1846 } else 1847 return ATASTART_POLL; 1848 } 1849 1850 void 1851 siisata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1852 { 1853 struct siisata_channel *schp = (struct siisata_channel *)chp; 1854 1855 /* 1856 * polled command 1857 */ 1858 for (int i = 0; i < ATA_DELAY * 10; i++) { 1859 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1860 break; 1861 siisata_intr_port(schp); 1862 DELAY(100); 1863 } 1864 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1865 ata_timeout(xfer); 1866 } 1867 /* reenable interrupts */ 1868 siisata_enable_port_interrupt(chp); 1869 1870 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1871 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1872 DEBUG_FUNCS); 1873 } 1874 1875 void 1876 siisata_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1877 { 1878 siisata_atapi_complete(chp, xfer, 0); 1879 } 1880 1881 int 1882 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1883 int tfd) 1884 { 1885 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1886 struct siisata_channel *schp = (struct siisata_channel *)chp; 1887 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1888 1889 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1890 DEBUG_INTR); 1891 1892 if (ata_waitdrain_xfer_check(chp, xfer)) 1893 return 0; 1894 1895 if (xfer->c_flags & C_TIMEOU) { 1896 sc_xfer->error = XS_TIMEOUT; 1897 } 1898 1899 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1900 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1901 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1902 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1903 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1904 1905 sc_xfer->resid = sc_xfer->datalen; 1906 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1907 PRSO_RTC)); 1908 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1909 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1910 if ((ATACH_ST(tfd) & WDCS_ERR) && 1911 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1912 sc_xfer->resid == sc_xfer->datalen)) { 1913 sc_xfer->error = XS_SHORTSENSE; 1914 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1915 if ((sc_xfer->xs_periph->periph_quirks & 1916 PQUIRK_NOSENSE) == 0) { 1917 /* request sense */ 1918 sc_xfer->error = XS_BUSY; 1919 sc_xfer->status = SCSI_CHECK; 1920 } 1921 } 1922 1923 siisata_deactivate_prb(schp, xfer->c_slot); 1924 ata_deactivate_xfer(chp, xfer); 1925 1926 ata_free_xfer(chp, xfer); 1927 scsipi_done(sc_xfer); 1928 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1929 atastart(chp); 1930 return 0; 1931 } 1932 1933 #endif /* NATAPIBUS */ 1934
Indexes created Tue Oct 21 12:09:54 GMT 2025