siisata.c revision 1.35.6.6
1 /* $NetBSD: siisata.c,v 1.35.6.6 2018/10/03 19:20:48 jdolecek Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.35.6.6 2018/10/03 19:20:48 jdolecek Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define WDC_RESET_WAIT 31000 /* 31s for drive reset */ 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #if _BYTE_ORDER == _LITTLE_ENDIAN 116 #define bus_space_read_stream_4 bus_space_read_4 117 #define bus_space_read_region_stream_4 bus_space_read_region_4 118 #else 119 static inline uint32_t 120 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 121 { 122 return htole32(bus_space_read_4(t, h, o)); 123 } 124 125 static inline void 126 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 127 bus_size_t o, uint32_t *p, bus_size_t c) 128 { 129 bus_space_read_region_4(t, h, o, p, c); 130 for (bus_size_t i = 0; i < c; i++) { 131 p[i] = htole32(p[i]); 132 } 133 } 134 #endif 135 #endif 136 137 static void siisata_attach_port(struct siisata_softc *, int); 138 static void siisata_intr_port(struct siisata_channel *); 139 140 void siisata_probe_drive(struct ata_channel *); 141 void siisata_setup_channel(struct ata_channel *); 142 143 int siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 144 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 145 void siisata_reset_channel(struct ata_channel *, int); 146 int siisata_ata_addref(struct ata_drive_datas *); 147 void siisata_ata_delref(struct ata_drive_datas *); 148 void siisata_killpending(struct ata_drive_datas *); 149 150 int siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 151 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_cmd_poll(struct ata_channel *, struct ata_xfer *); 153 void siisata_cmd_abort(struct ata_channel *, struct ata_xfer *); 154 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 155 static void siisata_cmd_done_end(struct ata_channel *, struct ata_xfer *); 156 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 158 int siisata_bio_start(struct ata_channel *, struct ata_xfer *); 159 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 160 void siisata_bio_poll(struct ata_channel *, struct ata_xfer *); 161 void siisata_bio_abort(struct ata_channel *, struct ata_xfer *); 162 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 163 int siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 164 165 static void siisata_reinit_port(struct ata_channel *, int); 166 static void siisata_device_reset(struct ata_channel *); 167 static void siisata_activate_prb(struct siisata_channel *, int); 168 static void siisata_deactivate_prb(struct siisata_channel *, int); 169 static int siisata_dma_setup(struct ata_channel *, int, void *, size_t, int); 170 void siisata_channel_recover(struct ata_channel *, uint32_t); 171 172 #if NATAPIBUS > 0 173 void siisata_atapibus_attach(struct atabus_softc *); 174 void siisata_atapi_probe_device(struct atapibus_softc *, int); 175 void siisata_atapi_minphys(struct buf *); 176 int siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 177 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 178 void siisata_atapi_poll(struct ata_channel *, struct ata_xfer *); 179 void siisata_atapi_abort(struct ata_channel *, struct ata_xfer *); 180 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 181 void siisata_atapi_scsipi_request(struct scsipi_channel *, 182 scsipi_adapter_req_t, void *); 183 void siisata_atapi_kill_pending(struct scsipi_periph *); 184 #endif /* NATAPIBUS */ 185 186 const struct ata_bustype siisata_ata_bustype = { 187 SCSIPI_BUSTYPE_ATA, 188 siisata_ata_bio, 189 siisata_reset_drive, 190 siisata_reset_channel, 191 siisata_exec_command, 192 ata_get_params, 193 siisata_ata_addref, 194 siisata_ata_delref, 195 siisata_killpending 196 }; 197 198 #if NATAPIBUS > 0 199 static const struct scsipi_bustype siisata_atapi_bustype = { 200 SCSIPI_BUSTYPE_ATAPI, 201 atapi_scsipi_cmd, 202 atapi_interpret_sense, 203 atapi_print_addr, 204 siisata_atapi_kill_pending, 205 NULL, 206 }; 207 #endif /* NATAPIBUS */ 208 209 210 void 211 siisata_attach(struct siisata_softc *sc) 212 { 213 int i; 214 215 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 216 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 217 218 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 219 sc->sc_atac.atac_pio_cap = 4; 220 sc->sc_atac.atac_dma_cap = 2; 221 sc->sc_atac.atac_udma_cap = 6; 222 sc->sc_atac.atac_channels = sc->sc_chanarray; 223 sc->sc_atac.atac_probe = siisata_probe_drive; 224 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 225 sc->sc_atac.atac_set_modes = siisata_setup_channel; 226 #if NATAPIBUS > 0 227 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 228 #endif 229 230 /* come out of reset state */ 231 GRWRITE(sc, GR_GC, 0); 232 233 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 234 siisata_attach_port(sc, i); 235 } 236 237 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 238 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 239 return; 240 } 241 242 static void 243 siisata_disable_port_interrupt(struct ata_channel *chp) 244 { 245 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 246 247 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 248 } 249 250 static void 251 siisata_enable_port_interrupt(struct ata_channel *chp) 252 { 253 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 254 255 /* clear any interrupts */ 256 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 257 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 258 /* and enable CmdErrr+CmdCmpl interrupting */ 259 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 260 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 261 } 262 263 static void 264 siisata_init_port(struct siisata_softc *sc, int port) 265 { 266 struct siisata_channel *schp; 267 struct ata_channel *chp; 268 269 schp = &sc->sc_channels[port]; 270 chp = (struct ata_channel *)schp; 271 272 /* 273 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 274 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 275 */ 276 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 277 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 278 /* initialize port */ 279 siisata_reinit_port(chp, -1); 280 /* enable CmdErrr+CmdCmpl interrupting */ 281 siisata_enable_port_interrupt(chp); 282 /* enable port interrupt */ 283 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 284 } 285 286 static void 287 siisata_attach_port(struct siisata_softc *sc, int port) 288 { 289 int j; 290 int dmasize; 291 int error; 292 void *prbp; 293 struct siisata_channel *schp; 294 struct ata_channel *chp; 295 296 schp = &sc->sc_channels[port]; 297 chp = (struct ata_channel *)schp; 298 sc->sc_chanarray[port] = chp; 299 chp->ch_channel = port; 300 chp->ch_atac = &sc->sc_atac; 301 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 302 if (chp->ch_queue == NULL) { 303 aprint_error_dev(sc->sc_atac.atac_dev, 304 "port %d: can't allocate memory " 305 "for command queue\n", chp->ch_channel); 306 return; 307 } 308 309 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 310 311 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 312 __func__, dmasize), DEBUG_FUNCS); 313 314 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 315 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 316 if (error) { 317 aprint_error_dev(sc->sc_atac.atac_dev, 318 "unable to allocate PRB table memory, " 319 "error=%d\n", error); 320 return; 321 } 322 323 error = bus_dmamem_map(sc->sc_dmat, 324 &schp->sch_prb_seg, schp->sch_prb_nseg, 325 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 326 if (error) { 327 aprint_error_dev(sc->sc_atac.atac_dev, 328 "unable to map PRB table memory, " 329 "error=%d\n", error); 330 bus_dmamem_free(sc->sc_dmat, 331 &schp->sch_prb_seg, schp->sch_prb_nseg); 332 return; 333 } 334 335 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 336 BUS_DMA_NOWAIT, &schp->sch_prbd); 337 if (error) { 338 aprint_error_dev(sc->sc_atac.atac_dev, 339 "unable to create PRB table map, " 340 "error=%d\n", error); 341 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 342 bus_dmamem_free(sc->sc_dmat, 343 &schp->sch_prb_seg, schp->sch_prb_nseg); 344 return; 345 } 346 347 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 348 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 349 if (error) { 350 aprint_error_dev(sc->sc_atac.atac_dev, 351 "unable to load PRB table map, " 352 "error=%d\n", error); 353 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 354 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 355 bus_dmamem_free(sc->sc_dmat, 356 &schp->sch_prb_seg, schp->sch_prb_nseg); 357 return; 358 } 359 360 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 361 schp->sch_prb[j] = (struct siisata_prb *) 362 ((char *)prbp + SIISATA_CMD_SIZE * j); 363 schp->sch_bus_prb[j] = 364 schp->sch_prbd->dm_segs[0].ds_addr + 365 SIISATA_CMD_SIZE * j; 366 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 367 SIISATA_NSGE, MAXPHYS, 0, 368 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 369 &schp->sch_datad[j]); 370 if (error) { 371 aprint_error_dev(sc->sc_atac.atac_dev, 372 "couldn't create xfer DMA map, error=%d\n", 373 error); 374 return; 375 } 376 } 377 378 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 379 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 380 aprint_error_dev(sc->sc_atac.atac_dev, 381 "couldn't map port %d SStatus regs\n", 382 chp->ch_channel); 383 return; 384 } 385 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 386 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 387 aprint_error_dev(sc->sc_atac.atac_dev, 388 "couldn't map port %d SControl regs\n", 389 chp->ch_channel); 390 return; 391 } 392 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 393 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 394 aprint_error_dev(sc->sc_atac.atac_dev, 395 "couldn't map port %d SError regs\n", 396 chp->ch_channel); 397 return; 398 } 399 400 siisata_init_port(sc, port); 401 402 ata_channel_attach(chp); 403 404 return; 405 } 406 407 int 408 siisata_detach(struct siisata_softc *sc, int flags) 409 { 410 struct atac_softc *atac = &sc->sc_atac; 411 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 412 struct siisata_channel *schp; 413 struct ata_channel *chp; 414 int i, j, error; 415 416 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 417 schp = &sc->sc_channels[i]; 418 chp = sc->sc_chanarray[i]; 419 420 if (chp->atabus == NULL) 421 continue; 422 if ((error = config_detach(chp->atabus, flags)) != 0) 423 return error; 424 425 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 426 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 427 428 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 429 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 430 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 431 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 432 bus_dmamem_free(sc->sc_dmat, 433 &schp->sch_prb_seg, schp->sch_prb_nseg); 434 435 chp->atabus = NULL; 436 437 ata_channel_detach(chp); 438 } 439 440 if (adapt->adapt_refcnt != 0) 441 return EBUSY; 442 443 /* leave the chip in reset */ 444 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 445 446 return 0; 447 } 448 449 void 450 siisata_resume(struct siisata_softc *sc) 451 { 452 int i; 453 454 /* come out of reset state */ 455 GRWRITE(sc, GR_GC, 0); 456 457 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 458 siisata_init_port(sc, i); 459 } 460 461 } 462 463 int 464 siisata_intr(void *v) 465 { 466 struct siisata_softc *sc = v; 467 uint32_t is; 468 int i, r = 0; 469 while ((is = GRREAD(sc, GR_GIS))) { 470 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 471 SIISATANAME(sc), __func__, is), DEBUG_INTR); 472 r = 1; 473 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 474 if (is & GR_GIS_PXIS(i)) 475 siisata_intr_port(&sc->sc_channels[i]); 476 } 477 return r; 478 } 479 480 static void 481 siisata_intr_port(struct siisata_channel *schp) 482 { 483 struct siisata_softc *sc = 484 (struct siisata_softc *)schp->ata_channel.ch_atac; 485 struct ata_channel *chp = &schp->ata_channel; 486 struct ata_xfer *xfer = NULL; 487 uint32_t pss, pis, tfd = 0; 488 bool recover = false; 489 490 /* get slot status, clearing completion interrupt */ 491 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 492 493 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x ", 494 SIISATANAME(sc), __func__, chp->ch_channel, pss), 495 DEBUG_INTR); 496 497 if (__predict_true((pss & PR_PSS_ATTENTION) == 0)) { 498 SIISATA_DEBUG_PRINT(("no attention"), DEBUG_INTR); 499 goto process; 500 } 501 502 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 503 504 SIISATA_DEBUG_PRINT(("pis 0x%x\n", pss), DEBUG_INTR); 505 506 if (pis & PR_PIS_CMDERRR) { 507 uint32_t ec; 508 509 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 510 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 511 512 /* emulate a CRC error by default */ 513 tfd = ATACH_ERR_ST(WDCE_CRC, WDCS_ERR); 514 515 if (ec <= PR_PCE_DATAFISERROR) { 516 if (ec == PR_PCE_DEVICEERROR 517 && (chp->ch_flags & ATACH_NCQ) == 0) { 518 xfer = ata_queue_get_active_xfer(chp); 519 520 /* read in specific information about error */ 521 uint32_t prbfis = bus_space_read_stream_4( 522 sc->sc_prt, sc->sc_prh, 523 PRSX(chp->ch_channel, xfer->c_slot, 524 PRSO_FIS)); 525 526 /* get status and error */ 527 int ntfd = satafis_rdh_parse(chp, 528 (uint8_t *)&prbfis); 529 530 if (ATACH_ST(ntfd) & WDCS_ERR) 531 tfd = ntfd; 532 } 533 534 /* 535 * We don't expect the recovery to trigger error, 536 * but handle this just in case. 537 */ 538 if (!schp->sch_recovering) 539 recover = true; 540 else { 541 aprint_error_dev(sc->sc_atac.atac_dev, 542 "error ec %x while recovering\n", ec); 543 544 /* Command will be marked as errored out */ 545 pss = 0; 546 } 547 } else { 548 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 549 " on channel %d (ctx 0x%x), resetting\n", 550 ec, chp->ch_channel, 551 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 552 553 /* okay, we have a "Fatal Error" */ 554 siisata_device_reset(chp); 555 } 556 } 557 558 /* clear some (ok, all) ints */ 559 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 560 561 if (__predict_false(recover)) 562 ata_channel_freeze(chp); 563 564 process: 565 if (xfer != NULL) { 566 xfer->ops->c_intr(chp, xfer, tfd); 567 } else { 568 /* 569 * For NCQ, HBA halts processing when error is notified, 570 * and any further D2H FISes are ignored until the error 571 * condition is cleared. Hence if a command is inactive, 572 * it means it actually already finished successfully. 573 * Note: active slots can change as c_intr() callback 574 * can activate another command(s), so must only process 575 * commands active before we start processing. 576 */ 577 uint32_t aslots = schp->sch_active_slots; 578 579 for (int slot=0; slot < SIISATA_MAX_SLOTS; slot++) { 580 if ((aslots & __BIT(slot)) != 0 && 581 (pss & PR_PXSS(slot)) == 0) { 582 xfer = ata_queue_hwslot_to_xfer(chp, slot); 583 xfer->ops->c_intr(chp, xfer, 0); 584 } 585 } 586 } 587 588 if (__predict_false(recover)) { 589 ata_channel_thaw(chp); 590 siisata_channel_recover(chp, tfd); 591 } 592 } 593 594 static void 595 siisata_hold(struct siisata_channel *schp) 596 { 597 schp->sch_hold_slots |= schp->sch_active_slots; 598 schp->sch_active_slots = 0; 599 } 600 601 static void 602 siisata_unhold(struct siisata_channel *schp) 603 { 604 schp->sch_active_slots = schp->sch_hold_slots; 605 schp->sch_hold_slots = 0; 606 } 607 608 /* Recover channel after transfer aborted */ 609 void 610 siisata_channel_recover(struct ata_channel *chp, uint32_t tfd) 611 { 612 struct siisata_channel *schp = (struct siisata_channel *)chp; 613 struct siisata_softc *sc = 614 (struct siisata_softc *)schp->ata_channel.ch_atac; 615 struct ata_drive_datas *drvp; 616 int drive, error; 617 uint8_t eslot, slot, st, err; 618 struct ata_xfer *xfer; 619 620 KASSERT(!schp->sch_recovering); 621 622 schp->sch_recovering = true; 623 624 if (chp->ch_ndrives > PMP_PORT_CTL) { 625 /* Get PM port number for the device in error */ 626 int pcr = PRREAD(sc, PRX(chp->ch_channel, PRO_PCR)); 627 drive = PRO_PCR_PMP(pcr); 628 } else 629 drive = 0; 630 631 drvp = &chp->ch_drive[drive]; 632 633 /* 634 * If BSY or DRQ bits are set, must execute COMRESET to return 635 * device to idle state. Otherwise, commands can be reissued 636 * after reinitalization of port. After that, need to execute 637 * READ LOG EXT for NCQ to unblock device processing if COMRESET 638 * was not done. 639 */ 640 if ((ATACH_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) 641 goto reset; 642 643 KASSERT(drive >= 0); 644 siisata_reinit_port(chp, drive); 645 646 siisata_hold(schp); 647 648 /* 649 * When running NCQ commands, READ LOG EXT is necessary to clear the 650 * error condition and unblock the device. 651 */ 652 error = ata_read_log_ext_ncq(drvp, AT_POLL, &eslot, &st, &err); 653 654 siisata_unhold(schp); 655 656 switch (error) { 657 case 0: 658 /* Error out the particular NCQ xfer, then requeue the others */ 659 if ((schp->sch_active_slots & (1 << eslot)) != 0) { 660 xfer = ata_queue_hwslot_to_xfer(chp, eslot); 661 xfer->c_flags |= C_RECOVERED; 662 xfer->ops->c_intr(chp, xfer, ATACH_ERR_ST(err, st)); 663 } 664 break; 665 666 case EOPNOTSUPP: 667 /* 668 * Non-NCQ command error, just find the slot and end it with 669 * the error. 670 */ 671 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 672 if ((schp->sch_active_slots & (1 << slot)) != 0) { 673 xfer = ata_queue_hwslot_to_xfer(chp, slot); 674 if (xfer->c_drive != drive) 675 continue; 676 677 xfer->ops->c_intr(chp, xfer, tfd); 678 } 679 } 680 break; 681 682 case EAGAIN: 683 /* 684 * Failed to get resources to run the recovery command, must 685 * reset the drive. This will also kill all still outstanding 686 * transfers. 687 */ 688 reset: 689 siisata_device_reset(chp); 690 goto out; 691 /* NOTREACHED */ 692 693 default: 694 /* 695 * The command to get the slot failed. Kill outstanding 696 * commands for the same drive only. No need to reset 697 * the drive, it's unblocked nevertheless. 698 */ 699 break; 700 } 701 702 /* Requeue the non-errorred commands */ 703 for (slot = 0; slot < SIISATA_MAX_SLOTS; slot++) { 704 if (((schp->sch_active_slots >> slot) & 1) == 0) 705 continue; 706 707 xfer = ata_queue_hwslot_to_xfer(chp, slot); 708 if (xfer->c_drive != drive) 709 continue; 710 711 xfer->ops->c_kill_xfer(chp, xfer, 712 (error == 0) ? KILL_REQUEUE : KILL_RESET); 713 } 714 715 out: 716 /* Drive unblocked, back to normal operation */ 717 schp->sch_recovering = false; 718 atastart(chp); 719 } 720 721 void 722 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 723 { 724 struct ata_channel *chp = drvp->chnl_softc; 725 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 726 struct siisata_channel *schp = (struct siisata_channel *)chp; 727 struct siisata_prb *prb; 728 uint8_t c_slot; 729 uint32_t pss, pis; 730 int i; 731 bool timed_out; 732 733 siisata_reinit_port(chp, drvp->drive); 734 735 ata_channel_lock_owned(chp); 736 737 /* get a slot for running the command on */ 738 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 739 panic("%s: %s: failed to get xfer for reset, port %d\n", 740 device_xname(sc->sc_atac.atac_dev), 741 __func__, chp->ch_channel); 742 /* NOTREACHED */ 743 } 744 745 prb = schp->sch_prb[c_slot]; 746 memset(prb, 0, SIISATA_CMD_SIZE); 747 prb->prb_control = 748 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 749 KASSERT(drvp->drive <= PMP_PORT_CTL); 750 prb->prb_fis[rhd_c] = drvp->drive; 751 752 siisata_disable_port_interrupt(chp); 753 754 siisata_activate_prb(schp, c_slot); 755 756 timed_out = true; 757 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 758 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 759 if ((pss & PR_PXSS(c_slot)) == 0) { 760 timed_out = false; 761 break; 762 } 763 if (pss & PR_PSS_ATTENTION) 764 break; 765 ata_delay(chp, 10, "siiprb", flags); 766 } 767 768 siisata_deactivate_prb(schp, c_slot); 769 770 if ((pss & PR_PSS_ATTENTION) != 0) { 771 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 772 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 773 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 774 775 if (slot != c_slot) 776 device_printf(sc->sc_atac.atac_dev, "%s port %d " 777 "drive %d slot %d c_slot %d", __func__, 778 chp->ch_channel, drvp->drive, slot, c_slot); 779 780 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 781 PR_PIS_CMDERRR); 782 } 783 784 siisata_enable_port_interrupt(chp); 785 786 if (timed_out) { 787 /* timeout */ 788 siisata_device_reset(chp); /* XXX is this right? */ 789 if (sigp) 790 *sigp = 0xffffffff; 791 } else { 792 /* read the signature out of the FIS */ 793 if (sigp) { 794 *sigp = 0; 795 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 796 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 797 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 798 PRSO_FIS+0xc)) & 0xff; 799 } 800 } 801 802 ata_queue_free_slot(chp, c_slot); 803 } 804 805 void 806 siisata_reset_channel(struct ata_channel *chp, int flags) 807 { 808 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 809 struct siisata_channel *schp = (struct siisata_channel *)chp; 810 811 SIISATA_DEBUG_PRINT(("%s: %s channel %d\n", SIISATANAME(sc), __func__, 812 chp->ch_channel), DEBUG_FUNCS); 813 814 ata_channel_lock_owned(chp); 815 816 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 817 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 818 aprint_error("%s port %d: reset failed\n", 819 SIISATANAME(sc), chp->ch_channel); 820 /* XXX and then ? */ 821 } 822 823 siisata_device_reset(chp); 824 825 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 826 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 827 828 return; 829 } 830 831 int 832 siisata_ata_addref(struct ata_drive_datas *drvp) 833 { 834 return 0; 835 } 836 837 void 838 siisata_ata_delref(struct ata_drive_datas *drvp) 839 { 840 return; 841 } 842 843 void 844 siisata_killpending(struct ata_drive_datas *drvp) 845 { 846 return; 847 } 848 849 void 850 siisata_probe_drive(struct ata_channel *chp) 851 { 852 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 853 struct siisata_channel *schp = (struct siisata_channel *)chp; 854 int i; 855 uint32_t sig; 856 struct siisata_prb *prb; 857 bool timed_out; 858 uint8_t c_slot; 859 860 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 861 __func__, chp->ch_channel), DEBUG_FUNCS); 862 863 ata_channel_lock(chp); 864 865 /* get a slot for running the command on */ 866 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 867 aprint_error_dev(sc->sc_atac.atac_dev, 868 "%s: failed to get xfer port %d\n", 869 __func__, chp->ch_channel); 870 ata_channel_unlock(chp); 871 return; 872 } 873 874 /* 875 * disable port interrupt as we're polling for PHY up and 876 * prb completion 877 */ 878 siisata_disable_port_interrupt(chp); 879 880 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 881 schp->sch_sstatus, AT_WAIT)) { 882 case SStatus_DET_DEV: 883 /* clear any interrupts */ 884 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 885 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 886 887 /* wait for ready */ 888 timed_out = 1; 889 for (i = 0; i < ATA_DELAY / 10; i++) { 890 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & 891 PR_PS_PORT_READY) { 892 timed_out = 0; 893 break; 894 } 895 896 ata_delay(chp, 10, "siiprbrd", AT_WAIT); 897 } 898 if (timed_out) { 899 aprint_error_dev(sc->sc_atac.atac_dev, 900 "timed out waiting for PORT_READY on port %d, " 901 "reinitializing\n", chp->ch_channel); 902 siisata_reinit_port(chp, -1); 903 } 904 905 prb = schp->sch_prb[c_slot]; 906 memset(prb, 0, SIISATA_CMD_SIZE); 907 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 908 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 909 910 siisata_activate_prb(schp, c_slot); 911 912 timed_out = 1; 913 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 914 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 915 PR_PXSS(c_slot)) == 0) { 916 /* prb completed */ 917 timed_out = 0; 918 break; 919 } 920 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 921 PR_PIS_CMDERRR) { 922 /* we got an error; handle as timeout */ 923 break; 924 } 925 926 ata_delay(chp, 10, "siiprb", AT_WAIT); 927 } 928 929 siisata_deactivate_prb(schp, c_slot); 930 931 if (timed_out) { 932 aprint_error_dev(sc->sc_atac.atac_dev, 933 "SOFT_RESET failed on port %d (error %d PSS 0x%x PIS 0x%x), " 934 "resetting\n", chp->ch_channel, 935 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 936 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)), 937 PRREAD(sc, PRX(chp->ch_channel, PRO_PIS))); 938 siisata_reinit_port(chp, -1); 939 break; 940 } 941 942 /* read the signature out of the FIS */ 943 sig = 0; 944 sig |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 945 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 946 sig |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 947 PRSO_FIS+0xc)) & 0xff; 948 949 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 950 __func__, sig), DEBUG_PROBE); 951 952 if (sig == 0x96690101) 953 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 954 PR_PC_PMP_ENABLE); 955 sata_interpret_sig(chp, 0, sig); 956 break; 957 default: 958 break; 959 } 960 961 siisata_enable_port_interrupt(chp); 962 963 ata_queue_free_slot(chp, c_slot); 964 965 ata_channel_unlock(chp); 966 967 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 968 __func__, chp->ch_channel), DEBUG_PROBE); 969 return; 970 } 971 972 void 973 siisata_setup_channel(struct ata_channel *chp) 974 { 975 return; 976 } 977 978 static const struct ata_xfer_ops siisata_cmd_xfer_ops = { 979 .c_start = siisata_cmd_start, 980 .c_intr = siisata_cmd_complete, 981 .c_poll = siisata_cmd_poll, 982 .c_abort = siisata_cmd_abort, 983 .c_kill_xfer = siisata_cmd_kill_xfer, 984 }; 985 986 int 987 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 988 { 989 struct ata_channel *chp = drvp->chnl_softc; 990 struct ata_command *ata_c = &xfer->c_ata_c; 991 int ret; 992 int s; 993 994 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 995 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 996 DEBUG_FUNCS); 997 998 if (ata_c->flags & AT_POLL) 999 xfer->c_flags |= C_POLL; 1000 if (ata_c->flags & AT_WAIT) 1001 xfer->c_flags |= C_WAIT; 1002 xfer->c_drive = drvp->drive; 1003 xfer->c_databuf = ata_c->data; 1004 xfer->c_bcount = ata_c->bcount; 1005 xfer->ops = &siisata_cmd_xfer_ops; 1006 s = splbio(); 1007 ata_exec_xfer(chp, xfer); 1008 #ifdef DIAGNOSTIC 1009 if ((ata_c->flags & AT_POLL) != 0 && 1010 (ata_c->flags & AT_DONE) == 0) 1011 panic("%s: polled command not done", __func__); 1012 #endif 1013 if (ata_c->flags & AT_DONE) { 1014 ret = ATACMD_COMPLETE; 1015 } else { 1016 if (ata_c->flags & AT_WAIT) { 1017 ata_wait_cmd(chp, xfer); 1018 ret = ATACMD_COMPLETE; 1019 } else { 1020 ret = ATACMD_QUEUED; 1021 } 1022 } 1023 splx(s); 1024 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 1025 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1026 DEBUG_FUNCS); 1027 return ret; 1028 } 1029 1030 int 1031 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 1032 { 1033 struct siisata_channel *schp = (struct siisata_channel *)chp; 1034 struct ata_command *ata_c = &xfer->c_ata_c; 1035 struct siisata_prb *prb; 1036 1037 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 1038 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1039 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 1040 DEBUG_FUNCS|DEBUG_XFERS); 1041 1042 ata_channel_lock_owned(chp); 1043 1044 prb = schp->sch_prb[xfer->c_slot]; 1045 memset(prb, 0, SIISATA_CMD_SIZE); 1046 1047 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 1048 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1049 prb->prb_fis[rhd_c] |= xfer->c_drive; 1050 1051 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 1052 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 1053 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 1054 } 1055 1056 if (siisata_dma_setup(chp, xfer->c_slot, 1057 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 1058 ata_c->bcount, 1059 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1060 ata_c->flags |= AT_DF; 1061 return ATASTART_ABORT; 1062 } 1063 1064 if (xfer->c_flags & C_POLL) { 1065 /* polled command, disable interrupts */ 1066 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1067 siisata_disable_port_interrupt(chp); 1068 } 1069 1070 /* go for it */ 1071 siisata_activate_prb(schp, xfer->c_slot); 1072 1073 if ((ata_c->flags & AT_POLL) == 0) { 1074 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1075 ata_timeout, chp); 1076 return ATASTART_STARTED; 1077 } else 1078 return ATASTART_POLL; 1079 } 1080 1081 void 1082 siisata_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1083 { 1084 struct siisata_channel *schp = (struct siisata_channel *)chp; 1085 1086 /* 1087 * polled command 1088 */ 1089 for (int i = 0; i < xfer->c_ata_c.timeout * 10; i++) { 1090 if (xfer->c_ata_c.flags & AT_DONE) 1091 break; 1092 siisata_intr_port(schp); 1093 DELAY(100); 1094 } 1095 1096 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1097 ata_timeout(xfer); 1098 } 1099 1100 /* reenable interrupts */ 1101 siisata_enable_port_interrupt(chp); 1102 1103 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1104 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1105 DEBUG_FUNCS); 1106 } 1107 1108 void 1109 siisata_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1110 { 1111 siisata_cmd_complete(chp, xfer, 0); 1112 } 1113 1114 void 1115 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1116 int reason) 1117 { 1118 struct ata_command *ata_c = &xfer->c_ata_c; 1119 struct siisata_channel *schp = (struct siisata_channel *)chp; 1120 bool deactivate = true; 1121 1122 switch (reason) { 1123 case KILL_GONE_INACTIVE: 1124 deactivate = false; 1125 /* FALLTHROUGH */ 1126 case KILL_GONE: 1127 ata_c->flags |= AT_GONE; 1128 break; 1129 case KILL_RESET: 1130 ata_c->flags |= AT_RESET; 1131 break; 1132 case KILL_REQUEUE: 1133 panic("%s: not supposed to be requeued\n", __func__); 1134 break; 1135 default: 1136 panic("%s: port %d: unknown reason %d", 1137 __func__, chp->ch_channel, reason); 1138 } 1139 1140 siisata_cmd_done_end(chp, xfer); 1141 1142 if (deactivate) { 1143 siisata_deactivate_prb(schp, xfer->c_slot); 1144 ata_deactivate_xfer(chp, xfer); 1145 } 1146 } 1147 1148 int 1149 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1150 { 1151 struct siisata_channel *schp = (struct siisata_channel *)chp; 1152 struct ata_command *ata_c = &xfer->c_ata_c; 1153 #ifdef SIISATA_DEBUG 1154 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1155 #endif 1156 1157 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1158 SIISATANAME(sc), __func__, 1159 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1160 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1161 DEBUG_FUNCS|DEBUG_XFERS); 1162 1163 if (ata_waitdrain_xfer_check(chp, xfer)) 1164 return 0; 1165 1166 if (xfer->c_flags & C_TIMEOU) 1167 ata_c->flags |= AT_TIMEOU; 1168 1169 if (ATACH_ST(tfd) & WDCS_BSY) { 1170 ata_c->flags |= AT_TIMEOU; 1171 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1172 ata_c->r_error = ATACH_ERR(tfd); 1173 ata_c->flags |= AT_ERROR; 1174 } 1175 1176 siisata_cmd_done(chp, xfer, tfd); 1177 1178 siisata_deactivate_prb(schp, xfer->c_slot); 1179 ata_deactivate_xfer(chp, xfer); 1180 1181 return 0; 1182 } 1183 1184 void 1185 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1186 { 1187 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1188 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1189 struct siisata_channel *schp = (struct siisata_channel *)chp; 1190 struct ata_command *ata_c = &xfer->c_ata_c; 1191 uint16_t *idwordbuf; 1192 int i; 1193 1194 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1195 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1196 1197 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1198 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1199 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1200 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1201 BUS_DMASYNC_POSTWRITE); 1202 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1203 } 1204 1205 if (ata_c->flags & AT_READREG) { 1206 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1207 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1208 fis, __arraycount(fis)); 1209 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1210 } 1211 1212 /* correct the endianess of IDENTIFY data */ 1213 if (ata_c->r_command == WDCC_IDENTIFY || 1214 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1215 idwordbuf = xfer->c_databuf; 1216 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1217 idwordbuf[i] = le16toh(idwordbuf[i]); 1218 } 1219 } 1220 1221 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1222 ata_c->flags |= AT_XFDONE; 1223 1224 siisata_cmd_done_end(chp, xfer); 1225 } 1226 1227 static void 1228 siisata_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1229 { 1230 struct ata_command *ata_c = &xfer->c_ata_c; 1231 1232 ata_c->flags |= AT_DONE; 1233 } 1234 1235 static const struct ata_xfer_ops siisata_bio_xfer_ops = { 1236 .c_start = siisata_bio_start, 1237 .c_intr = siisata_bio_complete, 1238 .c_poll = siisata_bio_poll, 1239 .c_abort = siisata_bio_abort, 1240 .c_kill_xfer = siisata_bio_kill_xfer, 1241 }; 1242 1243 int 1244 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1245 { 1246 struct ata_channel *chp = drvp->chnl_softc; 1247 struct ata_bio *ata_bio = &xfer->c_bio; 1248 1249 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1250 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1251 DEBUG_FUNCS); 1252 1253 if (xfer == NULL) 1254 return ATACMD_TRY_AGAIN; 1255 if (ata_bio->flags & ATA_POLL) 1256 xfer->c_flags |= C_POLL; 1257 xfer->c_drive = drvp->drive; 1258 xfer->c_databuf = ata_bio->databuf; 1259 xfer->c_bcount = ata_bio->bcount; 1260 xfer->ops = &siisata_bio_xfer_ops; 1261 ata_exec_xfer(chp, xfer); 1262 return (ata_bio->flags & ATA_ITSDONE) ? 1263 ATACMD_COMPLETE : ATACMD_QUEUED; 1264 } 1265 1266 int 1267 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1268 { 1269 struct siisata_channel *schp = (struct siisata_channel *)chp; 1270 struct siisata_prb *prb; 1271 struct ata_bio *ata_bio = &xfer->c_bio; 1272 1273 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1274 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1275 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1276 1277 ata_channel_lock_owned(chp); 1278 1279 prb = schp->sch_prb[xfer->c_slot]; 1280 memset(prb, 0, SIISATA_CMD_SIZE); 1281 1282 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1283 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1284 prb->prb_fis[rhd_c] |= xfer->c_drive; 1285 1286 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1287 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1288 ata_bio->error = ERR_DMA; 1289 ata_bio->r_error = 0; 1290 return ATASTART_ABORT; 1291 } 1292 1293 if (xfer->c_flags & C_POLL) { 1294 /* polled command, disable interrupts */ 1295 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1296 siisata_disable_port_interrupt(chp); 1297 } 1298 1299 siisata_activate_prb(schp, xfer->c_slot); 1300 1301 if ((ata_bio->flags & ATA_POLL) == 0) { 1302 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1303 ata_timeout, chp); 1304 return ATASTART_STARTED; 1305 } else 1306 return ATASTART_POLL; 1307 } 1308 1309 void 1310 siisata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1311 { 1312 struct siisata_channel *schp = (struct siisata_channel *)chp; 1313 1314 /* 1315 * polled command 1316 */ 1317 for (int i = 0; i < ATA_DELAY * 10; i++) { 1318 if (xfer->c_bio.flags & ATA_ITSDONE) 1319 break; 1320 siisata_intr_port(schp); 1321 DELAY(100); 1322 } 1323 1324 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1325 ata_timeout(xfer); 1326 } 1327 1328 siisata_enable_port_interrupt(chp); 1329 1330 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1331 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1332 DEBUG_FUNCS); 1333 } 1334 1335 void 1336 siisata_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1337 { 1338 siisata_cmd_complete(chp, xfer, 0); 1339 } 1340 1341 void 1342 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1343 int reason) 1344 { 1345 struct siisata_channel *schp = (struct siisata_channel *)chp; 1346 struct ata_bio *ata_bio = &xfer->c_bio; 1347 int drive = xfer->c_drive; 1348 bool deactivate = true; 1349 1350 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1351 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1352 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1353 1354 ata_bio->flags |= ATA_ITSDONE; 1355 switch (reason) { 1356 case KILL_GONE_INACTIVE: 1357 deactivate = false; 1358 /* FALLTHROUGH */ 1359 case KILL_GONE: 1360 ata_bio->error = ERR_NODEV; 1361 break; 1362 case KILL_RESET: 1363 ata_bio->error = ERR_RESET; 1364 break; 1365 case KILL_REQUEUE: 1366 ata_bio->error = REQUEUE; 1367 break; 1368 default: 1369 panic("%s: port %d: unknown reason %d", 1370 __func__, chp->ch_channel, reason); 1371 } 1372 ata_bio->r_error = WDCE_ABRT; 1373 1374 if (deactivate) { 1375 siisata_deactivate_prb(schp, xfer->c_slot); 1376 ata_deactivate_xfer(chp, xfer); 1377 } 1378 1379 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1380 } 1381 1382 int 1383 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1384 { 1385 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1386 struct siisata_channel *schp = (struct siisata_channel *)chp; 1387 struct ata_bio *ata_bio = &xfer->c_bio; 1388 int drive = xfer->c_drive; 1389 1390 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d tfd %x\n", 1391 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1392 chp->ch_channel, xfer->c_slot, xfer->c_drive, tfd), DEBUG_FUNCS); 1393 1394 if (ata_waitdrain_xfer_check(chp, xfer)) 1395 return 0; 1396 1397 if (xfer->c_flags & C_TIMEOU) { 1398 ata_bio->error = TIMEOUT; 1399 } 1400 1401 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1402 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1403 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1404 BUS_DMASYNC_POSTWRITE); 1405 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1406 1407 ata_bio->flags |= ATA_ITSDONE; 1408 if (ATACH_ST(tfd) & WDCS_DWF) { 1409 ata_bio->error = ERR_DF; 1410 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1411 ata_bio->error = ERROR; 1412 ata_bio->r_error = ATACH_ERR(tfd); 1413 } else if (ATACH_ST(tfd) & WDCS_CORR) 1414 ata_bio->flags |= ATA_CORR; 1415 1416 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1417 ata_bio->bcount), DEBUG_XFERS); 1418 if (ata_bio->error == NOERROR) { 1419 if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ) 1420 ata_bio->bcount -= 1421 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1422 else 1423 ata_bio->bcount = 0; 1424 } 1425 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1426 1427 siisata_deactivate_prb(schp, xfer->c_slot); 1428 ata_deactivate_xfer(chp, xfer); 1429 1430 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1431 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1432 atastart(chp); 1433 return 0; 1434 } 1435 1436 static int 1437 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1438 size_t count, int op) 1439 { 1440 1441 int error, seg; 1442 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1443 struct siisata_channel *schp = (struct siisata_channel *)chp; 1444 1445 struct siisata_prb *prbp; 1446 1447 prbp = schp->sch_prb[slot]; 1448 1449 if (data == NULL) { 1450 goto end; 1451 } 1452 1453 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1454 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1455 if (error) { 1456 aprint_error("%s port %d: " 1457 "failed to load xfer in slot %d: error %d\n", 1458 SIISATANAME(sc), chp->ch_channel, slot, error); 1459 return error; 1460 } 1461 1462 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1463 schp->sch_datad[slot]->dm_mapsize, 1464 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1465 1466 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1467 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1468 DEBUG_FUNCS | DEBUG_DEBUG); 1469 1470 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1471 prbp->prb_sge[seg].sge_da = 1472 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1473 prbp->prb_sge[seg].sge_dc = 1474 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1475 prbp->prb_sge[seg].sge_flags = htole32(0); 1476 } 1477 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1478 end: 1479 return 0; 1480 } 1481 1482 static void 1483 siisata_activate_prb(struct siisata_channel *schp, int slot) 1484 { 1485 struct siisata_softc *sc; 1486 bus_size_t offset; 1487 uint64_t pprb; 1488 1489 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1490 1491 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) == 0, 1492 "%s: trying to activate active slot %d", SIISATANAME(sc), slot); 1493 1494 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1495 /* keep track of what's going on */ 1496 schp->sch_active_slots |= __BIT(slot); 1497 1498 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1499 1500 pprb = schp->sch_bus_prb[slot]; 1501 1502 PRWRITE(sc, offset + 0, pprb >> 0); 1503 PRWRITE(sc, offset + 4, pprb >> 32); 1504 } 1505 1506 static void 1507 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1508 { 1509 struct siisata_softc *sc; 1510 1511 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1512 1513 KASSERTMSG((schp->sch_active_slots & __BIT(slot)) != 0, 1514 "%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1515 slot); 1516 1517 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1518 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1519 } 1520 1521 static void 1522 siisata_reinit_port(struct ata_channel *chp, int drive) 1523 { 1524 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1525 int ps; 1526 1527 1528 if (chp->ch_ndrives > 1) { 1529 /* 1530 * Proper recovery would SET this bit, which makes it 1531 * not possible to submit new commands and resume execution 1532 * on non-errored drives, then wait for those commands, 1533 * to finish, and only then clear the bit and reset the state. 1534 * For now this is okay, since we never queue commands for 1535 * more than one drive. 1536 * XXX FIS-based switching 1537 */ 1538 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_RESUME); 1539 1540 for (int i = 0; i < chp->ch_ndrives; i++) { 1541 if (drive >= 0 && i != drive) 1542 continue; 1543 1544 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPSTS(i)), 0); 1545 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPQACT(i)), 0); 1546 } 1547 } 1548 1549 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1550 for (int i = 0; i < ATA_DELAY * 100; i++) { 1551 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1552 if ((ps & PR_PS_PORT_READY) != 0) 1553 break; 1554 1555 DELAY(10); 1556 } 1557 if ((ps & PR_PS_PORT_READY) == 0) { 1558 printf("%s: timeout waiting for port to be ready\n", __func__); 1559 siisata_reset_channel(chp, AT_POLL); 1560 } 1561 1562 if (chp->ch_ndrives > 1) 1563 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1564 } 1565 1566 static void 1567 siisata_device_reset(struct ata_channel *chp) 1568 { 1569 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1570 int ps; 1571 1572 ata_channel_lock_owned(chp); 1573 1574 /* 1575 * This is always called after siisata_reinit_port(), so don't 1576 * need to deal with RESUME and clearing device error state. 1577 */ 1578 1579 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1580 1581 for (int i = 0; i < ATA_DELAY * 100; i++) { 1582 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1583 if ((ps & PR_PS_PORT_READY) != 0) 1584 break; 1585 1586 DELAY(10); 1587 } 1588 if ((ps & PR_PS_PORT_READY) == 0) { 1589 printf("%s: timeout waiting for port to be ready\n", __func__); 1590 siisata_reset_channel(chp, AT_POLL); 1591 } 1592 1593 ata_kill_active(chp, KILL_RESET, 0); 1594 } 1595 1596 1597 #if NATAPIBUS > 0 1598 void 1599 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1600 { 1601 struct ata_channel *chp = ata_sc->sc_chan; 1602 struct atac_softc *atac = chp->ch_atac; 1603 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1604 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1605 1606 /* 1607 * Fill in the scsipi_adapter. 1608 */ 1609 adapt->adapt_dev = atac->atac_dev; 1610 adapt->adapt_nchannels = atac->atac_nchannels; 1611 adapt->adapt_request = siisata_atapi_scsipi_request; 1612 adapt->adapt_minphys = siisata_atapi_minphys; 1613 atac->atac_atapi_adapter.atapi_probe_device = 1614 siisata_atapi_probe_device; 1615 1616 /* 1617 * Fill in the scsipi_channel. 1618 */ 1619 memset(chan, 0, sizeof(*chan)); 1620 chan->chan_adapter = adapt; 1621 chan->chan_bustype = &siisata_atapi_bustype; 1622 chan->chan_channel = chp->ch_channel; 1623 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1624 chan->chan_openings = 1; 1625 chan->chan_max_periph = 1; 1626 chan->chan_ntargets = 1; 1627 chan->chan_nluns = 1; 1628 1629 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1630 atapiprint); 1631 } 1632 1633 void 1634 siisata_atapi_minphys(struct buf *bp) 1635 { 1636 if (bp->b_bcount > MAXPHYS) 1637 bp->b_bcount = MAXPHYS; 1638 minphys(bp); 1639 } 1640 1641 /* 1642 * Kill off all pending xfers for a periph. 1643 * 1644 * Must be called at splbio(). 1645 */ 1646 void 1647 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1648 { 1649 struct atac_softc *atac = 1650 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1651 struct ata_channel *chp = 1652 atac->atac_channels[periph->periph_channel->chan_channel]; 1653 1654 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1655 } 1656 1657 void 1658 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1659 int reason) 1660 { 1661 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1662 struct siisata_channel *schp = (struct siisata_channel *)chp; 1663 bool deactivate = true; 1664 1665 /* remove this command from xfer queue */ 1666 switch (reason) { 1667 case KILL_GONE_INACTIVE: 1668 deactivate = false; 1669 /* FALLTHROUGH */ 1670 case KILL_GONE: 1671 sc_xfer->error = XS_DRIVER_STUFFUP; 1672 break; 1673 case KILL_RESET: 1674 sc_xfer->error = XS_RESET; 1675 break; 1676 case KILL_REQUEUE: 1677 sc_xfer->error = XS_REQUEUE; 1678 break; 1679 default: 1680 panic("%s: port %d: unknown reason %d", 1681 __func__, chp->ch_channel, reason); 1682 } 1683 1684 if (deactivate) { 1685 siisata_deactivate_prb(schp, xfer->c_slot); 1686 ata_deactivate_xfer(chp, xfer); 1687 } 1688 1689 ata_free_xfer(chp, xfer); 1690 scsipi_done(sc_xfer); 1691 } 1692 1693 void 1694 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1695 { 1696 struct scsipi_channel *chan = sc->sc_channel; 1697 struct scsipi_periph *periph; 1698 struct ataparams ids; 1699 struct ataparams *id = &ids; 1700 struct siisata_softc *siic = 1701 device_private(chan->chan_adapter->adapt_dev); 1702 struct atac_softc *atac = &siic->sc_atac; 1703 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1704 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1705 struct scsipibus_attach_args sa; 1706 char serial_number[21], model[41], firmware_revision[9]; 1707 int s; 1708 1709 /* skip if already attached */ 1710 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1711 return; 1712 1713 /* if no ATAPI device detected at attach time, skip */ 1714 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1715 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1716 target), DEBUG_PROBE); 1717 return; 1718 } 1719 1720 /* Some ATAPI devices need a bit more time after software reset. */ 1721 DELAY(5000); 1722 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1723 #ifdef ATAPI_DEBUG_PROBE 1724 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1725 device_xname(sc->sc_dev), target, 1726 id->atap_config & ATAPI_CFG_CMD_MASK, 1727 id->atap_config & ATAPI_CFG_DRQ_MASK); 1728 #endif 1729 periph = scsipi_alloc_periph(M_NOWAIT); 1730 if (periph == NULL) { 1731 aprint_error_dev(sc->sc_dev, 1732 "%s: unable to allocate periph for " 1733 "channel %d drive %d\n", __func__, 1734 chp->ch_channel, target); 1735 return; 1736 } 1737 periph->periph_dev = NULL; 1738 periph->periph_channel = chan; 1739 periph->periph_switch = &atapi_probe_periphsw; 1740 periph->periph_target = target; 1741 periph->periph_lun = 0; 1742 periph->periph_quirks = PQUIRK_ONLYBIG; 1743 1744 #ifdef SCSIPI_DEBUG 1745 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1746 SCSIPI_DEBUG_TARGET == target) 1747 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1748 #endif 1749 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1750 if (id->atap_config & ATAPI_CFG_REMOV) 1751 periph->periph_flags |= PERIPH_REMOVABLE; 1752 sa.sa_periph = periph; 1753 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1754 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1755 T_REMOV : T_FIXED; 1756 strnvisx(model, sizeof(model), id->atap_model, 40, 1757 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1758 strnvisx(serial_number, sizeof(serial_number), 1759 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1760 strnvisx(firmware_revision, sizeof(firmware_revision), 1761 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1762 sa.sa_inqbuf.vendor = model; 1763 sa.sa_inqbuf.product = serial_number; 1764 sa.sa_inqbuf.revision = firmware_revision; 1765 1766 /* 1767 * Determine the operating mode capabilities of the device. 1768 */ 1769 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1770 == ATAPI_CFG_CMD_16) { 1771 periph->periph_cap |= PERIPH_CAP_CMD16; 1772 1773 /* configure port for packet length */ 1774 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1775 PR_PC_PACKET_LENGTH); 1776 } else { 1777 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1778 PR_PC_PACKET_LENGTH); 1779 } 1780 1781 /* XXX This is gross. */ 1782 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1783 1784 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1785 1786 if (drvp->drv_softc) 1787 ata_probe_caps(drvp); 1788 else { 1789 s = splbio(); 1790 drvp->drive_type &= ATA_DRIVET_NONE; 1791 splx(s); 1792 } 1793 } else { 1794 s = splbio(); 1795 drvp->drive_type &= ATA_DRIVET_NONE; 1796 splx(s); 1797 } 1798 } 1799 1800 static const struct ata_xfer_ops siisata_atapi_xfer_ops = { 1801 .c_start = siisata_atapi_start, 1802 .c_intr = siisata_atapi_complete, 1803 .c_poll = siisata_atapi_poll, 1804 .c_abort = siisata_atapi_abort, 1805 .c_kill_xfer = siisata_atapi_kill_xfer, 1806 }; 1807 1808 void 1809 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1810 scsipi_adapter_req_t req, void *arg) 1811 { 1812 struct scsipi_adapter *adapt = chan->chan_adapter; 1813 struct scsipi_periph *periph; 1814 struct scsipi_xfer *sc_xfer; 1815 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1816 struct atac_softc *atac = &sc->sc_atac; 1817 struct ata_xfer *xfer; 1818 int channel = chan->chan_channel; 1819 int drive, s; 1820 1821 switch (req) { 1822 case ADAPTER_REQ_RUN_XFER: 1823 sc_xfer = arg; 1824 periph = sc_xfer->xs_periph; 1825 drive = periph->periph_target; 1826 1827 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1828 device_xname(atac->atac_dev), channel, drive), 1829 DEBUG_XFERS); 1830 1831 if (!device_is_active(atac->atac_dev)) { 1832 sc_xfer->error = XS_DRIVER_STUFFUP; 1833 scsipi_done(sc_xfer); 1834 return; 1835 } 1836 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1837 if (xfer == NULL) { 1838 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1839 scsipi_done(sc_xfer); 1840 return; 1841 } 1842 1843 if (sc_xfer->xs_control & XS_CTL_POLL) 1844 xfer->c_flags |= C_POLL; 1845 xfer->c_drive = drive; 1846 xfer->c_flags |= C_ATAPI; 1847 xfer->c_databuf = sc_xfer->data; 1848 xfer->c_bcount = sc_xfer->datalen; 1849 xfer->ops = &siisata_atapi_xfer_ops; 1850 xfer->c_scsipi = sc_xfer; 1851 xfer->c_atapi.c_dscpoll = 0; 1852 s = splbio(); 1853 ata_exec_xfer(atac->atac_channels[channel], xfer); 1854 #ifdef DIAGNOSTIC 1855 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1856 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1857 panic("%s: polled command not done", __func__); 1858 #endif 1859 splx(s); 1860 return; 1861 1862 default: 1863 /* Not supported, nothing to do. */ 1864 ; 1865 } 1866 } 1867 1868 int 1869 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1870 { 1871 struct siisata_channel *schp = (struct siisata_channel *)chp; 1872 struct siisata_prb *prbp; 1873 1874 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1875 1876 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1877 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1878 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1879 DEBUG_XFERS); 1880 1881 ata_channel_lock_owned(chp); 1882 1883 prbp = schp->sch_prb[xfer->c_slot]; 1884 memset(prbp, 0, SIISATA_CMD_SIZE); 1885 1886 /* fill in direction for ATAPI command */ 1887 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1888 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1889 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1890 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1891 1892 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1893 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1894 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1895 1896 /* copy over ATAPI command */ 1897 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1898 1899 if (siisata_dma_setup(chp, xfer->c_slot, 1900 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1901 xfer->c_databuf : NULL, 1902 xfer->c_bcount, 1903 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1904 BUS_DMA_READ : BUS_DMA_WRITE) 1905 ) { 1906 sc_xfer->error = XS_DRIVER_STUFFUP; 1907 return ATASTART_ABORT; 1908 } 1909 1910 if (xfer->c_flags & C_POLL) { 1911 /* polled command, disable interrupts */ 1912 prbp->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1913 siisata_disable_port_interrupt(chp); 1914 } 1915 1916 siisata_activate_prb(schp, xfer->c_slot); 1917 1918 if ((xfer->c_flags & C_POLL) == 0) { 1919 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1920 ata_timeout, chp); 1921 return ATASTART_STARTED; 1922 } else 1923 return ATASTART_POLL; 1924 } 1925 1926 void 1927 siisata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1928 { 1929 struct siisata_channel *schp = (struct siisata_channel *)chp; 1930 1931 /* 1932 * polled command 1933 */ 1934 for (int i = 0; i < ATA_DELAY * 10; i++) { 1935 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1936 break; 1937 siisata_intr_port(schp); 1938 DELAY(100); 1939 } 1940 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1941 ata_timeout(xfer); 1942 } 1943 /* reenable interrupts */ 1944 siisata_enable_port_interrupt(chp); 1945 1946 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1947 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1948 DEBUG_FUNCS); 1949 } 1950 1951 void 1952 siisata_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1953 { 1954 siisata_atapi_complete(chp, xfer, 0); 1955 } 1956 1957 int 1958 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1959 int tfd) 1960 { 1961 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1962 struct siisata_channel *schp = (struct siisata_channel *)chp; 1963 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1964 1965 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1966 DEBUG_INTR); 1967 1968 if (ata_waitdrain_xfer_check(chp, xfer)) 1969 return 0; 1970 1971 if (xfer->c_flags & C_TIMEOU) { 1972 sc_xfer->error = XS_TIMEOUT; 1973 } 1974 1975 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1976 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1977 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1978 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1979 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1980 1981 sc_xfer->resid = sc_xfer->datalen; 1982 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1983 PRSO_RTC)); 1984 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1985 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1986 if ((ATACH_ST(tfd) & WDCS_ERR) && 1987 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1988 sc_xfer->resid == sc_xfer->datalen)) { 1989 sc_xfer->error = XS_SHORTSENSE; 1990 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1991 if ((sc_xfer->xs_periph->periph_quirks & 1992 PQUIRK_NOSENSE) == 0) { 1993 /* request sense */ 1994 sc_xfer->error = XS_BUSY; 1995 sc_xfer->status = SCSI_CHECK; 1996 } 1997 } 1998 1999 siisata_deactivate_prb(schp, xfer->c_slot); 2000 ata_deactivate_xfer(chp, xfer); 2001 2002 ata_free_xfer(chp, xfer); 2003 scsipi_done(sc_xfer); 2004 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 2005 atastart(chp); 2006 return 0; 2007 } 2008 2009 #endif /* NATAPIBUS */ 2010
Indexes created Mon Oct 27 08:10:08 GMT 2025