siisata.c revision 1.41.4.1
1 /* $NetBSD: siisata.c,v 1.41.4.1 2020/04/20 11:29:03 bouyer Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.41.4.1 2020/04/20 11:29:03 bouyer Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define WDC_RESET_WAIT 31000 /* 31s for drive reset */ 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #if _BYTE_ORDER == _LITTLE_ENDIAN 116 #define bus_space_read_stream_4 bus_space_read_4 117 #define bus_space_read_region_stream_4 bus_space_read_region_4 118 #else 119 static inline uint32_t 120 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 121 { 122 return htole32(bus_space_read_4(t, h, o)); 123 } 124 125 static inline void 126 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 127 bus_size_t o, uint32_t *p, bus_size_t c) 128 { 129 bus_space_read_region_4(t, h, o, p, c); 130 for (bus_size_t i = 0; i < c; i++) { 131 p[i] = htole32(p[i]); 132 } 133 } 134 #endif 135 #endif 136 137 static void siisata_attach_port(struct siisata_softc *, int); 138 static void siisata_intr_port(struct siisata_channel *); 139 140 void siisata_probe_drive(struct ata_channel *); 141 void siisata_setup_channel(struct ata_channel *); 142 143 void siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 144 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 145 void siisata_reset_channel(struct ata_channel *, int); 146 int siisata_ata_addref(struct ata_drive_datas *); 147 void siisata_ata_delref(struct ata_drive_datas *); 148 void siisata_killpending(struct ata_drive_datas *); 149 150 int siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 151 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_cmd_poll(struct ata_channel *, struct ata_xfer *); 153 void siisata_cmd_abort(struct ata_channel *, struct ata_xfer *); 154 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 155 static void siisata_cmd_done_end(struct ata_channel *, struct ata_xfer *); 156 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 158 int siisata_bio_start(struct ata_channel *, struct ata_xfer *); 159 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 160 void siisata_bio_poll(struct ata_channel *, struct ata_xfer *); 161 void siisata_bio_abort(struct ata_channel *, struct ata_xfer *); 162 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 163 void siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 164 165 static int siisata_reinit_port(struct ata_channel *, int); 166 static void siisata_device_reset(struct ata_channel *); 167 static void siisata_activate_prb(struct siisata_channel *, int); 168 static void siisata_deactivate_prb(struct siisata_channel *, int); 169 static int siisata_dma_setup(struct ata_channel *, int, void *, size_t, int); 170 static void siisata_channel_recover(struct ata_channel *, int, uint32_t); 171 172 #if NATAPIBUS > 0 173 void siisata_atapibus_attach(struct atabus_softc *); 174 void siisata_atapi_probe_device(struct atapibus_softc *, int); 175 void siisata_atapi_minphys(struct buf *); 176 int siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 177 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 178 void siisata_atapi_poll(struct ata_channel *, struct ata_xfer *); 179 void siisata_atapi_abort(struct ata_channel *, struct ata_xfer *); 180 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 181 void siisata_atapi_scsipi_request(struct scsipi_channel *, 182 scsipi_adapter_req_t, void *); 183 void siisata_atapi_kill_pending(struct scsipi_periph *); 184 #endif /* NATAPIBUS */ 185 186 const struct ata_bustype siisata_ata_bustype = { 187 SCSIPI_BUSTYPE_ATA, 188 siisata_ata_bio, 189 siisata_reset_drive, 190 siisata_reset_channel, 191 siisata_exec_command, 192 ata_get_params, 193 siisata_ata_addref, 194 siisata_ata_delref, 195 siisata_killpending, 196 siisata_channel_recover, 197 }; 198 199 #if NATAPIBUS > 0 200 static const struct scsipi_bustype siisata_atapi_bustype = { 201 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 202 .bustype_cmd = atapi_scsipi_cmd, 203 .bustype_interpret_sense = atapi_interpret_sense, 204 .bustype_printaddr = atapi_print_addr, 205 .bustype_kill_pending = siisata_atapi_kill_pending, 206 .bustype_async_event_xfer_mode = NULL, 207 }; 208 #endif /* NATAPIBUS */ 209 210 211 void 212 siisata_attach(struct siisata_softc *sc) 213 { 214 int i; 215 216 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 217 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 218 219 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 220 sc->sc_atac.atac_pio_cap = 4; 221 sc->sc_atac.atac_dma_cap = 2; 222 sc->sc_atac.atac_udma_cap = 6; 223 sc->sc_atac.atac_channels = sc->sc_chanarray; 224 sc->sc_atac.atac_probe = siisata_probe_drive; 225 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 226 sc->sc_atac.atac_set_modes = siisata_setup_channel; 227 #if NATAPIBUS > 0 228 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 229 #endif 230 231 /* come out of reset state */ 232 GRWRITE(sc, GR_GC, 0); 233 234 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 235 siisata_attach_port(sc, i); 236 } 237 238 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 239 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 240 return; 241 } 242 243 static void 244 siisata_disable_port_interrupt(struct ata_channel *chp) 245 { 246 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 247 248 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 249 } 250 251 static void 252 siisata_enable_port_interrupt(struct ata_channel *chp) 253 { 254 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 255 256 /* clear any interrupts */ 257 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 258 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 259 /* and enable CmdErrr+CmdCmpl interrupting */ 260 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 261 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 262 } 263 264 static int 265 siisata_init_port(struct siisata_softc *sc, int port) 266 { 267 struct siisata_channel *schp; 268 struct ata_channel *chp; 269 int error; 270 271 schp = &sc->sc_channels[port]; 272 chp = (struct ata_channel *)schp; 273 274 /* 275 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 276 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 277 */ 278 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 279 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 280 /* initialize port */ 281 error = siisata_reinit_port(chp, -1); 282 /* enable CmdErrr+CmdCmpl interrupting */ 283 siisata_enable_port_interrupt(chp); 284 /* enable port interrupt */ 285 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 286 287 return error; 288 } 289 290 static void 291 siisata_attach_port(struct siisata_softc *sc, int port) 292 { 293 int j; 294 int dmasize; 295 int error; 296 void *prbp; 297 struct siisata_channel *schp; 298 struct ata_channel *chp; 299 300 schp = &sc->sc_channels[port]; 301 chp = (struct ata_channel *)schp; 302 sc->sc_chanarray[port] = chp; 303 chp->ch_channel = port; 304 chp->ch_atac = &sc->sc_atac; 305 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 306 if (chp->ch_queue == NULL) { 307 aprint_error_dev(sc->sc_atac.atac_dev, 308 "port %d: can't allocate memory " 309 "for command queue\n", chp->ch_channel); 310 return; 311 } 312 313 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 314 315 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 316 __func__, dmasize), DEBUG_FUNCS); 317 318 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 319 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 320 if (error) { 321 aprint_error_dev(sc->sc_atac.atac_dev, 322 "unable to allocate PRB table memory, " 323 "error=%d\n", error); 324 return; 325 } 326 327 error = bus_dmamem_map(sc->sc_dmat, 328 &schp->sch_prb_seg, schp->sch_prb_nseg, 329 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 330 if (error) { 331 aprint_error_dev(sc->sc_atac.atac_dev, 332 "unable to map PRB table memory, " 333 "error=%d\n", error); 334 bus_dmamem_free(sc->sc_dmat, 335 &schp->sch_prb_seg, schp->sch_prb_nseg); 336 return; 337 } 338 339 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 340 BUS_DMA_NOWAIT, &schp->sch_prbd); 341 if (error) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "unable to create PRB table map, " 344 "error=%d\n", error); 345 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 346 bus_dmamem_free(sc->sc_dmat, 347 &schp->sch_prb_seg, schp->sch_prb_nseg); 348 return; 349 } 350 351 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 352 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 353 if (error) { 354 aprint_error_dev(sc->sc_atac.atac_dev, 355 "unable to load PRB table map, " 356 "error=%d\n", error); 357 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 358 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 359 bus_dmamem_free(sc->sc_dmat, 360 &schp->sch_prb_seg, schp->sch_prb_nseg); 361 return; 362 } 363 364 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 365 schp->sch_prb[j] = (struct siisata_prb *) 366 ((char *)prbp + SIISATA_CMD_SIZE * j); 367 schp->sch_bus_prb[j] = 368 schp->sch_prbd->dm_segs[0].ds_addr + 369 SIISATA_CMD_SIZE * j; 370 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 371 SIISATA_NSGE, MAXPHYS, 0, 372 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 373 &schp->sch_datad[j]); 374 if (error) { 375 aprint_error_dev(sc->sc_atac.atac_dev, 376 "couldn't create xfer DMA map, error=%d\n", 377 error); 378 return; 379 } 380 } 381 382 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 383 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 384 aprint_error_dev(sc->sc_atac.atac_dev, 385 "couldn't map port %d SStatus regs\n", 386 chp->ch_channel); 387 return; 388 } 389 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 390 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 391 aprint_error_dev(sc->sc_atac.atac_dev, 392 "couldn't map port %d SControl regs\n", 393 chp->ch_channel); 394 return; 395 } 396 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 397 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 398 aprint_error_dev(sc->sc_atac.atac_dev, 399 "couldn't map port %d SError regs\n", 400 chp->ch_channel); 401 return; 402 } 403 404 (void)siisata_init_port(sc, port); 405 406 ata_channel_attach(chp); 407 408 return; 409 } 410 411 void 412 siisata_childdetached(struct siisata_softc *sc, device_t child) 413 { 414 struct ata_channel *chp; 415 416 for (int i = 0; i < sc->sc_atac.atac_nchannels; i++) { 417 chp = sc->sc_chanarray[i]; 418 419 if (child == chp->atabus) 420 chp->atabus = NULL; 421 } 422 } 423 424 int 425 siisata_detach(struct siisata_softc *sc, int flags) 426 { 427 struct atac_softc *atac = &sc->sc_atac; 428 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 429 struct siisata_channel *schp; 430 struct ata_channel *chp; 431 int i, j, error; 432 433 if (adapt->adapt_refcnt != 0) 434 return EBUSY; 435 436 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 437 schp = &sc->sc_channels[i]; 438 chp = sc->sc_chanarray[i]; 439 440 if (chp->atabus != NULL) { 441 if ((error = config_detach(chp->atabus, flags)) != 0) 442 return error; 443 444 KASSERT(chp->atabus == NULL); 445 } 446 447 if (chp->ch_flags & ATACH_DETACHED) 448 continue; 449 450 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 451 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 452 453 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 454 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 455 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 456 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 457 bus_dmamem_free(sc->sc_dmat, 458 &schp->sch_prb_seg, schp->sch_prb_nseg); 459 460 ata_channel_detach(chp); 461 } 462 463 /* leave the chip in reset */ 464 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 465 466 return 0; 467 } 468 469 void 470 siisata_resume(struct siisata_softc *sc) 471 { 472 /* come out of reset state */ 473 GRWRITE(sc, GR_GC, 0); 474 475 for (int port = 0; port < sc->sc_atac.atac_nchannels; port++) { 476 int error; 477 478 error = siisata_init_port(sc, port); 479 if (error) { 480 struct siisata_channel *schp = &sc->sc_channels[port]; 481 struct ata_channel *chp = (struct ata_channel *)schp; 482 483 ata_channel_lock(chp); 484 siisata_reset_channel(chp, AT_POLL); 485 ata_channel_unlock(chp); 486 } 487 } 488 } 489 490 int 491 siisata_intr(void *v) 492 { 493 struct siisata_softc *sc = v; 494 uint32_t is; 495 int i, r = 0; 496 while ((is = GRREAD(sc, GR_GIS))) { 497 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 498 SIISATANAME(sc), __func__, is), DEBUG_INTR); 499 r = 1; 500 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 501 if (is & GR_GIS_PXIS(i)) 502 siisata_intr_port(&sc->sc_channels[i]); 503 } 504 return r; 505 } 506 507 static void 508 siisata_intr_port(struct siisata_channel *schp) 509 { 510 struct siisata_softc *sc = 511 (struct siisata_softc *)schp->ata_channel.ch_atac; 512 struct ata_channel *chp = &schp->ata_channel; 513 struct ata_xfer *xfer = NULL; 514 uint32_t pss, pis, tfd = 0; 515 bool recover = false; 516 517 /* get slot status, clearing completion interrupt */ 518 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 519 520 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x ", 521 SIISATANAME(sc), __func__, chp->ch_channel, pss), 522 DEBUG_INTR); 523 524 if (__predict_true((pss & PR_PSS_ATTENTION) == 0)) { 525 SIISATA_DEBUG_PRINT(("no attention"), DEBUG_INTR); 526 goto process; 527 } 528 529 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 530 531 SIISATA_DEBUG_PRINT(("pis 0x%x\n", pss), DEBUG_INTR); 532 533 if (pis & PR_PIS_CMDERRR) { 534 uint32_t ec; 535 536 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 537 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 538 539 /* emulate a CRC error by default */ 540 tfd = ATACH_ERR_ST(WDCE_CRC, WDCS_ERR); 541 542 if (ec <= PR_PCE_DATAFISERROR) { 543 if (ec == PR_PCE_DEVICEERROR 544 && (chp->ch_flags & ATACH_NCQ) == 0) { 545 xfer = ata_queue_get_active_xfer(chp); 546 547 /* read in specific information about error */ 548 uint32_t prbfis = bus_space_read_stream_4( 549 sc->sc_prt, sc->sc_prh, 550 PRSX(chp->ch_channel, xfer->c_slot, 551 PRSO_FIS)); 552 553 /* get status and error */ 554 int ntfd = satafis_rdh_parse(chp, 555 (uint8_t *)&prbfis); 556 557 if (ATACH_ST(ntfd) & WDCS_ERR) 558 tfd = ntfd; 559 } 560 561 /* 562 * We don't expect the recovery to trigger error, 563 * but handle this just in case. 564 */ 565 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 566 recover = true; 567 else { 568 aprint_error_dev(sc->sc_atac.atac_dev, 569 "error ec %x while recovering\n", ec); 570 571 /* Command will be marked as errored out */ 572 pss = 0; 573 } 574 } else { 575 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 576 " on port %d (ctx 0x%x), resetting\n", 577 ec, chp->ch_channel, 578 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 579 580 /* okay, we have a "Fatal Error" */ 581 ata_channel_lock(chp); 582 siisata_device_reset(chp); 583 ata_channel_unlock(chp); 584 } 585 } 586 587 /* clear some (ok, all) ints */ 588 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 589 590 if (__predict_false(recover)) 591 ata_channel_freeze(chp); 592 593 process: 594 if (xfer != NULL) { 595 xfer->ops->c_intr(chp, xfer, tfd); 596 } else { 597 /* 598 * For NCQ, HBA halts processing when error is notified, 599 * and any further D2H FISes are ignored until the error 600 * condition is cleared. Hence if a command is inactive, 601 * it means it actually already finished successfully. 602 * Note: active slots can change as c_intr() callback 603 * can activate another command(s), so must only process 604 * commands active before we start processing. 605 */ 606 uint32_t aslots = ata_queue_active(chp); 607 608 for (int slot=0; slot < SIISATA_MAX_SLOTS; slot++) { 609 if ((aslots & __BIT(slot)) != 0 && 610 (pss & PR_PXSS(slot)) == 0) { 611 xfer = ata_queue_hwslot_to_xfer(chp, slot); 612 xfer->ops->c_intr(chp, xfer, 0); 613 } 614 } 615 } 616 617 if (__predict_false(recover)) { 618 ata_channel_lock(chp); 619 ata_channel_thaw_locked(chp); 620 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 621 ata_channel_unlock(chp); 622 } 623 } 624 625 /* Recover channel after transfer aborted */ 626 void 627 siisata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 628 { 629 struct siisata_channel *schp = (struct siisata_channel *)chp; 630 struct siisata_softc *sc = 631 (struct siisata_softc *)schp->ata_channel.ch_atac; 632 int drive; 633 634 ata_channel_lock_owned(chp); 635 636 if (chp->ch_ndrives > PMP_PORT_CTL) { 637 /* Get PM port number for the device in error */ 638 int pcr = PRREAD(sc, PRX(chp->ch_channel, PRO_PCR)); 639 drive = PRO_PCR_PMP(pcr); 640 } else 641 drive = 0; 642 643 /* 644 * If BSY or DRQ bits are set, must execute COMRESET to return 645 * device to idle state. Otherwise, commands can be reissued 646 * after reinitalization of port. After that, need to execute 647 * READ LOG EXT for NCQ to unblock device processing if COMRESET 648 * was not done. 649 */ 650 if ((ATACH_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 651 siisata_device_reset(chp); 652 goto out; 653 } 654 655 KASSERT(drive >= 0); 656 (void)siisata_reinit_port(chp, drive); 657 658 ata_recovery_resume(chp, drive, tfd, flags); 659 660 out: 661 /* Drive unblocked, back to normal operation */ 662 return; 663 } 664 665 void 666 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 667 { 668 struct ata_channel *chp = drvp->chnl_softc; 669 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 670 struct siisata_channel *schp = (struct siisata_channel *)chp; 671 struct siisata_prb *prb; 672 uint8_t c_slot; 673 uint32_t pss, pis; 674 int i; 675 bool timed_out; 676 677 ata_channel_lock_owned(chp); 678 679 if (siisata_reinit_port(chp, drvp->drive)) 680 siisata_reset_channel(chp, flags); 681 682 /* get a slot for running the command on */ 683 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 684 panic("%s: %s: failed to get xfer for reset, port %d\n", 685 device_xname(sc->sc_atac.atac_dev), 686 __func__, chp->ch_channel); 687 /* NOTREACHED */ 688 } 689 690 prb = schp->sch_prb[c_slot]; 691 memset(prb, 0, SIISATA_CMD_SIZE); 692 prb->prb_control = 693 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 694 KASSERT(drvp->drive <= PMP_PORT_CTL); 695 prb->prb_fis[rhd_c] = drvp->drive; 696 697 siisata_disable_port_interrupt(chp); 698 699 siisata_activate_prb(schp, c_slot); 700 701 timed_out = true; 702 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 703 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 704 if ((pss & PR_PXSS(c_slot)) == 0) { 705 timed_out = false; 706 break; 707 } 708 if (pss & PR_PSS_ATTENTION) 709 break; 710 ata_delay(chp, 10, "siiprb", flags); 711 } 712 713 siisata_deactivate_prb(schp, c_slot); 714 715 if ((pss & PR_PSS_ATTENTION) != 0) { 716 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 717 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 718 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 719 720 if (slot != c_slot) 721 device_printf(sc->sc_atac.atac_dev, "%s port %d " 722 "drive %d slot %d c_slot %d", __func__, 723 chp->ch_channel, drvp->drive, slot, c_slot); 724 725 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 726 PR_PIS_CMDERRR); 727 } 728 729 siisata_enable_port_interrupt(chp); 730 731 if (timed_out) { 732 /* timeout */ 733 siisata_device_reset(chp); /* XXX is this right? */ 734 if (sigp) 735 *sigp = 0xffffffff; 736 } else { 737 /* read the signature out of the FIS */ 738 if (sigp) { 739 *sigp = 0; 740 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 741 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 742 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 743 PRSO_FIS+0xc)) & 0xff; 744 } 745 } 746 747 ata_queue_free_slot(chp, c_slot); 748 } 749 750 void 751 siisata_reset_channel(struct ata_channel *chp, int flags) 752 { 753 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 754 struct siisata_channel *schp = (struct siisata_channel *)chp; 755 756 SIISATA_DEBUG_PRINT(("%s: %s port %d\n", SIISATANAME(sc), __func__, 757 chp->ch_channel), DEBUG_FUNCS); 758 759 ata_channel_lock_owned(chp); 760 761 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 762 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 763 aprint_error("%s port %d: reset failed\n", 764 SIISATANAME(sc), chp->ch_channel); 765 /* XXX and then ? */ 766 } 767 768 siisata_device_reset(chp); 769 770 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 771 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 772 773 return; 774 } 775 776 int 777 siisata_ata_addref(struct ata_drive_datas *drvp) 778 { 779 return 0; 780 } 781 782 void 783 siisata_ata_delref(struct ata_drive_datas *drvp) 784 { 785 return; 786 } 787 788 void 789 siisata_killpending(struct ata_drive_datas *drvp) 790 { 791 return; 792 } 793 794 void 795 siisata_probe_drive(struct ata_channel *chp) 796 { 797 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 798 struct siisata_channel *schp = (struct siisata_channel *)chp; 799 int i; 800 uint32_t sig; 801 struct siisata_prb *prb; 802 bool timed_out; 803 uint8_t c_slot; 804 805 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 806 __func__, chp->ch_channel), DEBUG_FUNCS); 807 808 ata_channel_lock(chp); 809 810 /* get a slot for running the command on */ 811 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 812 aprint_error_dev(sc->sc_atac.atac_dev, 813 "%s: failed to get xfer port %d\n", 814 __func__, chp->ch_channel); 815 ata_channel_unlock(chp); 816 return; 817 } 818 819 /* 820 * disable port interrupt as we're polling for PHY up and 821 * prb completion 822 */ 823 siisata_disable_port_interrupt(chp); 824 825 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 826 schp->sch_sstatus, AT_WAIT)) { 827 case SStatus_DET_DEV: 828 /* clear any interrupts */ 829 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 830 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 831 832 /* wait for ready */ 833 timed_out = 1; 834 for (i = 0; i < ATA_DELAY / 10; i++) { 835 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & 836 PR_PS_PORT_READY) { 837 timed_out = 0; 838 break; 839 } 840 841 ata_delay(chp, 10, "siiprbrd", AT_WAIT); 842 } 843 if (timed_out) { 844 aprint_error_dev(sc->sc_atac.atac_dev, 845 "timed out waiting for PORT_READY on port %d, " 846 "reinitializing\n", chp->ch_channel); 847 if (siisata_reinit_port(chp, -1)) 848 siisata_reset_channel(chp, AT_WAIT); 849 } 850 851 prb = schp->sch_prb[c_slot]; 852 memset(prb, 0, SIISATA_CMD_SIZE); 853 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 854 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 855 856 siisata_activate_prb(schp, c_slot); 857 858 timed_out = 1; 859 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 860 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 861 PR_PXSS(c_slot)) == 0) { 862 /* prb completed */ 863 timed_out = 0; 864 break; 865 } 866 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 867 PR_PIS_CMDERRR) { 868 /* we got an error; handle as timeout */ 869 break; 870 } 871 872 ata_delay(chp, 10, "siiprb", AT_WAIT); 873 } 874 875 siisata_deactivate_prb(schp, c_slot); 876 877 if (timed_out) { 878 aprint_error_dev(sc->sc_atac.atac_dev, 879 "SOFT_RESET failed on port %d (error %d PSS 0x%x PIS 0x%x), " 880 "resetting\n", chp->ch_channel, 881 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 882 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)), 883 PRREAD(sc, PRX(chp->ch_channel, PRO_PIS))); 884 if (siisata_reinit_port(chp, -1)) 885 siisata_reset_channel(chp, AT_WAIT); 886 break; 887 } 888 889 /* read the signature out of the FIS */ 890 sig = 0; 891 sig |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 892 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 893 sig |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 894 PRSO_FIS+0xc)) & 0xff; 895 896 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 897 __func__, sig), DEBUG_PROBE); 898 899 if (sig == 0x96690101) 900 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 901 PR_PC_PMP_ENABLE); 902 sata_interpret_sig(chp, 0, sig); 903 break; 904 default: 905 break; 906 } 907 908 siisata_enable_port_interrupt(chp); 909 910 ata_queue_free_slot(chp, c_slot); 911 912 ata_channel_unlock(chp); 913 914 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 915 __func__, chp->ch_channel), DEBUG_PROBE); 916 return; 917 } 918 919 void 920 siisata_setup_channel(struct ata_channel *chp) 921 { 922 return; 923 } 924 925 static const struct ata_xfer_ops siisata_cmd_xfer_ops = { 926 .c_start = siisata_cmd_start, 927 .c_intr = siisata_cmd_complete, 928 .c_poll = siisata_cmd_poll, 929 .c_abort = siisata_cmd_abort, 930 .c_kill_xfer = siisata_cmd_kill_xfer, 931 }; 932 933 void 934 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 935 { 936 struct ata_channel *chp = drvp->chnl_softc; 937 struct ata_command *ata_c = &xfer->c_ata_c; 938 939 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 940 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 941 DEBUG_FUNCS); 942 943 if (ata_c->flags & AT_POLL) 944 xfer->c_flags |= C_POLL; 945 if (ata_c->flags & AT_WAIT) 946 xfer->c_flags |= C_WAIT; 947 xfer->c_drive = drvp->drive; 948 xfer->c_databuf = ata_c->data; 949 xfer->c_bcount = ata_c->bcount; 950 xfer->ops = &siisata_cmd_xfer_ops; 951 952 ata_exec_xfer(chp, xfer); 953 954 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 955 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 956 DEBUG_FUNCS); 957 } 958 959 int 960 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 961 { 962 struct siisata_channel *schp = (struct siisata_channel *)chp; 963 struct ata_command *ata_c = &xfer->c_ata_c; 964 struct siisata_prb *prb; 965 966 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 967 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 968 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 969 DEBUG_FUNCS|DEBUG_XFERS); 970 971 ata_channel_lock_owned(chp); 972 973 prb = schp->sch_prb[xfer->c_slot]; 974 memset(prb, 0, SIISATA_CMD_SIZE); 975 976 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 977 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 978 prb->prb_fis[rhd_c] |= xfer->c_drive; 979 980 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 981 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 982 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 983 } 984 985 if (siisata_dma_setup(chp, xfer->c_slot, 986 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 987 ata_c->bcount, 988 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 989 ata_c->flags |= AT_DF; 990 return ATASTART_ABORT; 991 } 992 993 if (xfer->c_flags & C_POLL) { 994 /* polled command, disable interrupts */ 995 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 996 siisata_disable_port_interrupt(chp); 997 } 998 999 /* go for it */ 1000 siisata_activate_prb(schp, xfer->c_slot); 1001 1002 if ((ata_c->flags & AT_POLL) == 0) { 1003 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1004 ata_timeout, chp); 1005 return ATASTART_STARTED; 1006 } else 1007 return ATASTART_POLL; 1008 } 1009 1010 void 1011 siisata_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1012 { 1013 struct siisata_channel *schp = (struct siisata_channel *)chp; 1014 1015 /* 1016 * polled command 1017 */ 1018 for (int i = 0; i < xfer->c_ata_c.timeout * 10; i++) { 1019 if (xfer->c_ata_c.flags & AT_DONE) 1020 break; 1021 siisata_intr_port(schp); 1022 DELAY(100); 1023 } 1024 1025 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1026 ata_timeout(xfer); 1027 } 1028 1029 /* reenable interrupts */ 1030 siisata_enable_port_interrupt(chp); 1031 1032 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1033 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1034 DEBUG_FUNCS); 1035 } 1036 1037 void 1038 siisata_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1039 { 1040 siisata_cmd_complete(chp, xfer, 0); 1041 } 1042 1043 void 1044 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1045 int reason) 1046 { 1047 struct ata_command *ata_c = &xfer->c_ata_c; 1048 struct siisata_channel *schp = (struct siisata_channel *)chp; 1049 bool deactivate = true; 1050 1051 switch (reason) { 1052 case KILL_GONE_INACTIVE: 1053 deactivate = false; 1054 /* FALLTHROUGH */ 1055 case KILL_GONE: 1056 ata_c->flags |= AT_GONE; 1057 break; 1058 case KILL_RESET: 1059 ata_c->flags |= AT_RESET; 1060 break; 1061 case KILL_REQUEUE: 1062 panic("%s: not supposed to be requeued\n", __func__); 1063 break; 1064 default: 1065 panic("%s: port %d: unknown reason %d", 1066 __func__, chp->ch_channel, reason); 1067 } 1068 1069 siisata_cmd_done_end(chp, xfer); 1070 1071 if (deactivate) { 1072 siisata_deactivate_prb(schp, xfer->c_slot); 1073 ata_deactivate_xfer(chp, xfer); 1074 } 1075 } 1076 1077 int 1078 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1079 { 1080 struct siisata_channel *schp = (struct siisata_channel *)chp; 1081 struct ata_command *ata_c = &xfer->c_ata_c; 1082 #ifdef SIISATA_DEBUG 1083 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1084 #endif 1085 1086 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1087 SIISATANAME(sc), __func__, 1088 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1089 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1090 DEBUG_FUNCS|DEBUG_XFERS); 1091 1092 if (ata_waitdrain_xfer_check(chp, xfer)) 1093 return 0; 1094 1095 if (xfer->c_flags & C_TIMEOU) 1096 ata_c->flags |= AT_TIMEOU; 1097 1098 if (ATACH_ST(tfd) & WDCS_BSY) { 1099 ata_c->flags |= AT_TIMEOU; 1100 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1101 ata_c->r_error = ATACH_ERR(tfd); 1102 ata_c->flags |= AT_ERROR; 1103 } 1104 1105 siisata_cmd_done(chp, xfer, tfd); 1106 1107 siisata_deactivate_prb(schp, xfer->c_slot); 1108 ata_deactivate_xfer(chp, xfer); 1109 1110 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1111 atastart(chp); 1112 1113 return 0; 1114 } 1115 1116 void 1117 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1118 { 1119 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1120 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1121 struct siisata_channel *schp = (struct siisata_channel *)chp; 1122 struct ata_command *ata_c = &xfer->c_ata_c; 1123 uint16_t *idwordbuf; 1124 int i; 1125 1126 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1127 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1128 1129 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1130 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1131 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1132 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1133 BUS_DMASYNC_POSTWRITE); 1134 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1135 } 1136 1137 if (ata_c->flags & AT_READREG) { 1138 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1139 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1140 fis, __arraycount(fis)); 1141 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1142 } 1143 1144 /* correct the endianess of IDENTIFY data */ 1145 if (ata_c->r_command == WDCC_IDENTIFY || 1146 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1147 idwordbuf = xfer->c_databuf; 1148 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1149 idwordbuf[i] = le16toh(idwordbuf[i]); 1150 } 1151 } 1152 1153 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1154 ata_c->flags |= AT_XFDONE; 1155 1156 siisata_cmd_done_end(chp, xfer); 1157 } 1158 1159 static void 1160 siisata_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1161 { 1162 struct ata_command *ata_c = &xfer->c_ata_c; 1163 1164 ata_c->flags |= AT_DONE; 1165 } 1166 1167 static const struct ata_xfer_ops siisata_bio_xfer_ops = { 1168 .c_start = siisata_bio_start, 1169 .c_intr = siisata_bio_complete, 1170 .c_poll = siisata_bio_poll, 1171 .c_abort = siisata_bio_abort, 1172 .c_kill_xfer = siisata_bio_kill_xfer, 1173 }; 1174 1175 void 1176 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1177 { 1178 struct ata_channel *chp = drvp->chnl_softc; 1179 struct ata_bio *ata_bio = &xfer->c_bio; 1180 1181 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1182 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1183 DEBUG_FUNCS); 1184 1185 if (ata_bio->flags & ATA_POLL) 1186 xfer->c_flags |= C_POLL; 1187 xfer->c_drive = drvp->drive; 1188 xfer->c_databuf = ata_bio->databuf; 1189 xfer->c_bcount = ata_bio->bcount; 1190 xfer->ops = &siisata_bio_xfer_ops; 1191 ata_exec_xfer(chp, xfer); 1192 } 1193 1194 int 1195 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1196 { 1197 struct siisata_channel *schp = (struct siisata_channel *)chp; 1198 struct siisata_prb *prb; 1199 struct ata_bio *ata_bio = &xfer->c_bio; 1200 1201 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1202 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1203 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1204 1205 ata_channel_lock_owned(chp); 1206 1207 prb = schp->sch_prb[xfer->c_slot]; 1208 memset(prb, 0, SIISATA_CMD_SIZE); 1209 1210 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1211 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1212 prb->prb_fis[rhd_c] |= xfer->c_drive; 1213 1214 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1215 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1216 ata_bio->error = ERR_DMA; 1217 ata_bio->r_error = 0; 1218 return ATASTART_ABORT; 1219 } 1220 1221 if (xfer->c_flags & C_POLL) { 1222 /* polled command, disable interrupts */ 1223 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1224 siisata_disable_port_interrupt(chp); 1225 } 1226 1227 siisata_activate_prb(schp, xfer->c_slot); 1228 1229 if ((ata_bio->flags & ATA_POLL) == 0) { 1230 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1231 ata_timeout, chp); 1232 return ATASTART_STARTED; 1233 } else 1234 return ATASTART_POLL; 1235 } 1236 1237 void 1238 siisata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1239 { 1240 struct siisata_channel *schp = (struct siisata_channel *)chp; 1241 1242 /* 1243 * polled command 1244 */ 1245 for (int i = 0; i < ATA_DELAY * 10; i++) { 1246 if (xfer->c_bio.flags & ATA_ITSDONE) 1247 break; 1248 siisata_intr_port(schp); 1249 DELAY(100); 1250 } 1251 1252 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1253 ata_timeout(xfer); 1254 } 1255 1256 siisata_enable_port_interrupt(chp); 1257 1258 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1259 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1260 DEBUG_FUNCS); 1261 } 1262 1263 void 1264 siisata_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1265 { 1266 siisata_cmd_complete(chp, xfer, 0); 1267 } 1268 1269 void 1270 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1271 int reason) 1272 { 1273 struct siisata_channel *schp = (struct siisata_channel *)chp; 1274 struct ata_bio *ata_bio = &xfer->c_bio; 1275 int drive = xfer->c_drive; 1276 bool deactivate = true; 1277 1278 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1279 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1280 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1281 1282 ata_bio->flags |= ATA_ITSDONE; 1283 switch (reason) { 1284 case KILL_GONE_INACTIVE: 1285 deactivate = false; 1286 /* FALLTHROUGH */ 1287 case KILL_GONE: 1288 ata_bio->error = ERR_NODEV; 1289 break; 1290 case KILL_RESET: 1291 ata_bio->error = ERR_RESET; 1292 break; 1293 case KILL_REQUEUE: 1294 ata_bio->error = REQUEUE; 1295 break; 1296 default: 1297 panic("%s: port %d: unknown reason %d", 1298 __func__, chp->ch_channel, reason); 1299 } 1300 ata_bio->r_error = WDCE_ABRT; 1301 1302 if (deactivate) { 1303 siisata_deactivate_prb(schp, xfer->c_slot); 1304 ata_deactivate_xfer(chp, xfer); 1305 } 1306 1307 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1308 } 1309 1310 int 1311 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1312 { 1313 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1314 struct siisata_channel *schp = (struct siisata_channel *)chp; 1315 struct ata_bio *ata_bio = &xfer->c_bio; 1316 int drive = xfer->c_drive; 1317 1318 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d tfd %x\n", 1319 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1320 chp->ch_channel, xfer->c_slot, xfer->c_drive, tfd), DEBUG_FUNCS); 1321 1322 if (ata_waitdrain_xfer_check(chp, xfer)) 1323 return 0; 1324 1325 if (xfer->c_flags & C_TIMEOU) { 1326 ata_bio->error = TIMEOUT; 1327 } 1328 1329 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1330 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1331 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1332 BUS_DMASYNC_POSTWRITE); 1333 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1334 1335 ata_bio->flags |= ATA_ITSDONE; 1336 if (ATACH_ST(tfd) & WDCS_DWF) { 1337 ata_bio->error = ERR_DF; 1338 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1339 ata_bio->error = ERROR; 1340 ata_bio->r_error = ATACH_ERR(tfd); 1341 } else if (ATACH_ST(tfd) & WDCS_CORR) 1342 ata_bio->flags |= ATA_CORR; 1343 1344 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1345 ata_bio->bcount), DEBUG_XFERS); 1346 if (ata_bio->error == NOERROR) { 1347 if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ) 1348 ata_bio->bcount -= 1349 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1350 else 1351 ata_bio->bcount = 0; 1352 } 1353 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1354 1355 siisata_deactivate_prb(schp, xfer->c_slot); 1356 ata_deactivate_xfer(chp, xfer); 1357 1358 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1359 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1360 atastart(chp); 1361 return 0; 1362 } 1363 1364 static int 1365 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1366 size_t count, int op) 1367 { 1368 1369 int error, seg; 1370 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1371 struct siisata_channel *schp = (struct siisata_channel *)chp; 1372 1373 struct siisata_prb *prbp; 1374 1375 prbp = schp->sch_prb[slot]; 1376 1377 if (data == NULL) { 1378 goto end; 1379 } 1380 1381 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1382 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1383 if (error) { 1384 aprint_error("%s port %d: " 1385 "failed to load xfer in slot %d: error %d\n", 1386 SIISATANAME(sc), chp->ch_channel, slot, error); 1387 return error; 1388 } 1389 1390 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1391 schp->sch_datad[slot]->dm_mapsize, 1392 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1393 1394 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1395 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1396 DEBUG_FUNCS | DEBUG_DEBUG); 1397 1398 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1399 prbp->prb_sge[seg].sge_da = 1400 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1401 prbp->prb_sge[seg].sge_dc = 1402 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1403 prbp->prb_sge[seg].sge_flags = htole32(0); 1404 } 1405 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1406 end: 1407 return 0; 1408 } 1409 1410 static void 1411 siisata_activate_prb(struct siisata_channel *schp, int slot) 1412 { 1413 struct siisata_softc *sc; 1414 bus_size_t offset; 1415 uint64_t pprb; 1416 1417 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1418 1419 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1420 1421 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1422 1423 pprb = schp->sch_bus_prb[slot]; 1424 1425 PRWRITE(sc, offset + 0, pprb >> 0); 1426 PRWRITE(sc, offset + 4, pprb >> 32); 1427 } 1428 1429 static void 1430 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1431 { 1432 struct siisata_softc *sc; 1433 1434 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1435 1436 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1437 } 1438 1439 static int 1440 siisata_reinit_port(struct ata_channel *chp, int drive) 1441 { 1442 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1443 int ps; 1444 int error = 0; 1445 1446 if (chp->ch_ndrives > 1) { 1447 /* 1448 * Proper recovery would SET this bit, which makes it 1449 * not possible to submit new commands and resume execution 1450 * on non-errored drives, then wait for those commands, 1451 * to finish, and only then clear the bit and reset the state. 1452 * For now this is okay, since we never queue commands for 1453 * more than one drive. 1454 * XXX FIS-based switching 1455 */ 1456 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_RESUME); 1457 1458 for (int i = 0; i < chp->ch_ndrives; i++) { 1459 if (drive >= 0 && i != drive) 1460 continue; 1461 1462 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPSTS(i)), 0); 1463 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPQACT(i)), 0); 1464 } 1465 } 1466 1467 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1468 for (int i = 0; i < ATA_DELAY * 100; i++) { 1469 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1470 if ((ps & PR_PS_PORT_READY) != 0) 1471 break; 1472 1473 DELAY(10); 1474 } 1475 if ((ps & PR_PS_PORT_READY) == 0) { 1476 printf("%s: timeout waiting for port to be ready\n", __func__); 1477 error = EBUSY; 1478 } 1479 1480 if (chp->ch_ndrives > 1) 1481 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1482 1483 return error; 1484 } 1485 1486 static void 1487 siisata_device_reset(struct ata_channel *chp) 1488 { 1489 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1490 int ps; 1491 1492 ata_channel_lock_owned(chp); 1493 1494 /* 1495 * This is always called after siisata_reinit_port(), so don't 1496 * need to deal with RESUME and clearing device error state. 1497 */ 1498 1499 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1500 1501 for (int i = 0; i < ATA_DELAY * 100; i++) { 1502 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1503 if ((ps & PR_PS_PORT_READY) != 0) 1504 break; 1505 1506 DELAY(10); 1507 } 1508 if ((ps & PR_PS_PORT_READY) == 0) { 1509 printf("%s: timeout waiting for port to be ready\n", __func__); 1510 siisata_reset_channel(chp, AT_POLL); 1511 } 1512 1513 ata_kill_active(chp, KILL_RESET, 0); 1514 } 1515 1516 1517 #if NATAPIBUS > 0 1518 void 1519 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1520 { 1521 struct ata_channel *chp = ata_sc->sc_chan; 1522 struct atac_softc *atac = chp->ch_atac; 1523 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1524 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1525 1526 /* 1527 * Fill in the scsipi_adapter. 1528 */ 1529 adapt->adapt_dev = atac->atac_dev; 1530 adapt->adapt_nchannels = atac->atac_nchannels; 1531 adapt->adapt_request = siisata_atapi_scsipi_request; 1532 adapt->adapt_minphys = siisata_atapi_minphys; 1533 atac->atac_atapi_adapter.atapi_probe_device = 1534 siisata_atapi_probe_device; 1535 1536 /* 1537 * Fill in the scsipi_channel. 1538 */ 1539 memset(chan, 0, sizeof(*chan)); 1540 chan->chan_adapter = adapt; 1541 chan->chan_bustype = &siisata_atapi_bustype; 1542 chan->chan_channel = chp->ch_channel; 1543 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1544 chan->chan_openings = 1; 1545 chan->chan_max_periph = 1; 1546 chan->chan_ntargets = 1; 1547 chan->chan_nluns = 1; 1548 1549 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1550 atapiprint); 1551 } 1552 1553 void 1554 siisata_atapi_minphys(struct buf *bp) 1555 { 1556 if (bp->b_bcount > MAXPHYS) 1557 bp->b_bcount = MAXPHYS; 1558 minphys(bp); 1559 } 1560 1561 /* 1562 * Kill off all pending xfers for a periph. 1563 * 1564 * Must be called at splbio(). 1565 */ 1566 void 1567 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1568 { 1569 struct atac_softc *atac = 1570 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1571 struct ata_channel *chp = 1572 atac->atac_channels[periph->periph_channel->chan_channel]; 1573 1574 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1575 } 1576 1577 void 1578 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1579 int reason) 1580 { 1581 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1582 struct siisata_channel *schp = (struct siisata_channel *)chp; 1583 bool deactivate = true; 1584 1585 /* remove this command from xfer queue */ 1586 switch (reason) { 1587 case KILL_GONE_INACTIVE: 1588 deactivate = false; 1589 /* FALLTHROUGH */ 1590 case KILL_GONE: 1591 sc_xfer->error = XS_DRIVER_STUFFUP; 1592 break; 1593 case KILL_RESET: 1594 sc_xfer->error = XS_RESET; 1595 break; 1596 case KILL_REQUEUE: 1597 sc_xfer->error = XS_REQUEUE; 1598 break; 1599 default: 1600 panic("%s: port %d: unknown reason %d", 1601 __func__, chp->ch_channel, reason); 1602 } 1603 1604 if (deactivate) { 1605 siisata_deactivate_prb(schp, xfer->c_slot); 1606 ata_deactivate_xfer(chp, xfer); 1607 } 1608 1609 ata_free_xfer(chp, xfer); 1610 scsipi_done(sc_xfer); 1611 } 1612 1613 void 1614 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1615 { 1616 struct scsipi_channel *chan = sc->sc_channel; 1617 struct scsipi_periph *periph; 1618 struct ataparams ids; 1619 struct ataparams *id = &ids; 1620 struct siisata_softc *siic = 1621 device_private(chan->chan_adapter->adapt_dev); 1622 struct atac_softc *atac = &siic->sc_atac; 1623 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1624 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1625 struct scsipibus_attach_args sa; 1626 char serial_number[21], model[41], firmware_revision[9]; 1627 int s; 1628 1629 /* skip if already attached */ 1630 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1631 return; 1632 1633 /* if no ATAPI device detected at attach time, skip */ 1634 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1635 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1636 target), DEBUG_PROBE); 1637 return; 1638 } 1639 1640 /* Some ATAPI devices need a bit more time after software reset. */ 1641 DELAY(5000); 1642 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1643 #ifdef ATAPI_DEBUG_PROBE 1644 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1645 device_xname(sc->sc_dev), target, 1646 id->atap_config & ATAPI_CFG_CMD_MASK, 1647 id->atap_config & ATAPI_CFG_DRQ_MASK); 1648 #endif 1649 periph = scsipi_alloc_periph(M_WAITOK); 1650 periph->periph_dev = NULL; 1651 periph->periph_channel = chan; 1652 periph->periph_switch = &atapi_probe_periphsw; 1653 periph->periph_target = target; 1654 periph->periph_lun = 0; 1655 periph->periph_quirks = PQUIRK_ONLYBIG; 1656 1657 #ifdef SCSIPI_DEBUG 1658 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1659 SCSIPI_DEBUG_TARGET == target) 1660 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1661 #endif 1662 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1663 if (id->atap_config & ATAPI_CFG_REMOV) 1664 periph->periph_flags |= PERIPH_REMOVABLE; 1665 sa.sa_periph = periph; 1666 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1667 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1668 T_REMOV : T_FIXED; 1669 strnvisx(model, sizeof(model), id->atap_model, 40, 1670 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1671 strnvisx(serial_number, sizeof(serial_number), 1672 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1673 strnvisx(firmware_revision, sizeof(firmware_revision), 1674 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1675 sa.sa_inqbuf.vendor = model; 1676 sa.sa_inqbuf.product = serial_number; 1677 sa.sa_inqbuf.revision = firmware_revision; 1678 1679 /* 1680 * Determine the operating mode capabilities of the device. 1681 */ 1682 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1683 == ATAPI_CFG_CMD_16) { 1684 periph->periph_cap |= PERIPH_CAP_CMD16; 1685 1686 /* configure port for packet length */ 1687 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1688 PR_PC_PACKET_LENGTH); 1689 } else { 1690 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1691 PR_PC_PACKET_LENGTH); 1692 } 1693 1694 /* XXX This is gross. */ 1695 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1696 1697 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1698 1699 if (drvp->drv_softc) 1700 ata_probe_caps(drvp); 1701 else { 1702 s = splbio(); 1703 drvp->drive_type &= ATA_DRIVET_NONE; 1704 splx(s); 1705 } 1706 } else { 1707 s = splbio(); 1708 drvp->drive_type &= ATA_DRIVET_NONE; 1709 splx(s); 1710 } 1711 } 1712 1713 static const struct ata_xfer_ops siisata_atapi_xfer_ops = { 1714 .c_start = siisata_atapi_start, 1715 .c_intr = siisata_atapi_complete, 1716 .c_poll = siisata_atapi_poll, 1717 .c_abort = siisata_atapi_abort, 1718 .c_kill_xfer = siisata_atapi_kill_xfer, 1719 }; 1720 1721 void 1722 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1723 scsipi_adapter_req_t req, void *arg) 1724 { 1725 struct scsipi_adapter *adapt = chan->chan_adapter; 1726 struct scsipi_periph *periph; 1727 struct scsipi_xfer *sc_xfer; 1728 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1729 struct atac_softc *atac = &sc->sc_atac; 1730 struct ata_xfer *xfer; 1731 int channel = chan->chan_channel; 1732 int drive, s; 1733 1734 switch (req) { 1735 case ADAPTER_REQ_RUN_XFER: 1736 sc_xfer = arg; 1737 periph = sc_xfer->xs_periph; 1738 drive = periph->periph_target; 1739 1740 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1741 device_xname(atac->atac_dev), channel, drive), 1742 DEBUG_XFERS); 1743 1744 if (!device_is_active(atac->atac_dev)) { 1745 sc_xfer->error = XS_DRIVER_STUFFUP; 1746 scsipi_done(sc_xfer); 1747 return; 1748 } 1749 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1750 if (xfer == NULL) { 1751 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1752 scsipi_done(sc_xfer); 1753 return; 1754 } 1755 1756 if (sc_xfer->xs_control & XS_CTL_POLL) 1757 xfer->c_flags |= C_POLL; 1758 xfer->c_drive = drive; 1759 xfer->c_flags |= C_ATAPI; 1760 xfer->c_databuf = sc_xfer->data; 1761 xfer->c_bcount = sc_xfer->datalen; 1762 xfer->ops = &siisata_atapi_xfer_ops; 1763 xfer->c_scsipi = sc_xfer; 1764 xfer->c_atapi.c_dscpoll = 0; 1765 s = splbio(); 1766 ata_exec_xfer(atac->atac_channels[channel], xfer); 1767 #ifdef DIAGNOSTIC 1768 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1769 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1770 panic("%s: polled command not done", __func__); 1771 #endif 1772 splx(s); 1773 return; 1774 1775 default: 1776 /* Not supported, nothing to do. */ 1777 ; 1778 } 1779 } 1780 1781 int 1782 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1783 { 1784 struct siisata_channel *schp = (struct siisata_channel *)chp; 1785 struct siisata_prb *prbp; 1786 1787 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1788 1789 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1790 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1791 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1792 DEBUG_XFERS); 1793 1794 ata_channel_lock_owned(chp); 1795 1796 prbp = schp->sch_prb[xfer->c_slot]; 1797 memset(prbp, 0, SIISATA_CMD_SIZE); 1798 1799 /* fill in direction for ATAPI command */ 1800 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1801 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1802 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1803 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1804 1805 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1806 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1807 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1808 1809 /* copy over ATAPI command */ 1810 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1811 1812 if (siisata_dma_setup(chp, xfer->c_slot, 1813 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1814 xfer->c_databuf : NULL, 1815 xfer->c_bcount, 1816 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1817 BUS_DMA_READ : BUS_DMA_WRITE) 1818 ) { 1819 sc_xfer->error = XS_DRIVER_STUFFUP; 1820 return ATASTART_ABORT; 1821 } 1822 1823 if (xfer->c_flags & C_POLL) { 1824 /* polled command, disable interrupts */ 1825 prbp->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1826 siisata_disable_port_interrupt(chp); 1827 } 1828 1829 siisata_activate_prb(schp, xfer->c_slot); 1830 1831 if ((xfer->c_flags & C_POLL) == 0) { 1832 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1833 ata_timeout, chp); 1834 return ATASTART_STARTED; 1835 } else 1836 return ATASTART_POLL; 1837 } 1838 1839 void 1840 siisata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1841 { 1842 struct siisata_channel *schp = (struct siisata_channel *)chp; 1843 1844 /* 1845 * polled command 1846 */ 1847 for (int i = 0; i < ATA_DELAY * 10; i++) { 1848 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1849 break; 1850 siisata_intr_port(schp); 1851 DELAY(100); 1852 } 1853 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1854 ata_timeout(xfer); 1855 } 1856 /* reenable interrupts */ 1857 siisata_enable_port_interrupt(chp); 1858 1859 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1860 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1861 DEBUG_FUNCS); 1862 } 1863 1864 void 1865 siisata_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1866 { 1867 siisata_atapi_complete(chp, xfer, 0); 1868 } 1869 1870 int 1871 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1872 int tfd) 1873 { 1874 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1875 struct siisata_channel *schp = (struct siisata_channel *)chp; 1876 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1877 1878 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1879 DEBUG_INTR); 1880 1881 if (ata_waitdrain_xfer_check(chp, xfer)) 1882 return 0; 1883 1884 if (xfer->c_flags & C_TIMEOU) { 1885 sc_xfer->error = XS_TIMEOUT; 1886 } 1887 1888 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1889 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1890 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1891 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1892 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1893 1894 sc_xfer->resid = sc_xfer->datalen; 1895 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1896 PRSO_RTC)); 1897 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1898 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1899 if ((ATACH_ST(tfd) & WDCS_ERR) && 1900 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1901 sc_xfer->resid == sc_xfer->datalen)) { 1902 sc_xfer->error = XS_SHORTSENSE; 1903 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1904 if ((sc_xfer->xs_periph->periph_quirks & 1905 PQUIRK_NOSENSE) == 0) { 1906 /* request sense */ 1907 sc_xfer->error = XS_BUSY; 1908 sc_xfer->status = SCSI_CHECK; 1909 } 1910 } 1911 1912 siisata_deactivate_prb(schp, xfer->c_slot); 1913 ata_deactivate_xfer(chp, xfer); 1914 1915 ata_free_xfer(chp, xfer); 1916 scsipi_done(sc_xfer); 1917 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1918 atastart(chp); 1919 return 0; 1920 } 1921 1922 #endif /* NATAPIBUS */ 1923
Indexes created Mon Oct 20 05:10:11 GMT 2025