siisata.c revision 1.43
1 /* $NetBSD: siisata.c,v 1.43 2020/10/10 20:27:54 thorpej Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009, 2010 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.43 2020/10/10 20:27:54 thorpej Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/param.h> 86 #include <sys/kernel.h> 87 #include <sys/malloc.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 #include <sys/proc.h> 93 94 #include <dev/ata/atareg.h> 95 #include <dev/ata/satavar.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satafisvar.h> 98 #include <dev/ata/satafisreg.h> 99 #include <dev/ata/satapmpreg.h> 100 #include <dev/ic/siisatavar.h> 101 #include <dev/ic/siisatareg.h> 102 103 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 104 105 #include "atapibus.h" 106 107 #ifdef SIISATA_DEBUG 108 int siisata_debug_mask = 0; 109 #endif 110 111 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 112 #define WDC_RESET_WAIT 31000 /* 31s for drive reset */ 113 114 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 115 #if _BYTE_ORDER == _LITTLE_ENDIAN 116 #define bus_space_read_stream_4 bus_space_read_4 117 #define bus_space_read_region_stream_4 bus_space_read_region_4 118 #else 119 static inline uint32_t 120 bus_space_read_stream_4(bus_space_tag_t t, bus_space_handle_t h, bus_size_t o) 121 { 122 return htole32(bus_space_read_4(t, h, o)); 123 } 124 125 static inline void 126 bus_space_read_region_stream_4(bus_space_tag_t t, bus_space_handle_t h, 127 bus_size_t o, uint32_t *p, bus_size_t c) 128 { 129 bus_space_read_region_4(t, h, o, p, c); 130 for (bus_size_t i = 0; i < c; i++) { 131 p[i] = htole32(p[i]); 132 } 133 } 134 #endif 135 #endif 136 137 static void siisata_attach_port(struct siisata_softc *, int); 138 static void siisata_intr_port(struct siisata_channel *); 139 140 void siisata_probe_drive(struct ata_channel *); 141 void siisata_setup_channel(struct ata_channel *); 142 143 void siisata_ata_bio(struct ata_drive_datas *, struct ata_xfer *); 144 void siisata_reset_drive(struct ata_drive_datas *, int, uint32_t *); 145 void siisata_reset_channel(struct ata_channel *, int); 146 int siisata_ata_addref(struct ata_drive_datas *); 147 void siisata_ata_delref(struct ata_drive_datas *); 148 void siisata_killpending(struct ata_drive_datas *); 149 150 int siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 151 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_cmd_poll(struct ata_channel *, struct ata_xfer *); 153 void siisata_cmd_abort(struct ata_channel *, struct ata_xfer *); 154 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 155 static void siisata_cmd_done_end(struct ata_channel *, struct ata_xfer *); 156 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 157 158 int siisata_bio_start(struct ata_channel *, struct ata_xfer *); 159 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 160 void siisata_bio_poll(struct ata_channel *, struct ata_xfer *); 161 void siisata_bio_abort(struct ata_channel *, struct ata_xfer *); 162 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 163 void siisata_exec_command(struct ata_drive_datas *, struct ata_xfer *); 164 165 static int siisata_reinit_port(struct ata_channel *, int); 166 static void siisata_device_reset(struct ata_channel *); 167 static void siisata_activate_prb(struct siisata_channel *, int); 168 static void siisata_deactivate_prb(struct siisata_channel *, int); 169 static int siisata_dma_setup(struct ata_channel *, int, void *, size_t, int); 170 static void siisata_channel_recover(struct ata_channel *, int, uint32_t); 171 172 #if NATAPIBUS > 0 173 void siisata_atapibus_attach(struct atabus_softc *); 174 void siisata_atapi_probe_device(struct atapibus_softc *, int); 175 void siisata_atapi_minphys(struct buf *); 176 int siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 177 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 178 void siisata_atapi_poll(struct ata_channel *, struct ata_xfer *); 179 void siisata_atapi_abort(struct ata_channel *, struct ata_xfer *); 180 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 181 void siisata_atapi_scsipi_request(struct scsipi_channel *, 182 scsipi_adapter_req_t, void *); 183 void siisata_atapi_kill_pending(struct scsipi_periph *); 184 #endif /* NATAPIBUS */ 185 186 const struct ata_bustype siisata_ata_bustype = { 187 SCSIPI_BUSTYPE_ATA, 188 siisata_ata_bio, 189 siisata_reset_drive, 190 siisata_reset_channel, 191 siisata_exec_command, 192 ata_get_params, 193 siisata_ata_addref, 194 siisata_ata_delref, 195 siisata_killpending, 196 siisata_channel_recover, 197 }; 198 199 #if NATAPIBUS > 0 200 static const struct scsipi_bustype siisata_atapi_bustype = { 201 .bustype_type = SCSIPI_BUSTYPE_ATAPI, 202 .bustype_cmd = atapi_scsipi_cmd, 203 .bustype_interpret_sense = atapi_interpret_sense, 204 .bustype_printaddr = atapi_print_addr, 205 .bustype_kill_pending = siisata_atapi_kill_pending, 206 .bustype_async_event_xfer_mode = NULL, 207 }; 208 #endif /* NATAPIBUS */ 209 210 211 void 212 siisata_attach(struct siisata_softc *sc) 213 { 214 int i; 215 216 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 217 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 218 219 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA | ATAC_CAP_NCQ; 220 sc->sc_atac.atac_pio_cap = 4; 221 sc->sc_atac.atac_dma_cap = 2; 222 sc->sc_atac.atac_udma_cap = 6; 223 sc->sc_atac.atac_channels = sc->sc_chanarray; 224 sc->sc_atac.atac_probe = siisata_probe_drive; 225 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 226 sc->sc_atac.atac_set_modes = siisata_setup_channel; 227 #if NATAPIBUS > 0 228 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 229 #endif 230 231 /* come out of reset state */ 232 GRWRITE(sc, GR_GC, 0); 233 234 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 235 siisata_attach_port(sc, i); 236 } 237 238 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", SIISATANAME(sc), 239 __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 240 return; 241 } 242 243 static void 244 siisata_disable_port_interrupt(struct ata_channel *chp) 245 { 246 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 247 248 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIEC), 0xffffffff); 249 } 250 251 static void 252 siisata_enable_port_interrupt(struct ata_channel *chp) 253 { 254 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 255 256 /* clear any interrupts */ 257 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 258 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 259 /* and enable CmdErrr+CmdCmpl interrupting */ 260 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 261 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 262 } 263 264 static int 265 siisata_init_port(struct siisata_softc *sc, int port) 266 { 267 struct siisata_channel *schp; 268 struct ata_channel *chp; 269 int error; 270 271 schp = &sc->sc_channels[port]; 272 chp = (struct ata_channel *)schp; 273 274 /* 275 * Come out of reset. Disable no clearing of PR_PIS_CMDCMPL on read 276 * of PR_PSS. Disable 32-bit PRB activation, we use 64-bit activation. 277 */ 278 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 279 PR_PC_32BA | PR_PC_INCOR | PR_PC_PORT_RESET); 280 /* initialize port */ 281 error = siisata_reinit_port(chp, -1); 282 /* enable CmdErrr+CmdCmpl interrupting */ 283 siisata_enable_port_interrupt(chp); 284 /* enable port interrupt */ 285 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 286 287 return error; 288 } 289 290 static void 291 siisata_attach_port(struct siisata_softc *sc, int port) 292 { 293 int j; 294 int dmasize; 295 int error; 296 void *prbp; 297 struct siisata_channel *schp; 298 struct ata_channel *chp; 299 300 schp = &sc->sc_channels[port]; 301 chp = (struct ata_channel *)schp; 302 sc->sc_chanarray[port] = chp; 303 chp->ch_channel = port; 304 chp->ch_atac = &sc->sc_atac; 305 chp->ch_queue = ata_queue_alloc(SIISATA_MAX_SLOTS); 306 if (chp->ch_queue == NULL) { 307 aprint_error_dev(sc->sc_atac.atac_dev, 308 "port %d: can't allocate memory " 309 "for command queue\n", chp->ch_channel); 310 return; 311 } 312 313 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 314 315 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 316 __func__, dmasize), DEBUG_FUNCS); 317 318 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 319 &schp->sch_prb_seg, 1, &schp->sch_prb_nseg, BUS_DMA_NOWAIT); 320 if (error) { 321 aprint_error_dev(sc->sc_atac.atac_dev, 322 "unable to allocate PRB table memory, " 323 "error=%d\n", error); 324 return; 325 } 326 327 error = bus_dmamem_map(sc->sc_dmat, 328 &schp->sch_prb_seg, schp->sch_prb_nseg, 329 dmasize, &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 330 if (error) { 331 aprint_error_dev(sc->sc_atac.atac_dev, 332 "unable to map PRB table memory, " 333 "error=%d\n", error); 334 bus_dmamem_free(sc->sc_dmat, 335 &schp->sch_prb_seg, schp->sch_prb_nseg); 336 return; 337 } 338 339 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 340 BUS_DMA_NOWAIT, &schp->sch_prbd); 341 if (error) { 342 aprint_error_dev(sc->sc_atac.atac_dev, 343 "unable to create PRB table map, " 344 "error=%d\n", error); 345 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 346 bus_dmamem_free(sc->sc_dmat, 347 &schp->sch_prb_seg, schp->sch_prb_nseg); 348 return; 349 } 350 351 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 352 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 353 if (error) { 354 aprint_error_dev(sc->sc_atac.atac_dev, 355 "unable to load PRB table map, " 356 "error=%d\n", error); 357 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 358 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 359 bus_dmamem_free(sc->sc_dmat, 360 &schp->sch_prb_seg, schp->sch_prb_nseg); 361 return; 362 } 363 364 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 365 schp->sch_prb[j] = (struct siisata_prb *) 366 ((char *)prbp + SIISATA_CMD_SIZE * j); 367 schp->sch_bus_prb[j] = 368 schp->sch_prbd->dm_segs[0].ds_addr + 369 SIISATA_CMD_SIZE * j; 370 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 371 SIISATA_NSGE, MAXPHYS, 0, 372 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 373 &schp->sch_datad[j]); 374 if (error) { 375 aprint_error_dev(sc->sc_atac.atac_dev, 376 "couldn't create xfer DMA map, error=%d\n", 377 error); 378 return; 379 } 380 } 381 382 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 383 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 384 aprint_error_dev(sc->sc_atac.atac_dev, 385 "couldn't map port %d SStatus regs\n", 386 chp->ch_channel); 387 return; 388 } 389 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 390 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 391 aprint_error_dev(sc->sc_atac.atac_dev, 392 "couldn't map port %d SControl regs\n", 393 chp->ch_channel); 394 return; 395 } 396 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 397 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 398 aprint_error_dev(sc->sc_atac.atac_dev, 399 "couldn't map port %d SError regs\n", 400 chp->ch_channel); 401 return; 402 } 403 404 (void)siisata_init_port(sc, port); 405 406 ata_channel_attach(chp); 407 408 return; 409 } 410 411 void 412 siisata_childdetached(struct siisata_softc *sc, device_t child) 413 { 414 struct ata_channel *chp; 415 416 for (int i = 0; i < sc->sc_atac.atac_nchannels; i++) { 417 chp = sc->sc_chanarray[i]; 418 419 if (child == chp->atabus) 420 chp->atabus = NULL; 421 } 422 } 423 424 int 425 siisata_detach(struct siisata_softc *sc, int flags) 426 { 427 struct atac_softc *atac = &sc->sc_atac; 428 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 429 struct siisata_channel *schp; 430 struct ata_channel *chp; 431 int i, j, error; 432 433 if (adapt->adapt_refcnt != 0) 434 return EBUSY; 435 436 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 437 schp = &sc->sc_channels[i]; 438 chp = sc->sc_chanarray[i]; 439 440 if (chp->atabus != NULL) { 441 if ((error = config_detach(chp->atabus, flags)) != 0) 442 return error; 443 444 KASSERT(chp->atabus == NULL); 445 } 446 447 if (chp->ch_flags & ATACH_DETACHED) 448 continue; 449 450 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 451 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 452 453 bus_dmamap_unload(sc->sc_dmat, schp->sch_prbd); 454 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 455 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 456 SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS); 457 bus_dmamem_free(sc->sc_dmat, 458 &schp->sch_prb_seg, schp->sch_prb_nseg); 459 460 ata_channel_detach(chp); 461 } 462 463 /* leave the chip in reset */ 464 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 465 466 return 0; 467 } 468 469 void 470 siisata_resume(struct siisata_softc *sc) 471 { 472 /* come out of reset state */ 473 GRWRITE(sc, GR_GC, 0); 474 475 for (int port = 0; port < sc->sc_atac.atac_nchannels; port++) { 476 int error; 477 478 error = siisata_init_port(sc, port); 479 if (error) { 480 struct siisata_channel *schp = &sc->sc_channels[port]; 481 struct ata_channel *chp = (struct ata_channel *)schp; 482 483 ata_channel_lock(chp); 484 siisata_reset_channel(chp, AT_POLL); 485 ata_channel_unlock(chp); 486 } 487 } 488 } 489 490 int 491 siisata_intr(void *v) 492 { 493 struct siisata_softc *sc = v; 494 uint32_t is; 495 int i, r = 0; 496 while ((is = GRREAD(sc, GR_GIS))) { 497 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 498 SIISATANAME(sc), __func__, is), DEBUG_INTR); 499 r = 1; 500 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 501 if (is & GR_GIS_PXIS(i)) 502 siisata_intr_port(&sc->sc_channels[i]); 503 } 504 return r; 505 } 506 507 static void 508 siisata_intr_port(struct siisata_channel *schp) 509 { 510 struct siisata_softc *sc = 511 (struct siisata_softc *)schp->ata_channel.ch_atac; 512 struct ata_channel *chp = &schp->ata_channel; 513 struct ata_xfer *xfer = NULL; 514 uint32_t pss, pis, tfd = 0; 515 bool recover = false; 516 517 /* get slot status, clearing completion interrupt */ 518 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 519 520 SIISATA_DEBUG_PRINT(("%s: %s port %d, pss 0x%x ", 521 SIISATANAME(sc), __func__, chp->ch_channel, pss), 522 DEBUG_INTR); 523 524 if (__predict_true((pss & PR_PSS_ATTENTION) == 0)) { 525 SIISATA_DEBUG_PRINT(("no attention"), DEBUG_INTR); 526 goto process; 527 } 528 529 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 530 531 SIISATA_DEBUG_PRINT(("pis 0x%x\n", pss), DEBUG_INTR); 532 533 if (pis & PR_PIS_CMDERRR) { 534 uint32_t ec; 535 536 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 537 SIISATA_DEBUG_PRINT(("ec %d\n", ec), DEBUG_INTR); 538 539 /* emulate a CRC error by default */ 540 tfd = ATACH_ERR_ST(WDCE_CRC, WDCS_ERR); 541 542 if (ec <= PR_PCE_DATAFISERROR) { 543 if (ec == PR_PCE_DEVICEERROR && 544 (chp->ch_flags & ATACH_NCQ) == 0 && 545 (xfer = ata_queue_get_active_xfer(chp)) != NULL) { 546 /* read in specific information about error */ 547 uint32_t prbfis = bus_space_read_stream_4( 548 sc->sc_prt, sc->sc_prh, 549 PRSX(chp->ch_channel, xfer->c_slot, 550 PRSO_FIS)); 551 552 /* get status and error */ 553 int ntfd = satafis_rdh_parse(chp, 554 (uint8_t *)&prbfis); 555 556 if (ATACH_ST(ntfd) & WDCS_ERR) 557 tfd = ntfd; 558 } 559 560 /* 561 * We don't expect the recovery to trigger error, 562 * but handle this just in case. 563 */ 564 if (!ISSET(chp->ch_flags, ATACH_RECOVERING)) 565 recover = true; 566 else { 567 aprint_error_dev(sc->sc_atac.atac_dev, 568 "error ec %x while recovering\n", ec); 569 570 /* Command will be marked as errored out */ 571 pss = 0; 572 } 573 } else { 574 aprint_error_dev(sc->sc_atac.atac_dev, "fatal error %d" 575 " on port %d (ctx 0x%x), resetting\n", 576 ec, chp->ch_channel, 577 PRREAD(sc, PRX(chp->ch_channel, PRO_PCR))); 578 579 /* okay, we have a "Fatal Error" */ 580 ata_channel_lock(chp); 581 siisata_device_reset(chp); 582 ata_channel_unlock(chp); 583 } 584 } 585 586 /* clear some (ok, all) ints */ 587 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 588 589 if (__predict_false(recover)) 590 ata_channel_freeze(chp); 591 592 process: 593 if (xfer != NULL) { 594 xfer->ops->c_intr(chp, xfer, tfd); 595 } else { 596 /* 597 * For NCQ, HBA halts processing when error is notified, 598 * and any further D2H FISes are ignored until the error 599 * condition is cleared. Hence if a command is inactive, 600 * it means it actually already finished successfully. 601 * Note: active slots can change as c_intr() callback 602 * can activate another command(s), so must only process 603 * commands active before we start processing. 604 */ 605 uint32_t aslots = ata_queue_active(chp); 606 607 for (int slot=0; slot < SIISATA_MAX_SLOTS; slot++) { 608 if ((aslots & __BIT(slot)) != 0 && 609 (pss & PR_PXSS(slot)) == 0) { 610 xfer = ata_queue_hwslot_to_xfer(chp, slot); 611 xfer->ops->c_intr(chp, xfer, 0); 612 } 613 } 614 } 615 616 if (__predict_false(recover)) { 617 ata_channel_lock(chp); 618 ata_channel_thaw_locked(chp); 619 ata_thread_run(chp, 0, ATACH_TH_RECOVERY, tfd); 620 ata_channel_unlock(chp); 621 } 622 } 623 624 /* Recover channel after transfer aborted */ 625 void 626 siisata_channel_recover(struct ata_channel *chp, int flags, uint32_t tfd) 627 { 628 struct siisata_channel *schp = (struct siisata_channel *)chp; 629 struct siisata_softc *sc = 630 (struct siisata_softc *)schp->ata_channel.ch_atac; 631 int drive; 632 633 ata_channel_lock_owned(chp); 634 635 if (chp->ch_ndrives > PMP_PORT_CTL) { 636 /* Get PM port number for the device in error */ 637 int pcr = PRREAD(sc, PRX(chp->ch_channel, PRO_PCR)); 638 drive = PRO_PCR_PMP(pcr); 639 } else 640 drive = 0; 641 642 /* 643 * If BSY or DRQ bits are set, must execute COMRESET to return 644 * device to idle state. Otherwise, commands can be reissued 645 * after reinitalization of port. After that, need to execute 646 * READ LOG EXT for NCQ to unblock device processing if COMRESET 647 * was not done. 648 */ 649 if ((ATACH_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) { 650 siisata_device_reset(chp); 651 goto out; 652 } 653 654 KASSERT(drive >= 0); 655 (void)siisata_reinit_port(chp, drive); 656 657 ata_recovery_resume(chp, drive, tfd, flags); 658 659 out: 660 /* Drive unblocked, back to normal operation */ 661 return; 662 } 663 664 void 665 siisata_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 666 { 667 struct ata_channel *chp = drvp->chnl_softc; 668 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 669 struct siisata_channel *schp = (struct siisata_channel *)chp; 670 struct siisata_prb *prb; 671 uint8_t c_slot; 672 uint32_t pss, pis; 673 int i; 674 bool timed_out; 675 676 ata_channel_lock_owned(chp); 677 678 if (siisata_reinit_port(chp, drvp->drive)) 679 siisata_reset_channel(chp, flags); 680 681 /* get a slot for running the command on */ 682 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 683 panic("%s: %s: failed to get xfer for reset, port %d\n", 684 device_xname(sc->sc_atac.atac_dev), 685 __func__, chp->ch_channel); 686 /* NOTREACHED */ 687 } 688 689 prb = schp->sch_prb[c_slot]; 690 memset(prb, 0, SIISATA_CMD_SIZE); 691 prb->prb_control = 692 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 693 KASSERT(drvp->drive <= PMP_PORT_CTL); 694 prb->prb_fis[rhd_c] = drvp->drive; 695 696 siisata_disable_port_interrupt(chp); 697 698 siisata_activate_prb(schp, c_slot); 699 700 timed_out = true; 701 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 702 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 703 if ((pss & PR_PXSS(c_slot)) == 0) { 704 timed_out = false; 705 break; 706 } 707 if (pss & PR_PSS_ATTENTION) 708 break; 709 ata_delay(chp, 10, "siiprb", flags); 710 } 711 712 siisata_deactivate_prb(schp, c_slot); 713 714 if ((pss & PR_PSS_ATTENTION) != 0) { 715 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 716 const uint32_t ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 717 const u_int slot = PR_PS_ACTIVE_SLOT(ps); 718 719 if (slot != c_slot) 720 device_printf(sc->sc_atac.atac_dev, "%s port %d " 721 "drive %d slot %d c_slot %d", __func__, 722 chp->ch_channel, drvp->drive, slot, c_slot); 723 724 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), pis & 725 PR_PIS_CMDERRR); 726 } 727 728 siisata_enable_port_interrupt(chp); 729 730 if (timed_out) { 731 /* timeout */ 732 siisata_device_reset(chp); /* XXX is this right? */ 733 if (sigp) 734 *sigp = 0xffffffff; 735 } else { 736 /* read the signature out of the FIS */ 737 if (sigp) { 738 *sigp = 0; 739 *sigp |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 740 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 741 *sigp |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 742 PRSO_FIS+0xc)) & 0xff; 743 } 744 } 745 746 ata_queue_free_slot(chp, c_slot); 747 } 748 749 void 750 siisata_reset_channel(struct ata_channel *chp, int flags) 751 { 752 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 753 struct siisata_channel *schp = (struct siisata_channel *)chp; 754 755 SIISATA_DEBUG_PRINT(("%s: %s port %d\n", SIISATANAME(sc), __func__, 756 chp->ch_channel), DEBUG_FUNCS); 757 758 ata_channel_lock_owned(chp); 759 760 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 761 schp->sch_sstatus, flags) != SStatus_DET_DEV) { 762 aprint_error("%s port %d: reset failed\n", 763 SIISATANAME(sc), chp->ch_channel); 764 /* XXX and then ? */ 765 } 766 767 siisata_device_reset(chp); 768 769 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 770 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 771 772 return; 773 } 774 775 int 776 siisata_ata_addref(struct ata_drive_datas *drvp) 777 { 778 return 0; 779 } 780 781 void 782 siisata_ata_delref(struct ata_drive_datas *drvp) 783 { 784 return; 785 } 786 787 void 788 siisata_killpending(struct ata_drive_datas *drvp) 789 { 790 return; 791 } 792 793 void 794 siisata_probe_drive(struct ata_channel *chp) 795 { 796 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 797 struct siisata_channel *schp = (struct siisata_channel *)chp; 798 int i; 799 uint32_t sig; 800 struct siisata_prb *prb; 801 bool timed_out; 802 uint8_t c_slot; 803 804 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 805 __func__, chp->ch_channel), DEBUG_FUNCS); 806 807 ata_channel_lock(chp); 808 809 /* get a slot for running the command on */ 810 if (!ata_queue_alloc_slot(chp, &c_slot, ATA_MAX_OPENINGS)) { 811 aprint_error_dev(sc->sc_atac.atac_dev, 812 "%s: failed to get xfer port %d\n", 813 __func__, chp->ch_channel); 814 ata_channel_unlock(chp); 815 return; 816 } 817 818 /* 819 * disable port interrupt as we're polling for PHY up and 820 * prb completion 821 */ 822 siisata_disable_port_interrupt(chp); 823 824 switch(sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 825 schp->sch_sstatus, AT_WAIT)) { 826 case SStatus_DET_DEV: 827 /* clear any interrupts */ 828 (void)PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 829 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 830 831 /* wait for ready */ 832 timed_out = 1; 833 for (i = 0; i < ATA_DELAY / 10; i++) { 834 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & 835 PR_PS_PORT_READY) { 836 timed_out = 0; 837 break; 838 } 839 840 ata_delay(chp, 10, "siiprbrd", AT_WAIT); 841 } 842 if (timed_out) { 843 aprint_error_dev(sc->sc_atac.atac_dev, 844 "timed out waiting for PORT_READY on port %d, " 845 "reinitializing\n", chp->ch_channel); 846 if (siisata_reinit_port(chp, -1)) 847 siisata_reset_channel(chp, AT_WAIT); 848 } 849 850 prb = schp->sch_prb[c_slot]; 851 memset(prb, 0, SIISATA_CMD_SIZE); 852 prb->prb_control = htole16(PRB_CF_SOFT_RESET); 853 prb->prb_fis[rhd_c] = PMP_PORT_CTL; 854 855 siisata_activate_prb(schp, c_slot); 856 857 timed_out = 1; 858 for(i = 0; i < WDC_RESET_WAIT / 10; i++) { 859 if ((PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 860 PR_PXSS(c_slot)) == 0) { 861 /* prb completed */ 862 timed_out = 0; 863 break; 864 } 865 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)) & 866 PR_PIS_CMDERRR) { 867 /* we got an error; handle as timeout */ 868 break; 869 } 870 871 ata_delay(chp, 10, "siiprb", AT_WAIT); 872 } 873 874 siisata_deactivate_prb(schp, c_slot); 875 876 if (timed_out) { 877 aprint_error_dev(sc->sc_atac.atac_dev, 878 "SOFT_RESET failed on port %d (error %d PSS 0x%x PIS 0x%x), " 879 "resetting\n", chp->ch_channel, 880 PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)), 881 PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)), 882 PRREAD(sc, PRX(chp->ch_channel, PRO_PIS))); 883 if (siisata_reinit_port(chp, -1)) 884 siisata_reset_channel(chp, AT_WAIT); 885 break; 886 } 887 888 /* read the signature out of the FIS */ 889 sig = 0; 890 sig |= (PRREAD(sc, PRSX(chp->ch_channel, c_slot, 891 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 892 sig |= PRREAD(sc, PRSX(chp->ch_channel, c_slot, 893 PRSO_FIS+0xc)) & 0xff; 894 895 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 896 __func__, sig), DEBUG_PROBE); 897 898 if (sig == 0x96690101) 899 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), 900 PR_PC_PMP_ENABLE); 901 sata_interpret_sig(chp, 0, sig); 902 break; 903 default: 904 break; 905 } 906 907 siisata_enable_port_interrupt(chp); 908 909 ata_queue_free_slot(chp, c_slot); 910 911 ata_channel_unlock(chp); 912 913 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 914 __func__, chp->ch_channel), DEBUG_PROBE); 915 return; 916 } 917 918 void 919 siisata_setup_channel(struct ata_channel *chp) 920 { 921 return; 922 } 923 924 static const struct ata_xfer_ops siisata_cmd_xfer_ops = { 925 .c_start = siisata_cmd_start, 926 .c_intr = siisata_cmd_complete, 927 .c_poll = siisata_cmd_poll, 928 .c_abort = siisata_cmd_abort, 929 .c_kill_xfer = siisata_cmd_kill_xfer, 930 }; 931 932 void 933 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 934 { 935 struct ata_channel *chp = drvp->chnl_softc; 936 struct ata_command *ata_c = &xfer->c_ata_c; 937 938 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 939 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 940 DEBUG_FUNCS); 941 942 if (ata_c->flags & AT_POLL) 943 xfer->c_flags |= C_POLL; 944 if (ata_c->flags & AT_WAIT) 945 xfer->c_flags |= C_WAIT; 946 xfer->c_drive = drvp->drive; 947 xfer->c_databuf = ata_c->data; 948 xfer->c_bcount = ata_c->bcount; 949 xfer->ops = &siisata_cmd_xfer_ops; 950 951 ata_exec_xfer(chp, xfer); 952 953 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 954 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 955 DEBUG_FUNCS); 956 } 957 958 int 959 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 960 { 961 struct siisata_channel *schp = (struct siisata_channel *)chp; 962 struct ata_command *ata_c = &xfer->c_ata_c; 963 struct siisata_prb *prb; 964 965 SIISATA_DEBUG_PRINT(("%s: %s port %d drive %d command 0x%x, slot %d\n", 966 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 967 chp->ch_channel, xfer->c_drive, ata_c->r_command, xfer->c_slot), 968 DEBUG_FUNCS|DEBUG_XFERS); 969 970 ata_channel_lock_owned(chp); 971 972 prb = schp->sch_prb[xfer->c_slot]; 973 memset(prb, 0, SIISATA_CMD_SIZE); 974 975 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 976 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 977 prb->prb_fis[rhd_c] |= xfer->c_drive; 978 979 if (ata_c->r_command == ATA_DATA_SET_MANAGEMENT) { 980 prb->prb_control |= htole16(PRB_CF_PROTOCOL_OVERRIDE); 981 prb->prb_protocol_override |= htole16(PRB_PO_WRITE); 982 } 983 984 if (siisata_dma_setup(chp, xfer->c_slot, 985 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 986 ata_c->bcount, 987 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 988 ata_c->flags |= AT_DF; 989 return ATASTART_ABORT; 990 } 991 992 if (xfer->c_flags & C_POLL) { 993 /* polled command, disable interrupts */ 994 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 995 siisata_disable_port_interrupt(chp); 996 } 997 998 /* go for it */ 999 siisata_activate_prb(schp, xfer->c_slot); 1000 1001 if ((ata_c->flags & AT_POLL) == 0) { 1002 callout_reset(&chp->c_timo_callout, mstohz(ata_c->timeout), 1003 ata_timeout, chp); 1004 return ATASTART_STARTED; 1005 } else 1006 return ATASTART_POLL; 1007 } 1008 1009 void 1010 siisata_cmd_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1011 { 1012 struct siisata_channel *schp = (struct siisata_channel *)chp; 1013 1014 /* 1015 * polled command 1016 */ 1017 for (int i = 0; i < xfer->c_ata_c.timeout * 10; i++) { 1018 if (xfer->c_ata_c.flags & AT_DONE) 1019 break; 1020 siisata_intr_port(schp); 1021 DELAY(100); 1022 } 1023 1024 if ((xfer->c_ata_c.flags & AT_DONE) == 0) { 1025 ata_timeout(xfer); 1026 } 1027 1028 /* reenable interrupts */ 1029 siisata_enable_port_interrupt(chp); 1030 1031 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1032 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1033 DEBUG_FUNCS); 1034 } 1035 1036 void 1037 siisata_cmd_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1038 { 1039 siisata_cmd_complete(chp, xfer, 0); 1040 } 1041 1042 void 1043 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1044 int reason) 1045 { 1046 struct ata_command *ata_c = &xfer->c_ata_c; 1047 struct siisata_channel *schp = (struct siisata_channel *)chp; 1048 bool deactivate = true; 1049 1050 switch (reason) { 1051 case KILL_GONE_INACTIVE: 1052 deactivate = false; 1053 /* FALLTHROUGH */ 1054 case KILL_GONE: 1055 ata_c->flags |= AT_GONE; 1056 break; 1057 case KILL_RESET: 1058 ata_c->flags |= AT_RESET; 1059 break; 1060 case KILL_REQUEUE: 1061 panic("%s: not supposed to be requeued\n", __func__); 1062 break; 1063 default: 1064 panic("%s: port %d: unknown reason %d", 1065 __func__, chp->ch_channel, reason); 1066 } 1067 1068 siisata_cmd_done_end(chp, xfer); 1069 1070 if (deactivate) { 1071 siisata_deactivate_prb(schp, xfer->c_slot); 1072 ata_deactivate_xfer(chp, xfer); 1073 } 1074 } 1075 1076 int 1077 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1078 { 1079 struct siisata_channel *schp = (struct siisata_channel *)chp; 1080 struct ata_command *ata_c = &xfer->c_ata_c; 1081 #ifdef SIISATA_DEBUG 1082 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1083 #endif 1084 1085 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1086 SIISATANAME(sc), __func__, 1087 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1088 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 1089 DEBUG_FUNCS|DEBUG_XFERS); 1090 1091 if (ata_waitdrain_xfer_check(chp, xfer)) 1092 return 0; 1093 1094 if (xfer->c_flags & C_TIMEOU) 1095 ata_c->flags |= AT_TIMEOU; 1096 1097 if (ATACH_ST(tfd) & WDCS_BSY) { 1098 ata_c->flags |= AT_TIMEOU; 1099 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1100 ata_c->r_error = ATACH_ERR(tfd); 1101 ata_c->flags |= AT_ERROR; 1102 } 1103 1104 siisata_cmd_done(chp, xfer, tfd); 1105 1106 siisata_deactivate_prb(schp, xfer->c_slot); 1107 ata_deactivate_xfer(chp, xfer); 1108 1109 if ((ata_c->flags & (AT_TIMEOU|AT_ERROR)) == 0) 1110 atastart(chp); 1111 1112 return 0; 1113 } 1114 1115 void 1116 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1117 { 1118 uint32_t fis[howmany(RDH_FISLEN,sizeof(uint32_t))]; 1119 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1120 struct siisata_channel *schp = (struct siisata_channel *)chp; 1121 struct ata_command *ata_c = &xfer->c_ata_c; 1122 uint16_t *idwordbuf; 1123 int i; 1124 1125 SIISATA_DEBUG_PRINT(("%s: %s flags 0x%x error 0x%x\n", SIISATANAME(sc), 1126 __func__, ata_c->flags, ata_c->r_error), DEBUG_FUNCS|DEBUG_XFERS); 1127 1128 if (ata_c->flags & (AT_READ | AT_WRITE)) { 1129 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1130 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1131 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 1132 BUS_DMASYNC_POSTWRITE); 1133 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1134 } 1135 1136 if (ata_c->flags & AT_READREG) { 1137 bus_space_read_region_stream_4(sc->sc_prt, sc->sc_prh, 1138 PRSX(chp->ch_channel, xfer->c_slot, PRSO_FIS), 1139 fis, __arraycount(fis)); 1140 satafis_rdh_cmd_readreg(ata_c, (uint8_t *)fis); 1141 } 1142 1143 /* correct the endianess of IDENTIFY data */ 1144 if (ata_c->r_command == WDCC_IDENTIFY || 1145 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1146 idwordbuf = xfer->c_databuf; 1147 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 1148 idwordbuf[i] = le16toh(idwordbuf[i]); 1149 } 1150 } 1151 1152 if (PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC))) 1153 ata_c->flags |= AT_XFDONE; 1154 1155 siisata_cmd_done_end(chp, xfer); 1156 } 1157 1158 static void 1159 siisata_cmd_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1160 { 1161 struct ata_command *ata_c = &xfer->c_ata_c; 1162 1163 ata_c->flags |= AT_DONE; 1164 } 1165 1166 static const struct ata_xfer_ops siisata_bio_xfer_ops = { 1167 .c_start = siisata_bio_start, 1168 .c_intr = siisata_bio_complete, 1169 .c_poll = siisata_bio_poll, 1170 .c_abort = siisata_bio_abort, 1171 .c_kill_xfer = siisata_bio_kill_xfer, 1172 }; 1173 1174 void 1175 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1176 { 1177 struct ata_channel *chp = drvp->chnl_softc; 1178 struct ata_bio *ata_bio = &xfer->c_bio; 1179 1180 SIISATA_DEBUG_PRINT(("%s: %s.\n", 1181 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1182 DEBUG_FUNCS); 1183 1184 if (ata_bio->flags & ATA_POLL) 1185 xfer->c_flags |= C_POLL; 1186 xfer->c_drive = drvp->drive; 1187 xfer->c_databuf = ata_bio->databuf; 1188 xfer->c_bcount = ata_bio->bcount; 1189 xfer->ops = &siisata_bio_xfer_ops; 1190 ata_exec_xfer(chp, xfer); 1191 } 1192 1193 int 1194 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 1195 { 1196 struct siisata_channel *schp = (struct siisata_channel *)chp; 1197 struct siisata_prb *prb; 1198 struct ata_bio *ata_bio = &xfer->c_bio; 1199 1200 SIISATA_DEBUG_PRINT(("%s: %s port %d slot %d drive %d\n", 1201 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1202 chp->ch_channel, xfer->c_slot, xfer->c_drive), DEBUG_FUNCS); 1203 1204 ata_channel_lock_owned(chp); 1205 1206 prb = schp->sch_prb[xfer->c_slot]; 1207 memset(prb, 0, SIISATA_CMD_SIZE); 1208 1209 satafis_rhd_construct_bio(xfer, prb->prb_fis); 1210 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1211 prb->prb_fis[rhd_c] |= xfer->c_drive; 1212 1213 if (siisata_dma_setup(chp, xfer->c_slot, ata_bio->databuf, ata_bio->bcount, 1214 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 1215 ata_bio->error = ERR_DMA; 1216 ata_bio->r_error = 0; 1217 return ATASTART_ABORT; 1218 } 1219 1220 if (xfer->c_flags & C_POLL) { 1221 /* polled command, disable interrupts */ 1222 prb->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1223 siisata_disable_port_interrupt(chp); 1224 } 1225 1226 siisata_activate_prb(schp, xfer->c_slot); 1227 1228 if ((ata_bio->flags & ATA_POLL) == 0) { 1229 callout_reset(&chp->c_timo_callout, mstohz(ATA_DELAY), 1230 ata_timeout, chp); 1231 return ATASTART_STARTED; 1232 } else 1233 return ATASTART_POLL; 1234 } 1235 1236 void 1237 siisata_bio_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1238 { 1239 struct siisata_channel *schp = (struct siisata_channel *)chp; 1240 1241 /* 1242 * polled command 1243 */ 1244 for (int i = 0; i < ATA_DELAY * 10; i++) { 1245 if (xfer->c_bio.flags & ATA_ITSDONE) 1246 break; 1247 siisata_intr_port(schp); 1248 DELAY(100); 1249 } 1250 1251 if ((xfer->c_bio.flags & ATA_ITSDONE) == 0) { 1252 ata_timeout(xfer); 1253 } 1254 1255 siisata_enable_port_interrupt(chp); 1256 1257 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1258 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1259 DEBUG_FUNCS); 1260 } 1261 1262 void 1263 siisata_bio_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1264 { 1265 siisata_cmd_complete(chp, xfer, 0); 1266 } 1267 1268 void 1269 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1270 int reason) 1271 { 1272 struct siisata_channel *schp = (struct siisata_channel *)chp; 1273 struct ata_bio *ata_bio = &xfer->c_bio; 1274 int drive = xfer->c_drive; 1275 bool deactivate = true; 1276 1277 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d\n", 1278 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1279 chp->ch_channel, xfer->c_slot), DEBUG_FUNCS); 1280 1281 ata_bio->flags |= ATA_ITSDONE; 1282 switch (reason) { 1283 case KILL_GONE_INACTIVE: 1284 deactivate = false; 1285 /* FALLTHROUGH */ 1286 case KILL_GONE: 1287 ata_bio->error = ERR_NODEV; 1288 break; 1289 case KILL_RESET: 1290 ata_bio->error = ERR_RESET; 1291 break; 1292 case KILL_REQUEUE: 1293 ata_bio->error = REQUEUE; 1294 break; 1295 default: 1296 panic("%s: port %d: unknown reason %d", 1297 __func__, chp->ch_channel, reason); 1298 } 1299 ata_bio->r_error = WDCE_ABRT; 1300 1301 if (deactivate) { 1302 siisata_deactivate_prb(schp, xfer->c_slot); 1303 ata_deactivate_xfer(chp, xfer); 1304 } 1305 1306 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1307 } 1308 1309 int 1310 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int tfd) 1311 { 1312 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1313 struct siisata_channel *schp = (struct siisata_channel *)chp; 1314 struct ata_bio *ata_bio = &xfer->c_bio; 1315 int drive = xfer->c_drive; 1316 1317 SIISATA_DEBUG_PRINT(("%s: %s: port %d slot %d drive %d tfd %x\n", 1318 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__, 1319 chp->ch_channel, xfer->c_slot, xfer->c_drive, tfd), DEBUG_FUNCS); 1320 1321 if (ata_waitdrain_xfer_check(chp, xfer)) 1322 return 0; 1323 1324 if (xfer->c_flags & C_TIMEOU) { 1325 ata_bio->error = TIMEOUT; 1326 } 1327 1328 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1329 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1330 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1331 BUS_DMASYNC_POSTWRITE); 1332 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1333 1334 ata_bio->flags |= ATA_ITSDONE; 1335 if (ATACH_ST(tfd) & WDCS_DWF) { 1336 ata_bio->error = ERR_DF; 1337 } else if (ATACH_ST(tfd) & WDCS_ERR) { 1338 ata_bio->error = ERROR; 1339 ata_bio->r_error = ATACH_ERR(tfd); 1340 } else if (ATACH_ST(tfd) & WDCS_CORR) 1341 ata_bio->flags |= ATA_CORR; 1342 1343 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), __func__, 1344 ata_bio->bcount), DEBUG_XFERS); 1345 if (ata_bio->error == NOERROR) { 1346 if ((xfer->c_flags & C_NCQ) != 0 && ata_bio->flags & ATA_READ) 1347 ata_bio->bcount -= 1348 PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, PRSO_RTC)); 1349 else 1350 ata_bio->bcount = 0; 1351 } 1352 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1353 1354 siisata_deactivate_prb(schp, xfer->c_slot); 1355 ata_deactivate_xfer(chp, xfer); 1356 1357 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc, xfer); 1358 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1359 atastart(chp); 1360 return 0; 1361 } 1362 1363 static int 1364 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1365 size_t count, int op) 1366 { 1367 1368 int error, seg; 1369 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1370 struct siisata_channel *schp = (struct siisata_channel *)chp; 1371 1372 struct siisata_prb *prbp; 1373 1374 prbp = schp->sch_prb[slot]; 1375 1376 if (data == NULL) { 1377 goto end; 1378 } 1379 1380 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1381 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1382 if (error) { 1383 aprint_error("%s port %d: " 1384 "failed to load xfer in slot %d: error %d\n", 1385 SIISATANAME(sc), chp->ch_channel, slot, error); 1386 return error; 1387 } 1388 1389 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1390 schp->sch_datad[slot]->dm_mapsize, 1391 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1392 1393 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1394 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1395 DEBUG_FUNCS | DEBUG_DEBUG); 1396 1397 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1398 prbp->prb_sge[seg].sge_da = 1399 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1400 prbp->prb_sge[seg].sge_dc = 1401 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1402 prbp->prb_sge[seg].sge_flags = htole32(0); 1403 } 1404 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1405 end: 1406 return 0; 1407 } 1408 1409 static void 1410 siisata_activate_prb(struct siisata_channel *schp, int slot) 1411 { 1412 struct siisata_softc *sc; 1413 bus_size_t offset; 1414 uint64_t pprb; 1415 1416 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1417 1418 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1419 1420 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1421 1422 pprb = schp->sch_bus_prb[slot]; 1423 1424 PRWRITE(sc, offset + 0, pprb >> 0); 1425 PRWRITE(sc, offset + 4, pprb >> 32); 1426 } 1427 1428 static void 1429 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1430 { 1431 struct siisata_softc *sc; 1432 1433 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1434 1435 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1436 } 1437 1438 static int 1439 siisata_reinit_port(struct ata_channel *chp, int drive) 1440 { 1441 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1442 int ps; 1443 int error = 0; 1444 1445 if (chp->ch_ndrives > 1) { 1446 /* 1447 * Proper recovery would SET this bit, which makes it 1448 * not possible to submit new commands and resume execution 1449 * on non-errored drives, then wait for those commands, 1450 * to finish, and only then clear the bit and reset the state. 1451 * For now this is okay, since we never queue commands for 1452 * more than one drive. 1453 * XXX FIS-based switching 1454 */ 1455 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), PR_PC_RESUME); 1456 1457 for (int i = 0; i < chp->ch_ndrives; i++) { 1458 if (drive >= 0 && i != drive) 1459 continue; 1460 1461 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPSTS(i)), 0); 1462 PRWRITE(sc, PRX(chp->ch_channel, PRO_PMPQACT(i)), 0); 1463 } 1464 } 1465 1466 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1467 for (int i = 0; i < ATA_DELAY * 100; i++) { 1468 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1469 if ((ps & PR_PS_PORT_READY) != 0) 1470 break; 1471 1472 DELAY(10); 1473 } 1474 if ((ps & PR_PS_PORT_READY) == 0) { 1475 printf("%s: timeout waiting for port to be ready\n", __func__); 1476 error = EBUSY; 1477 } 1478 1479 if (chp->ch_ndrives > 1) 1480 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PMP_ENABLE); 1481 1482 return error; 1483 } 1484 1485 static void 1486 siisata_device_reset(struct ata_channel *chp) 1487 { 1488 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1489 int ps; 1490 1491 ata_channel_lock_owned(chp); 1492 1493 /* 1494 * This is always called after siisata_reinit_port(), so don't 1495 * need to deal with RESUME and clearing device error state. 1496 */ 1497 1498 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1499 1500 for (int i = 0; i < ATA_DELAY * 100; i++) { 1501 ps = PRREAD(sc, PRX(chp->ch_channel, PRO_PS)); 1502 if ((ps & PR_PS_PORT_READY) != 0) 1503 break; 1504 1505 DELAY(10); 1506 } 1507 if ((ps & PR_PS_PORT_READY) == 0) { 1508 printf("%s: timeout waiting for port to be ready\n", __func__); 1509 siisata_reset_channel(chp, AT_POLL); 1510 } 1511 1512 ata_kill_active(chp, KILL_RESET, 0); 1513 } 1514 1515 1516 #if NATAPIBUS > 0 1517 void 1518 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1519 { 1520 struct ata_channel *chp = ata_sc->sc_chan; 1521 struct atac_softc *atac = chp->ch_atac; 1522 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1523 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1524 1525 /* 1526 * Fill in the scsipi_adapter. 1527 */ 1528 adapt->adapt_dev = atac->atac_dev; 1529 adapt->adapt_nchannels = atac->atac_nchannels; 1530 adapt->adapt_request = siisata_atapi_scsipi_request; 1531 adapt->adapt_minphys = siisata_atapi_minphys; 1532 atac->atac_atapi_adapter.atapi_probe_device = 1533 siisata_atapi_probe_device; 1534 1535 /* 1536 * Fill in the scsipi_channel. 1537 */ 1538 memset(chan, 0, sizeof(*chan)); 1539 chan->chan_adapter = adapt; 1540 chan->chan_bustype = &siisata_atapi_bustype; 1541 chan->chan_channel = chp->ch_channel; 1542 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1543 chan->chan_openings = 1; 1544 chan->chan_max_periph = 1; 1545 chan->chan_ntargets = 1; 1546 chan->chan_nluns = 1; 1547 1548 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1549 atapiprint); 1550 } 1551 1552 void 1553 siisata_atapi_minphys(struct buf *bp) 1554 { 1555 if (bp->b_bcount > MAXPHYS) 1556 bp->b_bcount = MAXPHYS; 1557 minphys(bp); 1558 } 1559 1560 /* 1561 * Kill off all pending xfers for a periph. 1562 * 1563 * Must be called at splbio(). 1564 */ 1565 void 1566 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1567 { 1568 struct atac_softc *atac = 1569 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1570 struct ata_channel *chp = 1571 atac->atac_channels[periph->periph_channel->chan_channel]; 1572 1573 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1574 } 1575 1576 void 1577 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1578 int reason) 1579 { 1580 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1581 struct siisata_channel *schp = (struct siisata_channel *)chp; 1582 bool deactivate = true; 1583 1584 /* remove this command from xfer queue */ 1585 switch (reason) { 1586 case KILL_GONE_INACTIVE: 1587 deactivate = false; 1588 /* FALLTHROUGH */ 1589 case KILL_GONE: 1590 sc_xfer->error = XS_DRIVER_STUFFUP; 1591 break; 1592 case KILL_RESET: 1593 sc_xfer->error = XS_RESET; 1594 break; 1595 case KILL_REQUEUE: 1596 sc_xfer->error = XS_REQUEUE; 1597 break; 1598 default: 1599 panic("%s: port %d: unknown reason %d", 1600 __func__, chp->ch_channel, reason); 1601 } 1602 1603 if (deactivate) { 1604 siisata_deactivate_prb(schp, xfer->c_slot); 1605 ata_deactivate_xfer(chp, xfer); 1606 } 1607 1608 ata_free_xfer(chp, xfer); 1609 scsipi_done(sc_xfer); 1610 } 1611 1612 void 1613 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1614 { 1615 struct scsipi_channel *chan = sc->sc_channel; 1616 struct scsipi_periph *periph; 1617 struct ataparams ids; 1618 struct ataparams *id = &ids; 1619 struct siisata_softc *siic = 1620 device_private(chan->chan_adapter->adapt_dev); 1621 struct atac_softc *atac = &siic->sc_atac; 1622 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1623 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1624 struct scsipibus_attach_args sa; 1625 char serial_number[21], model[41], firmware_revision[9]; 1626 int s; 1627 1628 /* skip if already attached */ 1629 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1630 return; 1631 1632 /* if no ATAPI device detected at attach time, skip */ 1633 if (drvp->drive_type != ATA_DRIVET_ATAPI) { 1634 SIISATA_DEBUG_PRINT(("%s: drive %d not present\n", __func__, 1635 target), DEBUG_PROBE); 1636 return; 1637 } 1638 1639 /* Some ATAPI devices need a bit more time after software reset. */ 1640 DELAY(5000); 1641 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1642 #ifdef ATAPI_DEBUG_PROBE 1643 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1644 device_xname(sc->sc_dev), target, 1645 id->atap_config & ATAPI_CFG_CMD_MASK, 1646 id->atap_config & ATAPI_CFG_DRQ_MASK); 1647 #endif 1648 periph = scsipi_alloc_periph(M_WAITOK); 1649 periph->periph_dev = NULL; 1650 periph->periph_channel = chan; 1651 periph->periph_switch = &atapi_probe_periphsw; 1652 periph->periph_target = target; 1653 periph->periph_lun = 0; 1654 periph->periph_quirks = PQUIRK_ONLYBIG; 1655 1656 #ifdef SCSIPI_DEBUG 1657 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1658 SCSIPI_DEBUG_TARGET == target) 1659 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1660 #endif 1661 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1662 if (id->atap_config & ATAPI_CFG_REMOV) 1663 periph->periph_flags |= PERIPH_REMOVABLE; 1664 sa.sa_periph = periph; 1665 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1666 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1667 T_REMOV : T_FIXED; 1668 strnvisx(model, sizeof(model), id->atap_model, 40, 1669 VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1670 strnvisx(serial_number, sizeof(serial_number), 1671 id->atap_serial, 20, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1672 strnvisx(firmware_revision, sizeof(firmware_revision), 1673 id->atap_revision, 8, VIS_TRIM|VIS_SAFE|VIS_OCTAL); 1674 sa.sa_inqbuf.vendor = model; 1675 sa.sa_inqbuf.product = serial_number; 1676 sa.sa_inqbuf.revision = firmware_revision; 1677 1678 /* 1679 * Determine the operating mode capabilities of the device. 1680 */ 1681 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1682 == ATAPI_CFG_CMD_16) { 1683 periph->periph_cap |= PERIPH_CAP_CMD16; 1684 1685 /* configure port for packet length */ 1686 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1687 PR_PC_PACKET_LENGTH); 1688 } else { 1689 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1690 PR_PC_PACKET_LENGTH); 1691 } 1692 1693 /* XXX This is gross. */ 1694 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1695 1696 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1697 1698 if (drvp->drv_softc) 1699 ata_probe_caps(drvp); 1700 else { 1701 s = splbio(); 1702 drvp->drive_type &= ATA_DRIVET_NONE; 1703 splx(s); 1704 } 1705 } else { 1706 s = splbio(); 1707 drvp->drive_type &= ATA_DRIVET_NONE; 1708 splx(s); 1709 } 1710 } 1711 1712 static const struct ata_xfer_ops siisata_atapi_xfer_ops = { 1713 .c_start = siisata_atapi_start, 1714 .c_intr = siisata_atapi_complete, 1715 .c_poll = siisata_atapi_poll, 1716 .c_abort = siisata_atapi_abort, 1717 .c_kill_xfer = siisata_atapi_kill_xfer, 1718 }; 1719 1720 void 1721 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1722 scsipi_adapter_req_t req, void *arg) 1723 { 1724 struct scsipi_adapter *adapt = chan->chan_adapter; 1725 struct scsipi_periph *periph; 1726 struct scsipi_xfer *sc_xfer; 1727 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1728 struct atac_softc *atac = &sc->sc_atac; 1729 struct ata_xfer *xfer; 1730 int channel = chan->chan_channel; 1731 int drive, s; 1732 1733 switch (req) { 1734 case ADAPTER_REQ_RUN_XFER: 1735 sc_xfer = arg; 1736 periph = sc_xfer->xs_periph; 1737 drive = periph->periph_target; 1738 1739 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1740 device_xname(atac->atac_dev), channel, drive), 1741 DEBUG_XFERS); 1742 1743 if (!device_is_active(atac->atac_dev)) { 1744 sc_xfer->error = XS_DRIVER_STUFFUP; 1745 scsipi_done(sc_xfer); 1746 return; 1747 } 1748 xfer = ata_get_xfer(atac->atac_channels[channel], false); 1749 if (xfer == NULL) { 1750 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1751 scsipi_done(sc_xfer); 1752 return; 1753 } 1754 1755 if (sc_xfer->xs_control & XS_CTL_POLL) 1756 xfer->c_flags |= C_POLL; 1757 xfer->c_drive = drive; 1758 xfer->c_flags |= C_ATAPI; 1759 xfer->c_databuf = sc_xfer->data; 1760 xfer->c_bcount = sc_xfer->datalen; 1761 xfer->ops = &siisata_atapi_xfer_ops; 1762 xfer->c_scsipi = sc_xfer; 1763 xfer->c_atapi.c_dscpoll = 0; 1764 s = splbio(); 1765 ata_exec_xfer(atac->atac_channels[channel], xfer); 1766 #ifdef DIAGNOSTIC 1767 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1768 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1769 panic("%s: polled command not done", __func__); 1770 #endif 1771 splx(s); 1772 return; 1773 1774 default: 1775 /* Not supported, nothing to do. */ 1776 ; 1777 } 1778 } 1779 1780 int 1781 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1782 { 1783 struct siisata_channel *schp = (struct siisata_channel *)chp; 1784 struct siisata_prb *prbp; 1785 1786 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1787 1788 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1789 SIISATANAME((struct siisata_softc *)chp->ch_atac), chp->ch_channel, 1790 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1791 DEBUG_XFERS); 1792 1793 ata_channel_lock_owned(chp); 1794 1795 prbp = schp->sch_prb[xfer->c_slot]; 1796 memset(prbp, 0, SIISATA_CMD_SIZE); 1797 1798 /* fill in direction for ATAPI command */ 1799 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1800 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1801 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1802 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1803 1804 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1805 KASSERT(xfer->c_drive <= PMP_PORT_CTL); 1806 prbp->prb_fis[rhd_c] |= xfer->c_drive; 1807 1808 /* copy over ATAPI command */ 1809 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1810 1811 if (siisata_dma_setup(chp, xfer->c_slot, 1812 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1813 xfer->c_databuf : NULL, 1814 xfer->c_bcount, 1815 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1816 BUS_DMA_READ : BUS_DMA_WRITE) 1817 ) { 1818 sc_xfer->error = XS_DRIVER_STUFFUP; 1819 return ATASTART_ABORT; 1820 } 1821 1822 if (xfer->c_flags & C_POLL) { 1823 /* polled command, disable interrupts */ 1824 prbp->prb_control |= htole16(PRB_CF_INTERRUPT_MASK); 1825 siisata_disable_port_interrupt(chp); 1826 } 1827 1828 siisata_activate_prb(schp, xfer->c_slot); 1829 1830 if ((xfer->c_flags & C_POLL) == 0) { 1831 callout_reset(&chp->c_timo_callout, mstohz(sc_xfer->timeout), 1832 ata_timeout, chp); 1833 return ATASTART_STARTED; 1834 } else 1835 return ATASTART_POLL; 1836 } 1837 1838 void 1839 siisata_atapi_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1840 { 1841 struct siisata_channel *schp = (struct siisata_channel *)chp; 1842 1843 /* 1844 * polled command 1845 */ 1846 for (int i = 0; i < ATA_DELAY * 10; i++) { 1847 if (xfer->c_scsipi->xs_status & XS_STS_DONE) 1848 break; 1849 siisata_intr_port(schp); 1850 DELAY(100); 1851 } 1852 if ((xfer->c_scsipi->xs_status & XS_STS_DONE) == 0) { 1853 ata_timeout(xfer); 1854 } 1855 /* reenable interrupts */ 1856 siisata_enable_port_interrupt(chp); 1857 1858 SIISATA_DEBUG_PRINT(("%s: %s: done\n", 1859 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 1860 DEBUG_FUNCS); 1861 } 1862 1863 void 1864 siisata_atapi_abort(struct ata_channel *chp, struct ata_xfer *xfer) 1865 { 1866 siisata_atapi_complete(chp, xfer, 0); 1867 } 1868 1869 int 1870 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1871 int tfd) 1872 { 1873 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1874 struct siisata_channel *schp = (struct siisata_channel *)chp; 1875 struct scsipi_xfer *sc_xfer = xfer->c_scsipi; 1876 1877 SIISATA_DEBUG_PRINT(("%s: %s()\n", SIISATANAME(sc), __func__), 1878 DEBUG_INTR); 1879 1880 if (ata_waitdrain_xfer_check(chp, xfer)) 1881 return 0; 1882 1883 if (xfer->c_flags & C_TIMEOU) { 1884 sc_xfer->error = XS_TIMEOUT; 1885 } 1886 1887 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[xfer->c_slot], 0, 1888 schp->sch_datad[xfer->c_slot]->dm_mapsize, 1889 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1890 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1891 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[xfer->c_slot]); 1892 1893 sc_xfer->resid = sc_xfer->datalen; 1894 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, xfer->c_slot, 1895 PRSO_RTC)); 1896 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1897 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1898 if ((ATACH_ST(tfd) & WDCS_ERR) && 1899 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1900 sc_xfer->resid == sc_xfer->datalen)) { 1901 sc_xfer->error = XS_SHORTSENSE; 1902 sc_xfer->sense.atapi_sense = ATACH_ERR(tfd); 1903 if ((sc_xfer->xs_periph->periph_quirks & 1904 PQUIRK_NOSENSE) == 0) { 1905 /* request sense */ 1906 sc_xfer->error = XS_BUSY; 1907 sc_xfer->status = SCSI_CHECK; 1908 } 1909 } 1910 1911 siisata_deactivate_prb(schp, xfer->c_slot); 1912 ata_deactivate_xfer(chp, xfer); 1913 1914 ata_free_xfer(chp, xfer); 1915 scsipi_done(sc_xfer); 1916 if ((ATACH_ST(tfd) & WDCS_ERR) == 0) 1917 atastart(chp); 1918 return 0; 1919 } 1920 1921 #endif /* NATAPIBUS */ 1922
Indexes created Fri Sep 26 20:09:58 GMT 2025