siisata.c revision 1.8
1 /* $NetBSD: siisata.c,v 1.8 2009/10/19 18:41:13 bouyer Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /*- 57 * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 * 80 */ 81 82 #include <sys/types.h> 83 #include <sys/malloc.h> 84 #include <sys/param.h> 85 #include <sys/kernel.h> 86 #include <sys/systm.h> 87 #include <sys/syslog.h> 88 #include <sys/disklabel.h> 89 #include <sys/buf.h> 90 91 #include <uvm/uvm_extern.h> 92 93 #include <dev/ata/atareg.h> 94 #include <dev/ata/satavar.h> 95 #include <dev/ata/satareg.h> 96 #include <dev/ata/satafisvar.h> 97 #include <dev/ic/siisatavar.h> 98 #include <dev/ic/wdcreg.h> 99 100 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 101 102 #include "atapibus.h" 103 104 #ifdef SIISATA_DEBUG 105 #if 0 106 int siisata_debug_mask = 0xffff; 107 #else 108 int siisata_debug_mask = 0; 109 #endif 110 #endif 111 112 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 113 114 static void siisata_attach_port(struct siisata_softc *, int); 115 static void siisata_intr_port(struct siisata_channel *); 116 117 void siisata_probe_drive(struct ata_channel *); 118 void siisata_setup_channel(struct ata_channel *); 119 120 int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); 121 void siisata_reset_drive(struct ata_drive_datas *, int); 122 void siisata_reset_channel(struct ata_channel *, int); 123 int siisata_ata_addref(struct ata_drive_datas *); 124 void siisata_ata_delref(struct ata_drive_datas *); 125 void siisata_killpending(struct ata_drive_datas *); 126 127 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 128 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 129 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 130 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 131 132 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 133 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 134 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 135 int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); 136 137 void siisata_timeout(void *); 138 139 static void siisata_reinit_port(struct ata_channel *); 140 static void siisata_device_reset(struct ata_channel *); 141 static void siisata_activate_prb(struct siisata_channel *, int); 142 static void siisata_deactivate_prb(struct siisata_channel *, int); 143 static int siisata_dma_setup(struct ata_channel *chp, int slot, 144 void *data, size_t, int); 145 146 #if NATAPIBUS > 0 147 void siisata_atapibus_attach(struct atabus_softc *); 148 void siisata_atapi_probe_device(struct atapibus_softc *, int); 149 void siisata_atapi_minphys(struct buf *); 150 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 151 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 152 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 153 void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 154 void siisata_atapi_scsipi_request(struct scsipi_channel *, 155 scsipi_adapter_req_t, void *); 156 void siisata_atapi_kill_pending(struct scsipi_periph *); 157 #endif /* NATAPIBUS */ 158 159 const struct ata_bustype siisata_ata_bustype = { 160 SCSIPI_BUSTYPE_ATA, 161 siisata_ata_bio, 162 siisata_reset_drive, 163 siisata_reset_channel, 164 siisata_exec_command, 165 ata_get_params, 166 siisata_ata_addref, 167 siisata_ata_delref, 168 siisata_killpending 169 }; 170 171 #if NATAPIBUS > 0 172 static const struct scsipi_bustype siisata_atapi_bustype = { 173 SCSIPI_BUSTYPE_ATAPI, 174 atapi_scsipi_cmd, 175 atapi_interpret_sense, 176 atapi_print_addr, 177 siisata_atapi_kill_pending 178 }; 179 #endif /* NATAPIBUS */ 180 181 182 void 183 siisata_attach(struct siisata_softc *sc) 184 { 185 int i; 186 187 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 188 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 189 190 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 191 sc->sc_atac.atac_pio_cap = 4; 192 sc->sc_atac.atac_dma_cap = 2; 193 sc->sc_atac.atac_udma_cap = 6; 194 sc->sc_atac.atac_channels = sc->sc_chanarray; 195 sc->sc_atac.atac_probe = siisata_probe_drive; 196 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 197 sc->sc_atac.atac_set_modes = siisata_setup_channel; 198 #if NATAPIBUS > 0 199 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 200 #endif 201 202 /* come out of reset state */ 203 GRWRITE(sc, GR_GC, 0); 204 205 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 206 siisata_attach_port(sc, i); 207 } 208 209 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 210 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 211 DEBUG_FUNCS); 212 return; 213 } 214 215 static void 216 siisata_init_port(struct siisata_softc *sc, int port) 217 { 218 struct siisata_channel *schp; 219 struct ata_channel *chp; 220 221 schp = &sc->sc_channels[port]; 222 chp = (struct ata_channel *)schp; 223 224 /* come out of reset, 64-bit activation */ 225 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 226 PR_PC_32BA | PR_PC_PORT_RESET); 227 /* initialize port */ 228 siisata_reinit_port(chp); 229 /* clear any interrupts */ 230 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 231 /* enable CmdErrr+CmdCmpl interrupting */ 232 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 233 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 234 /* enable port interrupt */ 235 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 236 } 237 238 static void 239 siisata_attach_port(struct siisata_softc *sc, int port) 240 { 241 int j; 242 bus_dma_segment_t seg; 243 int dmasize; 244 int error; 245 int rseg; 246 void *prbp; 247 struct siisata_channel *schp; 248 struct ata_channel *chp; 249 250 schp = &sc->sc_channels[port]; 251 chp = (struct ata_channel *)schp; 252 sc->sc_chanarray[port] = chp; 253 chp->ch_channel = port; 254 chp->ch_atac = &sc->sc_atac; 255 chp->ch_queue = malloc(sizeof(struct ata_queue), 256 M_DEVBUF, M_NOWAIT); 257 if (chp->ch_queue == NULL) { 258 aprint_error_dev(sc->sc_atac.atac_dev, 259 "port %d: can't allocate memory " 260 "for command queue\n", chp->ch_channel); 261 return; 262 } 263 264 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 265 266 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 267 __func__, dmasize), DEBUG_FUNCS); 268 269 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 270 &seg, 1, &rseg, BUS_DMA_NOWAIT); 271 if (error) { 272 aprint_error_dev(sc->sc_atac.atac_dev, 273 "unable to allocate PRB table memory, " 274 "error=%d\n", error); 275 return; 276 } 277 278 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 279 &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 280 if (error) { 281 aprint_error_dev(sc->sc_atac.atac_dev, 282 "unable to map PRB table memory, " 283 "error=%d\n", error); 284 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 285 return; 286 } 287 288 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 289 BUS_DMA_NOWAIT, &schp->sch_prbd); 290 if (error) { 291 aprint_error_dev(sc->sc_atac.atac_dev, 292 "unable to create PRB table map, " 293 "error=%d\n", error); 294 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 295 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 296 return; 297 } 298 299 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 300 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 301 if (error) { 302 aprint_error_dev(sc->sc_atac.atac_dev, 303 "unable to load PRB table map, " 304 "error=%d\n", error); 305 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 306 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 307 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 308 return; 309 } 310 311 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 312 schp->sch_prb[j] = (struct siisata_prb *) 313 ((char *)prbp + SIISATA_CMD_SIZE * j); 314 schp->sch_bus_prb[j] = 315 schp->sch_prbd->dm_segs[0].ds_addr + 316 SIISATA_CMD_SIZE * j; 317 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 318 SIISATA_NSGE, MAXPHYS, 0, 319 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 320 &schp->sch_datad[j]); 321 if (error) { 322 aprint_error_dev(sc->sc_atac.atac_dev, 323 "couldn't create xfer DMA map, error=%d\n", 324 error); 325 return; 326 } 327 } 328 329 chp->ch_ndrive = 1; 330 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 331 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 332 aprint_error_dev(sc->sc_atac.atac_dev, 333 "couldn't map port %d SStatus regs\n", 334 chp->ch_channel); 335 return; 336 } 337 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 338 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 339 aprint_error_dev(sc->sc_atac.atac_dev, 340 "couldn't map port %d SControl regs\n", 341 chp->ch_channel); 342 return; 343 } 344 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 345 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 346 aprint_error_dev(sc->sc_atac.atac_dev, 347 "couldn't map port %d SError regs\n", 348 chp->ch_channel); 349 return; 350 } 351 352 siisata_init_port(sc, port); 353 354 ata_channel_attach(chp); 355 356 return; 357 } 358 359 int 360 siisata_detach(struct siisata_softc *sc, int flags) 361 { 362 struct atac_softc *atac = &sc->sc_atac; 363 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 364 struct siisata_channel *schp; 365 struct ata_channel *chp; 366 bus_dmamap_t dmam; 367 int i, j, error; 368 369 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 370 schp = &sc->sc_channels[i]; 371 chp = sc->sc_chanarray[i]; 372 373 if (chp->atabus == NULL) 374 continue; 375 if ((error = config_detach(chp->atabus, flags)) != 0) 376 return error; 377 378 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 379 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 380 381 dmam = schp->sch_prbd; 382 bus_dmamap_unload(sc->sc_dmat, dmam); 383 bus_dmamap_destroy(sc->sc_dmat, dmam); 384 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 385 dmam->dm_mapsize); 386 bus_dmamem_free(sc->sc_dmat, dmam->dm_segs, dmam->dm_nsegs); 387 388 free(chp->ch_queue, M_DEVBUF); 389 chp->atabus = NULL; 390 } 391 392 if (adapt->adapt_refcnt != 0) 393 return EBUSY; 394 395 /* leave the chip in reset */ 396 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 397 398 return 0; 399 } 400 401 void 402 siisata_resume(struct siisata_softc *sc) 403 { 404 int i; 405 406 /* come out of reset state */ 407 GRWRITE(sc, GR_GC, 0); 408 409 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 410 siisata_init_port(sc, i); 411 } 412 413 } 414 415 int 416 siisata_intr(void *v) 417 { 418 struct siisata_softc *sc = v; 419 uint32_t is; 420 int i, r = 0; 421 while ((is = GRREAD(sc, GR_GIS))) { 422 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 423 SIISATANAME(sc), __func__, is), DEBUG_INTR); 424 r = 1; 425 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 426 if (is & GR_GIS_PXIS(i)) 427 siisata_intr_port(&sc->sc_channels[i]); 428 } 429 return r; 430 } 431 432 static void 433 siisata_intr_port(struct siisata_channel *schp) 434 { 435 struct siisata_softc *sc; 436 struct ata_channel *chp; 437 struct ata_xfer *xfer; 438 int slot; 439 uint32_t pss, pis; 440 uint32_t prbfis; 441 442 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 443 chp = &schp->ata_channel; 444 xfer = chp->ch_queue->active_xfer; 445 slot = SIISATA_NON_NCQ_SLOT; 446 447 SIISATA_DEBUG_PRINT(("%s: %s port %d\n", 448 SIISATANAME(sc), __func__, chp->ch_channel), DEBUG_INTR); 449 450 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 451 452 if (pis & PR_PIS_CMDCMPL) { 453 /* get slot status, clearing completion interrupt */ 454 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 455 /* is this expected? */ 456 /* XXX improve */ 457 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 458 log(LOG_WARNING, "%s: unexpected command " 459 "completion on port %d\n", 460 SIISATANAME(sc), chp->ch_channel); 461 return; 462 } 463 } else if (pis & PR_PIS_CMDERRR) { 464 uint32_t ec; 465 466 /* emulate a CRC error by default */ 467 chp->ch_status = WDCS_ERR; 468 chp->ch_error = WDCE_CRC; 469 470 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 471 if (ec <= PR_PCE_DATAFISERROR) { 472 if (ec == PR_PCE_DEVICEERROR) { 473 /* read in specific information about error */ 474 prbfis = bus_space_read_stream_4( 475 sc->sc_prt, sc->sc_prh, 476 PRSX(chp->ch_channel, slot, PRSO_FIS)); 477 /* set ch_status and ch_error */ 478 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 479 } 480 siisata_reinit_port(chp); 481 } else { 482 /* okay, we have a "Fatal Error" */ 483 siisata_device_reset(chp); 484 } 485 } 486 487 /* clear some (ok, all) ints */ 488 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 489 490 KASSERT(xfer != NULL); 491 KASSERT(xfer->c_intr != NULL); 492 xfer->c_intr(chp, xfer, slot); 493 494 return; 495 } 496 497 void 498 siisata_reset_drive(struct ata_drive_datas *drvp, int flags) 499 { 500 struct ata_channel *chp = drvp->chnl_softc; 501 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 502 struct siisata_channel *schp = (struct siisata_channel *)chp; 503 struct siisata_prb *prb; 504 int slot = SIISATA_NON_NCQ_SLOT; 505 int i; 506 507 /* wait for ready */ 508 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 509 DELAY(10); 510 511 prb = schp->sch_prb[slot]; 512 memset(prb, 0, sizeof(struct siisata_prb)); 513 prb->prb_control = 514 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 515 516 siisata_activate_prb(schp, slot); 517 518 for(i = 0; i < 31000; i++) { 519 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 520 PR_PXSS(slot)) 521 DELAY(1000); 522 else 523 break; 524 } 525 526 siisata_deactivate_prb(schp, slot); 527 528 log(LOG_DEBUG, "%s: port %d: ch_status %x ch_error %x\n", 529 __func__, chp->ch_channel, chp->ch_status, chp->ch_error); 530 531 #if 1 532 /* attempt to downgrade signaling in event of CRC error */ 533 /* XXX should be part of the MI (S)ATA subsystem */ 534 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 535 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 536 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 537 DELAY(10); 538 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 539 SControl_IPM_NONE | SControl_SPD_G1); 540 DELAY(10); 541 for (;;) { 542 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 543 & SStatus_DET_mask) == SStatus_DET_DEV) 544 break; 545 DELAY(10); 546 } 547 } 548 #endif 549 550 #if 1 551 chp->ch_status = 0; 552 chp->ch_error = 0; 553 #endif 554 555 return; 556 } 557 558 void 559 siisata_reset_channel(struct ata_channel *chp, int flags) 560 { 561 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 562 struct siisata_channel *schp = (struct siisata_channel *)chp; 563 564 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 565 DEBUG_FUNCS); 566 567 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 568 schp->sch_sstatus) != SStatus_DET_DEV) { 569 log(LOG_CRIT, "%s port %d: reset failed\n", 570 SIISATANAME(sc), chp->ch_channel); 571 /* XXX and then ? */ 572 } 573 /* wait for ready */ 574 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 575 DELAY(10); 576 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 577 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 578 if (chp->ch_queue->active_xfer) { 579 chp->ch_queue->active_xfer->c_kill_xfer(chp, 580 chp->ch_queue->active_xfer, KILL_RESET); 581 } 582 583 return; 584 } 585 586 int 587 siisata_ata_addref(struct ata_drive_datas *drvp) 588 { 589 return 0; 590 } 591 592 void 593 siisata_ata_delref(struct ata_drive_datas *drvp) 594 { 595 return; 596 } 597 598 void 599 siisata_killpending(struct ata_drive_datas *drvp) 600 { 601 return; 602 } 603 604 void 605 siisata_probe_drive(struct ata_channel *chp) 606 { 607 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 608 struct siisata_channel *schp = (struct siisata_channel *)chp; 609 int i; 610 int s; 611 uint32_t sig; 612 int slot = SIISATA_NON_NCQ_SLOT; 613 struct siisata_prb *prb; 614 615 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 616 __func__, chp->ch_channel), DEBUG_FUNCS); 617 618 /* XXX This should be done by other code. */ 619 for (i = 0; i < chp->ch_ndrive; i++) { 620 chp->ch_drive[i].chnl_softc = chp; 621 chp->ch_drive[i].drive = i; 622 } 623 624 switch (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 625 schp->sch_sstatus)) { 626 case SStatus_DET_DEV: 627 /* wait for ready */ 628 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 629 & PR_PS_PORT_READY)) 630 DELAY(10); 631 632 prb = schp->sch_prb[slot]; 633 memset(prb, 0, sizeof(struct siisata_prb)); 634 prb->prb_control = 635 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 636 637 siisata_activate_prb(schp, slot); 638 639 for(i = 0; i < 31000; i++) { 640 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 641 PR_PXSS(slot)) 642 DELAY(1000); 643 else 644 break; 645 } 646 647 siisata_deactivate_prb(schp, slot); 648 649 /* read the signature out of the FIS */ 650 sig = 0; 651 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 652 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 653 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 654 PRSO_FIS+0xc)) & 0xff; 655 656 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 657 __func__, sig), DEBUG_PROBE); 658 659 /* some ATAPI devices have bogus lower two bytes, sigh */ 660 if ((sig & 0xffff0000) == 0xeb140000) { 661 sig &= 0xffff0000; 662 sig |= 0x00000101; 663 } 664 665 s = splbio(); 666 switch (sig) { 667 case 0xeb140101: 668 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 669 break; 670 case 0x00000101: 671 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 672 break; 673 default: 674 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 675 aprint_verbose_dev(sc->sc_atac.atac_dev, 676 "Unrecognized signature 0x%08x on port %d. " 677 "Assuming it's a disk.\n", sig, chp->ch_channel); 678 break; 679 } 680 splx(s); 681 break; 682 default: 683 break; 684 } 685 686 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 687 __func__, chp->ch_channel), DEBUG_PROBE); 688 return; 689 } 690 691 void 692 siisata_setup_channel(struct ata_channel *chp) 693 { 694 return; 695 } 696 697 int 698 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 699 { 700 struct ata_channel *chp = drvp->chnl_softc; 701 struct ata_xfer *xfer; 702 int ret; 703 int s; 704 705 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 706 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 707 DEBUG_FUNCS); 708 709 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? 710 ATAXF_CANSLEEP : ATAXF_NOSLEEP); 711 if (xfer == NULL) 712 return ATACMD_TRY_AGAIN; 713 if (ata_c->flags & AT_POLL) 714 xfer->c_flags |= C_POLL; 715 if (ata_c->flags & AT_WAIT) 716 xfer->c_flags |= C_WAIT; 717 xfer->c_drive = drvp->drive; 718 xfer->c_databuf = ata_c->data; 719 xfer->c_bcount = ata_c->bcount; 720 xfer->c_cmd = ata_c; 721 xfer->c_start = siisata_cmd_start; 722 xfer->c_intr = siisata_cmd_complete; 723 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 724 s = splbio(); 725 ata_exec_xfer(chp, xfer); 726 #ifdef DIAGNOSTIC 727 if ((ata_c->flags & AT_POLL) != 0 && 728 (ata_c->flags & AT_DONE) == 0) 729 panic("%s: polled command not done", __func__); 730 #endif 731 if (ata_c->flags & AT_DONE) { 732 ret = ATACMD_COMPLETE; 733 } else { 734 if (ata_c->flags & AT_WAIT) { 735 while ((ata_c->flags & AT_DONE) == 0) { 736 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 737 SIISATANAME( 738 (struct siisata_softc *)chp->ch_atac), 739 __func__), DEBUG_FUNCS); 740 tsleep(ata_c, PRIBIO, "siicmd", 0); 741 } 742 ret = ATACMD_COMPLETE; 743 } else { 744 ret = ATACMD_QUEUED; 745 } 746 } 747 splx(s); 748 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 749 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 750 DEBUG_FUNCS); 751 return ret; 752 } 753 754 void 755 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 756 { 757 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 758 struct siisata_channel *schp = (struct siisata_channel *)chp; 759 struct ata_command *ata_c = xfer->c_cmd; 760 int slot = SIISATA_NON_NCQ_SLOT; 761 struct siisata_prb *prb; 762 int i; 763 764 SIISATA_DEBUG_PRINT(("%s: %s port %d, slot %d\n", 765 SIISATANAME(sc), __func__, chp->ch_channel, slot), DEBUG_FUNCS); 766 767 chp->ch_status = 0; 768 chp->ch_error = 0; 769 770 prb = schp->sch_prb[slot]; 771 memset(prb, 0, sizeof(struct siisata_prb)); 772 773 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 774 775 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 776 777 if (siisata_dma_setup(chp, slot, 778 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 779 ata_c->bcount, 780 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 781 ata_c->flags |= AT_DF; 782 siisata_cmd_complete(chp, xfer, slot); 783 return; 784 } 785 786 if (xfer->c_flags & C_POLL) { 787 /* polled command, disable interrupts */ 788 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 789 } 790 791 /* go for it */ 792 siisata_activate_prb(schp, slot); 793 794 if ((ata_c->flags & AT_POLL) == 0) { 795 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 796 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 797 siisata_timeout, chp); 798 goto out; 799 } 800 801 /* 802 * polled command 803 */ 804 for (i = 0; i < ata_c->timeout / 10; i++) { 805 if (ata_c->flags & AT_DONE) 806 break; 807 siisata_intr_port(schp); 808 DELAY(1000); 809 } 810 811 if ((ata_c->flags & AT_DONE) == 0) { 812 ata_c->flags |= AT_TIMEOU; 813 siisata_cmd_complete(chp, xfer, slot); 814 } 815 816 /* reenable interrupts */ 817 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 818 out: 819 SIISATA_DEBUG_PRINT( 820 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 821 return; 822 } 823 824 void 825 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 826 int reason) 827 { 828 int slot = SIISATA_NON_NCQ_SLOT; 829 830 struct ata_command *ata_c = xfer->c_cmd; 831 switch (reason) { 832 case KILL_GONE: 833 ata_c->flags |= AT_GONE; 834 break; 835 case KILL_RESET: 836 ata_c->flags |= AT_RESET; 837 break; 838 default: 839 panic("%s: port %d: unknown reason %d", 840 __func__, chp->ch_channel, reason); 841 } 842 siisata_cmd_done(chp, xfer, slot); 843 } 844 845 int 846 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 847 { 848 struct ata_command *ata_c = xfer->c_cmd; 849 #ifdef SIISATA_DEBUG 850 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 851 #endif 852 853 SIISATA_DEBUG_PRINT( 854 ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 855 856 chp->ch_flags &= ~ATACH_IRQ_WAIT; 857 if (xfer->c_flags & C_TIMEOU) 858 ata_c->flags |= AT_TIMEOU; 859 else 860 callout_stop(&chp->ch_callout); 861 862 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 863 siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); 864 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 865 wakeup(&chp->ch_queue->active_xfer); 866 return 0; 867 } 868 869 chp->ch_queue->active_xfer = NULL; 870 871 { 872 ata_c->r_head = 0; 873 ata_c->r_count = 0; 874 ata_c->r_sector = 0; 875 ata_c->r_cyl = 0; 876 if (chp->ch_status & WDCS_BSY) { 877 ata_c->flags |= AT_TIMEOU; 878 } else if (chp->ch_status & WDCS_ERR) { 879 ata_c->r_error = chp->ch_error; 880 ata_c->flags |= AT_ERROR; 881 } 882 } 883 siisata_cmd_done(chp, xfer, slot); 884 return 0; 885 } 886 887 void 888 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 889 { 890 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 891 struct siisata_channel *schp = (struct siisata_channel *)chp; 892 struct ata_command *ata_c = xfer->c_cmd; 893 int i; 894 uint16_t *idwordbuf; 895 896 SIISATA_DEBUG_PRINT( 897 ("%s: %s.\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 898 899 siisata_deactivate_prb(schp, slot); 900 901 if (ata_c->flags & (AT_READ | AT_WRITE)) { 902 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 903 schp->sch_datad[slot]->dm_mapsize, 904 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 905 BUS_DMASYNC_POSTWRITE); 906 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 907 } 908 909 idwordbuf = xfer->c_databuf; 910 911 /* correct the endianess of IDENTIFY data */ 912 if (ata_c->r_command == WDCC_IDENTIFY || 913 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 914 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 915 idwordbuf[i] = le16toh(idwordbuf[i]); 916 } 917 } 918 919 ata_c->flags |= AT_DONE; 920 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 921 ata_c->flags |= AT_XFDONE; 922 923 ata_free_xfer(chp, xfer); 924 if (ata_c->flags & AT_WAIT) 925 wakeup(ata_c); 926 else if (ata_c->callback) 927 ata_c->callback(ata_c->callback_arg); 928 atastart(chp); 929 return; 930 } 931 932 int 933 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 934 { 935 struct ata_channel *chp = drvp->chnl_softc; 936 struct ata_xfer *xfer; 937 938 SIISATA_DEBUG_PRINT( ("%s: %s.\n", 939 SIISATANAME((struct siisata_softc *)chp->ch_atac), 940 __func__), DEBUG_FUNCS); 941 942 xfer = ata_get_xfer(ATAXF_NOSLEEP); 943 if (xfer == NULL) 944 return ATACMD_TRY_AGAIN; 945 if (ata_bio->flags & ATA_POLL) 946 xfer->c_flags |= C_POLL; 947 xfer->c_drive = drvp->drive; 948 xfer->c_cmd = ata_bio; 949 xfer->c_databuf = ata_bio->databuf; 950 xfer->c_bcount = ata_bio->bcount; 951 xfer->c_start = siisata_bio_start; 952 xfer->c_intr = siisata_bio_complete; 953 xfer->c_kill_xfer = siisata_bio_kill_xfer; 954 ata_exec_xfer(chp, xfer); 955 return (ata_bio->flags & ATA_ITSDONE) ? 956 ATACMD_COMPLETE : ATACMD_QUEUED; 957 } 958 959 void 960 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 961 { 962 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 963 struct siisata_channel *schp = (struct siisata_channel *)chp; 964 struct siisata_prb *prb; 965 struct ata_bio *ata_bio = xfer->c_cmd; 966 int slot = SIISATA_NON_NCQ_SLOT; 967 int i; 968 969 SIISATA_DEBUG_PRINT( 970 ("%s: %s port %d, slot %d\n", 971 SIISATANAME(sc), __func__, chp->ch_channel, slot), 972 DEBUG_FUNCS); 973 974 chp->ch_status = 0; 975 chp->ch_error = 0; 976 977 prb = schp->sch_prb[slot]; 978 memset(prb, 0, sizeof(struct siisata_prb)); 979 980 satafis_rhd_construct_bio(xfer, prb->prb_fis); 981 982 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 983 984 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 985 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 986 ata_bio->error = ERR_DMA; 987 ata_bio->r_error = 0; 988 siisata_bio_complete(chp, xfer, slot); 989 return; 990 } 991 992 if (xfer->c_flags & C_POLL) { 993 /* polled command, disable interrupts */ 994 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 995 } 996 997 siisata_activate_prb(schp, slot); 998 999 if ((ata_bio->flags & ATA_POLL) == 0) { 1000 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1001 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1002 siisata_timeout, chp); 1003 goto out; 1004 } 1005 1006 /* 1007 * polled command 1008 */ 1009 for (i = 0; i < ATA_DELAY / 10; i++) { 1010 if (ata_bio->flags & ATA_ITSDONE) 1011 break; 1012 siisata_intr_port(schp); 1013 DELAY(1000); 1014 } 1015 1016 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1017 out: 1018 SIISATA_DEBUG_PRINT( 1019 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1020 return; 1021 } 1022 1023 void 1024 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1025 int reason) 1026 { 1027 struct siisata_channel *schp = (struct siisata_channel *)chp; 1028 struct ata_bio *ata_bio = xfer->c_cmd; 1029 int drive = xfer->c_drive; 1030 int slot = SIISATA_NON_NCQ_SLOT; 1031 1032 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1033 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1034 __func__, chp->ch_channel), DEBUG_FUNCS); 1035 1036 siisata_deactivate_prb(schp, slot); 1037 1038 ata_free_xfer(chp, xfer); 1039 ata_bio->flags |= ATA_ITSDONE; 1040 switch (reason) { 1041 case KILL_GONE: 1042 ata_bio->error = ERR_NODEV; 1043 break; 1044 case KILL_RESET: 1045 ata_bio->error = ERR_RESET; 1046 break; 1047 default: 1048 panic("%s: port %d: unknown reason %d", 1049 __func__, chp->ch_channel, reason); 1050 } 1051 ata_bio->r_error = WDCE_ABRT; 1052 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1053 } 1054 1055 int 1056 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1057 { 1058 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1059 struct siisata_channel *schp = (struct siisata_channel *)chp; 1060 struct ata_bio *ata_bio = xfer->c_cmd; 1061 int drive = xfer->c_drive; 1062 1063 schp->sch_active_slots &= ~__BIT(slot); 1064 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1065 if (xfer->c_flags & C_TIMEOU) { 1066 ata_bio->error = TIMEOUT; 1067 } else { 1068 callout_stop(&chp->ch_callout); 1069 ata_bio->error = NOERROR; 1070 } 1071 1072 chp->ch_queue->active_xfer = NULL; 1073 1074 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1075 schp->sch_datad[slot]->dm_mapsize, 1076 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1077 BUS_DMASYNC_POSTWRITE); 1078 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1079 1080 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1081 siisata_bio_kill_xfer(chp, xfer, KILL_GONE); 1082 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1083 wakeup(&chp->ch_queue->active_xfer); 1084 return 0; 1085 } 1086 ata_free_xfer(chp, xfer); 1087 ata_bio->flags |= ATA_ITSDONE; 1088 if (chp->ch_status & WDCS_DWF) { 1089 ata_bio->error = ERR_DF; 1090 } else if (chp->ch_status & WDCS_ERR) { 1091 ata_bio->error = ERROR; 1092 ata_bio->r_error = chp->ch_error; 1093 } else if (chp->ch_status & WDCS_CORR) 1094 ata_bio->flags |= ATA_CORR; 1095 1096 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), 1097 __func__, ata_bio->bcount), DEBUG_XFERS); 1098 if (ata_bio->error == NOERROR) { 1099 if (ata_bio->flags & ATA_READ) 1100 ata_bio->bcount -= 1101 PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1102 else 1103 ata_bio->bcount = 0; 1104 } 1105 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1106 if (ata_bio->flags & ATA_POLL) 1107 return 1; 1108 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1109 atastart(chp); 1110 return 0; 1111 } 1112 1113 void 1114 siisata_timeout(void *v) 1115 { 1116 struct ata_channel *chp = (struct ata_channel *)v; 1117 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1118 int slot = SIISATA_NON_NCQ_SLOT; 1119 int s = splbio(); 1120 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1121 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1122 xfer->c_flags |= C_TIMEOU; 1123 xfer->c_intr(chp, xfer, slot); 1124 } 1125 splx(s); 1126 } 1127 1128 static int 1129 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1130 size_t count, int op) 1131 { 1132 1133 int error, seg; 1134 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1135 struct siisata_channel *schp = (struct siisata_channel *)chp; 1136 1137 struct siisata_prb *prbp; 1138 1139 prbp = schp->sch_prb[slot]; 1140 1141 if (data == NULL) { 1142 goto end; 1143 } 1144 1145 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1146 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1147 if (error) { 1148 log(LOG_ERR, "%s port %d: " 1149 "failed to load xfer in slot %d: error %d\n", 1150 SIISATANAME(sc), chp->ch_channel, slot, error); 1151 return error; 1152 } 1153 1154 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1155 schp->sch_datad[slot]->dm_mapsize, 1156 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1157 1158 /* make sure it's clean */ 1159 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1160 1161 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1162 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1163 DEBUG_FUNCS | DEBUG_DEBUG); 1164 1165 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1166 prbp->prb_sge[seg].sge_da = 1167 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1168 prbp->prb_sge[seg].sge_dc = 1169 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1170 prbp->prb_sge[seg].sge_flags = htole32(0); 1171 } 1172 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1173 end: 1174 return 0; 1175 } 1176 1177 static void 1178 siisata_activate_prb(struct siisata_channel *schp, int slot) 1179 { 1180 struct siisata_softc *sc; 1181 bus_size_t offset; 1182 uint64_t pprb; 1183 1184 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1185 1186 KASSERTMSG(((schp->sch_active_slots & __BIT(slot)) == __BIT(slot)), 1187 ("%s: trying to activate active slot %d", SIISATANAME(sc), slot)); 1188 1189 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1190 /* keep track of what's going on */ 1191 schp->sch_active_slots |= __BIT(slot); 1192 1193 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1194 1195 pprb = schp->sch_bus_prb[slot]; 1196 1197 PRWRITE(sc, offset + 0, pprb >> 0); 1198 PRWRITE(sc, offset + 4, pprb >> 32); 1199 } 1200 1201 static void 1202 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1203 { 1204 struct siisata_softc *sc; 1205 1206 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1207 1208 KASSERTMSG(((schp->sch_active_slots & __BIT(slot)) == 0), 1209 ("%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1210 slot)); 1211 1212 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1213 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1214 } 1215 1216 static void 1217 siisata_reinit_port(struct ata_channel *chp) 1218 { 1219 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1220 1221 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1222 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1223 DELAY(10); 1224 } 1225 1226 static void 1227 siisata_device_reset(struct ata_channel *chp) 1228 { 1229 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1230 1231 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1232 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1233 DELAY(10); 1234 } 1235 1236 1237 #if NATAPIBUS > 0 1238 void 1239 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1240 { 1241 struct ata_channel *chp = ata_sc->sc_chan; 1242 struct atac_softc *atac = chp->ch_atac; 1243 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1244 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1245 1246 /* 1247 * Fill in the scsipi_adapter. 1248 */ 1249 adapt->adapt_dev = atac->atac_dev; 1250 adapt->adapt_nchannels = atac->atac_nchannels; 1251 adapt->adapt_request = siisata_atapi_scsipi_request; 1252 adapt->adapt_minphys = siisata_atapi_minphys; 1253 atac->atac_atapi_adapter.atapi_probe_device = 1254 siisata_atapi_probe_device; 1255 1256 /* 1257 * Fill in the scsipi_channel. 1258 */ 1259 memset(chan, 0, sizeof(*chan)); 1260 chan->chan_adapter = adapt; 1261 chan->chan_bustype = &siisata_atapi_bustype; 1262 chan->chan_channel = chp->ch_channel; 1263 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1264 chan->chan_openings = 1; 1265 chan->chan_max_periph = 1; 1266 chan->chan_ntargets = 1; 1267 chan->chan_nluns = 1; 1268 1269 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1270 atapiprint); 1271 } 1272 1273 void 1274 siisata_atapi_minphys(struct buf *bp) 1275 { 1276 if (bp->b_bcount > MAXPHYS) 1277 bp->b_bcount = MAXPHYS; 1278 minphys(bp); 1279 } 1280 1281 /* 1282 * Kill off all pending xfers for a periph. 1283 * 1284 * Must be called at splbio(). 1285 */ 1286 void 1287 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1288 { 1289 struct atac_softc *atac = 1290 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1291 struct ata_channel *chp = 1292 atac->atac_channels[periph->periph_channel->chan_channel]; 1293 1294 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1295 } 1296 1297 void 1298 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1299 int reason) 1300 { 1301 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1302 1303 /* remove this command from xfer queue */ 1304 switch (reason) { 1305 case KILL_GONE: 1306 sc_xfer->error = XS_DRIVER_STUFFUP; 1307 break; 1308 case KILL_RESET: 1309 sc_xfer->error = XS_RESET; 1310 break; 1311 default: 1312 panic("%s: port %d: unknown reason %d", 1313 __func__, chp->ch_channel, reason); 1314 } 1315 ata_free_xfer(chp, xfer); 1316 scsipi_done(sc_xfer); 1317 } 1318 1319 void 1320 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1321 { 1322 struct scsipi_channel *chan = sc->sc_channel; 1323 struct scsipi_periph *periph; 1324 struct ataparams ids; 1325 struct ataparams *id = &ids; 1326 struct siisata_softc *siic = 1327 device_private(chan->chan_adapter->adapt_dev); 1328 struct atac_softc *atac = &siic->sc_atac; 1329 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1330 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1331 struct scsipibus_attach_args sa; 1332 char serial_number[21], model[41], firmware_revision[9]; 1333 int s; 1334 1335 /* skip if already attached */ 1336 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1337 return; 1338 1339 /* if no ATAPI device detected at attach time, skip */ 1340 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1341 SIISATA_DEBUG_PRINT(("%s: drive %d " 1342 "not present\n", __func__, target), DEBUG_PROBE); 1343 return; 1344 } 1345 1346 /* Some ATAPI devices need a bit more time after software reset. */ 1347 DELAY(5000); 1348 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1349 #ifdef ATAPI_DEBUG_PROBE 1350 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1351 device_xname(sc->sc_dev), target, 1352 id->atap_config & ATAPI_CFG_CMD_MASK, 1353 id->atap_config & ATAPI_CFG_DRQ_MASK); 1354 #endif 1355 periph = scsipi_alloc_periph(M_NOWAIT); 1356 if (periph == NULL) { 1357 aprint_error_dev(sc->sc_dev, 1358 "%s: unable to allocate periph for " 1359 "channel %d drive %d\n", __func__, 1360 chp->ch_channel, target); 1361 return; 1362 } 1363 periph->periph_dev = NULL; 1364 periph->periph_channel = chan; 1365 periph->periph_switch = &atapi_probe_periphsw; 1366 periph->periph_target = target; 1367 periph->periph_lun = 0; 1368 periph->periph_quirks = PQUIRK_ONLYBIG; 1369 1370 #ifdef SCSIPI_DEBUG 1371 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1372 SCSIPI_DEBUG_TARGET == target) 1373 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1374 #endif 1375 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1376 if (id->atap_config & ATAPI_CFG_REMOV) 1377 periph->periph_flags |= PERIPH_REMOVABLE; 1378 if (periph->periph_type == T_SEQUENTIAL) { 1379 s = splbio(); 1380 drvp->drive_flags |= DRIVE_ATAPIST; 1381 splx(s); 1382 } 1383 1384 sa.sa_periph = periph; 1385 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1386 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1387 T_REMOV : T_FIXED; 1388 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1389 scsipi_strvis((u_char *)serial_number, 20, 1390 id->atap_serial, 20); 1391 scsipi_strvis((u_char *)firmware_revision, 8, 1392 id->atap_revision, 8); 1393 sa.sa_inqbuf.vendor = model; 1394 sa.sa_inqbuf.product = serial_number; 1395 sa.sa_inqbuf.revision = firmware_revision; 1396 1397 /* 1398 * Determine the operating mode capabilities of the device. 1399 */ 1400 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1401 == ATAPI_CFG_CMD_16) { 1402 periph->periph_cap |= PERIPH_CAP_CMD16; 1403 1404 /* configure port for packet length */ 1405 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1406 PR_PC_PACKET_LENGTH); 1407 } else { 1408 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1409 PR_PC_PACKET_LENGTH); 1410 } 1411 1412 /* XXX This is gross. */ 1413 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1414 1415 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1416 1417 if (drvp->drv_softc) 1418 ata_probe_caps(drvp); 1419 else { 1420 s = splbio(); 1421 drvp->drive_flags &= ~DRIVE_ATAPI; 1422 splx(s); 1423 } 1424 } else { 1425 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1426 "failed for drive %s:%d:%d: error 0x%x\n", 1427 __func__, SIISATANAME(siic), chp->ch_channel, target, 1428 chp->ch_error), DEBUG_PROBE); 1429 s = splbio(); 1430 drvp->drive_flags &= ~DRIVE_ATAPI; 1431 splx(s); 1432 } 1433 } 1434 1435 void 1436 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1437 scsipi_adapter_req_t req, void *arg) 1438 { 1439 struct scsipi_adapter *adapt = chan->chan_adapter; 1440 struct scsipi_periph *periph; 1441 struct scsipi_xfer *sc_xfer; 1442 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1443 struct atac_softc *atac = &sc->sc_atac; 1444 struct ata_xfer *xfer; 1445 int channel = chan->chan_channel; 1446 int drive, s; 1447 1448 switch (req) { 1449 case ADAPTER_REQ_RUN_XFER: 1450 sc_xfer = arg; 1451 periph = sc_xfer->xs_periph; 1452 drive = periph->periph_target; 1453 1454 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1455 device_xname(atac->atac_dev), channel, drive), 1456 DEBUG_XFERS); 1457 1458 if (!device_is_active(atac->atac_dev)) { 1459 sc_xfer->error = XS_DRIVER_STUFFUP; 1460 scsipi_done(sc_xfer); 1461 return; 1462 } 1463 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1464 if (xfer == NULL) { 1465 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1466 scsipi_done(sc_xfer); 1467 return; 1468 } 1469 1470 if (sc_xfer->xs_control & XS_CTL_POLL) 1471 xfer->c_flags |= C_POLL; 1472 xfer->c_drive = drive; 1473 xfer->c_flags |= C_ATAPI; 1474 xfer->c_cmd = sc_xfer; 1475 xfer->c_databuf = sc_xfer->data; 1476 xfer->c_bcount = sc_xfer->datalen; 1477 xfer->c_start = siisata_atapi_start; 1478 xfer->c_intr = siisata_atapi_complete; 1479 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1480 xfer->c_dscpoll = 0; 1481 s = splbio(); 1482 ata_exec_xfer(atac->atac_channels[channel], xfer); 1483 #ifdef DIAGNOSTIC 1484 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1485 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1486 panic("%s: polled command not done", __func__); 1487 #endif 1488 splx(s); 1489 return; 1490 1491 default: 1492 /* Not supported, nothing to do. */ 1493 ; 1494 } 1495 } 1496 1497 void 1498 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1499 { 1500 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1501 struct siisata_channel *schp = (struct siisata_channel *)chp; 1502 struct siisata_prb *prbp; 1503 1504 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1505 1506 int slot = SIISATA_NON_NCQ_SLOT; 1507 int i; 1508 1509 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1510 SIISATANAME(sc), chp->ch_channel, 1511 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1512 DEBUG_XFERS); 1513 1514 chp->ch_status = 0; 1515 chp->ch_error = 0; 1516 1517 prbp = schp->sch_prb[slot]; 1518 memset(prbp, 0, sizeof(struct siisata_prb)); 1519 1520 1521 /* fill in direction for ATAPI command */ 1522 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1523 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1524 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1525 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1526 1527 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1528 1529 /* copy over ATAPI command */ 1530 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1531 1532 if (siisata_dma_setup(chp, slot, 1533 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1534 xfer->c_databuf : NULL, 1535 xfer->c_bcount, 1536 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1537 BUS_DMA_READ : BUS_DMA_WRITE) 1538 ) 1539 panic("%s", __func__); 1540 1541 if (xfer->c_flags & C_POLL) { 1542 /* polled command, disable interrupts */ 1543 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1544 } 1545 1546 siisata_activate_prb(schp, slot); 1547 1548 if ((xfer->c_flags & C_POLL) == 0) { 1549 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1550 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1551 siisata_timeout, chp); 1552 goto out; 1553 } 1554 1555 /* 1556 * polled command 1557 */ 1558 for (i = 0; i < ATA_DELAY / 10; i++) { 1559 if (sc_xfer->xs_status & XS_STS_DONE) 1560 break; 1561 siisata_intr_port(schp); 1562 DELAY(1000); 1563 } 1564 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1565 sc_xfer->error = XS_TIMEOUT; 1566 siisata_atapi_complete(chp, xfer, slot); 1567 } 1568 /* reenable interrupts */ 1569 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1570 out: 1571 SIISATA_DEBUG_PRINT( 1572 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1573 return; 1574 } 1575 1576 int 1577 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1578 int slot) 1579 { 1580 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1581 struct siisata_channel *schp = (struct siisata_channel *)chp; 1582 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1583 1584 SIISATA_DEBUG_PRINT( 1585 ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1586 1587 /* this comamnd is not active any more */ 1588 schp->sch_active_slots &= ~__BIT(slot); 1589 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1590 if (xfer->c_flags & C_TIMEOU) { 1591 sc_xfer->error = XS_TIMEOUT; 1592 } else { 1593 callout_stop(&chp->ch_callout); 1594 sc_xfer->error = XS_NOERROR; 1595 } 1596 1597 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1598 schp->sch_datad[slot]->dm_mapsize, 1599 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1600 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1601 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1602 1603 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1604 siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); 1605 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1606 wakeup(&chp->ch_queue->active_xfer); 1607 return 0; /* XXX verify */ 1608 } 1609 1610 chp->ch_queue->active_xfer = NULL; 1611 ata_free_xfer(chp, xfer); 1612 1613 sc_xfer->resid = sc_xfer->datalen; 1614 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1615 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1616 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1617 if ((chp->ch_status & WDCS_ERR) && 1618 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1619 sc_xfer->resid == sc_xfer->datalen)) { 1620 sc_xfer->error = XS_SHORTSENSE; 1621 sc_xfer->sense.atapi_sense = chp->ch_error; 1622 if ((sc_xfer->xs_periph->periph_quirks & 1623 PQUIRK_NOSENSE) == 0) { 1624 /* request sense */ 1625 sc_xfer->error = XS_BUSY; 1626 sc_xfer->status = SCSI_CHECK; 1627 } 1628 } 1629 scsipi_done(sc_xfer); 1630 atastart(chp); 1631 return 0; /* XXX verify */ 1632 } 1633 1634 #endif /* NATAPIBUS */ 1635
Indexes created Thu Oct 23 22:10:10 GMT 2025