siisata.c revision 1.9
1 /* $NetBSD: siisata.c,v 1.9 2010/01/30 16:16:35 jakllsch Exp $ */ 2 3 /* from ahcisata_core.c */ 4 5 /* 6 * Copyright (c) 2006 Manuel Bouyer. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30 /* from atapi_wdc.c */ 31 32 /* 33 * Copyright (c) 1998, 2001 Manuel Bouyer. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch. 58 * All rights reserved. 59 * 60 * Redistribution and use in source and binary forms, with or without 61 * modification, are permitted provided that the following conditions 62 * are met: 63 * 1. Redistributions of source code must retain the above copyright 64 * notice, this list of conditions and the following disclaimer. 65 * 2. Redistributions in binary form must reproduce the above copyright 66 * notice, this list of conditions and the following disclaimer in the 67 * documentation and/or other materials provided with the distribution. 68 * 69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 71 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 72 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 73 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 74 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 75 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 76 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 77 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 78 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: siisata.c,v 1.9 2010/01/30 16:16:35 jakllsch Exp $"); 83 84 #include <sys/types.h> 85 #include <sys/malloc.h> 86 #include <sys/param.h> 87 #include <sys/kernel.h> 88 #include <sys/systm.h> 89 #include <sys/syslog.h> 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 93 #include <uvm/uvm_extern.h> 94 95 #include <dev/ata/atareg.h> 96 #include <dev/ata/satavar.h> 97 #include <dev/ata/satareg.h> 98 #include <dev/ata/satafisvar.h> 99 #include <dev/ic/siisatavar.h> 100 #include <dev/ic/wdcreg.h> 101 102 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 103 104 #include "atapibus.h" 105 106 #ifdef SIISATA_DEBUG 107 #if 0 108 int siisata_debug_mask = 0xffff; 109 #else 110 int siisata_debug_mask = 0; 111 #endif 112 #endif 113 114 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 115 116 static void siisata_attach_port(struct siisata_softc *, int); 117 static void siisata_intr_port(struct siisata_channel *); 118 119 void siisata_probe_drive(struct ata_channel *); 120 void siisata_setup_channel(struct ata_channel *); 121 122 int siisata_ata_bio(struct ata_drive_datas *, struct ata_bio *); 123 void siisata_reset_drive(struct ata_drive_datas *, int); 124 void siisata_reset_channel(struct ata_channel *, int); 125 int siisata_ata_addref(struct ata_drive_datas *); 126 void siisata_ata_delref(struct ata_drive_datas *); 127 void siisata_killpending(struct ata_drive_datas *); 128 129 void siisata_cmd_start(struct ata_channel *, struct ata_xfer *); 130 int siisata_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 131 void siisata_cmd_done(struct ata_channel *, struct ata_xfer *, int); 132 void siisata_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 133 134 void siisata_bio_start(struct ata_channel *, struct ata_xfer *); 135 int siisata_bio_complete(struct ata_channel *, struct ata_xfer *, int); 136 void siisata_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 137 int siisata_exec_command(struct ata_drive_datas *, struct ata_command *); 138 139 void siisata_timeout(void *); 140 141 static void siisata_reinit_port(struct ata_channel *); 142 static void siisata_device_reset(struct ata_channel *); 143 static void siisata_activate_prb(struct siisata_channel *, int); 144 static void siisata_deactivate_prb(struct siisata_channel *, int); 145 static int siisata_dma_setup(struct ata_channel *chp, int slot, 146 void *data, size_t, int); 147 148 #if NATAPIBUS > 0 149 void siisata_atapibus_attach(struct atabus_softc *); 150 void siisata_atapi_probe_device(struct atapibus_softc *, int); 151 void siisata_atapi_minphys(struct buf *); 152 void siisata_atapi_start(struct ata_channel *,struct ata_xfer *); 153 int siisata_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 154 void siisata_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 155 void siisata_atapi_done(struct ata_channel *, struct ata_xfer *, int); 156 void siisata_atapi_scsipi_request(struct scsipi_channel *, 157 scsipi_adapter_req_t, void *); 158 void siisata_atapi_kill_pending(struct scsipi_periph *); 159 #endif /* NATAPIBUS */ 160 161 const struct ata_bustype siisata_ata_bustype = { 162 SCSIPI_BUSTYPE_ATA, 163 siisata_ata_bio, 164 siisata_reset_drive, 165 siisata_reset_channel, 166 siisata_exec_command, 167 ata_get_params, 168 siisata_ata_addref, 169 siisata_ata_delref, 170 siisata_killpending 171 }; 172 173 #if NATAPIBUS > 0 174 static const struct scsipi_bustype siisata_atapi_bustype = { 175 SCSIPI_BUSTYPE_ATAPI, 176 atapi_scsipi_cmd, 177 atapi_interpret_sense, 178 atapi_print_addr, 179 siisata_atapi_kill_pending 180 }; 181 #endif /* NATAPIBUS */ 182 183 184 void 185 siisata_attach(struct siisata_softc *sc) 186 { 187 int i; 188 189 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 190 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), DEBUG_FUNCS); 191 192 sc->sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA; 193 sc->sc_atac.atac_pio_cap = 4; 194 sc->sc_atac.atac_dma_cap = 2; 195 sc->sc_atac.atac_udma_cap = 6; 196 sc->sc_atac.atac_channels = sc->sc_chanarray; 197 sc->sc_atac.atac_probe = siisata_probe_drive; 198 sc->sc_atac.atac_bustype_ata = &siisata_ata_bustype; 199 sc->sc_atac.atac_set_modes = siisata_setup_channel; 200 #if NATAPIBUS > 0 201 sc->sc_atac.atac_atapibus_attach = siisata_atapibus_attach; 202 #endif 203 204 /* come out of reset state */ 205 GRWRITE(sc, GR_GC, 0); 206 207 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 208 siisata_attach_port(sc, i); 209 } 210 211 SIISATA_DEBUG_PRINT(("%s: %s: GR_GC: 0x%08x\n", 212 SIISATANAME(sc), __func__, GRREAD(sc, GR_GC)), 213 DEBUG_FUNCS); 214 return; 215 } 216 217 static void 218 siisata_init_port(struct siisata_softc *sc, int port) 219 { 220 struct siisata_channel *schp; 221 struct ata_channel *chp; 222 223 schp = &sc->sc_channels[port]; 224 chp = (struct ata_channel *)schp; 225 226 /* come out of reset, 64-bit activation */ 227 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCC), 228 PR_PC_32BA | PR_PC_PORT_RESET); 229 /* initialize port */ 230 siisata_reinit_port(chp); 231 /* clear any interrupts */ 232 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 233 /* enable CmdErrr+CmdCmpl interrupting */ 234 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIES), 235 PR_PIS_CMDERRR | PR_PIS_CMDCMPL); 236 /* enable port interrupt */ 237 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 238 } 239 240 static void 241 siisata_attach_port(struct siisata_softc *sc, int port) 242 { 243 int j; 244 bus_dma_segment_t seg; 245 int dmasize; 246 int error; 247 int rseg; 248 void *prbp; 249 struct siisata_channel *schp; 250 struct ata_channel *chp; 251 252 schp = &sc->sc_channels[port]; 253 chp = (struct ata_channel *)schp; 254 sc->sc_chanarray[port] = chp; 255 chp->ch_channel = port; 256 chp->ch_atac = &sc->sc_atac; 257 chp->ch_queue = malloc(sizeof(struct ata_queue), 258 M_DEVBUF, M_NOWAIT); 259 if (chp->ch_queue == NULL) { 260 aprint_error_dev(sc->sc_atac.atac_dev, 261 "port %d: can't allocate memory " 262 "for command queue\n", chp->ch_channel); 263 return; 264 } 265 266 dmasize = SIISATA_CMD_SIZE * SIISATA_MAX_SLOTS; 267 268 SIISATA_DEBUG_PRINT(("%s: %s: dmasize: %d\n", SIISATANAME(sc), 269 __func__, dmasize), DEBUG_FUNCS); 270 271 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 272 &seg, 1, &rseg, BUS_DMA_NOWAIT); 273 if (error) { 274 aprint_error_dev(sc->sc_atac.atac_dev, 275 "unable to allocate PRB table memory, " 276 "error=%d\n", error); 277 return; 278 } 279 280 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 281 &prbp, BUS_DMA_NOWAIT | BUS_DMA_COHERENT); 282 if (error) { 283 aprint_error_dev(sc->sc_atac.atac_dev, 284 "unable to map PRB table memory, " 285 "error=%d\n", error); 286 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 287 return; 288 } 289 290 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 291 BUS_DMA_NOWAIT, &schp->sch_prbd); 292 if (error) { 293 aprint_error_dev(sc->sc_atac.atac_dev, 294 "unable to create PRB table map, " 295 "error=%d\n", error); 296 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 297 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 298 return; 299 } 300 301 error = bus_dmamap_load(sc->sc_dmat, schp->sch_prbd, 302 prbp, dmasize, NULL, BUS_DMA_NOWAIT); 303 if (error) { 304 aprint_error_dev(sc->sc_atac.atac_dev, 305 "unable to load PRB table map, " 306 "error=%d\n", error); 307 bus_dmamap_destroy(sc->sc_dmat, schp->sch_prbd); 308 bus_dmamem_unmap(sc->sc_dmat, prbp, dmasize); 309 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 310 return; 311 } 312 313 for (j = 0; j < SIISATA_MAX_SLOTS; j++) { 314 schp->sch_prb[j] = (struct siisata_prb *) 315 ((char *)prbp + SIISATA_CMD_SIZE * j); 316 schp->sch_bus_prb[j] = 317 schp->sch_prbd->dm_segs[0].ds_addr + 318 SIISATA_CMD_SIZE * j; 319 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 320 SIISATA_NSGE, MAXPHYS, 0, 321 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 322 &schp->sch_datad[j]); 323 if (error) { 324 aprint_error_dev(sc->sc_atac.atac_dev, 325 "couldn't create xfer DMA map, error=%d\n", 326 error); 327 return; 328 } 329 } 330 331 chp->ch_ndrive = 1; 332 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 333 PRX(chp->ch_channel, PRO_SSTATUS), 4, &schp->sch_sstatus) != 0) { 334 aprint_error_dev(sc->sc_atac.atac_dev, 335 "couldn't map port %d SStatus regs\n", 336 chp->ch_channel); 337 return; 338 } 339 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 340 PRX(chp->ch_channel, PRO_SCONTROL), 4, &schp->sch_scontrol) != 0) { 341 aprint_error_dev(sc->sc_atac.atac_dev, 342 "couldn't map port %d SControl regs\n", 343 chp->ch_channel); 344 return; 345 } 346 if (bus_space_subregion(sc->sc_prt, sc->sc_prh, 347 PRX(chp->ch_channel, PRO_SERROR), 4, &schp->sch_serror) != 0) { 348 aprint_error_dev(sc->sc_atac.atac_dev, 349 "couldn't map port %d SError regs\n", 350 chp->ch_channel); 351 return; 352 } 353 354 siisata_init_port(sc, port); 355 356 ata_channel_attach(chp); 357 358 return; 359 } 360 361 int 362 siisata_detach(struct siisata_softc *sc, int flags) 363 { 364 struct atac_softc *atac = &sc->sc_atac; 365 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 366 struct siisata_channel *schp; 367 struct ata_channel *chp; 368 bus_dmamap_t dmam; 369 int i, j, error; 370 371 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 372 schp = &sc->sc_channels[i]; 373 chp = sc->sc_chanarray[i]; 374 375 if (chp->atabus == NULL) 376 continue; 377 if ((error = config_detach(chp->atabus, flags)) != 0) 378 return error; 379 380 for (j = 0; j < SIISATA_MAX_SLOTS; j++) 381 bus_dmamap_destroy(sc->sc_dmat, schp->sch_datad[j]); 382 383 dmam = schp->sch_prbd; 384 bus_dmamap_unload(sc->sc_dmat, dmam); 385 bus_dmamap_destroy(sc->sc_dmat, dmam); 386 bus_dmamem_unmap(sc->sc_dmat, schp->sch_prb[0], 387 dmam->dm_mapsize); 388 bus_dmamem_free(sc->sc_dmat, dmam->dm_segs, dmam->dm_nsegs); 389 390 free(chp->ch_queue, M_DEVBUF); 391 chp->atabus = NULL; 392 } 393 394 if (adapt->adapt_refcnt != 0) 395 return EBUSY; 396 397 /* leave the chip in reset */ 398 GRWRITE(sc, GR_GC, GR_GC_GLBLRST); 399 400 return 0; 401 } 402 403 void 404 siisata_resume(struct siisata_softc *sc) 405 { 406 int i; 407 408 /* come out of reset state */ 409 GRWRITE(sc, GR_GC, 0); 410 411 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) { 412 siisata_init_port(sc, i); 413 } 414 415 } 416 417 int 418 siisata_intr(void *v) 419 { 420 struct siisata_softc *sc = v; 421 uint32_t is; 422 int i, r = 0; 423 while ((is = GRREAD(sc, GR_GIS))) { 424 SIISATA_DEBUG_PRINT(("%s: %s: GR_GIS: 0x%08x\n", 425 SIISATANAME(sc), __func__, is), DEBUG_INTR); 426 r = 1; 427 for (i = 0; i < sc->sc_atac.atac_nchannels; i++) 428 if (is & GR_GIS_PXIS(i)) 429 siisata_intr_port(&sc->sc_channels[i]); 430 } 431 return r; 432 } 433 434 static void 435 siisata_intr_port(struct siisata_channel *schp) 436 { 437 struct siisata_softc *sc; 438 struct ata_channel *chp; 439 struct ata_xfer *xfer; 440 int slot; 441 uint32_t pss, pis; 442 uint32_t prbfis; 443 444 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 445 chp = &schp->ata_channel; 446 xfer = chp->ch_queue->active_xfer; 447 slot = SIISATA_NON_NCQ_SLOT; 448 449 SIISATA_DEBUG_PRINT(("%s: %s port %d\n", 450 SIISATANAME(sc), __func__, chp->ch_channel), DEBUG_INTR); 451 452 pis = PRREAD(sc, PRX(chp->ch_channel, PRO_PIS)); 453 454 if (pis & PR_PIS_CMDCMPL) { 455 /* get slot status, clearing completion interrupt */ 456 pss = PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)); 457 /* is this expected? */ 458 /* XXX improve */ 459 if ((schp->sch_active_slots & __BIT(slot)) == 0) { 460 log(LOG_WARNING, "%s: unexpected command " 461 "completion on port %d\n", 462 SIISATANAME(sc), chp->ch_channel); 463 return; 464 } 465 } else if (pis & PR_PIS_CMDERRR) { 466 uint32_t ec; 467 468 /* emulate a CRC error by default */ 469 chp->ch_status = WDCS_ERR; 470 chp->ch_error = WDCE_CRC; 471 472 ec = PRREAD(sc, PRX(chp->ch_channel, PRO_PCE)); 473 if (ec <= PR_PCE_DATAFISERROR) { 474 if (ec == PR_PCE_DEVICEERROR) { 475 /* read in specific information about error */ 476 prbfis = bus_space_read_stream_4( 477 sc->sc_prt, sc->sc_prh, 478 PRSX(chp->ch_channel, slot, PRSO_FIS)); 479 /* set ch_status and ch_error */ 480 satafis_rdh_parse(chp, (uint8_t *)&prbfis); 481 } 482 siisata_reinit_port(chp); 483 } else { 484 /* okay, we have a "Fatal Error" */ 485 siisata_device_reset(chp); 486 } 487 } 488 489 /* clear some (ok, all) ints */ 490 PRWRITE(sc, PRX(chp->ch_channel, PRO_PIS), 0xffffffff); 491 492 KASSERT(xfer != NULL); 493 KASSERT(xfer->c_intr != NULL); 494 xfer->c_intr(chp, xfer, slot); 495 496 return; 497 } 498 499 void 500 siisata_reset_drive(struct ata_drive_datas *drvp, int flags) 501 { 502 struct ata_channel *chp = drvp->chnl_softc; 503 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 504 struct siisata_channel *schp = (struct siisata_channel *)chp; 505 struct siisata_prb *prb; 506 int slot = SIISATA_NON_NCQ_SLOT; 507 int i; 508 509 /* wait for ready */ 510 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 511 DELAY(10); 512 513 prb = schp->sch_prb[slot]; 514 memset(prb, 0, sizeof(struct siisata_prb)); 515 prb->prb_control = 516 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 517 518 siisata_activate_prb(schp, slot); 519 520 for(i = 0; i < 31000; i++) { 521 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 522 PR_PXSS(slot)) 523 DELAY(1000); 524 else 525 break; 526 } 527 528 siisata_deactivate_prb(schp, slot); 529 530 log(LOG_DEBUG, "%s: port %d: ch_status %x ch_error %x\n", 531 __func__, chp->ch_channel, chp->ch_status, chp->ch_error); 532 533 #if 1 534 /* attempt to downgrade signaling in event of CRC error */ 535 /* XXX should be part of the MI (S)ATA subsystem */ 536 if (chp->ch_status == 0x51 && chp->ch_error == 0x84) { 537 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 538 SControl_IPM_NONE | SControl_SPD_G1 | SControl_DET_INIT); 539 DELAY(10); 540 bus_space_write_4(sc->sc_prt, schp->sch_scontrol, 0, 541 SControl_IPM_NONE | SControl_SPD_G1); 542 DELAY(10); 543 for (;;) { 544 if ((bus_space_read_4(sc->sc_prt, schp->sch_sstatus, 0) 545 & SStatus_DET_mask) == SStatus_DET_DEV) 546 break; 547 DELAY(10); 548 } 549 } 550 #endif 551 552 #if 1 553 chp->ch_status = 0; 554 chp->ch_error = 0; 555 #endif 556 557 return; 558 } 559 560 void 561 siisata_reset_channel(struct ata_channel *chp, int flags) 562 { 563 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 564 struct siisata_channel *schp = (struct siisata_channel *)chp; 565 566 SIISATA_DEBUG_PRINT(("%s: %s\n", SIISATANAME(sc), __func__), 567 DEBUG_FUNCS); 568 569 if (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 570 schp->sch_sstatus) != SStatus_DET_DEV) { 571 log(LOG_CRIT, "%s port %d: reset failed\n", 572 SIISATANAME(sc), chp->ch_channel); 573 /* XXX and then ? */ 574 } 575 /* wait for ready */ 576 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 577 DELAY(10); 578 PRWRITE(sc, PRX(chp->ch_channel, PRO_SERROR), 579 PRREAD(sc, PRX(chp->ch_channel, PRO_SERROR))); 580 if (chp->ch_queue->active_xfer) { 581 chp->ch_queue->active_xfer->c_kill_xfer(chp, 582 chp->ch_queue->active_xfer, KILL_RESET); 583 } 584 585 return; 586 } 587 588 int 589 siisata_ata_addref(struct ata_drive_datas *drvp) 590 { 591 return 0; 592 } 593 594 void 595 siisata_ata_delref(struct ata_drive_datas *drvp) 596 { 597 return; 598 } 599 600 void 601 siisata_killpending(struct ata_drive_datas *drvp) 602 { 603 return; 604 } 605 606 void 607 siisata_probe_drive(struct ata_channel *chp) 608 { 609 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 610 struct siisata_channel *schp = (struct siisata_channel *)chp; 611 int i; 612 int s; 613 uint32_t sig; 614 int slot = SIISATA_NON_NCQ_SLOT; 615 struct siisata_prb *prb; 616 617 SIISATA_DEBUG_PRINT(("%s: %s: port %d start\n", SIISATANAME(sc), 618 __func__, chp->ch_channel), DEBUG_FUNCS); 619 620 /* XXX This should be done by other code. */ 621 for (i = 0; i < chp->ch_ndrive; i++) { 622 chp->ch_drive[i].chnl_softc = chp; 623 chp->ch_drive[i].drive = i; 624 } 625 626 switch (sata_reset_interface(chp, sc->sc_prt, schp->sch_scontrol, 627 schp->sch_sstatus)) { 628 case SStatus_DET_DEV: 629 /* wait for ready */ 630 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) 631 & PR_PS_PORT_READY)) 632 DELAY(10); 633 634 prb = schp->sch_prb[slot]; 635 memset(prb, 0, sizeof(struct siisata_prb)); 636 prb->prb_control = 637 htole16(PRB_CF_SOFT_RESET | PRB_CF_INTERRUPT_MASK); 638 639 siisata_activate_prb(schp, slot); 640 641 for(i = 0; i < 31000; i++) { 642 if (PRREAD(sc, PRX(chp->ch_channel, PRO_PSS)) & 643 PR_PXSS(slot)) 644 DELAY(1000); 645 else 646 break; 647 } 648 649 siisata_deactivate_prb(schp, slot); 650 651 /* read the signature out of the FIS */ 652 sig = 0; 653 sig |= (PRREAD(sc, PRSX(chp->ch_channel, slot, 654 PRSO_FIS+0x4)) & 0x00ffffff) << 8; 655 sig |= PRREAD(sc, PRSX(chp->ch_channel, slot, 656 PRSO_FIS+0xc)) & 0xff; 657 658 SIISATA_DEBUG_PRINT(("%s: %s: sig=0x%08x\n", SIISATANAME(sc), 659 __func__, sig), DEBUG_PROBE); 660 661 /* some ATAPI devices have bogus lower two bytes, sigh */ 662 if ((sig & 0xffff0000) == 0xeb140000) { 663 sig &= 0xffff0000; 664 sig |= 0x00000101; 665 } 666 667 s = splbio(); 668 switch (sig) { 669 case 0xeb140101: 670 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 671 break; 672 case 0x00000101: 673 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 674 break; 675 default: 676 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 677 aprint_verbose_dev(sc->sc_atac.atac_dev, 678 "Unrecognized signature 0x%08x on port %d. " 679 "Assuming it's a disk.\n", sig, chp->ch_channel); 680 break; 681 } 682 splx(s); 683 break; 684 default: 685 break; 686 } 687 688 SIISATA_DEBUG_PRINT(("%s: %s: port %d done\n", SIISATANAME(sc), 689 __func__, chp->ch_channel), DEBUG_PROBE); 690 return; 691 } 692 693 void 694 siisata_setup_channel(struct ata_channel *chp) 695 { 696 return; 697 } 698 699 int 700 siisata_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 701 { 702 struct ata_channel *chp = drvp->chnl_softc; 703 struct ata_xfer *xfer; 704 int ret; 705 int s; 706 707 SIISATA_DEBUG_PRINT(("%s: %s begins\n", 708 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 709 DEBUG_FUNCS); 710 711 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? 712 ATAXF_CANSLEEP : ATAXF_NOSLEEP); 713 if (xfer == NULL) 714 return ATACMD_TRY_AGAIN; 715 if (ata_c->flags & AT_POLL) 716 xfer->c_flags |= C_POLL; 717 if (ata_c->flags & AT_WAIT) 718 xfer->c_flags |= C_WAIT; 719 xfer->c_drive = drvp->drive; 720 xfer->c_databuf = ata_c->data; 721 xfer->c_bcount = ata_c->bcount; 722 xfer->c_cmd = ata_c; 723 xfer->c_start = siisata_cmd_start; 724 xfer->c_intr = siisata_cmd_complete; 725 xfer->c_kill_xfer = siisata_cmd_kill_xfer; 726 s = splbio(); 727 ata_exec_xfer(chp, xfer); 728 #ifdef DIAGNOSTIC 729 if ((ata_c->flags & AT_POLL) != 0 && 730 (ata_c->flags & AT_DONE) == 0) 731 panic("%s: polled command not done", __func__); 732 #endif 733 if (ata_c->flags & AT_DONE) { 734 ret = ATACMD_COMPLETE; 735 } else { 736 if (ata_c->flags & AT_WAIT) { 737 while ((ata_c->flags & AT_DONE) == 0) { 738 SIISATA_DEBUG_PRINT(("%s: %s: sleeping\n", 739 SIISATANAME( 740 (struct siisata_softc *)chp->ch_atac), 741 __func__), DEBUG_FUNCS); 742 tsleep(ata_c, PRIBIO, "siicmd", 0); 743 } 744 ret = ATACMD_COMPLETE; 745 } else { 746 ret = ATACMD_QUEUED; 747 } 748 } 749 splx(s); 750 SIISATA_DEBUG_PRINT( ("%s: %s ends\n", 751 SIISATANAME((struct siisata_softc *)chp->ch_atac), __func__), 752 DEBUG_FUNCS); 753 return ret; 754 } 755 756 void 757 siisata_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 758 { 759 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 760 struct siisata_channel *schp = (struct siisata_channel *)chp; 761 struct ata_command *ata_c = xfer->c_cmd; 762 int slot = SIISATA_NON_NCQ_SLOT; 763 struct siisata_prb *prb; 764 int i; 765 766 SIISATA_DEBUG_PRINT(("%s: %s port %d, slot %d\n", 767 SIISATANAME(sc), __func__, chp->ch_channel, slot), DEBUG_FUNCS); 768 769 chp->ch_status = 0; 770 chp->ch_error = 0; 771 772 prb = schp->sch_prb[slot]; 773 memset(prb, 0, sizeof(struct siisata_prb)); 774 775 satafis_rhd_construct_cmd(ata_c, prb->prb_fis); 776 777 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 778 779 if (siisata_dma_setup(chp, slot, 780 (ata_c->flags & (AT_READ | AT_WRITE)) ? ata_c->data : NULL, 781 ata_c->bcount, 782 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 783 ata_c->flags |= AT_DF; 784 siisata_cmd_complete(chp, xfer, slot); 785 return; 786 } 787 788 if (xfer->c_flags & C_POLL) { 789 /* polled command, disable interrupts */ 790 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 791 } 792 793 /* go for it */ 794 siisata_activate_prb(schp, slot); 795 796 if ((ata_c->flags & AT_POLL) == 0) { 797 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 798 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 799 siisata_timeout, chp); 800 goto out; 801 } 802 803 /* 804 * polled command 805 */ 806 for (i = 0; i < ata_c->timeout / 10; i++) { 807 if (ata_c->flags & AT_DONE) 808 break; 809 siisata_intr_port(schp); 810 DELAY(1000); 811 } 812 813 if ((ata_c->flags & AT_DONE) == 0) { 814 ata_c->flags |= AT_TIMEOU; 815 siisata_cmd_complete(chp, xfer, slot); 816 } 817 818 /* reenable interrupts */ 819 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 820 out: 821 SIISATA_DEBUG_PRINT( 822 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 823 return; 824 } 825 826 void 827 siisata_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 828 int reason) 829 { 830 int slot = SIISATA_NON_NCQ_SLOT; 831 832 struct ata_command *ata_c = xfer->c_cmd; 833 switch (reason) { 834 case KILL_GONE: 835 ata_c->flags |= AT_GONE; 836 break; 837 case KILL_RESET: 838 ata_c->flags |= AT_RESET; 839 break; 840 default: 841 panic("%s: port %d: unknown reason %d", 842 __func__, chp->ch_channel, reason); 843 } 844 siisata_cmd_done(chp, xfer, slot); 845 } 846 847 int 848 siisata_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 849 { 850 struct ata_command *ata_c = xfer->c_cmd; 851 #ifdef SIISATA_DEBUG 852 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 853 #endif 854 855 SIISATA_DEBUG_PRINT( 856 ("%s: %s\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 857 858 chp->ch_flags &= ~ATACH_IRQ_WAIT; 859 if (xfer->c_flags & C_TIMEOU) 860 ata_c->flags |= AT_TIMEOU; 861 else 862 callout_stop(&chp->ch_callout); 863 864 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 865 siisata_cmd_kill_xfer(chp, xfer, KILL_GONE); 866 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 867 wakeup(&chp->ch_queue->active_xfer); 868 return 0; 869 } 870 871 chp->ch_queue->active_xfer = NULL; 872 873 { 874 ata_c->r_head = 0; 875 ata_c->r_count = 0; 876 ata_c->r_sector = 0; 877 ata_c->r_cyl = 0; 878 if (chp->ch_status & WDCS_BSY) { 879 ata_c->flags |= AT_TIMEOU; 880 } else if (chp->ch_status & WDCS_ERR) { 881 ata_c->r_error = chp->ch_error; 882 ata_c->flags |= AT_ERROR; 883 } 884 } 885 siisata_cmd_done(chp, xfer, slot); 886 return 0; 887 } 888 889 void 890 siisata_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 891 { 892 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 893 struct siisata_channel *schp = (struct siisata_channel *)chp; 894 struct ata_command *ata_c = xfer->c_cmd; 895 int i; 896 uint16_t *idwordbuf; 897 898 SIISATA_DEBUG_PRINT( 899 ("%s: %s.\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 900 901 siisata_deactivate_prb(schp, slot); 902 903 if (ata_c->flags & (AT_READ | AT_WRITE)) { 904 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 905 schp->sch_datad[slot]->dm_mapsize, 906 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 907 BUS_DMASYNC_POSTWRITE); 908 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 909 } 910 911 idwordbuf = xfer->c_databuf; 912 913 /* correct the endianess of IDENTIFY data */ 914 if (ata_c->r_command == WDCC_IDENTIFY || 915 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 916 for (i = 0; i < (xfer->c_bcount / sizeof(*idwordbuf)); i++) { 917 idwordbuf[i] = le16toh(idwordbuf[i]); 918 } 919 } 920 921 ata_c->flags |= AT_DONE; 922 if (PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC))) 923 ata_c->flags |= AT_XFDONE; 924 925 ata_free_xfer(chp, xfer); 926 if (ata_c->flags & AT_WAIT) 927 wakeup(ata_c); 928 else if (ata_c->callback) 929 ata_c->callback(ata_c->callback_arg); 930 atastart(chp); 931 return; 932 } 933 934 int 935 siisata_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 936 { 937 struct ata_channel *chp = drvp->chnl_softc; 938 struct ata_xfer *xfer; 939 940 SIISATA_DEBUG_PRINT( ("%s: %s.\n", 941 SIISATANAME((struct siisata_softc *)chp->ch_atac), 942 __func__), DEBUG_FUNCS); 943 944 xfer = ata_get_xfer(ATAXF_NOSLEEP); 945 if (xfer == NULL) 946 return ATACMD_TRY_AGAIN; 947 if (ata_bio->flags & ATA_POLL) 948 xfer->c_flags |= C_POLL; 949 xfer->c_drive = drvp->drive; 950 xfer->c_cmd = ata_bio; 951 xfer->c_databuf = ata_bio->databuf; 952 xfer->c_bcount = ata_bio->bcount; 953 xfer->c_start = siisata_bio_start; 954 xfer->c_intr = siisata_bio_complete; 955 xfer->c_kill_xfer = siisata_bio_kill_xfer; 956 ata_exec_xfer(chp, xfer); 957 return (ata_bio->flags & ATA_ITSDONE) ? 958 ATACMD_COMPLETE : ATACMD_QUEUED; 959 } 960 961 void 962 siisata_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 963 { 964 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 965 struct siisata_channel *schp = (struct siisata_channel *)chp; 966 struct siisata_prb *prb; 967 struct ata_bio *ata_bio = xfer->c_cmd; 968 int slot = SIISATA_NON_NCQ_SLOT; 969 int i; 970 971 SIISATA_DEBUG_PRINT( 972 ("%s: %s port %d, slot %d\n", 973 SIISATANAME(sc), __func__, chp->ch_channel, slot), 974 DEBUG_FUNCS); 975 976 chp->ch_status = 0; 977 chp->ch_error = 0; 978 979 prb = schp->sch_prb[slot]; 980 memset(prb, 0, sizeof(struct siisata_prb)); 981 982 satafis_rhd_construct_bio(xfer, prb->prb_fis); 983 984 memset(prb->prb_atapi, 0, sizeof(prb->prb_atapi)); 985 986 if (siisata_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 987 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 988 ata_bio->error = ERR_DMA; 989 ata_bio->r_error = 0; 990 siisata_bio_complete(chp, xfer, slot); 991 return; 992 } 993 994 if (xfer->c_flags & C_POLL) { 995 /* polled command, disable interrupts */ 996 prb->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 997 } 998 999 siisata_activate_prb(schp, slot); 1000 1001 if ((ata_bio->flags & ATA_POLL) == 0) { 1002 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1003 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1004 siisata_timeout, chp); 1005 goto out; 1006 } 1007 1008 /* 1009 * polled command 1010 */ 1011 for (i = 0; i < ATA_DELAY / 10; i++) { 1012 if (ata_bio->flags & ATA_ITSDONE) 1013 break; 1014 siisata_intr_port(schp); 1015 DELAY(1000); 1016 } 1017 1018 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1019 out: 1020 SIISATA_DEBUG_PRINT( 1021 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1022 return; 1023 } 1024 1025 void 1026 siisata_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1027 int reason) 1028 { 1029 struct siisata_channel *schp = (struct siisata_channel *)chp; 1030 struct ata_bio *ata_bio = xfer->c_cmd; 1031 int drive = xfer->c_drive; 1032 int slot = SIISATA_NON_NCQ_SLOT; 1033 1034 SIISATA_DEBUG_PRINT(("%s: %s: port %d\n", 1035 SIISATANAME((struct siisata_softc *)chp->ch_atac), 1036 __func__, chp->ch_channel), DEBUG_FUNCS); 1037 1038 siisata_deactivate_prb(schp, slot); 1039 1040 ata_free_xfer(chp, xfer); 1041 ata_bio->flags |= ATA_ITSDONE; 1042 switch (reason) { 1043 case KILL_GONE: 1044 ata_bio->error = ERR_NODEV; 1045 break; 1046 case KILL_RESET: 1047 ata_bio->error = ERR_RESET; 1048 break; 1049 default: 1050 panic("%s: port %d: unknown reason %d", 1051 __func__, chp->ch_channel, reason); 1052 } 1053 ata_bio->r_error = WDCE_ABRT; 1054 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1055 } 1056 1057 int 1058 siisata_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 1059 { 1060 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1061 struct siisata_channel *schp = (struct siisata_channel *)chp; 1062 struct ata_bio *ata_bio = xfer->c_cmd; 1063 int drive = xfer->c_drive; 1064 1065 schp->sch_active_slots &= ~__BIT(slot); 1066 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1067 if (xfer->c_flags & C_TIMEOU) { 1068 ata_bio->error = TIMEOUT; 1069 } else { 1070 callout_stop(&chp->ch_callout); 1071 ata_bio->error = NOERROR; 1072 } 1073 1074 chp->ch_queue->active_xfer = NULL; 1075 1076 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1077 schp->sch_datad[slot]->dm_mapsize, 1078 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1079 BUS_DMASYNC_POSTWRITE); 1080 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1081 1082 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1083 siisata_bio_kill_xfer(chp, xfer, KILL_GONE); 1084 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1085 wakeup(&chp->ch_queue->active_xfer); 1086 return 0; 1087 } 1088 ata_free_xfer(chp, xfer); 1089 ata_bio->flags |= ATA_ITSDONE; 1090 if (chp->ch_status & WDCS_DWF) { 1091 ata_bio->error = ERR_DF; 1092 } else if (chp->ch_status & WDCS_ERR) { 1093 ata_bio->error = ERROR; 1094 ata_bio->r_error = chp->ch_error; 1095 } else if (chp->ch_status & WDCS_CORR) 1096 ata_bio->flags |= ATA_CORR; 1097 1098 SIISATA_DEBUG_PRINT(("%s: %s bcount: %ld", SIISATANAME(sc), 1099 __func__, ata_bio->bcount), DEBUG_XFERS); 1100 if (ata_bio->error == NOERROR) { 1101 if (ata_bio->flags & ATA_READ) 1102 ata_bio->bcount -= 1103 PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1104 else 1105 ata_bio->bcount = 0; 1106 } 1107 SIISATA_DEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1108 if (ata_bio->flags & ATA_POLL) 1109 return 1; 1110 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1111 atastart(chp); 1112 return 0; 1113 } 1114 1115 void 1116 siisata_timeout(void *v) 1117 { 1118 struct ata_channel *chp = (struct ata_channel *)v; 1119 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1120 int slot = SIISATA_NON_NCQ_SLOT; 1121 int s = splbio(); 1122 SIISATA_DEBUG_PRINT(("%s: %p\n", __func__, xfer), DEBUG_INTR); 1123 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1124 xfer->c_flags |= C_TIMEOU; 1125 xfer->c_intr(chp, xfer, slot); 1126 } 1127 splx(s); 1128 } 1129 1130 static int 1131 siisata_dma_setup(struct ata_channel *chp, int slot, void *data, 1132 size_t count, int op) 1133 { 1134 1135 int error, seg; 1136 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1137 struct siisata_channel *schp = (struct siisata_channel *)chp; 1138 1139 struct siisata_prb *prbp; 1140 1141 prbp = schp->sch_prb[slot]; 1142 1143 if (data == NULL) { 1144 goto end; 1145 } 1146 1147 error = bus_dmamap_load(sc->sc_dmat, schp->sch_datad[slot], 1148 data, count, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1149 if (error) { 1150 log(LOG_ERR, "%s port %d: " 1151 "failed to load xfer in slot %d: error %d\n", 1152 SIISATANAME(sc), chp->ch_channel, slot, error); 1153 return error; 1154 } 1155 1156 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1157 schp->sch_datad[slot]->dm_mapsize, 1158 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1159 1160 /* make sure it's clean */ 1161 memset(prbp->prb_sge, 0, SIISATA_NSGE * sizeof(struct siisata_prb)); 1162 1163 SIISATA_DEBUG_PRINT(("%s: %d segs, %ld count\n", __func__, 1164 schp->sch_datad[slot]->dm_nsegs, (long unsigned int) count), 1165 DEBUG_FUNCS | DEBUG_DEBUG); 1166 1167 for (seg = 0; seg < schp->sch_datad[slot]->dm_nsegs; seg++) { 1168 prbp->prb_sge[seg].sge_da = 1169 htole64(schp->sch_datad[slot]->dm_segs[seg].ds_addr); 1170 prbp->prb_sge[seg].sge_dc = 1171 htole32(schp->sch_datad[slot]->dm_segs[seg].ds_len); 1172 prbp->prb_sge[seg].sge_flags = htole32(0); 1173 } 1174 prbp->prb_sge[seg - 1].sge_flags |= htole32(SGE_FLAG_TRM); 1175 end: 1176 return 0; 1177 } 1178 1179 static void 1180 siisata_activate_prb(struct siisata_channel *schp, int slot) 1181 { 1182 struct siisata_softc *sc; 1183 bus_size_t offset; 1184 uint64_t pprb; 1185 1186 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1187 1188 KASSERTMSG(((schp->sch_active_slots & __BIT(slot)) == __BIT(slot)), 1189 ("%s: trying to activate active slot %d", SIISATANAME(sc), slot)); 1190 1191 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_PREWRITE); 1192 /* keep track of what's going on */ 1193 schp->sch_active_slots |= __BIT(slot); 1194 1195 offset = PRO_CARX(schp->ata_channel.ch_channel, slot); 1196 1197 pprb = schp->sch_bus_prb[slot]; 1198 1199 PRWRITE(sc, offset + 0, pprb >> 0); 1200 PRWRITE(sc, offset + 4, pprb >> 32); 1201 } 1202 1203 static void 1204 siisata_deactivate_prb(struct siisata_channel *schp, int slot) 1205 { 1206 struct siisata_softc *sc; 1207 1208 sc = (struct siisata_softc *)schp->ata_channel.ch_atac; 1209 1210 KASSERTMSG(((schp->sch_active_slots & __BIT(slot)) == 0), 1211 ("%s: trying to deactivate inactive slot %d", SIISATANAME(sc), 1212 slot)); 1213 1214 schp->sch_active_slots &= ~__BIT(slot); /* mark free */ 1215 SIISATA_PRB_SYNC(sc, schp, slot, BUS_DMASYNC_POSTWRITE); 1216 } 1217 1218 static void 1219 siisata_reinit_port(struct ata_channel *chp) 1220 { 1221 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1222 1223 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_PORT_INITIALIZE); 1224 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1225 DELAY(10); 1226 } 1227 1228 static void 1229 siisata_device_reset(struct ata_channel *chp) 1230 { 1231 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1232 1233 PRWRITE(sc, PRX(chp->ch_channel, PRO_PCS), PR_PC_DEVICE_RESET); 1234 while (!(PRREAD(sc, PRX(chp->ch_channel, PRO_PS)) & PR_PS_PORT_READY)) 1235 DELAY(10); 1236 } 1237 1238 1239 #if NATAPIBUS > 0 1240 void 1241 siisata_atapibus_attach(struct atabus_softc *ata_sc) 1242 { 1243 struct ata_channel *chp = ata_sc->sc_chan; 1244 struct atac_softc *atac = chp->ch_atac; 1245 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1246 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1247 1248 /* 1249 * Fill in the scsipi_adapter. 1250 */ 1251 adapt->adapt_dev = atac->atac_dev; 1252 adapt->adapt_nchannels = atac->atac_nchannels; 1253 adapt->adapt_request = siisata_atapi_scsipi_request; 1254 adapt->adapt_minphys = siisata_atapi_minphys; 1255 atac->atac_atapi_adapter.atapi_probe_device = 1256 siisata_atapi_probe_device; 1257 1258 /* 1259 * Fill in the scsipi_channel. 1260 */ 1261 memset(chan, 0, sizeof(*chan)); 1262 chan->chan_adapter = adapt; 1263 chan->chan_bustype = &siisata_atapi_bustype; 1264 chan->chan_channel = chp->ch_channel; 1265 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1266 chan->chan_openings = 1; 1267 chan->chan_max_periph = 1; 1268 chan->chan_ntargets = 1; 1269 chan->chan_nluns = 1; 1270 1271 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1272 atapiprint); 1273 } 1274 1275 void 1276 siisata_atapi_minphys(struct buf *bp) 1277 { 1278 if (bp->b_bcount > MAXPHYS) 1279 bp->b_bcount = MAXPHYS; 1280 minphys(bp); 1281 } 1282 1283 /* 1284 * Kill off all pending xfers for a periph. 1285 * 1286 * Must be called at splbio(). 1287 */ 1288 void 1289 siisata_atapi_kill_pending(struct scsipi_periph *periph) 1290 { 1291 struct atac_softc *atac = 1292 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1293 struct ata_channel *chp = 1294 atac->atac_channels[periph->periph_channel->chan_channel]; 1295 1296 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1297 } 1298 1299 void 1300 siisata_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1301 int reason) 1302 { 1303 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1304 1305 /* remove this command from xfer queue */ 1306 switch (reason) { 1307 case KILL_GONE: 1308 sc_xfer->error = XS_DRIVER_STUFFUP; 1309 break; 1310 case KILL_RESET: 1311 sc_xfer->error = XS_RESET; 1312 break; 1313 default: 1314 panic("%s: port %d: unknown reason %d", 1315 __func__, chp->ch_channel, reason); 1316 } 1317 ata_free_xfer(chp, xfer); 1318 scsipi_done(sc_xfer); 1319 } 1320 1321 void 1322 siisata_atapi_probe_device(struct atapibus_softc *sc, int target) 1323 { 1324 struct scsipi_channel *chan = sc->sc_channel; 1325 struct scsipi_periph *periph; 1326 struct ataparams ids; 1327 struct ataparams *id = &ids; 1328 struct siisata_softc *siic = 1329 device_private(chan->chan_adapter->adapt_dev); 1330 struct atac_softc *atac = &siic->sc_atac; 1331 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1332 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1333 struct scsipibus_attach_args sa; 1334 char serial_number[21], model[41], firmware_revision[9]; 1335 int s; 1336 1337 /* skip if already attached */ 1338 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1339 return; 1340 1341 /* if no ATAPI device detected at attach time, skip */ 1342 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1343 SIISATA_DEBUG_PRINT(("%s: drive %d " 1344 "not present\n", __func__, target), DEBUG_PROBE); 1345 return; 1346 } 1347 1348 /* Some ATAPI devices need a bit more time after software reset. */ 1349 DELAY(5000); 1350 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1351 #ifdef ATAPI_DEBUG_PROBE 1352 log(LOG_DEBUG, "%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1353 device_xname(sc->sc_dev), target, 1354 id->atap_config & ATAPI_CFG_CMD_MASK, 1355 id->atap_config & ATAPI_CFG_DRQ_MASK); 1356 #endif 1357 periph = scsipi_alloc_periph(M_NOWAIT); 1358 if (periph == NULL) { 1359 aprint_error_dev(sc->sc_dev, 1360 "%s: unable to allocate periph for " 1361 "channel %d drive %d\n", __func__, 1362 chp->ch_channel, target); 1363 return; 1364 } 1365 periph->periph_dev = NULL; 1366 periph->periph_channel = chan; 1367 periph->periph_switch = &atapi_probe_periphsw; 1368 periph->periph_target = target; 1369 periph->periph_lun = 0; 1370 periph->periph_quirks = PQUIRK_ONLYBIG; 1371 1372 #ifdef SCSIPI_DEBUG 1373 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1374 SCSIPI_DEBUG_TARGET == target) 1375 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1376 #endif 1377 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1378 if (id->atap_config & ATAPI_CFG_REMOV) 1379 periph->periph_flags |= PERIPH_REMOVABLE; 1380 if (periph->periph_type == T_SEQUENTIAL) { 1381 s = splbio(); 1382 drvp->drive_flags |= DRIVE_ATAPIST; 1383 splx(s); 1384 } 1385 1386 sa.sa_periph = periph; 1387 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1388 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1389 T_REMOV : T_FIXED; 1390 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1391 scsipi_strvis((u_char *)serial_number, 20, 1392 id->atap_serial, 20); 1393 scsipi_strvis((u_char *)firmware_revision, 8, 1394 id->atap_revision, 8); 1395 sa.sa_inqbuf.vendor = model; 1396 sa.sa_inqbuf.product = serial_number; 1397 sa.sa_inqbuf.revision = firmware_revision; 1398 1399 /* 1400 * Determine the operating mode capabilities of the device. 1401 */ 1402 if ((id->atap_config & ATAPI_CFG_CMD_MASK) 1403 == ATAPI_CFG_CMD_16) { 1404 periph->periph_cap |= PERIPH_CAP_CMD16; 1405 1406 /* configure port for packet length */ 1407 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCS), 1408 PR_PC_PACKET_LENGTH); 1409 } else { 1410 PRWRITE(siic, PRX(chp->ch_channel, PRO_PCC), 1411 PR_PC_PACKET_LENGTH); 1412 } 1413 1414 /* XXX This is gross. */ 1415 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1416 1417 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1418 1419 if (drvp->drv_softc) 1420 ata_probe_caps(drvp); 1421 else { 1422 s = splbio(); 1423 drvp->drive_flags &= ~DRIVE_ATAPI; 1424 splx(s); 1425 } 1426 } else { 1427 SIISATA_DEBUG_PRINT(("%s: ATAPI_IDENTIFY_DEVICE " 1428 "failed for drive %s:%d:%d: error 0x%x\n", 1429 __func__, SIISATANAME(siic), chp->ch_channel, target, 1430 chp->ch_error), DEBUG_PROBE); 1431 s = splbio(); 1432 drvp->drive_flags &= ~DRIVE_ATAPI; 1433 splx(s); 1434 } 1435 } 1436 1437 void 1438 siisata_atapi_scsipi_request(struct scsipi_channel *chan, 1439 scsipi_adapter_req_t req, void *arg) 1440 { 1441 struct scsipi_adapter *adapt = chan->chan_adapter; 1442 struct scsipi_periph *periph; 1443 struct scsipi_xfer *sc_xfer; 1444 struct siisata_softc *sc = device_private(adapt->adapt_dev); 1445 struct atac_softc *atac = &sc->sc_atac; 1446 struct ata_xfer *xfer; 1447 int channel = chan->chan_channel; 1448 int drive, s; 1449 1450 switch (req) { 1451 case ADAPTER_REQ_RUN_XFER: 1452 sc_xfer = arg; 1453 periph = sc_xfer->xs_periph; 1454 drive = periph->periph_target; 1455 1456 SIISATA_DEBUG_PRINT(("%s: %s:%d:%d\n", __func__, 1457 device_xname(atac->atac_dev), channel, drive), 1458 DEBUG_XFERS); 1459 1460 if (!device_is_active(atac->atac_dev)) { 1461 sc_xfer->error = XS_DRIVER_STUFFUP; 1462 scsipi_done(sc_xfer); 1463 return; 1464 } 1465 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1466 if (xfer == NULL) { 1467 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1468 scsipi_done(sc_xfer); 1469 return; 1470 } 1471 1472 if (sc_xfer->xs_control & XS_CTL_POLL) 1473 xfer->c_flags |= C_POLL; 1474 xfer->c_drive = drive; 1475 xfer->c_flags |= C_ATAPI; 1476 xfer->c_cmd = sc_xfer; 1477 xfer->c_databuf = sc_xfer->data; 1478 xfer->c_bcount = sc_xfer->datalen; 1479 xfer->c_start = siisata_atapi_start; 1480 xfer->c_intr = siisata_atapi_complete; 1481 xfer->c_kill_xfer = siisata_atapi_kill_xfer; 1482 xfer->c_dscpoll = 0; 1483 s = splbio(); 1484 ata_exec_xfer(atac->atac_channels[channel], xfer); 1485 #ifdef DIAGNOSTIC 1486 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1487 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1488 panic("%s: polled command not done", __func__); 1489 #endif 1490 splx(s); 1491 return; 1492 1493 default: 1494 /* Not supported, nothing to do. */ 1495 ; 1496 } 1497 } 1498 1499 void 1500 siisata_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1501 { 1502 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1503 struct siisata_channel *schp = (struct siisata_channel *)chp; 1504 struct siisata_prb *prbp; 1505 1506 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1507 1508 int slot = SIISATA_NON_NCQ_SLOT; 1509 int i; 1510 1511 SIISATA_DEBUG_PRINT( ("%s: %s:%d:%d, scsi flags 0x%x\n", __func__, 1512 SIISATANAME(sc), chp->ch_channel, 1513 chp->ch_drive[xfer->c_drive].drive, sc_xfer->xs_control), 1514 DEBUG_XFERS); 1515 1516 chp->ch_status = 0; 1517 chp->ch_error = 0; 1518 1519 prbp = schp->sch_prb[slot]; 1520 memset(prbp, 0, sizeof(struct siisata_prb)); 1521 1522 1523 /* fill in direction for ATAPI command */ 1524 if ((sc_xfer->xs_control & XS_CTL_DATA_IN)) 1525 prbp->prb_control |= htole16(PRB_CF_PACKET_READ); 1526 if ((sc_xfer->xs_control & XS_CTL_DATA_OUT)) 1527 prbp->prb_control |= htole16(PRB_CF_PACKET_WRITE); 1528 1529 satafis_rhd_construct_atapi(xfer, prbp->prb_fis); 1530 1531 /* copy over ATAPI command */ 1532 memcpy(prbp->prb_atapi, sc_xfer->cmd, sc_xfer->cmdlen); 1533 1534 if (siisata_dma_setup(chp, slot, 1535 (sc_xfer->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ? 1536 xfer->c_databuf : NULL, 1537 xfer->c_bcount, 1538 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1539 BUS_DMA_READ : BUS_DMA_WRITE) 1540 ) 1541 panic("%s", __func__); 1542 1543 if (xfer->c_flags & C_POLL) { 1544 /* polled command, disable interrupts */ 1545 prbp->prb_control = htole16(PRB_CF_INTERRUPT_MASK); 1546 } 1547 1548 siisata_activate_prb(schp, slot); 1549 1550 if ((xfer->c_flags & C_POLL) == 0) { 1551 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1552 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1553 siisata_timeout, chp); 1554 goto out; 1555 } 1556 1557 /* 1558 * polled command 1559 */ 1560 for (i = 0; i < ATA_DELAY / 10; i++) { 1561 if (sc_xfer->xs_status & XS_STS_DONE) 1562 break; 1563 siisata_intr_port(schp); 1564 DELAY(1000); 1565 } 1566 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1567 sc_xfer->error = XS_TIMEOUT; 1568 siisata_atapi_complete(chp, xfer, slot); 1569 } 1570 /* reenable interrupts */ 1571 GRWRITE(sc, GR_GC, GRREAD(sc, GR_GC) | GR_GC_PXIE(chp->ch_channel)); 1572 out: 1573 SIISATA_DEBUG_PRINT( 1574 ("%s: %s: done\n", SIISATANAME(sc), __func__), DEBUG_FUNCS); 1575 return; 1576 } 1577 1578 int 1579 siisata_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, 1580 int slot) 1581 { 1582 struct siisata_softc *sc = (struct siisata_softc *)chp->ch_atac; 1583 struct siisata_channel *schp = (struct siisata_channel *)chp; 1584 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1585 1586 SIISATA_DEBUG_PRINT( 1587 ("%s: %s()\n", SIISATANAME(sc), __func__), DEBUG_INTR); 1588 1589 /* this comamnd is not active any more */ 1590 schp->sch_active_slots &= ~__BIT(slot); 1591 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1592 if (xfer->c_flags & C_TIMEOU) { 1593 sc_xfer->error = XS_TIMEOUT; 1594 } else { 1595 callout_stop(&chp->ch_callout); 1596 sc_xfer->error = XS_NOERROR; 1597 } 1598 1599 bus_dmamap_sync(sc->sc_dmat, schp->sch_datad[slot], 0, 1600 schp->sch_datad[slot]->dm_mapsize, 1601 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1602 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1603 bus_dmamap_unload(sc->sc_dmat, schp->sch_datad[slot]); 1604 1605 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1606 siisata_atapi_kill_xfer(chp, xfer, KILL_GONE); 1607 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1608 wakeup(&chp->ch_queue->active_xfer); 1609 return 0; /* XXX verify */ 1610 } 1611 1612 chp->ch_queue->active_xfer = NULL; 1613 ata_free_xfer(chp, xfer); 1614 1615 sc_xfer->resid = sc_xfer->datalen; 1616 sc_xfer->resid -= PRREAD(sc, PRSX(chp->ch_channel, slot, PRSO_RTC)); 1617 SIISATA_DEBUG_PRINT(("%s: %s datalen %d resid %d\n", SIISATANAME(sc), 1618 __func__, sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1619 if ((chp->ch_status & WDCS_ERR) && 1620 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1621 sc_xfer->resid == sc_xfer->datalen)) { 1622 sc_xfer->error = XS_SHORTSENSE; 1623 sc_xfer->sense.atapi_sense = chp->ch_error; 1624 if ((sc_xfer->xs_periph->periph_quirks & 1625 PQUIRK_NOSENSE) == 0) { 1626 /* request sense */ 1627 sc_xfer->error = XS_BUSY; 1628 sc_xfer->status = SCSI_CHECK; 1629 } 1630 } 1631 scsipi_done(sc_xfer); 1632 atastart(chp); 1633 return 0; /* XXX verify */ 1634 } 1635 1636 #endif /* NATAPIBUS */ 1637
Indexes created Fri Sep 26 20:09:58 GMT 2025