siop.c revision 1.21.2.1
1 /* $NetBSD: siop.c,v 1.21.2.1 2000/06/26 08:49:11 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 42 #include <machine/endian.h> 43 #include <machine/bus.h> 44 45 #include <vm/vm.h> 46 #include <vm/vm_param.h> 47 #include <vm/vm_kern.h> 48 49 #include <dev/microcode/siop/siop.out> 50 51 #include <dev/scsipi/scsi_all.h> 52 #include <dev/scsipi/scsi_message.h> 53 #include <dev/scsipi/scsipi_all.h> 54 55 #include <dev/scsipi/scsiconf.h> 56 57 #include <dev/ic/siopreg.h> 58 #include <dev/ic/siopvar.h> 59 #include <dev/ic/siopvar_common.h> 60 61 #undef DEBUG 62 #undef DEBUG_DR 63 #undef DEBUG_INTR 64 #undef DEBUG_SHED 65 #undef DUMP_SCRIPT 66 67 #define SIOP_STATS 68 69 #ifndef SIOP_DEFAULT_TARGET 70 #define SIOP_DEFAULT_TARGET 7 71 #endif 72 73 /* number of cmd descriptors per block */ 74 #define SIOP_NCMDPB (NBPG / sizeof(struct siop_xfer)) 75 76 void siop_reset __P((struct siop_softc *)); 77 void siop_handle_reset __P((struct siop_softc *)); 78 void siop_scsicmd_end __P((struct siop_cmd *)); 79 void siop_start __P((struct siop_softc *)); 80 void siop_timeout __P((void *)); 81 int siop_scsicmd __P((struct scsipi_xfer *)); 82 void siop_dump_script __P((struct siop_softc *)); 83 int siop_morecbd __P((struct siop_softc *)); 84 85 struct scsipi_adapter siop_adapter = { 86 0, 87 siop_scsicmd, 88 siop_minphys, 89 siop_ioctl, 90 NULL, 91 NULL, 92 }; 93 94 struct scsipi_device siop_dev = { 95 NULL, 96 NULL, 97 NULL, 98 NULL, 99 }; 100 101 #ifdef SIOP_STATS 102 static int siop_stat_intr = 0; 103 static int siop_stat_intr_shortxfer = 0; 104 static int siop_stat_intr_sdp = 0; 105 static int siop_stat_intr_done = 0; 106 static int siop_stat_intr_reselect = 0; 107 static int siop_stat_intr_xferdisc = 0; 108 void siop_printstats __P((void)); 109 #define INCSTAT(x) x++ 110 #else 111 #define INCSTAT(x) 112 #endif 113 114 static __inline__ void siop_table_sync __P((struct siop_cmd *, int)); 115 static __inline__ void 116 siop_table_sync(siop_cmd, ops) 117 struct siop_cmd *siop_cmd; 118 int ops; 119 { 120 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 121 bus_addr_t offset; 122 123 offset = siop_cmd->dsa - 124 siop_cmd->siop_cbdp->xferdma->dm_segs[0].ds_addr; 125 bus_dmamap_sync(sc->sc_dmat, siop_cmd->siop_cbdp->xferdma, offset, 126 sizeof(struct siop_xfer), ops); 127 } 128 129 static __inline__ void siop_shed_sync __P((struct siop_softc *, int)); 130 static __inline__ void 131 siop_shed_sync(sc, ops) 132 struct siop_softc *sc; 133 int ops; 134 { 135 bus_dmamap_sync(sc->sc_dmat, sc->sc_sheddma, 0, NBPG, ops); 136 } 137 138 void 139 siop_attach(sc) 140 struct siop_softc *sc; 141 { 142 int error, i; 143 bus_dma_segment_t seg; 144 int rseg; 145 146 /* 147 * Allocate DMA-safe memory for the script and script scheduler 148 * and map it. 149 */ 150 if ((sc->features & SF_CHIP_RAM) == 0) { 151 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, 152 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 153 if (error) { 154 printf("%s: unable to allocate script DMA memory, " 155 "error = %d\n", sc->sc_dev.dv_xname, error); 156 return; 157 } 158 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 159 (caddr_t *)&sc->sc_script, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 160 if (error) { 161 printf("%s: unable to map script DMA memory, " 162 "error = %d\n", sc->sc_dev.dv_xname, error); 163 return; 164 } 165 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, 166 NBPG, 0, BUS_DMA_NOWAIT, &sc->sc_scriptdma); 167 if (error) { 168 printf("%s: unable to create script DMA map, " 169 "error = %d\n", sc->sc_dev.dv_xname, error); 170 return; 171 } 172 error = bus_dmamap_load(sc->sc_dmat, sc->sc_scriptdma, 173 sc->sc_script, 174 NBPG, NULL, BUS_DMA_NOWAIT); 175 if (error) { 176 printf("%s: unable to load script DMA map, " 177 "error = %d\n", sc->sc_dev.dv_xname, error); 178 return; 179 } 180 sc->sc_scriptaddr = sc->sc_scriptdma->dm_segs[0].ds_addr; 181 } 182 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, 183 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 184 if (error) { 185 printf("%s: unable to allocate scheduler DMA memory, " 186 "error = %d\n", sc->sc_dev.dv_xname, error); 187 return; 188 } 189 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 190 (caddr_t *)&sc->sc_shed, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 191 if (error) { 192 printf("%s: unable to map scheduler DMA memory, error = %d\n", 193 sc->sc_dev.dv_xname, error); 194 return; 195 } 196 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, 197 NBPG, 0, BUS_DMA_NOWAIT, &sc->sc_sheddma); 198 if (error) { 199 printf("%s: unable to create scheduler DMA map, error = %d\n", 200 sc->sc_dev.dv_xname, error); 201 return; 202 } 203 error = bus_dmamap_load(sc->sc_dmat, sc->sc_sheddma, sc->sc_shed, 204 NBPG, NULL, BUS_DMA_NOWAIT); 205 if (error) { 206 printf("%s: unable to load scheduler DMA map, error = %d\n", 207 sc->sc_dev.dv_xname, error); 208 return; 209 } 210 TAILQ_INIT(&sc->free_list); 211 TAILQ_INIT(&sc->cmds); 212 /* compute number of scheduler slots */ 213 sc->sc_nshedslots = ( 214 NBPG /* memory size allocated for scheduler */ 215 - sizeof(endslot_script) /* memory needed at end of scheduler */ 216 ) / (sizeof(slot_script) - 8); 217 sc->sc_currshedslot = 0; 218 #ifdef DEBUG 219 printf("%s: script size = %d, PHY addr=0x%x, VIRT=%p nslots %d\n", 220 sc->sc_dev.dv_xname, (int)sizeof(siop_script), 221 sc->sc_scriptaddr, sc->sc_script, sc->sc_nshedslots); 222 #endif 223 224 sc->sc_link.adapter_softc = sc; 225 sc->sc_link.openings = 1; 226 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 227 sc->sc_link.scsipi_scsi.max_target = 228 (sc->features & SF_BUS_WIDE) ? 15 : 7; 229 sc->sc_link.scsipi_scsi.max_lun = 7; 230 sc->sc_link.scsipi_scsi.adapter_target = bus_space_read_1(sc->sc_rt, 231 sc->sc_rh, SIOP_SCID); 232 if (sc->sc_link.scsipi_scsi.adapter_target == 0 || 233 sc->sc_link.scsipi_scsi.adapter_target > 234 sc->sc_link.scsipi_scsi.max_target) 235 sc->sc_link.scsipi_scsi.adapter_target = SIOP_DEFAULT_TARGET; 236 sc->sc_link.type = BUS_SCSI; 237 sc->sc_link.adapter = &siop_adapter; 238 sc->sc_link.device = &siop_dev; 239 sc->sc_link.flags = 0; 240 241 for (i = 0; i < 16; i++) 242 sc->targets[i] = NULL; 243 244 /* find min/max sync period for this chip */ 245 sc->maxsync = 0; 246 sc->minsync = 255; 247 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); i++) { 248 if (sc->clock_period != scf_period[i].clock) 249 continue; 250 if (sc->maxsync < scf_period[i].period) 251 sc->maxsync = scf_period[i].period; 252 if (sc->minsync > scf_period[i].period) 253 sc->minsync = scf_period[i].period; 254 } 255 if (sc->maxsync == 255 || sc->minsync == 0) 256 panic("siop: can't find my sync parameters\n"); 257 siop_reset(sc); 258 #ifdef DUMP_SCRIPT 259 siop_dump_script(sc); 260 #endif 261 262 config_found((struct device*)sc, &sc->sc_link, scsiprint); 263 } 264 265 void 266 siop_reset(sc) 267 struct siop_softc *sc; 268 { 269 int i, j; 270 u_int32_t *scr; 271 bus_addr_t physaddr; 272 273 siop_common_reset(sc); 274 275 /* copy and patch the script */ 276 if (sc->features & SF_CHIP_RAM) { 277 bus_space_write_region_4(sc->sc_ramt, sc->sc_ramh, 0, 278 siop_script, sizeof(siop_script) / sizeof(siop_script[0])); 279 for (j = 0; j < 280 (sizeof(E_script_abs_shed_Used) / 281 sizeof(E_script_abs_shed_Used[0])); 282 j++) { 283 bus_space_write_4(sc->sc_ramt, sc->sc_ramh, 284 E_script_abs_shed_Used[j] * 4, 285 sc->sc_sheddma->dm_segs[0].ds_addr); 286 } 287 } else { 288 for (j = 0; 289 j < (sizeof(siop_script) / sizeof(siop_script[0])); j++) { 290 sc->sc_script[j] = htole32(siop_script[j]); 291 } 292 for (j = 0; j < 293 (sizeof(E_script_abs_shed_Used) / 294 sizeof(E_script_abs_shed_Used[0])); 295 j++) { 296 sc->sc_script[E_script_abs_shed_Used[j]] = 297 htole32(sc->sc_sheddma->dm_segs[0].ds_addr); 298 } 299 } 300 /* copy and init the scheduler slots script */ 301 for (i = 0; i < sc->sc_nshedslots; i++) { 302 scr = &sc->sc_shed[(Ent_nextslot / 4) * i]; 303 physaddr = sc->sc_sheddma->dm_segs[0].ds_addr + 304 Ent_nextslot * i; 305 for (j = 0; j < (sizeof(slot_script) / sizeof(slot_script[0])); 306 j++) { 307 scr[j] = htole32(slot_script[j]); 308 } 309 /* 310 * save current jump offset and patch MOVE MEMORY operands 311 * to restore it. 312 */ 313 scr[Ent_slotdata/4 + 1] = scr[Ent_slot/4 + 1]; 314 scr[E_slot_nextp_Used[0]] = htole32(physaddr + Ent_slot + 4); 315 scr[E_slot_shed_addrsrc_Used[0]] = htole32(physaddr + 316 Ent_slotdata + 4); 317 /* JUMP selected, in main script */ 318 scr[E_slot_abs_selected_Used[0]] = 319 htole32(sc->sc_scriptaddr + Ent_selected); 320 /* JUMP addr if SELECT fail */ 321 scr[E_slot_abs_reselect_Used[0]] = 322 htole32(sc->sc_scriptaddr + Ent_reselect); 323 } 324 /* Now the final JUMP */ 325 scr = &sc->sc_shed[(Ent_nextslot / 4) * sc->sc_nshedslots]; 326 for (j = 0; j < (sizeof(endslot_script) / sizeof(endslot_script[0])); 327 j++) { 328 scr[j] = htole32(endslot_script[j]); 329 } 330 scr[E_endslot_abs_reselect_Used[0]] = 331 htole32(sc->sc_scriptaddr + Ent_reselect); 332 333 /* start script */ 334 if ((sc->features & SF_CHIP_RAM) == 0) { 335 bus_dmamap_sync(sc->sc_dmat, sc->sc_scriptdma, 0, NBPG, 336 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 337 } 338 siop_shed_sync(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 339 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 340 sc->sc_scriptaddr + Ent_reselect); 341 } 342 343 #if 0 344 #define CALL_SCRIPT(ent) do {\ 345 printf ("start script DSA 0x%lx DSP 0x%lx\n", \ 346 siop_cmd->dsa, \ 347 sc->sc_scriptaddr + ent); \ 348 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \ 349 } while (0) 350 #else 351 #define CALL_SCRIPT(ent) do {\ 352 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \ 353 } while (0) 354 #endif 355 356 int 357 siop_intr(v) 358 void *v; 359 { 360 struct siop_softc *sc = v; 361 struct siop_target *siop_target; 362 struct siop_cmd *siop_cmd; 363 struct scsipi_xfer *xs; 364 int istat, sist0, sist1, sstat1, dstat, scntl1; 365 u_int32_t irqcode; 366 int need_reset = 0; 367 int offset, target, lun; 368 bus_addr_t dsa; 369 struct siop_cbd *cbdp; 370 371 istat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT); 372 if ((istat & (ISTAT_INTF | ISTAT_DIP | ISTAT_SIP)) == 0) 373 return 0; 374 INCSTAT(siop_stat_intr); 375 if (istat & ISTAT_INTF) { 376 printf("INTRF\n"); 377 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_INTF); 378 } 379 /* use DSA to find the current siop_cmd */ 380 dsa = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA); 381 for (cbdp = TAILQ_FIRST(&sc->cmds); cbdp != NULL; 382 cbdp = TAILQ_NEXT(cbdp, next)) { 383 if (dsa >= cbdp->xferdma->dm_segs[0].ds_addr && 384 dsa < cbdp->xferdma->dm_segs[0].ds_addr + NBPG) { 385 dsa -= cbdp->xferdma->dm_segs[0].ds_addr; 386 siop_cmd = &cbdp->cmds[dsa / sizeof(struct siop_xfer)]; 387 siop_table_sync(siop_cmd, 388 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 389 break; 390 } 391 } 392 if (cbdp == NULL) { 393 siop_cmd = NULL; 394 } 395 if (istat & ISTAT_DIP) { 396 u_int32_t *p; 397 dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DSTAT); 398 if (dstat & DSTAT_SSI) { 399 printf("single step dsp 0x%08x dsa 0x08%x\n", 400 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 401 sc->sc_scriptaddr), 402 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA)); 403 if ((dstat & ~(DSTAT_DFE | DSTAT_SSI)) == 0 && 404 (istat & ISTAT_SIP) == 0) { 405 bus_space_write_1(sc->sc_rt, sc->sc_rh, 406 SIOP_DCNTL, bus_space_read_1(sc->sc_rt, 407 sc->sc_rh, SIOP_DCNTL) | DCNTL_STD); 408 } 409 return 1; 410 } 411 if (dstat & ~(DSTAT_SIR | DSTAT_DFE | DSTAT_SSI)) { 412 printf("DMA IRQ:"); 413 if (dstat & DSTAT_IID) 414 printf(" Illegal instruction"); 415 if (dstat & DSTAT_ABRT) 416 printf(" abort"); 417 if (dstat & DSTAT_BF) 418 printf(" bus fault"); 419 if (dstat & DSTAT_MDPE) 420 printf(" parity"); 421 if (dstat & DSTAT_DFE) 422 printf(" dma fifo empty"); 423 printf(", DSP=0x%x DSA=0x%x: ", 424 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 425 sc->sc_scriptaddr), 426 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA)); 427 p = sc->sc_script + 428 (bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 429 sc->sc_scriptaddr - 8) / 4; 430 printf("0x%x 0x%x 0x%x 0x%x\n", le32toh(p[0]), le32toh(p[1]), 431 le32toh(p[2]), le32toh(p[3])); 432 if (siop_cmd) 433 printf("last msg_in=0x%x status=0x%x\n", 434 siop_cmd->siop_table->msg_in[0], 435 le32toh(siop_cmd->siop_table->status)); 436 else 437 printf("%s: current DSA invalid\n", 438 sc->sc_dev.dv_xname); 439 need_reset = 1; 440 } 441 } 442 if (istat & ISTAT_SIP) { 443 /* 444 * SCSI interrupt. If current command is not active, 445 * we don't need siop_cmd 446 */ 447 if (siop_cmd && siop_cmd->status != CMDST_ACTIVE && 448 siop_cmd->status != CMDST_SENSE_ACTIVE) { 449 siop_cmd = NULL; 450 } 451 if (istat & ISTAT_DIP) 452 delay(10); 453 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 454 delay(10); 455 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 456 sstat1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1); 457 #ifdef DEBUG_INTR 458 printf("scsi interrupt, sist0=0x%x sist1=0x%x sstat1=0x%x " 459 "DSA=0x%x DSP=0x%lx\n", sist0, sist1, 460 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1), 461 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA), 462 (u_long)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 463 sc->sc_scriptaddr)); 464 #endif 465 if (siop_cmd) { 466 xs = siop_cmd->xs; 467 siop_target = siop_cmd->siop_target; 468 } 469 if (sist0 & SIST0_RST) { 470 siop_handle_reset(sc); 471 siop_start(sc); 472 /* no table to flush here */ 473 return 1; 474 } 475 if (sist0 & SIST0_SGE) { 476 if (siop_cmd) 477 scsi_print_addr(xs->sc_link); 478 else 479 printf("%s:", sc->sc_dev.dv_xname); 480 printf("scsi gross error\n"); 481 goto reset; 482 } 483 if ((sist0 & SIST0_MA) && need_reset == 0) { 484 if (siop_cmd) { 485 int scratcha0; 486 dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 487 SIOP_DSTAT); 488 /* 489 * first restore DSA, in case we were in a S/G 490 * operation. 491 */ 492 bus_space_write_4(sc->sc_rt, sc->sc_rh, 493 SIOP_DSA, siop_cmd->dsa); 494 scratcha0 = bus_space_read_1(sc->sc_rt, 495 sc->sc_rh, SIOP_SCRATCHA); 496 switch (sstat1 & SSTAT1_PHASE_MASK) { 497 case SSTAT1_PHASE_STATUS: 498 /* 499 * previous phase may be aborted for any reason 500 * ( for example, the target has less data to 501 * transfer than requested). Just go to status 502 * and the command should terminate. 503 */ 504 INCSTAT(siop_stat_intr_shortxfer); 505 CALL_SCRIPT(Ent_status); 506 if ((dstat & DSTAT_DFE) == 0) 507 siop_clearfifo(sc); 508 /* no table to flush here */ 509 return 1; 510 case SSTAT1_PHASE_MSGIN: 511 /* 512 * target may be ready to disconnect 513 * Save data pointers just in case. 514 */ 515 INCSTAT(siop_stat_intr_xferdisc); 516 if (scratcha0 & A_flag_data) 517 siop_sdp(siop_cmd); 518 else if ((dstat & DSTAT_DFE) == 0) 519 siop_clearfifo(sc); 520 bus_space_write_1(sc->sc_rt, sc->sc_rh, 521 SIOP_SCRATCHA, 522 scratcha0 & ~A_flag_data); 523 siop_table_sync(siop_cmd, 524 BUS_DMASYNC_PREREAD | 525 BUS_DMASYNC_PREWRITE); 526 CALL_SCRIPT(Ent_msgin); 527 return 1; 528 } 529 printf("%s: unexpected phase mismatch %d\n", 530 sc->sc_dev.dv_xname, 531 sstat1 & SSTAT1_PHASE_MASK); 532 } else { 533 printf("%s: phase mismatch without command\n", 534 sc->sc_dev.dv_xname); 535 } 536 need_reset = 1; 537 } 538 if (sist0 & SIST0_PAR) { 539 /* parity error, reset */ 540 if (siop_cmd) 541 scsi_print_addr(xs->sc_link); 542 else 543 printf("%s:", sc->sc_dev.dv_xname); 544 printf("parity error\n"); 545 goto reset; 546 } 547 if ((sist1 & SIST1_STO) && need_reset == 0) { 548 /* selection time out, assume there's no device here */ 549 if (siop_cmd) { 550 siop_cmd->status = CMDST_DONE; 551 xs->error = XS_SELTIMEOUT; 552 goto end; 553 } else { 554 printf("%s: selection timeout without " 555 "command\n", sc->sc_dev.dv_xname); 556 need_reset = 1; 557 } 558 } 559 if (sist0 & SIST0_UDC) { 560 /* 561 * unexpected disconnect. Usually the target signals 562 * a fatal condition this way. Attempt to get sense. 563 */ 564 if (siop_cmd) 565 goto check_sense; 566 printf("%s: unexpected disconnect without " 567 "command\n", sc->sc_dev.dv_xname); 568 goto reset; 569 } 570 if (sist1 & SIST1_SBMC) { 571 /* SCSI bus mode change */ 572 if (siop_modechange(sc) == 0 || need_reset == 1) 573 goto reset; 574 if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) { 575 /* 576 * we have a script interrupt, it will 577 * restart the script. 578 */ 579 goto scintr; 580 } 581 /* 582 * else we have to restart it ourselve, at the 583 * interrupted instruction. 584 */ 585 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 586 bus_space_read_4(sc->sc_rt, sc->sc_rh, 587 SIOP_DSP) - 8); 588 return 1; 589 } 590 /* Else it's an unhandled exeption (for now). */ 591 printf("%s: unhandled scsi interrupt, sist0=0x%x sist1=0x%x " 592 "sstat1=0x%x DSA=0x%x DSP=0x%x\n", sc->sc_dev.dv_xname, 593 sist0, sist1, 594 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1), 595 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA), 596 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 597 sc->sc_scriptaddr)); 598 if (siop_cmd) { 599 siop_cmd->status = CMDST_DONE; 600 xs->error = XS_SELTIMEOUT; 601 goto end; 602 } 603 need_reset = 1; 604 } 605 if (need_reset) { 606 reset: 607 /* fatal error, reset the bus */ 608 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 609 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 610 scntl1 | SCNTL1_RST); 611 /* minimum 25 us, more time won't hurt */ 612 delay(100); 613 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 614 /* no table to flush here */ 615 return 1; 616 } 617 618 scintr: 619 if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) { /* script interrupt */ 620 irqcode = bus_space_read_4(sc->sc_rt, sc->sc_rh, 621 SIOP_DSPS); 622 #ifdef DEBUG_INTR 623 printf("script interrupt 0x%x\n", irqcode); 624 #endif 625 if (siop_cmd == NULL) { 626 printf("%s: script interrupt (0x%x) with invalid " 627 "DSA !!!\n", sc->sc_dev.dv_xname, irqcode); 628 goto reset; 629 } 630 /* 631 * an inactive command is only valid if it's a reselect 632 * interrupt: we'll change siop_cmd to point to the rigth one 633 * just here 634 */ 635 if (irqcode != A_int_resel && irqcode != A_int_reseltag && 636 siop_cmd->status != CMDST_ACTIVE && 637 siop_cmd->status != CMDST_SENSE_ACTIVE) { 638 printf("%s: Aie, no command (IRQ code 0x%x current " 639 "status %d) !\n", sc->sc_dev.dv_xname, 640 irqcode, siop_cmd->status); 641 xs = NULL; 642 } else { 643 xs = siop_cmd->xs; 644 siop_target = siop_cmd->siop_target; 645 } 646 switch(irqcode) { 647 case A_int_err: 648 printf("error, DSP=0x%x\n", 649 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, 650 SIOP_DSP) - sc->sc_scriptaddr)); 651 if (xs) { 652 xs->error = XS_SELTIMEOUT; 653 goto end; 654 } else { 655 goto reset; 656 } 657 case A_int_msgin: 658 if (siop_cmd->siop_table->msg_in[0] == 659 MSG_MESSAGE_REJECT) { 660 int msg, extmsg; 661 if (siop_cmd->siop_table->msg_out[0] & 0x80) { 662 /* 663 * message was part of a identify + 664 * something else. Identify shoudl't 665 * have been rejected. 666 */ 667 msg = siop_cmd->siop_table->msg_out[1]; 668 extmsg = 669 siop_cmd->siop_table->msg_out[3]; 670 } else { 671 msg = siop_cmd->siop_table->msg_out[0]; 672 extmsg = 673 siop_cmd->siop_table->msg_out[2]; 674 } 675 if (msg == MSG_MESSAGE_REJECT) { 676 /* MSG_REJECT for a MSG_REJECT !*/ 677 if (xs) 678 scsi_print_addr(xs->sc_link); 679 else 680 printf("%s: ", 681 sc->sc_dev.dv_xname); 682 printf("our reject message was " 683 "rejected\n"); 684 goto reset; 685 } 686 if (msg == MSG_EXTENDED && 687 extmsg == MSG_EXT_WDTR) { 688 /* WDTR rejected, initiate sync */ 689 printf("%s: target %d using 8bit " 690 "transfers\n", sc->sc_dev.dv_xname, 691 xs->sc_link->scsipi_scsi.target); 692 siop_target->status = TARST_SYNC_NEG; 693 siop_cmd->siop_table->msg_out[0] = 694 MSG_EXTENDED; 695 siop_cmd->siop_table->msg_out[1] = 696 MSG_EXT_SDTR_LEN; 697 siop_cmd->siop_table->msg_out[2] = 698 MSG_EXT_SDTR; 699 siop_cmd->siop_table->msg_out[3] = 700 sc->minsync; 701 siop_cmd->siop_table->msg_out[4] = 702 sc->maxoff; 703 siop_cmd->siop_table->t_msgout.count = 704 htole32(MSG_EXT_SDTR_LEN + 2); 705 siop_cmd->siop_table->t_msgout.addr = 706 htole32(siop_cmd->dsa); 707 siop_table_sync(siop_cmd, 708 BUS_DMASYNC_PREREAD | 709 BUS_DMASYNC_PREWRITE); 710 CALL_SCRIPT(Ent_send_msgout); 711 return 1; 712 } else if (msg == MSG_EXTENDED && 713 extmsg == MSG_EXT_SDTR) { 714 /* sync rejected */ 715 printf("%s: target %d asynchronous\n", 716 sc->sc_dev.dv_xname, 717 xs->sc_link->scsipi_scsi.target); 718 siop_cmd->siop_target->status = 719 TARST_OK; 720 /* no table to flush here */ 721 CALL_SCRIPT(Ent_msgin_ack); 722 return 1; 723 } 724 if (xs) 725 scsi_print_addr(xs->sc_link); 726 else 727 printf("%s: ", sc->sc_dev.dv_xname); 728 if (msg == MSG_EXTENDED) { 729 printf("scsi message reject, extended " 730 "message sent was 0x%x\n", extmsg); 731 } else { 732 printf("scsi message reject, message " 733 "sent was 0x%x\n", msg); 734 } 735 /* no table to flush here */ 736 CALL_SCRIPT(Ent_msgin_ack); 737 return 1; 738 } 739 if (xs) 740 scsi_print_addr(xs->sc_link); 741 else 742 printf("%s: ", sc->sc_dev.dv_xname); 743 printf("unhandled message 0x%x\n", 744 siop_cmd->siop_table->msg_in[0]); 745 siop_cmd->siop_table->t_msgout.count= htole32(1); 746 siop_cmd->siop_table->t_msgout.addr = 747 htole32(siop_cmd->dsa); 748 siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT; 749 siop_table_sync(siop_cmd, 750 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 751 CALL_SCRIPT(Ent_send_msgout); 752 return 1; 753 case A_int_extmsgin: 754 #ifdef DEBUG_INTR 755 printf("extended message: msg 0x%x len %d\n", 756 siop_cmd->siop_table->msg_in[2], 757 siop_cmd->siop_table->msg_in[1]); 758 #endif 759 if (siop_cmd->siop_table->msg_in[1] > 6) 760 printf("%s: extended message too big (%d)\n", 761 sc->sc_dev.dv_xname, 762 siop_cmd->siop_table->msg_in[1]); 763 siop_cmd->siop_table->t_extmsgdata.count = 764 htole32(siop_cmd->siop_table->msg_in[1] - 1); 765 siop_cmd->siop_table->t_extmsgdata.addr = 766 htole32( 767 le32toh(siop_cmd->siop_table->t_extmsgin.addr) 768 + 2); 769 siop_table_sync(siop_cmd, 770 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 771 CALL_SCRIPT(Ent_get_extmsgdata); 772 return 1; 773 case A_int_extmsgdata: 774 #ifdef DEBUG_INTR 775 { 776 int i; 777 printf("extended message: 0x%x, data:", 778 siop_cmd->siop_table->msg_in[2]); 779 for (i = 3; i < 2 + siop_cmd->siop_table->msg_in[1]; 780 i++) 781 printf(" 0x%x", 782 siop_cmd->siop_table->msg_in[i]); 783 printf("\n"); 784 } 785 #endif 786 if (siop_cmd->siop_table->msg_in[2] == MSG_EXT_WDTR) { 787 switch (siop_wdtr_neg(siop_cmd)) { 788 case SIOP_NEG_NOP: 789 break; 790 case SIOP_NEG_MSGOUT: 791 siop_table_sync(siop_cmd, 792 BUS_DMASYNC_PREREAD | 793 BUS_DMASYNC_PREWRITE); 794 CALL_SCRIPT(Ent_send_msgout); 795 break; 796 default: 797 panic("invalid retval from " 798 "siop_wdtr_neg()"); 799 } 800 return(1); 801 } 802 if (siop_cmd->siop_table->msg_in[2] == MSG_EXT_SDTR) { 803 switch (siop_sdtr_neg(siop_cmd)) { 804 case SIOP_NEG_NOP: 805 break; 806 case SIOP_NEG_MSGOUT: 807 siop_table_sync(siop_cmd, 808 BUS_DMASYNC_PREREAD | 809 BUS_DMASYNC_PREWRITE); 810 CALL_SCRIPT(Ent_send_msgout); 811 break; 812 case SIOP_NEG_ACK: 813 CALL_SCRIPT(Ent_msgin_ack); 814 break; 815 default: 816 panic("invalid retval from " 817 "siop_wdtr_neg()"); 818 } 819 return(1); 820 } 821 /* send a message reject */ 822 siop_cmd->siop_table->t_msgout.count = 823 htole32(1); 824 siop_cmd->siop_table->t_msgout.addr = 825 htole32(siop_cmd->dsa); 826 siop_cmd->siop_table->msg_out[0] = 827 MSG_MESSAGE_REJECT; 828 siop_table_sync(siop_cmd, 829 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 830 CALL_SCRIPT(Ent_send_msgout); 831 return 1; 832 case A_int_resel: /* reselected */ 833 case A_int_reseltag: /* reselected with tag */ 834 INCSTAT(siop_stat_intr_reselect); 835 if ((siop_cmd->siop_table->msg_in[0] & 0x80) == 0) { 836 printf("%s: reselect without identify (%d)\n", 837 sc->sc_dev.dv_xname, 838 siop_cmd->siop_table->msg_in[0]); 839 goto reset; 840 } 841 target = bus_space_read_1(sc->sc_rt, 842 sc->sc_rh, SIOP_SCRATCHA); 843 if ((target & 0x80) == 0) { 844 printf("reselect without id (%d)\n", target); 845 goto reset; 846 } 847 target &= 0x0f; 848 lun = siop_cmd->siop_table->msg_in[0] & 0x07; 849 #ifdef DEBUG_DR 850 printf("reselected by target %d lun %d\n", 851 target, lun); 852 #endif 853 siop_cmd = 854 sc->targets[target]->active_list[lun].tqh_first; 855 if (siop_cmd == NULL) { 856 printf("%s: reselected without cmd\n", 857 sc->sc_dev.dv_xname); 858 goto reset; 859 } 860 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSA, 861 siop_cmd->dsa); 862 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 863 (sc->targets[target]->id >> 24) & 0xff); 864 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 865 (sc->targets[target]->id >> 8) & 0xff); 866 /* no table to flush */ 867 CALL_SCRIPT(Ent_selected); 868 return 1; 869 case A_int_disc: 870 INCSTAT(siop_stat_intr_sdp); 871 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, 872 SIOP_SCRATCHA + 1); 873 #ifdef DEBUG_DR 874 printf("disconnect offset %d\n", offset); 875 #endif 876 if (offset > SIOP_NSG) { 877 printf("%s: bad offset for disconnect (%d)\n", 878 sc->sc_dev.dv_xname, offset); 879 goto reset; 880 } 881 /* 882 * offset == SIOP_NSG may be a valid condition if 883 * we get a sdp when the xfer is done. 884 * Don't call memmove in this case. 885 */ 886 if (offset < SIOP_NSG) { 887 memmove(&siop_cmd->siop_table->data[0], 888 &siop_cmd->siop_table->data[offset], 889 (SIOP_NSG - offset) * sizeof(scr_table_t)); 890 siop_table_sync(siop_cmd, 891 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 892 } 893 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 894 sc->sc_sheddma->dm_segs[0].ds_addr); 895 return 1; 896 case A_int_resfail: 897 printf("reselect failed\n"); 898 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 899 sc->sc_sheddma->dm_segs[0].ds_addr); 900 return 1; 901 case A_int_done: 902 if (xs == NULL) { 903 printf("%s: done without command, DSA=0x%lx\n", 904 sc->sc_dev.dv_xname, (u_long)siop_cmd->dsa); 905 siop_cmd->status = CMDST_FREE; 906 bus_space_write_4(sc->sc_rt, sc->sc_rh, 907 SIOP_DSP, 908 sc->sc_sheddma->dm_segs[0].ds_addr); 909 siop_start(sc); 910 return 1; 911 } 912 if (siop_target->status == TARST_PROBING) 913 siop_target->status = TARST_ASYNC; 914 #ifdef DEBUG_INTR 915 printf("done, DSA=0x%lx target id 0x%x last msg " 916 "in=0x%x status=0x%x\n", (u_long)siop_cmd->dsa, 917 le32toh(siop_cmd->siop_table->id), 918 siop_cmd->siop_table->msg_in[0], 919 le32toh(siop_cmd->siop_table->status)); 920 #endif 921 INCSTAT(siop_stat_intr_done); 922 if (siop_cmd->status == CMDST_SENSE_ACTIVE) 923 siop_cmd->status = CMDST_SENSE_DONE; 924 else 925 siop_cmd->status = CMDST_DONE; 926 switch(le32toh(siop_cmd->siop_table->status)) { 927 case SCSI_OK: 928 xs->error = (siop_cmd->status == CMDST_DONE) ? 929 XS_NOERROR : XS_SENSE; 930 break; 931 case SCSI_BUSY: 932 xs->error = XS_BUSY; 933 break; 934 case SCSI_CHECK: 935 check_sense: 936 if (siop_cmd->status == CMDST_SENSE_DONE) { 937 /* request sense on a request sense ? */ 938 printf("request sense failed\n"); 939 xs->error = XS_DRIVER_STUFFUP; 940 } else { 941 siop_cmd->status = CMDST_SENSE; 942 } 943 break; 944 case 0xff: 945 /* 946 * the status byte was not updated, cmd was 947 * aborted 948 */ 949 xs->error = XS_SELTIMEOUT; 950 break; 951 default: 952 xs->error = XS_DRIVER_STUFFUP; 953 } 954 goto end; 955 default: 956 printf("unknown irqcode %x\n", irqcode); 957 xs->error = XS_SELTIMEOUT; 958 goto end; 959 } 960 return 1; 961 } 962 /* We just should't get there */ 963 panic("siop_intr: I shouldn't be there !"); 964 return 1; 965 end: 966 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 967 sc->sc_sheddma->dm_segs[0].ds_addr); 968 lun = siop_cmd->xs->sc_link->scsipi_scsi.lun; 969 siop_scsicmd_end(siop_cmd); 970 if (siop_cmd->status == CMDST_FREE) { 971 TAILQ_REMOVE(&siop_target->active_list[lun], 972 siop_cmd, next); 973 TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next); 974 } 975 siop_start(sc); 976 return 1; 977 } 978 979 void 980 siop_scsicmd_end(siop_cmd) 981 struct siop_cmd *siop_cmd; 982 { 983 struct scsipi_xfer *xs = siop_cmd->xs; 984 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 985 986 if (siop_cmd->status != CMDST_SENSE_DONE && 987 xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 988 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 989 siop_cmd->dmamap_data->dm_mapsize, 990 (xs->xs_control & XS_CTL_DATA_IN) ? 991 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 992 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data); 993 } 994 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 995 if (siop_cmd->status == CMDST_SENSE) { 996 /* issue a request sense for this target */ 997 int error, i; 998 siop_cmd->rs_cmd.opcode = REQUEST_SENSE; 999 siop_cmd->rs_cmd.byte2 = xs->sc_link->scsipi_scsi.lun << 5; 1000 siop_cmd->rs_cmd.unused[0] = siop_cmd->rs_cmd.unused[1] = 0; 1001 siop_cmd->rs_cmd.length = sizeof(struct scsipi_sense_data); 1002 siop_cmd->rs_cmd.control = 0; 1003 siop_cmd->siop_table->status = htole32(0xff); /*invalid status*/ 1004 siop_cmd->siop_table->t_msgout.count= htole32(1); 1005 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 1006 siop_cmd->siop_table->msg_out[0] = 1007 MSG_IDENTIFY(xs->sc_link->scsipi_scsi.lun, 1); 1008 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd, 1009 &siop_cmd->rs_cmd, sizeof(struct scsipi_sense), 1010 NULL, BUS_DMA_NOWAIT); 1011 if (error) { 1012 printf("%s: unable to load cmd DMA map: %d", 1013 sc->sc_dev.dv_xname, error); 1014 xs->error = XS_DRIVER_STUFFUP; 1015 goto out; 1016 } 1017 siop_cmd->siop_table->cmd.count = 1018 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 1019 siop_cmd->siop_table->cmd.addr = 1020 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 1021 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data, 1022 &xs->sense.scsi_sense, sizeof(struct scsipi_sense_data), 1023 NULL, BUS_DMA_NOWAIT); 1024 if (error) { 1025 printf("%s: unable to load sense DMA map: %d", 1026 sc->sc_dev.dv_xname, error); 1027 xs->error = XS_DRIVER_STUFFUP; 1028 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1029 goto out; 1030 } 1031 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 1032 siop_cmd->siop_table->data[i].count = 1033 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 1034 siop_cmd->siop_table->data[i].addr = 1035 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 1036 } 1037 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1038 siop_cmd->dmamap_data->dm_mapsize, BUS_DMASYNC_PREREAD); 1039 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd, 0, 1040 siop_cmd->dmamap_cmd->dm_mapsize, BUS_DMASYNC_PREWRITE); 1041 siop_table_sync(siop_cmd, BUS_DMASYNC_PREWRITE); 1042 return; 1043 } else if (siop_cmd->status == CMDST_SENSE_DONE) { 1044 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1045 siop_cmd->dmamap_data->dm_mapsize, BUS_DMASYNC_POSTREAD); 1046 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data); 1047 } 1048 out: 1049 callout_stop(&siop_cmd->xs->xs_callout); 1050 siop_cmd->status = CMDST_FREE; 1051 xs->xs_status |= XS_STS_DONE; 1052 xs->resid = 0; 1053 if ((xs->xs_control & XS_CTL_POLL) == 0) 1054 scsipi_done (xs); 1055 } 1056 1057 /* 1058 * handle a bus reset: reset chip, unqueue all active commands and report 1059 * loosage to upper layer. 1060 * As the upper layer may requeue immediatly we have to first store 1061 * all active commands in a temporary queue. 1062 */ 1063 void 1064 siop_handle_reset(sc) 1065 struct siop_softc *sc; 1066 { 1067 struct cmd_list reset_list; 1068 struct siop_cmd *siop_cmd, *next_siop_cmd; 1069 int target, lun; 1070 /* 1071 * scsi bus reset. reset the chip and restart 1072 * the queue. Need to clean up all active commands 1073 */ 1074 printf("%s: scsi bus reset\n", sc->sc_dev.dv_xname); 1075 /* stop, reset and restart the chip */ 1076 siop_reset(sc); 1077 TAILQ_INIT(&reset_list); 1078 /* find all active commands */ 1079 for (target = 0; target < sc->sc_link.scsipi_scsi.max_target; 1080 target++) { 1081 if (sc->targets[target] == NULL) 1082 continue; 1083 for (lun = 0; lun < 8; lun++) { 1084 for (siop_cmd = 1085 TAILQ_FIRST(&sc->targets[target]->active_list[lun]); 1086 siop_cmd != NULL; siop_cmd = next_siop_cmd) { 1087 next_siop_cmd = TAILQ_NEXT(siop_cmd, next); 1088 if (siop_cmd->status < CMDST_ACTIVE) 1089 continue; 1090 printf("cmd %p (target %d) in reset list\n", 1091 siop_cmd, target); 1092 TAILQ_REMOVE( 1093 &sc->targets[target]->active_list[lun], 1094 siop_cmd, next); 1095 TAILQ_INSERT_TAIL(&reset_list, siop_cmd, next); 1096 } 1097 } 1098 sc->targets[target]->status = TARST_ASYNC; 1099 sc->targets[target]->flags = ~(TARF_SYNC | TARF_WIDE); 1100 } 1101 for (siop_cmd = TAILQ_FIRST(&reset_list); siop_cmd != NULL; 1102 siop_cmd = next_siop_cmd) { 1103 next_siop_cmd = TAILQ_NEXT(siop_cmd, next); 1104 siop_cmd->xs->error = (siop_cmd->flags & CMDFL_TIMEOUT) ? 1105 XS_TIMEOUT : XS_RESET; 1106 printf("cmd %p about to be processed\n", siop_cmd); 1107 if (siop_cmd->status == CMDST_SENSE || 1108 siop_cmd->status == CMDST_SENSE_ACTIVE) 1109 siop_cmd->status = CMDST_SENSE_DONE; 1110 else 1111 siop_cmd->status = CMDST_DONE; 1112 TAILQ_REMOVE(&reset_list, siop_cmd, next); 1113 siop_scsicmd_end(siop_cmd); 1114 TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next); 1115 } 1116 } 1117 1118 int 1119 siop_scsicmd(xs) 1120 struct scsipi_xfer *xs; 1121 { 1122 struct siop_softc *sc = (struct siop_softc *)xs->sc_link->adapter_softc; 1123 struct siop_cmd *siop_cmd; 1124 int s, error, i; 1125 int target = xs->sc_link->scsipi_scsi.target; 1126 int lun = xs->sc_link->scsipi_scsi.lun; 1127 1128 s = splbio(); 1129 #ifdef DEBUG_SHED 1130 printf("starting cmd for %d:%d\n", target, lun); 1131 #endif 1132 siop_cmd = sc->free_list.tqh_first; 1133 if (siop_cmd) { 1134 TAILQ_REMOVE(&sc->free_list, siop_cmd, next); 1135 } else { 1136 if (siop_morecbd(sc) == 0) { 1137 siop_cmd = sc->free_list.tqh_first; 1138 #ifdef DIAGNOSTIC 1139 if (siop_cmd == NULL) 1140 panic("siop_morecbd succeed and does nothing"); 1141 #endif 1142 TAILQ_REMOVE(&sc->free_list, siop_cmd, next); 1143 } 1144 } 1145 splx(s); 1146 if (siop_cmd == NULL) { 1147 xs->error = XS_DRIVER_STUFFUP; 1148 return(TRY_AGAIN_LATER); 1149 } 1150 #ifdef DIAGNOSTIC 1151 if (siop_cmd->status != CMDST_FREE) 1152 panic("siop_scsicmd: new cmd not free"); 1153 #endif 1154 if (sc->targets[target] == NULL) { 1155 sc->targets[target] = 1156 malloc(sizeof(struct siop_target), M_DEVBUF, M_NOWAIT); 1157 if (sc->targets[target] == NULL) { 1158 printf("%s: can't malloc memory for target %d\n", 1159 sc->sc_dev.dv_xname, target); 1160 xs->error = XS_DRIVER_STUFFUP; 1161 return(TRY_AGAIN_LATER); 1162 } 1163 sc->targets[target]->siop_sc = sc; 1164 sc->targets[target]->status = TARST_PROBING; 1165 sc->targets[target]->flags = 0; 1166 sc->targets[target]->id = sc->clock_div << 24; /* scntl3 */ 1167 sc->targets[target]->id |= target << 16; /* id */ 1168 /* sc->targets[target]->id |= 0x0 << 8; scxfer is 0 */ 1169 for (i = 0; i < 8; i++) 1170 TAILQ_INIT(&sc->targets[target]->active_list[i]); 1171 } 1172 siop_cmd->siop_target = sc->targets[target]; 1173 siop_cmd->xs = xs; 1174 siop_cmd->siop_table->id = htole32(sc->targets[target]->id); 1175 siop_cmd->siop_table->t_msgout.count= htole32(1); 1176 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 1177 memset(siop_cmd->siop_table->msg_out, 0, 8); 1178 siop_cmd->siop_table->msg_out[0] = MSG_IDENTIFY(lun, 1); 1179 #if 0 1180 siop_cmd->siop_table->msg_out[1] = MSG_SIMPLE_Q_TAG; 1181 siop_cmd->siop_table->msg_out[2] = 0; 1182 #endif 1183 if (sc->targets[target]->status == TARST_ASYNC) { 1184 if (sc->features & SF_BUS_WIDE) { 1185 sc->targets[target]->status = TARST_WIDE_NEG; 1186 siop_cmd->siop_table->msg_out[1] = MSG_EXTENDED; 1187 siop_cmd->siop_table->msg_out[2] = MSG_EXT_WDTR_LEN; 1188 siop_cmd->siop_table->msg_out[3] = MSG_EXT_WDTR; 1189 siop_cmd->siop_table->msg_out[4] = 1190 MSG_EXT_WDTR_BUS_16_BIT; 1191 siop_cmd->siop_table->t_msgout.count= 1192 htole32(MSG_EXT_WDTR_LEN + 2 + 1); 1193 } else { 1194 sc->targets[target]->status = TARST_SYNC_NEG; 1195 siop_cmd->siop_table->msg_out[1] = MSG_EXTENDED; 1196 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR_LEN; 1197 siop_cmd->siop_table->msg_out[3] = MSG_EXT_SDTR; 1198 siop_cmd->siop_table->msg_out[4] = sc->minsync; 1199 siop_cmd->siop_table->msg_out[5] = sc->maxoff; 1200 siop_cmd->siop_table->t_msgout.count= 1201 htole32(MSG_EXT_SDTR_LEN + 2 +1); 1202 } 1203 } 1204 siop_cmd->siop_table->status = htole32(0xff); /* set invalid status */ 1205 1206 /* load the DMA maps */ 1207 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd, 1208 xs->cmd, xs->cmdlen, NULL, BUS_DMA_NOWAIT); 1209 if (error) { 1210 printf("%s: unable to load cmd DMA map: %d", 1211 sc->sc_dev.dv_xname, error); 1212 xs->error = XS_DRIVER_STUFFUP; 1213 return(TRY_AGAIN_LATER); 1214 } 1215 siop_cmd->siop_table->cmd.count = 1216 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 1217 siop_cmd->siop_table->cmd.addr = 1218 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 1219 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 1220 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data, 1221 xs->data, xs->datalen, NULL, BUS_DMA_NOWAIT); 1222 if (error) { 1223 printf("%s: unable to load cmd DMA map: %d", 1224 sc->sc_dev.dv_xname, error); 1225 xs->error = XS_DRIVER_STUFFUP; 1226 return(TRY_AGAIN_LATER); 1227 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1228 } 1229 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 1230 siop_cmd->siop_table->data[i].count = 1231 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 1232 siop_cmd->siop_table->data[i].addr = 1233 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 1234 } 1235 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1236 siop_cmd->dmamap_data->dm_mapsize, 1237 (xs->xs_control & XS_CTL_DATA_IN) ? 1238 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1239 } 1240 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd, 0, 1241 siop_cmd->dmamap_cmd->dm_mapsize, BUS_DMASYNC_PREWRITE); 1242 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1243 1244 siop_cmd->status = CMDST_READY; 1245 s = splbio(); 1246 TAILQ_INSERT_TAIL(&sc->targets[target]->active_list[lun], 1247 siop_cmd, next); 1248 siop_start(sc); 1249 if (xs->xs_control & XS_CTL_POLL) { 1250 /* poll for command completion */ 1251 while ((xs->xs_status & XS_STS_DONE) == 0) 1252 siop_intr(sc); 1253 splx(s); 1254 return (COMPLETE); 1255 } 1256 splx(s); 1257 return (SUCCESSFULLY_QUEUED); 1258 } 1259 1260 void 1261 siop_start(sc) 1262 struct siop_softc *sc; 1263 { 1264 struct siop_cmd *siop_cmd; 1265 u_int32_t *scr; 1266 u_int32_t dsa; 1267 int timeout; 1268 int target, lun, slot; 1269 int newcmd = 0; 1270 1271 /* 1272 * first make sure to read valid data 1273 */ 1274 siop_shed_sync(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1275 1276 /* 1277 * The queue management here is a bit tricky: the script always looks 1278 * at the slot from first to last, so if we always use the first 1279 * free slot commands can stay at the tail of the queue ~forever. 1280 * The algorithm used here is to restart from the head when we know 1281 * that the queue is empty, and only add commands after the last one. 1282 * When we're at the end of the queue wait for the script to clear it. 1283 * The best thing to do here would be to implement a circular queue, 1284 * but using only 53c720 features this can be "interesting". 1285 * A mid-way solution could be to implement 2 queues and swap orders. 1286 */ 1287 slot = sc->sc_currshedslot; 1288 scr = &sc->sc_shed[(Ent_nextslot / 4) * slot]; 1289 /* 1290 * if relative addr of first jump is not 0 the slot is free. As this is 1291 * the last used slot, all previous slots are free, we can restart 1292 * from 0. 1293 */ 1294 if (scr[Ent_slot / 4 + 1] != 0) { 1295 slot = sc->sc_currshedslot = 0; 1296 } else { 1297 slot++; 1298 } 1299 1300 for (target = 0; target <= sc->sc_link.scsipi_scsi.max_target; 1301 target++) { 1302 if (sc->targets[target] == NULL) 1303 continue; 1304 for (lun = 0; lun < 8; lun++) { 1305 siop_cmd = 1306 sc->targets[target]->active_list[lun].tqh_first; 1307 if (siop_cmd == NULL) 1308 continue; 1309 if (siop_cmd->status != CMDST_READY && 1310 siop_cmd->status != CMDST_SENSE) 1311 continue; 1312 /* find a free scheduler slot and load it */ 1313 for (; slot < sc->sc_nshedslots; slot++) { 1314 scr = &sc->sc_shed[(Ent_nextslot / 4) * slot]; 1315 /* 1316 * if relative addr of first jump is 0 the 1317 * slot isn't free 1318 */ 1319 if (scr[Ent_slot / 4 + 1] == 0) 1320 continue; 1321 #ifdef DEBUG_SHED 1322 printf("using slot %d for DSA 0x%lx\n", slot, 1323 (u_long)siop_cmd->dsa); 1324 #endif 1325 /* note that we started a new command */ 1326 newcmd = 1; 1327 /* mark command as active */ 1328 if (siop_cmd->status == CMDST_READY) 1329 siop_cmd->status = CMDST_ACTIVE; 1330 else if (siop_cmd->status == CMDST_SENSE) 1331 siop_cmd->status = CMDST_SENSE_ACTIVE; 1332 else 1333 panic("siop_start: bad status"); 1334 /* patch script with DSA addr */ 1335 dsa = siop_cmd->dsa; 1336 /* 1337 * 0x78000000 is a 'move data8 to reg'. data8 1338 * is the second octet, reg offset is the third. 1339 */ 1340 scr[Ent_idsa0 / 4] = 1341 htole32(0x78100000 | 1342 ((dsa & 0x000000ff) << 8)); 1343 scr[Ent_idsa1 / 4] = 1344 htole32(0x78110000 | 1345 ( dsa & 0x0000ff00 )); 1346 scr[Ent_idsa2 / 4] = 1347 htole32(0x78120000 | 1348 ((dsa & 0x00ff0000) >> 8)); 1349 scr[Ent_idsa3 / 4] = 1350 htole32(0x78130000 | 1351 ((dsa & 0xff000000) >> 16)); 1352 /* handle timeout */ 1353 if (siop_cmd->status == CMDST_ACTIVE) { 1354 if ((siop_cmd->xs->xs_control & 1355 XS_CTL_POLL) == 0) { 1356 /* start exire timer */ 1357 timeout = 1358 siop_cmd->xs->timeout * 1359 hz / 1000; 1360 if (timeout == 0) 1361 timeout = 1; 1362 callout_reset( 1363 &siop_cmd->xs->xs_callout, 1364 timeout, siop_timeout, 1365 siop_cmd); 1366 } 1367 } 1368 /* 1369 * Change jump offset so that this slot will be 1370 * handled 1371 */ 1372 scr[Ent_slot / 4 + 1] = 0; 1373 break; 1374 } 1375 /* no more free slot, no need to continue */ 1376 if (slot == sc->sc_nshedslots) { 1377 goto end; 1378 } 1379 sc->sc_currshedslot = slot; 1380 } 1381 } 1382 end: 1383 /* if nothing changed no need to flush cache and wakeup script */ 1384 if (newcmd == 0) 1385 return; 1386 /* make sure SCRIPT processor will read valid data */ 1387 siop_shed_sync(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1388 /* Signal script it has some work to do */ 1389 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SIGP); 1390 /* and wait for IRQ */ 1391 return; 1392 } 1393 1394 void 1395 siop_timeout(v) 1396 void *v; 1397 { 1398 struct siop_cmd *siop_cmd = v; 1399 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 1400 int s; 1401 u_int8_t scntl1; 1402 1403 scsi_print_addr(siop_cmd->xs->sc_link); 1404 printf("command timeout\n"); 1405 1406 s = splbio(); 1407 /* reset the scsi bus */ 1408 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 1409 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 1410 scntl1 | SCNTL1_RST); 1411 /* minimum 25 us, more time won't hurt */ 1412 delay(100); 1413 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 1414 1415 /* deactivate callout */ 1416 callout_stop(&siop_cmd->xs->xs_callout); 1417 /* mark command has being timed out; siop_intr will handle it */ 1418 /* 1419 * mark command has being timed out and just return; 1420 * the bus reset will generate an interrupt, 1421 * it will be handled in siop_intr() 1422 */ 1423 siop_cmd->flags |= CMDFL_TIMEOUT; 1424 splx(s); 1425 return; 1426 1427 } 1428 1429 void 1430 siop_dump_script(sc) 1431 struct siop_softc *sc; 1432 { 1433 int i; 1434 siop_shed_sync(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1435 for (i = 0; i < NBPG / 4; i += 2) { 1436 printf("0x%04x: 0x%08x 0x%08x", i * 4, 1437 le32toh(sc->sc_script[i]), le32toh(sc->sc_script[i+1])); 1438 if ((le32toh(sc->sc_script[i]) & 0xe0000000) == 0xc0000000) { 1439 i++; 1440 printf(" 0x%08x", le32toh(sc->sc_script[i+1])); 1441 } 1442 printf("\n"); 1443 } 1444 } 1445 1446 int 1447 siop_morecbd(sc) 1448 struct siop_softc *sc; 1449 { 1450 int error, i; 1451 bus_dma_segment_t seg; 1452 int rseg; 1453 struct siop_cbd *newcbd; 1454 1455 /* allocate a new list head */ 1456 newcbd = malloc(sizeof(struct siop_cbd), M_DEVBUF, M_NOWAIT); 1457 if (newcbd == NULL) { 1458 printf("%s: can't allocate memory for command descriptors " 1459 "head\n", sc->sc_dev.dv_xname); 1460 return ENOMEM; 1461 } 1462 1463 /* allocate cmd list */ 1464 newcbd->cmds = 1465 malloc(sizeof(struct siop_cmd) * SIOP_NCMDPB, M_DEVBUF, M_NOWAIT); 1466 if (newcbd->cmds == NULL) { 1467 printf("%s: can't allocate memory for command descriptors\n", 1468 sc->sc_dev.dv_xname); 1469 error = ENOMEM; 1470 goto bad3; 1471 } 1472 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, NBPG, 0, &seg, 1, &rseg, 1473 BUS_DMA_NOWAIT); 1474 if (error) { 1475 printf("%s: unable to allocate cbd DMA memory, error = %d\n", 1476 sc->sc_dev.dv_xname, error); 1477 goto bad2; 1478 } 1479 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 1480 (caddr_t *)&newcbd->xfers, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1481 if (error) { 1482 printf("%s: unable to map cbd DMA memory, error = %d\n", 1483 sc->sc_dev.dv_xname, error); 1484 goto bad2; 1485 } 1486 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, NBPG, 0, 1487 BUS_DMA_NOWAIT, &newcbd->xferdma); 1488 if (error) { 1489 printf("%s: unable to create cbd DMA map, error = %d\n", 1490 sc->sc_dev.dv_xname, error); 1491 goto bad1; 1492 } 1493 error = bus_dmamap_load(sc->sc_dmat, newcbd->xferdma, newcbd->xfers, 1494 NBPG, NULL, BUS_DMA_NOWAIT); 1495 if (error) { 1496 printf("%s: unable to load cbd DMA map, error = %d\n", 1497 sc->sc_dev.dv_xname, error); 1498 goto bad0; 1499 } 1500 1501 for (i = 0; i < SIOP_NCMDPB; i++) { 1502 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, SIOP_NSG, 1503 MAXPHYS, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1504 &newcbd->cmds[i].dmamap_data); 1505 if (error) { 1506 printf("%s: unable to create data DMA map for cbd: " 1507 "error %d\n", 1508 sc->sc_dev.dv_xname, error); 1509 goto bad0; 1510 } 1511 error = bus_dmamap_create(sc->sc_dmat, 1512 sizeof(struct scsipi_generic), 1, 1513 sizeof(struct scsipi_generic), 0, 1514 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1515 &newcbd->cmds[i].dmamap_cmd); 1516 if (error) { 1517 printf("%s: unable to create cmd DMA map for cbd %d\n", 1518 sc->sc_dev.dv_xname, error); 1519 goto bad0; 1520 } 1521 newcbd->cmds[i].siop_cbdp = newcbd; 1522 newcbd->cmds[i].siop_table = &newcbd->xfers[i]; 1523 memset(newcbd->cmds[i].siop_table, 0, sizeof(struct siop_xfer)); 1524 newcbd->cmds[i].dsa = newcbd->xferdma->dm_segs[0].ds_addr + 1525 i * sizeof(struct siop_xfer); 1526 newcbd->cmds[i].status = CMDST_FREE; 1527 newcbd->cmds[i].siop_table->t_msgout.count= htole32(1); 1528 newcbd->cmds[i].siop_table->t_msgout.addr = 1529 htole32(newcbd->cmds[i].dsa); 1530 newcbd->cmds[i].siop_table->t_msgin.count= htole32(1); 1531 newcbd->cmds[i].siop_table->t_msgin.addr = 1532 htole32(newcbd->cmds[i].dsa + 8); 1533 newcbd->cmds[i].siop_table->t_extmsgin.count= htole32(2); 1534 newcbd->cmds[i].siop_table->t_extmsgin.addr = htole32( 1535 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr) + 1); 1536 newcbd->cmds[i].siop_table->t_msgtag.count= htole32(2); 1537 newcbd->cmds[i].siop_table->t_msgtag.addr = htole32( 1538 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr) + 1); 1539 newcbd->cmds[i].siop_table->t_status.count= htole32(1); 1540 newcbd->cmds[i].siop_table->t_status.addr = htole32( 1541 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr) + 8); 1542 TAILQ_INSERT_TAIL(&sc->free_list, &newcbd->cmds[i], next); 1543 #ifdef DEBUG 1544 printf("tables[%d]: out=0x%x in=0x%x status=0x%x\n", i, 1545 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr), 1546 le32toh(newcbd->cmds[i].siop_table->t_msgout.addr), 1547 le32toh(newcbd->cmds[i].siop_table->t_status.addr)); 1548 #endif 1549 } 1550 TAILQ_INSERT_TAIL(&sc->cmds, newcbd, next); 1551 return 0; 1552 bad0: 1553 bus_dmamap_destroy(sc->sc_dmat, newcbd->xferdma); 1554 bad1: 1555 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1556 bad2: 1557 free(newcbd->cmds, M_DEVBUF); 1558 bad3: 1559 free(newcbd, M_DEVBUF); 1560 return error; 1561 } 1562 1563 #ifdef SIOP_STATS 1564 void 1565 siop_printstats() 1566 { 1567 printf("siop_stat_intr %d\n", siop_stat_intr); 1568 printf("siop_stat_intr_shortxfer %d\n", siop_stat_intr_shortxfer); 1569 printf("siop_stat_intr_xferdisc %d\n", siop_stat_intr_xferdisc); 1570 printf("siop_stat_intr_sdp %d\n", siop_stat_intr_sdp); 1571 printf("siop_stat_intr_reselect %d\n", siop_stat_intr_reselect); 1572 printf("siop_stat_intr_done %d\n", siop_stat_intr_done); 1573 } 1574 #endif 1575
Indexes created Mon Oct 20 11:09:49 GMT 2025