siop.c revision 1.21.2.4
1 /* $NetBSD: siop.c,v 1.21.2.4 2000/10/03 15:21:43 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 42 #include <machine/endian.h> 43 #include <machine/bus.h> 44 45 #include <vm/vm.h> 46 #include <vm/vm_param.h> 47 #include <vm/vm_kern.h> 48 49 #include <dev/microcode/siop/siop.out> 50 51 #include <dev/scsipi/scsi_all.h> 52 #include <dev/scsipi/scsi_message.h> 53 #include <dev/scsipi/scsipi_all.h> 54 55 #include <dev/scsipi/scsiconf.h> 56 57 #include <dev/ic/siopreg.h> 58 #include <dev/ic/siopvar.h> 59 #include <dev/ic/siopvar_common.h> 60 61 #undef DEBUG 62 #undef DEBUG_DR 63 #undef DEBUG_INTR 64 #undef DEBUG_SHED 65 #undef DUMP_SCRIPT 66 67 #define SIOP_STATS 68 69 #ifndef SIOP_DEFAULT_TARGET 70 #define SIOP_DEFAULT_TARGET 7 71 #endif 72 73 /* number of cmd descriptors per block */ 74 #define SIOP_NCMDPB (NBPG / sizeof(struct siop_xfer)) 75 76 void siop_reset __P((struct siop_softc *)); 77 void siop_handle_reset __P((struct siop_softc *)); 78 void siop_scsicmd_end __P((struct siop_cmd *)); 79 void siop_start __P((struct siop_softc *)); 80 void siop_timeout __P((void *)); 81 int siop_scsicmd __P((struct scsipi_xfer *)); 82 void siop_dump_script __P((struct siop_softc *)); 83 int siop_morecbd __P((struct siop_softc *)); 84 85 struct scsipi_adapter siop_adapter = { 86 0, 87 siop_scsicmd, 88 siop_minphys, 89 siop_ioctl, 90 NULL, 91 NULL, 92 }; 93 94 struct scsipi_device siop_dev = { 95 NULL, 96 NULL, 97 NULL, 98 NULL, 99 }; 100 101 #ifdef SIOP_STATS 102 static int siop_stat_intr = 0; 103 static int siop_stat_intr_shortxfer = 0; 104 static int siop_stat_intr_sdp = 0; 105 static int siop_stat_intr_done = 0; 106 static int siop_stat_intr_reselect = 0; 107 static int siop_stat_intr_xferdisc = 0; 108 void siop_printstats __P((void)); 109 #define INCSTAT(x) x++ 110 #else 111 #define INCSTAT(x) 112 #endif 113 114 static __inline__ void siop_table_sync __P((struct siop_cmd *, int)); 115 static __inline__ void 116 siop_table_sync(siop_cmd, ops) 117 struct siop_cmd *siop_cmd; 118 int ops; 119 { 120 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 121 bus_addr_t offset; 122 123 offset = siop_cmd->dsa - 124 siop_cmd->siop_cbdp->xferdma->dm_segs[0].ds_addr; 125 bus_dmamap_sync(sc->sc_dmat, siop_cmd->siop_cbdp->xferdma, offset, 126 sizeof(struct siop_xfer), ops); 127 } 128 129 static __inline__ void siop_shed_sync __P((struct siop_softc *, int)); 130 static __inline__ void 131 siop_shed_sync(sc, ops) 132 struct siop_softc *sc; 133 int ops; 134 { 135 bus_dmamap_sync(sc->sc_dmat, sc->sc_sheddma, 0, NBPG, ops); 136 } 137 138 void 139 siop_attach(sc) 140 struct siop_softc *sc; 141 { 142 int error, i; 143 bus_dma_segment_t seg; 144 int rseg; 145 146 /* 147 * Allocate DMA-safe memory for the script and script scheduler 148 * and map it. 149 */ 150 if ((sc->features & SF_CHIP_RAM) == 0) { 151 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, 152 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 153 if (error) { 154 printf("%s: unable to allocate script DMA memory, " 155 "error = %d\n", sc->sc_dev.dv_xname, error); 156 return; 157 } 158 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 159 (caddr_t *)&sc->sc_script, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 160 if (error) { 161 printf("%s: unable to map script DMA memory, " 162 "error = %d\n", sc->sc_dev.dv_xname, error); 163 return; 164 } 165 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, 166 NBPG, 0, BUS_DMA_NOWAIT, &sc->sc_scriptdma); 167 if (error) { 168 printf("%s: unable to create script DMA map, " 169 "error = %d\n", sc->sc_dev.dv_xname, error); 170 return; 171 } 172 error = bus_dmamap_load(sc->sc_dmat, sc->sc_scriptdma, 173 sc->sc_script, 174 NBPG, NULL, BUS_DMA_NOWAIT); 175 if (error) { 176 printf("%s: unable to load script DMA map, " 177 "error = %d\n", sc->sc_dev.dv_xname, error); 178 return; 179 } 180 sc->sc_scriptaddr = sc->sc_scriptdma->dm_segs[0].ds_addr; 181 } 182 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, 183 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 184 if (error) { 185 printf("%s: unable to allocate scheduler DMA memory, " 186 "error = %d\n", sc->sc_dev.dv_xname, error); 187 return; 188 } 189 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 190 (caddr_t *)&sc->sc_shed, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 191 if (error) { 192 printf("%s: unable to map scheduler DMA memory, error = %d\n", 193 sc->sc_dev.dv_xname, error); 194 return; 195 } 196 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, 197 NBPG, 0, BUS_DMA_NOWAIT, &sc->sc_sheddma); 198 if (error) { 199 printf("%s: unable to create scheduler DMA map, error = %d\n", 200 sc->sc_dev.dv_xname, error); 201 return; 202 } 203 error = bus_dmamap_load(sc->sc_dmat, sc->sc_sheddma, sc->sc_shed, 204 NBPG, NULL, BUS_DMA_NOWAIT); 205 if (error) { 206 printf("%s: unable to load scheduler DMA map, error = %d\n", 207 sc->sc_dev.dv_xname, error); 208 return; 209 } 210 TAILQ_INIT(&sc->free_list); 211 TAILQ_INIT(&sc->cmds); 212 /* compute number of scheduler slots */ 213 sc->sc_nshedslots = ( 214 NBPG /* memory size allocated for scheduler */ 215 - sizeof(endslot_script) /* memory needed at end of scheduler */ 216 ) / (sizeof(slot_script) - 8); 217 sc->sc_currshedslot = 0; 218 #ifdef DEBUG 219 printf("%s: script size = %d, PHY addr=0x%x, VIRT=%p nslots %d\n", 220 sc->sc_dev.dv_xname, (int)sizeof(siop_script), 221 sc->sc_scriptaddr, sc->sc_script, sc->sc_nshedslots); 222 #endif 223 224 sc->sc_link.adapter_softc = sc; 225 sc->sc_link.openings = 1; 226 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 227 sc->sc_link.scsipi_scsi.max_target = 228 (sc->features & SF_BUS_WIDE) ? 15 : 7; 229 sc->sc_link.scsipi_scsi.max_lun = 7; 230 sc->sc_link.scsipi_scsi.adapter_target = bus_space_read_1(sc->sc_rt, 231 sc->sc_rh, SIOP_SCID); 232 if (sc->sc_link.scsipi_scsi.adapter_target == 0 || 233 sc->sc_link.scsipi_scsi.adapter_target > 234 sc->sc_link.scsipi_scsi.max_target) 235 sc->sc_link.scsipi_scsi.adapter_target = SIOP_DEFAULT_TARGET; 236 sc->sc_link.type = BUS_SCSI; 237 sc->sc_link.adapter = &siop_adapter; 238 sc->sc_link.device = &siop_dev; 239 sc->sc_link.flags = 0; 240 241 for (i = 0; i < 16; i++) 242 sc->targets[i] = NULL; 243 244 /* find min/max sync period for this chip */ 245 sc->maxsync = 0; 246 sc->minsync = 255; 247 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); i++) { 248 if (sc->clock_period != scf_period[i].clock) 249 continue; 250 if (sc->maxsync < scf_period[i].period) 251 sc->maxsync = scf_period[i].period; 252 if (sc->minsync > scf_period[i].period) 253 sc->minsync = scf_period[i].period; 254 } 255 if (sc->maxsync == 255 || sc->minsync == 0) 256 panic("siop: can't find my sync parameters\n"); 257 /* Do a bus reset, so that devices fall back to narrow/async */ 258 siop_resetbus(sc); 259 /* 260 * siop_reset() will reset the chip, thus clearing pending interrupts 261 */ 262 siop_reset(sc); 263 #ifdef DUMP_SCRIPT 264 siop_dump_script(sc); 265 #endif 266 267 config_found((struct device*)sc, &sc->sc_link, scsiprint); 268 } 269 270 void 271 siop_reset(sc) 272 struct siop_softc *sc; 273 { 274 int i, j; 275 u_int32_t *scr; 276 bus_addr_t physaddr; 277 278 siop_common_reset(sc); 279 280 /* copy and patch the script */ 281 if (sc->features & SF_CHIP_RAM) { 282 bus_space_write_region_4(sc->sc_ramt, sc->sc_ramh, 0, 283 siop_script, sizeof(siop_script) / sizeof(siop_script[0])); 284 for (j = 0; j < 285 (sizeof(E_script_abs_shed_Used) / 286 sizeof(E_script_abs_shed_Used[0])); 287 j++) { 288 bus_space_write_4(sc->sc_ramt, sc->sc_ramh, 289 E_script_abs_shed_Used[j] * 4, 290 sc->sc_sheddma->dm_segs[0].ds_addr); 291 } 292 } else { 293 for (j = 0; 294 j < (sizeof(siop_script) / sizeof(siop_script[0])); j++) { 295 sc->sc_script[j] = htole32(siop_script[j]); 296 } 297 for (j = 0; j < 298 (sizeof(E_script_abs_shed_Used) / 299 sizeof(E_script_abs_shed_Used[0])); 300 j++) { 301 sc->sc_script[E_script_abs_shed_Used[j]] = 302 htole32(sc->sc_sheddma->dm_segs[0].ds_addr); 303 } 304 } 305 /* copy and init the scheduler slots script */ 306 for (i = 0; i < sc->sc_nshedslots; i++) { 307 scr = &sc->sc_shed[(Ent_nextslot / 4) * i]; 308 physaddr = sc->sc_sheddma->dm_segs[0].ds_addr + 309 Ent_nextslot * i; 310 for (j = 0; j < (sizeof(slot_script) / sizeof(slot_script[0])); 311 j++) { 312 scr[j] = htole32(slot_script[j]); 313 } 314 /* 315 * save current jump offset and patch MOVE MEMORY operands 316 * to restore it. 317 */ 318 scr[Ent_slotdata/4 + 1] = scr[Ent_slot/4 + 1]; 319 scr[E_slot_nextp_Used[0]] = htole32(physaddr + Ent_slot + 4); 320 scr[E_slot_shed_addrsrc_Used[0]] = htole32(physaddr + 321 Ent_slotdata + 4); 322 /* JUMP selected, in main script */ 323 scr[E_slot_abs_selected_Used[0]] = 324 htole32(sc->sc_scriptaddr + Ent_selected); 325 /* JUMP addr if SELECT fail */ 326 scr[E_slot_abs_reselect_Used[0]] = 327 htole32(sc->sc_scriptaddr + Ent_reselect); 328 } 329 /* Now the final JUMP */ 330 scr = &sc->sc_shed[(Ent_nextslot / 4) * sc->sc_nshedslots]; 331 for (j = 0; j < (sizeof(endslot_script) / sizeof(endslot_script[0])); 332 j++) { 333 scr[j] = htole32(endslot_script[j]); 334 } 335 scr[E_endslot_abs_reselect_Used[0]] = 336 htole32(sc->sc_scriptaddr + Ent_reselect); 337 338 /* start script */ 339 if ((sc->features & SF_CHIP_RAM) == 0) { 340 bus_dmamap_sync(sc->sc_dmat, sc->sc_scriptdma, 0, NBPG, 341 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 342 } 343 siop_shed_sync(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 344 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 345 sc->sc_scriptaddr + Ent_reselect); 346 } 347 348 #if 0 349 #define CALL_SCRIPT(ent) do {\ 350 printf ("start script DSA 0x%lx DSP 0x%lx\n", \ 351 siop_cmd->dsa, \ 352 sc->sc_scriptaddr + ent); \ 353 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \ 354 } while (0) 355 #else 356 #define CALL_SCRIPT(ent) do {\ 357 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \ 358 } while (0) 359 #endif 360 361 int 362 siop_intr(v) 363 void *v; 364 { 365 struct siop_softc *sc = v; 366 struct siop_target *siop_target; 367 struct siop_cmd *siop_cmd; 368 struct scsipi_xfer *xs; 369 int istat, sist0, sist1, sstat1, dstat; 370 u_int32_t irqcode; 371 int need_reset = 0; 372 int offset, target, lun; 373 bus_addr_t dsa; 374 struct siop_cbd *cbdp; 375 376 istat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT); 377 if ((istat & (ISTAT_INTF | ISTAT_DIP | ISTAT_SIP)) == 0) 378 return 0; 379 INCSTAT(siop_stat_intr); 380 if (istat & ISTAT_INTF) { 381 printf("INTRF\n"); 382 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_INTF); 383 } 384 /* use DSA to find the current siop_cmd */ 385 dsa = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA); 386 for (cbdp = TAILQ_FIRST(&sc->cmds); cbdp != NULL; 387 cbdp = TAILQ_NEXT(cbdp, next)) { 388 if (dsa >= cbdp->xferdma->dm_segs[0].ds_addr && 389 dsa < cbdp->xferdma->dm_segs[0].ds_addr + NBPG) { 390 dsa -= cbdp->xferdma->dm_segs[0].ds_addr; 391 siop_cmd = &cbdp->cmds[dsa / sizeof(struct siop_xfer)]; 392 siop_table_sync(siop_cmd, 393 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 394 break; 395 } 396 } 397 if (cbdp == NULL) { 398 siop_cmd = NULL; 399 } 400 if (istat & ISTAT_DIP) { 401 u_int32_t *p; 402 dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DSTAT); 403 if (dstat & DSTAT_SSI) { 404 printf("single step dsp 0x%08x dsa 0x08%x\n", 405 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 406 sc->sc_scriptaddr), 407 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA)); 408 if ((dstat & ~(DSTAT_DFE | DSTAT_SSI)) == 0 && 409 (istat & ISTAT_SIP) == 0) { 410 bus_space_write_1(sc->sc_rt, sc->sc_rh, 411 SIOP_DCNTL, bus_space_read_1(sc->sc_rt, 412 sc->sc_rh, SIOP_DCNTL) | DCNTL_STD); 413 } 414 return 1; 415 } 416 if (dstat & ~(DSTAT_SIR | DSTAT_DFE | DSTAT_SSI)) { 417 printf("DMA IRQ:"); 418 if (dstat & DSTAT_IID) 419 printf(" Illegal instruction"); 420 if (dstat & DSTAT_ABRT) 421 printf(" abort"); 422 if (dstat & DSTAT_BF) 423 printf(" bus fault"); 424 if (dstat & DSTAT_MDPE) 425 printf(" parity"); 426 if (dstat & DSTAT_DFE) 427 printf(" dma fifo empty"); 428 printf(", DSP=0x%x DSA=0x%x: ", 429 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 430 sc->sc_scriptaddr), 431 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA)); 432 p = sc->sc_script + 433 (bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 434 sc->sc_scriptaddr - 8) / 4; 435 printf("0x%x 0x%x 0x%x 0x%x\n", le32toh(p[0]), le32toh(p[1]), 436 le32toh(p[2]), le32toh(p[3])); 437 if (siop_cmd) 438 printf("last msg_in=0x%x status=0x%x\n", 439 siop_cmd->siop_table->msg_in[0], 440 le32toh(siop_cmd->siop_table->status)); 441 else 442 printf("%s: current DSA invalid\n", 443 sc->sc_dev.dv_xname); 444 need_reset = 1; 445 } 446 } 447 if (istat & ISTAT_SIP) { 448 /* 449 * SCSI interrupt. If current command is not active, 450 * we don't need siop_cmd 451 */ 452 if (siop_cmd && siop_cmd->status != CMDST_ACTIVE && 453 siop_cmd->status != CMDST_SENSE_ACTIVE) { 454 siop_cmd = NULL; 455 } 456 if (istat & ISTAT_DIP) 457 delay(10); 458 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 459 delay(10); 460 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 461 sstat1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1); 462 #ifdef DEBUG_INTR 463 printf("scsi interrupt, sist0=0x%x sist1=0x%x sstat1=0x%x " 464 "DSA=0x%x DSP=0x%lx\n", sist0, sist1, 465 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1), 466 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA), 467 (u_long)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 468 sc->sc_scriptaddr)); 469 #endif 470 if (siop_cmd) { 471 xs = siop_cmd->xs; 472 siop_target = siop_cmd->siop_target; 473 } 474 if (sist0 & SIST0_RST) { 475 siop_handle_reset(sc); 476 siop_start(sc); 477 /* no table to flush here */ 478 return 1; 479 } 480 if (sist0 & SIST0_SGE) { 481 if (siop_cmd) 482 scsi_print_addr(xs->sc_link); 483 else 484 printf("%s:", sc->sc_dev.dv_xname); 485 printf("scsi gross error\n"); 486 goto reset; 487 } 488 if ((sist0 & SIST0_MA) && need_reset == 0) { 489 if (siop_cmd) { 490 int scratcha0; 491 dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 492 SIOP_DSTAT); 493 /* 494 * first restore DSA, in case we were in a S/G 495 * operation. 496 */ 497 bus_space_write_4(sc->sc_rt, sc->sc_rh, 498 SIOP_DSA, siop_cmd->dsa); 499 scratcha0 = bus_space_read_1(sc->sc_rt, 500 sc->sc_rh, SIOP_SCRATCHA); 501 switch (sstat1 & SSTAT1_PHASE_MASK) { 502 case SSTAT1_PHASE_STATUS: 503 /* 504 * previous phase may be aborted for any reason 505 * ( for example, the target has less data to 506 * transfer than requested). Just go to status 507 * and the command should terminate. 508 */ 509 INCSTAT(siop_stat_intr_shortxfer); 510 CALL_SCRIPT(Ent_status); 511 if ((dstat & DSTAT_DFE) == 0) 512 siop_clearfifo(sc); 513 /* no table to flush here */ 514 return 1; 515 case SSTAT1_PHASE_MSGIN: 516 /* 517 * target may be ready to disconnect 518 * Save data pointers just in case. 519 */ 520 INCSTAT(siop_stat_intr_xferdisc); 521 if (scratcha0 & A_flag_data) 522 siop_sdp(siop_cmd); 523 else if ((dstat & DSTAT_DFE) == 0) 524 siop_clearfifo(sc); 525 bus_space_write_1(sc->sc_rt, sc->sc_rh, 526 SIOP_SCRATCHA, 527 scratcha0 & ~A_flag_data); 528 siop_table_sync(siop_cmd, 529 BUS_DMASYNC_PREREAD | 530 BUS_DMASYNC_PREWRITE); 531 CALL_SCRIPT(Ent_msgin); 532 return 1; 533 } 534 printf("%s: unexpected phase mismatch %d\n", 535 sc->sc_dev.dv_xname, 536 sstat1 & SSTAT1_PHASE_MASK); 537 } else { 538 printf("%s: phase mismatch without command\n", 539 sc->sc_dev.dv_xname); 540 } 541 need_reset = 1; 542 } 543 if (sist0 & SIST0_PAR) { 544 /* parity error, reset */ 545 if (siop_cmd) 546 scsi_print_addr(xs->sc_link); 547 else 548 printf("%s:", sc->sc_dev.dv_xname); 549 printf("parity error\n"); 550 goto reset; 551 } 552 if ((sist1 & SIST1_STO) && need_reset == 0) { 553 /* selection time out, assume there's no device here */ 554 if (siop_cmd) { 555 siop_cmd->status = CMDST_DONE; 556 xs->error = XS_SELTIMEOUT; 557 goto end; 558 } else { 559 printf("%s: selection timeout without " 560 "command\n", sc->sc_dev.dv_xname); 561 need_reset = 1; 562 } 563 } 564 if (sist0 & SIST0_UDC) { 565 /* 566 * unexpected disconnect. Usually the target signals 567 * a fatal condition this way. Attempt to get sense. 568 */ 569 if (siop_cmd) 570 goto check_sense; 571 printf("%s: unexpected disconnect without " 572 "command\n", sc->sc_dev.dv_xname); 573 goto reset; 574 } 575 if (sist1 & SIST1_SBMC) { 576 /* SCSI bus mode change */ 577 if (siop_modechange(sc) == 0 || need_reset == 1) 578 goto reset; 579 if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) { 580 /* 581 * we have a script interrupt, it will 582 * restart the script. 583 */ 584 goto scintr; 585 } 586 /* 587 * else we have to restart it ourselve, at the 588 * interrupted instruction. 589 */ 590 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 591 bus_space_read_4(sc->sc_rt, sc->sc_rh, 592 SIOP_DSP) - 8); 593 return 1; 594 } 595 /* Else it's an unhandled exeption (for now). */ 596 printf("%s: unhandled scsi interrupt, sist0=0x%x sist1=0x%x " 597 "sstat1=0x%x DSA=0x%x DSP=0x%x\n", sc->sc_dev.dv_xname, 598 sist0, sist1, 599 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1), 600 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA), 601 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 602 sc->sc_scriptaddr)); 603 if (siop_cmd) { 604 siop_cmd->status = CMDST_DONE; 605 xs->error = XS_SELTIMEOUT; 606 goto end; 607 } 608 need_reset = 1; 609 } 610 if (need_reset) { 611 reset: 612 /* fatal error, reset the bus */ 613 siop_resetbus(sc); 614 /* no table to flush here */ 615 return 1; 616 } 617 618 scintr: 619 if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) { /* script interrupt */ 620 irqcode = bus_space_read_4(sc->sc_rt, sc->sc_rh, 621 SIOP_DSPS); 622 #ifdef DEBUG_INTR 623 printf("script interrupt 0x%x\n", irqcode); 624 #endif 625 if (siop_cmd == NULL) { 626 printf("%s: script interrupt (0x%x) with invalid " 627 "DSA !!!\n", sc->sc_dev.dv_xname, irqcode); 628 goto reset; 629 } 630 /* 631 * an inactive command is only valid if it's a reselect 632 * interrupt: we'll change siop_cmd to point to the rigth one 633 * just here 634 */ 635 if (irqcode != A_int_resel && irqcode != A_int_reseltag && 636 siop_cmd->status != CMDST_ACTIVE && 637 siop_cmd->status != CMDST_SENSE_ACTIVE) { 638 printf("%s: Aie, no command (IRQ code 0x%x current " 639 "status %d) !\n", sc->sc_dev.dv_xname, 640 irqcode, siop_cmd->status); 641 xs = NULL; 642 } else { 643 xs = siop_cmd->xs; 644 siop_target = siop_cmd->siop_target; 645 } 646 switch(irqcode) { 647 case A_int_err: 648 printf("error, DSP=0x%x\n", 649 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, 650 SIOP_DSP) - sc->sc_scriptaddr)); 651 if (xs) { 652 xs->error = XS_SELTIMEOUT; 653 goto end; 654 } else { 655 goto reset; 656 } 657 case A_int_msgin: 658 if (siop_cmd->siop_table->msg_in[0] == 659 MSG_MESSAGE_REJECT) { 660 int msg, extmsg; 661 if (siop_cmd->siop_table->msg_out[0] & 0x80) { 662 /* 663 * message was part of a identify + 664 * something else. Identify shoudl't 665 * have been rejected. 666 */ 667 msg = siop_cmd->siop_table->msg_out[1]; 668 extmsg = 669 siop_cmd->siop_table->msg_out[3]; 670 } else { 671 msg = siop_cmd->siop_table->msg_out[0]; 672 extmsg = 673 siop_cmd->siop_table->msg_out[2]; 674 } 675 if (msg == MSG_MESSAGE_REJECT) { 676 /* MSG_REJECT for a MSG_REJECT !*/ 677 if (xs) 678 scsi_print_addr(xs->sc_link); 679 else 680 printf("%s: ", 681 sc->sc_dev.dv_xname); 682 printf("our reject message was " 683 "rejected\n"); 684 goto reset; 685 } 686 if (msg == MSG_EXTENDED && 687 extmsg == MSG_EXT_WDTR) { 688 /* WDTR rejected, initiate sync */ 689 printf("%s: target %d using 8bit " 690 "transfers\n", sc->sc_dev.dv_xname, 691 xs->sc_link->scsipi_scsi.target); 692 if (xs->sc_link->quirks & SDEV_NOSYNC) { 693 siop_cmd->siop_target->status = 694 TARST_OK; 695 /* no table to flush here */ 696 CALL_SCRIPT(Ent_msgin_ack); 697 return 1; 698 } 699 siop_target->status = TARST_SYNC_NEG; 700 siop_cmd->siop_table->msg_out[0] = 701 MSG_EXTENDED; 702 siop_cmd->siop_table->msg_out[1] = 703 MSG_EXT_SDTR_LEN; 704 siop_cmd->siop_table->msg_out[2] = 705 MSG_EXT_SDTR; 706 siop_cmd->siop_table->msg_out[3] = 707 sc->minsync; 708 siop_cmd->siop_table->msg_out[4] = 709 sc->maxoff; 710 siop_cmd->siop_table->t_msgout.count = 711 htole32(MSG_EXT_SDTR_LEN + 2); 712 siop_cmd->siop_table->t_msgout.addr = 713 htole32(siop_cmd->dsa); 714 siop_table_sync(siop_cmd, 715 BUS_DMASYNC_PREREAD | 716 BUS_DMASYNC_PREWRITE); 717 CALL_SCRIPT(Ent_send_msgout); 718 return 1; 719 } else if (msg == MSG_EXTENDED && 720 extmsg == MSG_EXT_SDTR) { 721 /* sync rejected */ 722 printf("%s: target %d asynchronous\n", 723 sc->sc_dev.dv_xname, 724 xs->sc_link->scsipi_scsi.target); 725 siop_cmd->siop_target->status = 726 TARST_OK; 727 /* no table to flush here */ 728 CALL_SCRIPT(Ent_msgin_ack); 729 return 1; 730 } 731 if (xs) 732 scsi_print_addr(xs->sc_link); 733 else 734 printf("%s: ", sc->sc_dev.dv_xname); 735 if (msg == MSG_EXTENDED) { 736 printf("scsi message reject, extended " 737 "message sent was 0x%x\n", extmsg); 738 } else { 739 printf("scsi message reject, message " 740 "sent was 0x%x\n", msg); 741 } 742 /* no table to flush here */ 743 CALL_SCRIPT(Ent_msgin_ack); 744 return 1; 745 } 746 if (xs) 747 scsi_print_addr(xs->sc_link); 748 else 749 printf("%s: ", sc->sc_dev.dv_xname); 750 printf("unhandled message 0x%x\n", 751 siop_cmd->siop_table->msg_in[0]); 752 siop_cmd->siop_table->t_msgout.count= htole32(1); 753 siop_cmd->siop_table->t_msgout.addr = 754 htole32(siop_cmd->dsa); 755 siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT; 756 siop_table_sync(siop_cmd, 757 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 758 CALL_SCRIPT(Ent_send_msgout); 759 return 1; 760 case A_int_extmsgin: 761 #ifdef DEBUG_INTR 762 printf("extended message: msg 0x%x len %d\n", 763 siop_cmd->siop_table->msg_in[2], 764 siop_cmd->siop_table->msg_in[1]); 765 #endif 766 if (siop_cmd->siop_table->msg_in[1] > 6) 767 printf("%s: extended message too big (%d)\n", 768 sc->sc_dev.dv_xname, 769 siop_cmd->siop_table->msg_in[1]); 770 siop_cmd->siop_table->t_extmsgdata.count = 771 htole32(siop_cmd->siop_table->msg_in[1] - 1); 772 siop_cmd->siop_table->t_extmsgdata.addr = 773 htole32( 774 le32toh(siop_cmd->siop_table->t_extmsgin.addr) 775 + 2); 776 siop_table_sync(siop_cmd, 777 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 778 CALL_SCRIPT(Ent_get_extmsgdata); 779 return 1; 780 case A_int_extmsgdata: 781 #ifdef DEBUG_INTR 782 { 783 int i; 784 printf("extended message: 0x%x, data:", 785 siop_cmd->siop_table->msg_in[2]); 786 for (i = 3; i < 2 + siop_cmd->siop_table->msg_in[1]; 787 i++) 788 printf(" 0x%x", 789 siop_cmd->siop_table->msg_in[i]); 790 printf("\n"); 791 } 792 #endif 793 if (siop_cmd->siop_table->msg_in[2] == MSG_EXT_WDTR) { 794 switch (siop_wdtr_neg(siop_cmd)) { 795 case SIOP_NEG_NOP: 796 break; 797 case SIOP_NEG_MSGOUT: 798 siop_table_sync(siop_cmd, 799 BUS_DMASYNC_PREREAD | 800 BUS_DMASYNC_PREWRITE); 801 CALL_SCRIPT(Ent_send_msgout); 802 break; 803 case SIOP_NEG_ACK: 804 CALL_SCRIPT(Ent_msgin_ack); 805 default: 806 panic("invalid retval from " 807 "siop_wdtr_neg()"); 808 } 809 return(1); 810 } 811 if (siop_cmd->siop_table->msg_in[2] == MSG_EXT_SDTR) { 812 switch (siop_sdtr_neg(siop_cmd)) { 813 case SIOP_NEG_NOP: 814 break; 815 case SIOP_NEG_MSGOUT: 816 siop_table_sync(siop_cmd, 817 BUS_DMASYNC_PREREAD | 818 BUS_DMASYNC_PREWRITE); 819 CALL_SCRIPT(Ent_send_msgout); 820 break; 821 case SIOP_NEG_ACK: 822 CALL_SCRIPT(Ent_msgin_ack); 823 break; 824 default: 825 panic("invalid retval from " 826 "siop_wdtr_neg()"); 827 } 828 return(1); 829 } 830 /* send a message reject */ 831 siop_cmd->siop_table->t_msgout.count = 832 htole32(1); 833 siop_cmd->siop_table->t_msgout.addr = 834 htole32(siop_cmd->dsa); 835 siop_cmd->siop_table->msg_out[0] = 836 MSG_MESSAGE_REJECT; 837 siop_table_sync(siop_cmd, 838 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 839 CALL_SCRIPT(Ent_send_msgout); 840 return 1; 841 case A_int_resel: /* reselected */ 842 case A_int_reseltag: /* reselected with tag */ 843 INCSTAT(siop_stat_intr_reselect); 844 if ((siop_cmd->siop_table->msg_in[0] & 0x80) == 0) { 845 printf("%s: reselect without identify (%d)\n", 846 sc->sc_dev.dv_xname, 847 siop_cmd->siop_table->msg_in[0]); 848 goto reset; 849 } 850 target = bus_space_read_1(sc->sc_rt, 851 sc->sc_rh, SIOP_SCRATCHA); 852 if ((target & 0x80) == 0) { 853 printf("reselect without id (%d)\n", target); 854 goto reset; 855 } 856 target &= 0x0f; 857 lun = siop_cmd->siop_table->msg_in[0] & 0x07; 858 #ifdef DEBUG_DR 859 printf("reselected by target %d lun %d\n", 860 target, lun); 861 #endif 862 siop_cmd = 863 sc->targets[target]->active_list[lun].tqh_first; 864 if (siop_cmd == NULL) { 865 printf("%s: reselected without cmd\n", 866 sc->sc_dev.dv_xname); 867 goto reset; 868 } 869 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSA, 870 siop_cmd->dsa); 871 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 872 (sc->targets[target]->id >> 24) & 0xff); 873 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 874 (sc->targets[target]->id >> 8) & 0xff); 875 /* no table to flush */ 876 CALL_SCRIPT(Ent_selected); 877 return 1; 878 case A_int_disc: 879 INCSTAT(siop_stat_intr_sdp); 880 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, 881 SIOP_SCRATCHA + 1); 882 #ifdef DEBUG_DR 883 printf("disconnect offset %d\n", offset); 884 #endif 885 if (offset > SIOP_NSG) { 886 printf("%s: bad offset for disconnect (%d)\n", 887 sc->sc_dev.dv_xname, offset); 888 goto reset; 889 } 890 /* 891 * offset == SIOP_NSG may be a valid condition if 892 * we get a sdp when the xfer is done. 893 * Don't call memmove in this case. 894 */ 895 if (offset < SIOP_NSG) { 896 memmove(&siop_cmd->siop_table->data[0], 897 &siop_cmd->siop_table->data[offset], 898 (SIOP_NSG - offset) * sizeof(scr_table_t)); 899 siop_table_sync(siop_cmd, 900 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 901 } 902 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 903 sc->sc_sheddma->dm_segs[0].ds_addr); 904 return 1; 905 case A_int_resfail: 906 printf("reselect failed\n"); 907 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 908 sc->sc_sheddma->dm_segs[0].ds_addr); 909 return 1; 910 case A_int_done: 911 if (xs == NULL) { 912 printf("%s: done without command, DSA=0x%lx\n", 913 sc->sc_dev.dv_xname, (u_long)siop_cmd->dsa); 914 siop_cmd->status = CMDST_FREE; 915 bus_space_write_4(sc->sc_rt, sc->sc_rh, 916 SIOP_DSP, 917 sc->sc_sheddma->dm_segs[0].ds_addr); 918 siop_start(sc); 919 return 1; 920 } 921 if (siop_target->status == TARST_PROBING && 922 xs->sc_link->device_softc != NULL) 923 siop_target->status = TARST_ASYNC; 924 #ifdef DEBUG_INTR 925 printf("done, DSA=0x%lx target id 0x%x last msg " 926 "in=0x%x status=0x%x\n", (u_long)siop_cmd->dsa, 927 le32toh(siop_cmd->siop_table->id), 928 siop_cmd->siop_table->msg_in[0], 929 le32toh(siop_cmd->siop_table->status)); 930 #endif 931 INCSTAT(siop_stat_intr_done); 932 if (siop_cmd->status == CMDST_SENSE_ACTIVE) 933 siop_cmd->status = CMDST_SENSE_DONE; 934 else 935 siop_cmd->status = CMDST_DONE; 936 switch(le32toh(siop_cmd->siop_table->status)) { 937 case SCSI_OK: 938 xs->error = (siop_cmd->status == CMDST_DONE) ? 939 XS_NOERROR : XS_SENSE; 940 break; 941 case SCSI_BUSY: 942 xs->error = XS_BUSY; 943 break; 944 case SCSI_CHECK: 945 check_sense: 946 if (siop_cmd->status == CMDST_SENSE_DONE) { 947 /* request sense on a request sense ? */ 948 printf("request sense failed\n"); 949 xs->error = XS_DRIVER_STUFFUP; 950 } else { 951 siop_cmd->status = CMDST_SENSE; 952 } 953 break; 954 case 0xff: 955 /* 956 * the status byte was not updated, cmd was 957 * aborted 958 */ 959 xs->error = XS_SELTIMEOUT; 960 break; 961 default: 962 xs->error = XS_DRIVER_STUFFUP; 963 } 964 goto end; 965 default: 966 printf("unknown irqcode %x\n", irqcode); 967 xs->error = XS_SELTIMEOUT; 968 goto end; 969 } 970 return 1; 971 } 972 /* We just should't get there */ 973 panic("siop_intr: I shouldn't be there !"); 974 return 1; 975 end: 976 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 977 sc->sc_sheddma->dm_segs[0].ds_addr); 978 lun = siop_cmd->xs->sc_link->scsipi_scsi.lun; 979 siop_scsicmd_end(siop_cmd); 980 if (siop_cmd->status == CMDST_FREE) { 981 TAILQ_REMOVE(&siop_target->active_list[lun], 982 siop_cmd, next); 983 TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next); 984 } 985 siop_start(sc); 986 return 1; 987 } 988 989 void 990 siop_scsicmd_end(siop_cmd) 991 struct siop_cmd *siop_cmd; 992 { 993 struct scsipi_xfer *xs = siop_cmd->xs; 994 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 995 996 if (siop_cmd->status != CMDST_SENSE_DONE && 997 xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 998 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 999 siop_cmd->dmamap_data->dm_mapsize, 1000 (xs->xs_control & XS_CTL_DATA_IN) ? 1001 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1002 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data); 1003 } 1004 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1005 if (siop_cmd->status == CMDST_SENSE) { 1006 /* issue a request sense for this target */ 1007 int error, i; 1008 siop_cmd->rs_cmd.opcode = REQUEST_SENSE; 1009 siop_cmd->rs_cmd.byte2 = xs->sc_link->scsipi_scsi.lun << 5; 1010 siop_cmd->rs_cmd.unused[0] = siop_cmd->rs_cmd.unused[1] = 0; 1011 siop_cmd->rs_cmd.length = sizeof(struct scsipi_sense_data); 1012 siop_cmd->rs_cmd.control = 0; 1013 siop_cmd->siop_table->status = htole32(0xff); /*invalid status*/ 1014 siop_cmd->siop_table->t_msgout.count= htole32(1); 1015 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 1016 siop_cmd->siop_table->msg_out[0] = 1017 MSG_IDENTIFY(xs->sc_link->scsipi_scsi.lun, 1); 1018 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd, 1019 &siop_cmd->rs_cmd, sizeof(struct scsipi_sense), 1020 NULL, BUS_DMA_NOWAIT); 1021 if (error) { 1022 printf("%s: unable to load cmd DMA map: %d", 1023 sc->sc_dev.dv_xname, error); 1024 xs->error = XS_DRIVER_STUFFUP; 1025 goto out; 1026 } 1027 siop_cmd->siop_table->cmd.count = 1028 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 1029 siop_cmd->siop_table->cmd.addr = 1030 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 1031 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data, 1032 &xs->sense.scsi_sense, sizeof(struct scsipi_sense_data), 1033 NULL, BUS_DMA_NOWAIT); 1034 if (error) { 1035 printf("%s: unable to load sense DMA map: %d", 1036 sc->sc_dev.dv_xname, error); 1037 xs->error = XS_DRIVER_STUFFUP; 1038 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1039 goto out; 1040 } 1041 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 1042 siop_cmd->siop_table->data[i].count = 1043 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 1044 siop_cmd->siop_table->data[i].addr = 1045 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 1046 } 1047 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1048 siop_cmd->dmamap_data->dm_mapsize, BUS_DMASYNC_PREREAD); 1049 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd, 0, 1050 siop_cmd->dmamap_cmd->dm_mapsize, BUS_DMASYNC_PREWRITE); 1051 siop_table_sync(siop_cmd, BUS_DMASYNC_PREWRITE); 1052 return; 1053 } else if (siop_cmd->status == CMDST_SENSE_DONE) { 1054 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1055 siop_cmd->dmamap_data->dm_mapsize, BUS_DMASYNC_POSTREAD); 1056 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data); 1057 } 1058 out: 1059 callout_stop(&siop_cmd->xs->xs_callout); 1060 siop_cmd->status = CMDST_FREE; 1061 xs->xs_status |= XS_STS_DONE; 1062 xs->resid = 0; 1063 if ((xs->xs_control & XS_CTL_POLL) == 0) 1064 scsipi_done (xs); 1065 } 1066 1067 /* 1068 * handle a bus reset: reset chip, unqueue all active commands and report 1069 * loosage to upper layer. 1070 * As the upper layer may requeue immediatly we have to first store 1071 * all active commands in a temporary queue. 1072 */ 1073 void 1074 siop_handle_reset(sc) 1075 struct siop_softc *sc; 1076 { 1077 struct cmd_list reset_list; 1078 struct siop_cmd *siop_cmd, *next_siop_cmd; 1079 int target, lun; 1080 /* 1081 * scsi bus reset. reset the chip and restart 1082 * the queue. Need to clean up all active commands 1083 */ 1084 printf("%s: scsi bus reset\n", sc->sc_dev.dv_xname); 1085 /* stop, reset and restart the chip */ 1086 siop_reset(sc); 1087 TAILQ_INIT(&reset_list); 1088 /* find all active commands */ 1089 for (target = 0; target <= sc->sc_link.scsipi_scsi.max_target; 1090 target++) { 1091 if (sc->targets[target] == NULL) 1092 continue; 1093 for (lun = 0; lun < 8; lun++) { 1094 for (siop_cmd = 1095 TAILQ_FIRST(&sc->targets[target]->active_list[lun]); 1096 siop_cmd != NULL; siop_cmd = next_siop_cmd) { 1097 next_siop_cmd = TAILQ_NEXT(siop_cmd, next); 1098 if (siop_cmd->status < CMDST_ACTIVE) 1099 continue; 1100 printf("cmd %p (target %d) in reset list\n", 1101 siop_cmd, target); 1102 TAILQ_REMOVE( 1103 &sc->targets[target]->active_list[lun], 1104 siop_cmd, next); 1105 TAILQ_INSERT_TAIL(&reset_list, siop_cmd, next); 1106 } 1107 } 1108 sc->targets[target]->status = TARST_ASYNC; 1109 sc->targets[target]->flags = ~(TARF_SYNC | TARF_WIDE); 1110 } 1111 for (siop_cmd = TAILQ_FIRST(&reset_list); siop_cmd != NULL; 1112 siop_cmd = next_siop_cmd) { 1113 next_siop_cmd = TAILQ_NEXT(siop_cmd, next); 1114 siop_cmd->xs->error = (siop_cmd->flags & CMDFL_TIMEOUT) ? 1115 XS_TIMEOUT : XS_RESET; 1116 printf("cmd %p about to be processed\n", siop_cmd); 1117 if (siop_cmd->status == CMDST_SENSE || 1118 siop_cmd->status == CMDST_SENSE_ACTIVE) 1119 siop_cmd->status = CMDST_SENSE_DONE; 1120 else 1121 siop_cmd->status = CMDST_DONE; 1122 TAILQ_REMOVE(&reset_list, siop_cmd, next); 1123 siop_scsicmd_end(siop_cmd); 1124 TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next); 1125 } 1126 } 1127 1128 int 1129 siop_scsicmd(xs) 1130 struct scsipi_xfer *xs; 1131 { 1132 struct siop_softc *sc = (struct siop_softc *)xs->sc_link->adapter_softc; 1133 struct siop_cmd *siop_cmd; 1134 int s, error, i; 1135 int target = xs->sc_link->scsipi_scsi.target; 1136 int lun = xs->sc_link->scsipi_scsi.lun; 1137 1138 s = splbio(); 1139 #ifdef DEBUG_SHED 1140 printf("starting cmd for %d:%d\n", target, lun); 1141 #endif 1142 siop_cmd = sc->free_list.tqh_first; 1143 if (siop_cmd) { 1144 TAILQ_REMOVE(&sc->free_list, siop_cmd, next); 1145 } else { 1146 if (siop_morecbd(sc) == 0) { 1147 siop_cmd = sc->free_list.tqh_first; 1148 #ifdef DIAGNOSTIC 1149 if (siop_cmd == NULL) 1150 panic("siop_morecbd succeed and does nothing"); 1151 #endif 1152 TAILQ_REMOVE(&sc->free_list, siop_cmd, next); 1153 } 1154 } 1155 splx(s); 1156 if (siop_cmd == NULL) { 1157 xs->error = XS_DRIVER_STUFFUP; 1158 return(TRY_AGAIN_LATER); 1159 } 1160 #ifdef DIAGNOSTIC 1161 if (siop_cmd->status != CMDST_FREE) 1162 panic("siop_scsicmd: new cmd not free"); 1163 #endif 1164 if (sc->targets[target] == NULL) { 1165 sc->targets[target] = 1166 malloc(sizeof(struct siop_target), M_DEVBUF, M_NOWAIT); 1167 if (sc->targets[target] == NULL) { 1168 printf("%s: can't malloc memory for target %d\n", 1169 sc->sc_dev.dv_xname, target); 1170 xs->error = XS_DRIVER_STUFFUP; 1171 return(TRY_AGAIN_LATER); 1172 } 1173 sc->targets[target]->siop_sc = sc; 1174 sc->targets[target]->status = TARST_PROBING; 1175 sc->targets[target]->flags = 0; 1176 sc->targets[target]->id = sc->clock_div << 24; /* scntl3 */ 1177 sc->targets[target]->id |= target << 16; /* id */ 1178 /* sc->targets[target]->id |= 0x0 << 8; scxfer is 0 */ 1179 for (i = 0; i < 8; i++) 1180 TAILQ_INIT(&sc->targets[target]->active_list[i]); 1181 } 1182 siop_cmd->siop_target = sc->targets[target]; 1183 siop_cmd->xs = xs; 1184 siop_cmd->siop_table->id = htole32(sc->targets[target]->id); 1185 siop_cmd->siop_table->t_msgout.count= htole32(1); 1186 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 1187 memset(siop_cmd->siop_table->msg_out, 0, 8); 1188 siop_cmd->siop_table->msg_out[0] = MSG_IDENTIFY(lun, 1); 1189 #if 0 1190 siop_cmd->siop_table->msg_out[1] = MSG_SIMPLE_Q_TAG; 1191 siop_cmd->siop_table->msg_out[2] = 0; 1192 #endif 1193 if (sc->targets[target]->status == TARST_ASYNC) { 1194 if (sc->features & SF_BUS_WIDE && 1195 (xs->sc_link->quirks & SDEV_NOWIDE) == 0) { 1196 sc->targets[target]->status = TARST_WIDE_NEG; 1197 siop_cmd->siop_table->msg_out[1] = MSG_EXTENDED; 1198 siop_cmd->siop_table->msg_out[2] = MSG_EXT_WDTR_LEN; 1199 siop_cmd->siop_table->msg_out[3] = MSG_EXT_WDTR; 1200 siop_cmd->siop_table->msg_out[4] = 1201 MSG_EXT_WDTR_BUS_16_BIT; 1202 siop_cmd->siop_table->t_msgout.count= 1203 htole32(MSG_EXT_WDTR_LEN + 2 + 1); 1204 } else if ((xs->sc_link->quirks & SDEV_NOSYNC) == 0) { 1205 sc->targets[target]->status = TARST_SYNC_NEG; 1206 siop_cmd->siop_table->msg_out[1] = MSG_EXTENDED; 1207 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR_LEN; 1208 siop_cmd->siop_table->msg_out[3] = MSG_EXT_SDTR; 1209 siop_cmd->siop_table->msg_out[4] = sc->minsync; 1210 siop_cmd->siop_table->msg_out[5] = sc->maxoff; 1211 siop_cmd->siop_table->t_msgout.count= 1212 htole32(MSG_EXT_SDTR_LEN + 2 +1); 1213 } else { 1214 sc->targets[target]->status = TARST_OK; 1215 } 1216 } 1217 siop_cmd->siop_table->status = htole32(0xff); /* set invalid status */ 1218 1219 /* load the DMA maps */ 1220 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd, 1221 xs->cmd, xs->cmdlen, NULL, BUS_DMA_NOWAIT); 1222 if (error) { 1223 printf("%s: unable to load cmd DMA map: %d", 1224 sc->sc_dev.dv_xname, error); 1225 xs->error = XS_DRIVER_STUFFUP; 1226 return(TRY_AGAIN_LATER); 1227 } 1228 siop_cmd->siop_table->cmd.count = 1229 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 1230 siop_cmd->siop_table->cmd.addr = 1231 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 1232 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 1233 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data, 1234 xs->data, xs->datalen, NULL, BUS_DMA_NOWAIT); 1235 if (error) { 1236 printf("%s: unable to load cmd DMA map: %d", 1237 sc->sc_dev.dv_xname, error); 1238 xs->error = XS_DRIVER_STUFFUP; 1239 return(TRY_AGAIN_LATER); 1240 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1241 } 1242 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 1243 siop_cmd->siop_table->data[i].count = 1244 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 1245 siop_cmd->siop_table->data[i].addr = 1246 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 1247 } 1248 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1249 siop_cmd->dmamap_data->dm_mapsize, 1250 (xs->xs_control & XS_CTL_DATA_IN) ? 1251 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1252 } 1253 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd, 0, 1254 siop_cmd->dmamap_cmd->dm_mapsize, BUS_DMASYNC_PREWRITE); 1255 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1256 1257 siop_cmd->status = CMDST_READY; 1258 s = splbio(); 1259 TAILQ_INSERT_TAIL(&sc->targets[target]->active_list[lun], 1260 siop_cmd, next); 1261 siop_start(sc); 1262 if (xs->xs_control & XS_CTL_POLL) { 1263 /* poll for command completion */ 1264 while ((xs->xs_status & XS_STS_DONE) == 0) 1265 siop_intr(sc); 1266 splx(s); 1267 return (COMPLETE); 1268 } 1269 splx(s); 1270 return (SUCCESSFULLY_QUEUED); 1271 } 1272 1273 void 1274 siop_start(sc) 1275 struct siop_softc *sc; 1276 { 1277 struct siop_cmd *siop_cmd; 1278 u_int32_t *scr; 1279 u_int32_t dsa; 1280 int timeout; 1281 int target, lun, slot; 1282 int newcmd = 0; 1283 1284 /* 1285 * first make sure to read valid data 1286 */ 1287 siop_shed_sync(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1288 1289 /* 1290 * The queue management here is a bit tricky: the script always looks 1291 * at the slot from first to last, so if we always use the first 1292 * free slot commands can stay at the tail of the queue ~forever. 1293 * The algorithm used here is to restart from the head when we know 1294 * that the queue is empty, and only add commands after the last one. 1295 * When we're at the end of the queue wait for the script to clear it. 1296 * The best thing to do here would be to implement a circular queue, 1297 * but using only 53c720 features this can be "interesting". 1298 * A mid-way solution could be to implement 2 queues and swap orders. 1299 */ 1300 slot = sc->sc_currshedslot; 1301 scr = &sc->sc_shed[(Ent_nextslot / 4) * slot]; 1302 /* 1303 * if relative addr of first jump is not 0 the slot is free. As this is 1304 * the last used slot, all previous slots are free, we can restart 1305 * from 0. 1306 */ 1307 if (scr[Ent_slot / 4 + 1] != 0) { 1308 slot = sc->sc_currshedslot = 0; 1309 } else { 1310 slot++; 1311 } 1312 1313 for (target = 0; target <= sc->sc_link.scsipi_scsi.max_target; 1314 target++) { 1315 if (sc->targets[target] == NULL) 1316 continue; 1317 for (lun = 0; lun < 8; lun++) { 1318 siop_cmd = 1319 sc->targets[target]->active_list[lun].tqh_first; 1320 if (siop_cmd == NULL) 1321 continue; 1322 if (siop_cmd->status != CMDST_READY && 1323 siop_cmd->status != CMDST_SENSE) 1324 continue; 1325 /* find a free scheduler slot and load it */ 1326 for (; slot < sc->sc_nshedslots; slot++) { 1327 scr = &sc->sc_shed[(Ent_nextslot / 4) * slot]; 1328 /* 1329 * if relative addr of first jump is 0 the 1330 * slot isn't free 1331 */ 1332 if (scr[Ent_slot / 4 + 1] == 0) 1333 continue; 1334 #ifdef DEBUG_SHED 1335 printf("using slot %d for DSA 0x%lx\n", slot, 1336 (u_long)siop_cmd->dsa); 1337 #endif 1338 /* note that we started a new command */ 1339 newcmd = 1; 1340 /* mark command as active */ 1341 if (siop_cmd->status == CMDST_READY) 1342 siop_cmd->status = CMDST_ACTIVE; 1343 else if (siop_cmd->status == CMDST_SENSE) 1344 siop_cmd->status = CMDST_SENSE_ACTIVE; 1345 else 1346 panic("siop_start: bad status"); 1347 /* patch script with DSA addr */ 1348 dsa = siop_cmd->dsa; 1349 /* 1350 * 0x78000000 is a 'move data8 to reg'. data8 1351 * is the second octet, reg offset is the third. 1352 */ 1353 scr[Ent_idsa0 / 4] = 1354 htole32(0x78100000 | 1355 ((dsa & 0x000000ff) << 8)); 1356 scr[Ent_idsa1 / 4] = 1357 htole32(0x78110000 | 1358 ( dsa & 0x0000ff00 )); 1359 scr[Ent_idsa2 / 4] = 1360 htole32(0x78120000 | 1361 ((dsa & 0x00ff0000) >> 8)); 1362 scr[Ent_idsa3 / 4] = 1363 htole32(0x78130000 | 1364 ((dsa & 0xff000000) >> 16)); 1365 /* handle timeout */ 1366 if (siop_cmd->status == CMDST_ACTIVE) { 1367 if ((siop_cmd->xs->xs_control & 1368 XS_CTL_POLL) == 0) { 1369 /* start exire timer */ 1370 timeout = (u_int64_t) 1371 siop_cmd->xs->timeout * 1372 (u_int64_t)hz / 1000; 1373 if (timeout == 0) 1374 timeout = 1; 1375 callout_reset( 1376 &siop_cmd->xs->xs_callout, 1377 timeout, siop_timeout, 1378 siop_cmd); 1379 } 1380 } 1381 /* 1382 * Change jump offset so that this slot will be 1383 * handled 1384 */ 1385 scr[Ent_slot / 4 + 1] = 0; 1386 break; 1387 } 1388 /* no more free slot, no need to continue */ 1389 if (slot == sc->sc_nshedslots) { 1390 goto end; 1391 } 1392 sc->sc_currshedslot = slot; 1393 } 1394 } 1395 end: 1396 /* if nothing changed no need to flush cache and wakeup script */ 1397 if (newcmd == 0) 1398 return; 1399 /* make sure SCRIPT processor will read valid data */ 1400 siop_shed_sync(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1401 /* Signal script it has some work to do */ 1402 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SIGP); 1403 /* and wait for IRQ */ 1404 return; 1405 } 1406 1407 void 1408 siop_timeout(v) 1409 void *v; 1410 { 1411 struct siop_cmd *siop_cmd = v; 1412 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 1413 int s; 1414 1415 scsi_print_addr(siop_cmd->xs->sc_link); 1416 printf("command timeout\n"); 1417 1418 s = splbio(); 1419 /* reset the scsi bus */ 1420 siop_resetbus(sc); 1421 1422 /* deactivate callout */ 1423 callout_stop(&siop_cmd->xs->xs_callout); 1424 /* mark command has being timed out; siop_intr will handle it */ 1425 /* 1426 * mark command has being timed out and just return; 1427 * the bus reset will generate an interrupt, 1428 * it will be handled in siop_intr() 1429 */ 1430 siop_cmd->flags |= CMDFL_TIMEOUT; 1431 splx(s); 1432 return; 1433 1434 } 1435 1436 void 1437 siop_dump_script(sc) 1438 struct siop_softc *sc; 1439 { 1440 int i; 1441 siop_shed_sync(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1442 for (i = 0; i < NBPG / 4; i += 2) { 1443 printf("0x%04x: 0x%08x 0x%08x", i * 4, 1444 le32toh(sc->sc_script[i]), le32toh(sc->sc_script[i+1])); 1445 if ((le32toh(sc->sc_script[i]) & 0xe0000000) == 0xc0000000) { 1446 i++; 1447 printf(" 0x%08x", le32toh(sc->sc_script[i+1])); 1448 } 1449 printf("\n"); 1450 } 1451 } 1452 1453 int 1454 siop_morecbd(sc) 1455 struct siop_softc *sc; 1456 { 1457 int error, i; 1458 bus_dma_segment_t seg; 1459 int rseg; 1460 struct siop_cbd *newcbd; 1461 1462 /* allocate a new list head */ 1463 newcbd = malloc(sizeof(struct siop_cbd), M_DEVBUF, M_NOWAIT); 1464 if (newcbd == NULL) { 1465 printf("%s: can't allocate memory for command descriptors " 1466 "head\n", sc->sc_dev.dv_xname); 1467 return ENOMEM; 1468 } 1469 1470 /* allocate cmd list */ 1471 newcbd->cmds = 1472 malloc(sizeof(struct siop_cmd) * SIOP_NCMDPB, M_DEVBUF, M_NOWAIT); 1473 if (newcbd->cmds == NULL) { 1474 printf("%s: can't allocate memory for command descriptors\n", 1475 sc->sc_dev.dv_xname); 1476 error = ENOMEM; 1477 goto bad3; 1478 } 1479 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, NBPG, 0, &seg, 1, &rseg, 1480 BUS_DMA_NOWAIT); 1481 if (error) { 1482 printf("%s: unable to allocate cbd DMA memory, error = %d\n", 1483 sc->sc_dev.dv_xname, error); 1484 goto bad2; 1485 } 1486 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 1487 (caddr_t *)&newcbd->xfers, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1488 if (error) { 1489 printf("%s: unable to map cbd DMA memory, error = %d\n", 1490 sc->sc_dev.dv_xname, error); 1491 goto bad2; 1492 } 1493 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, NBPG, 0, 1494 BUS_DMA_NOWAIT, &newcbd->xferdma); 1495 if (error) { 1496 printf("%s: unable to create cbd DMA map, error = %d\n", 1497 sc->sc_dev.dv_xname, error); 1498 goto bad1; 1499 } 1500 error = bus_dmamap_load(sc->sc_dmat, newcbd->xferdma, newcbd->xfers, 1501 NBPG, NULL, BUS_DMA_NOWAIT); 1502 if (error) { 1503 printf("%s: unable to load cbd DMA map, error = %d\n", 1504 sc->sc_dev.dv_xname, error); 1505 goto bad0; 1506 } 1507 1508 for (i = 0; i < SIOP_NCMDPB; i++) { 1509 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, SIOP_NSG, 1510 MAXPHYS, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1511 &newcbd->cmds[i].dmamap_data); 1512 if (error) { 1513 printf("%s: unable to create data DMA map for cbd: " 1514 "error %d\n", 1515 sc->sc_dev.dv_xname, error); 1516 goto bad0; 1517 } 1518 error = bus_dmamap_create(sc->sc_dmat, 1519 sizeof(struct scsipi_generic), 1, 1520 sizeof(struct scsipi_generic), 0, 1521 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1522 &newcbd->cmds[i].dmamap_cmd); 1523 if (error) { 1524 printf("%s: unable to create cmd DMA map for cbd %d\n", 1525 sc->sc_dev.dv_xname, error); 1526 goto bad0; 1527 } 1528 newcbd->cmds[i].siop_cbdp = newcbd; 1529 newcbd->cmds[i].siop_table = &newcbd->xfers[i]; 1530 memset(newcbd->cmds[i].siop_table, 0, sizeof(struct siop_xfer)); 1531 newcbd->cmds[i].dsa = newcbd->xferdma->dm_segs[0].ds_addr + 1532 i * sizeof(struct siop_xfer); 1533 newcbd->cmds[i].status = CMDST_FREE; 1534 newcbd->cmds[i].siop_table->t_msgout.count= htole32(1); 1535 newcbd->cmds[i].siop_table->t_msgout.addr = 1536 htole32(newcbd->cmds[i].dsa); 1537 newcbd->cmds[i].siop_table->t_msgin.count= htole32(1); 1538 newcbd->cmds[i].siop_table->t_msgin.addr = 1539 htole32(newcbd->cmds[i].dsa + 8); 1540 newcbd->cmds[i].siop_table->t_extmsgin.count= htole32(2); 1541 newcbd->cmds[i].siop_table->t_extmsgin.addr = htole32( 1542 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr) + 1); 1543 newcbd->cmds[i].siop_table->t_msgtag.count= htole32(2); 1544 newcbd->cmds[i].siop_table->t_msgtag.addr = htole32( 1545 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr) + 1); 1546 newcbd->cmds[i].siop_table->t_status.count= htole32(1); 1547 newcbd->cmds[i].siop_table->t_status.addr = htole32( 1548 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr) + 8); 1549 TAILQ_INSERT_TAIL(&sc->free_list, &newcbd->cmds[i], next); 1550 #ifdef DEBUG 1551 printf("tables[%d]: out=0x%x in=0x%x status=0x%x\n", i, 1552 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr), 1553 le32toh(newcbd->cmds[i].siop_table->t_msgout.addr), 1554 le32toh(newcbd->cmds[i].siop_table->t_status.addr)); 1555 #endif 1556 } 1557 TAILQ_INSERT_TAIL(&sc->cmds, newcbd, next); 1558 return 0; 1559 bad0: 1560 bus_dmamap_destroy(sc->sc_dmat, newcbd->xferdma); 1561 bad1: 1562 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1563 bad2: 1564 free(newcbd->cmds, M_DEVBUF); 1565 bad3: 1566 free(newcbd, M_DEVBUF); 1567 return error; 1568 } 1569 1570 #ifdef SIOP_STATS 1571 void 1572 siop_printstats() 1573 { 1574 printf("siop_stat_intr %d\n", siop_stat_intr); 1575 printf("siop_stat_intr_shortxfer %d\n", siop_stat_intr_shortxfer); 1576 printf("siop_stat_intr_xferdisc %d\n", siop_stat_intr_xferdisc); 1577 printf("siop_stat_intr_sdp %d\n", siop_stat_intr_sdp); 1578 printf("siop_stat_intr_reselect %d\n", siop_stat_intr_reselect); 1579 printf("siop_stat_intr_done %d\n", siop_stat_intr_done); 1580 } 1581 #endif 1582
Indexes created Mon Oct 20 20:10:13 GMT 2025