siop.c revision 1.25
1 /* $NetBSD: siop.c,v 1.25 2000/07/19 16:07:00 pk Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 42 #include <machine/endian.h> 43 #include <machine/bus.h> 44 45 #include <dev/microcode/siop/siop.out> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsi_message.h> 49 #include <dev/scsipi/scsipi_all.h> 50 51 #include <dev/scsipi/scsiconf.h> 52 53 #include <dev/ic/siopreg.h> 54 #include <dev/ic/siopvar.h> 55 #include <dev/ic/siopvar_common.h> 56 57 #undef DEBUG 58 #undef DEBUG_DR 59 #undef DEBUG_INTR 60 #undef DEBUG_SHED 61 #undef DUMP_SCRIPT 62 63 #define SIOP_STATS 64 65 #ifndef SIOP_DEFAULT_TARGET 66 #define SIOP_DEFAULT_TARGET 7 67 #endif 68 69 /* number of cmd descriptors per block */ 70 #define SIOP_NCMDPB (NBPG / sizeof(struct siop_xfer)) 71 72 void siop_reset __P((struct siop_softc *)); 73 void siop_handle_reset __P((struct siop_softc *)); 74 void siop_scsicmd_end __P((struct siop_cmd *)); 75 void siop_start __P((struct siop_softc *)); 76 void siop_timeout __P((void *)); 77 int siop_scsicmd __P((struct scsipi_xfer *)); 78 void siop_dump_script __P((struct siop_softc *)); 79 int siop_morecbd __P((struct siop_softc *)); 80 81 struct scsipi_adapter siop_adapter = { 82 0, 83 siop_scsicmd, 84 siop_minphys, 85 siop_ioctl, 86 NULL, 87 NULL, 88 }; 89 90 struct scsipi_device siop_dev = { 91 NULL, 92 NULL, 93 NULL, 94 NULL, 95 }; 96 97 #ifdef SIOP_STATS 98 static int siop_stat_intr = 0; 99 static int siop_stat_intr_shortxfer = 0; 100 static int siop_stat_intr_sdp = 0; 101 static int siop_stat_intr_done = 0; 102 static int siop_stat_intr_reselect = 0; 103 static int siop_stat_intr_xferdisc = 0; 104 void siop_printstats __P((void)); 105 #define INCSTAT(x) x++ 106 #else 107 #define INCSTAT(x) 108 #endif 109 110 static __inline__ void siop_table_sync __P((struct siop_cmd *, int)); 111 static __inline__ void 112 siop_table_sync(siop_cmd, ops) 113 struct siop_cmd *siop_cmd; 114 int ops; 115 { 116 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 117 bus_addr_t offset; 118 119 offset = siop_cmd->dsa - 120 siop_cmd->siop_cbdp->xferdma->dm_segs[0].ds_addr; 121 bus_dmamap_sync(sc->sc_dmat, siop_cmd->siop_cbdp->xferdma, offset, 122 sizeof(struct siop_xfer), ops); 123 } 124 125 static __inline__ void siop_shed_sync __P((struct siop_softc *, int)); 126 static __inline__ void 127 siop_shed_sync(sc, ops) 128 struct siop_softc *sc; 129 int ops; 130 { 131 bus_dmamap_sync(sc->sc_dmat, sc->sc_sheddma, 0, NBPG, ops); 132 } 133 134 void 135 siop_attach(sc) 136 struct siop_softc *sc; 137 { 138 int error, i; 139 bus_dma_segment_t seg; 140 int rseg; 141 142 /* 143 * Allocate DMA-safe memory for the script and script scheduler 144 * and map it. 145 */ 146 if ((sc->features & SF_CHIP_RAM) == 0) { 147 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, 148 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 149 if (error) { 150 printf("%s: unable to allocate script DMA memory, " 151 "error = %d\n", sc->sc_dev.dv_xname, error); 152 return; 153 } 154 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 155 (caddr_t *)&sc->sc_script, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 156 if (error) { 157 printf("%s: unable to map script DMA memory, " 158 "error = %d\n", sc->sc_dev.dv_xname, error); 159 return; 160 } 161 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, 162 NBPG, 0, BUS_DMA_NOWAIT, &sc->sc_scriptdma); 163 if (error) { 164 printf("%s: unable to create script DMA map, " 165 "error = %d\n", sc->sc_dev.dv_xname, error); 166 return; 167 } 168 error = bus_dmamap_load(sc->sc_dmat, sc->sc_scriptdma, 169 sc->sc_script, 170 NBPG, NULL, BUS_DMA_NOWAIT); 171 if (error) { 172 printf("%s: unable to load script DMA map, " 173 "error = %d\n", sc->sc_dev.dv_xname, error); 174 return; 175 } 176 sc->sc_scriptaddr = sc->sc_scriptdma->dm_segs[0].ds_addr; 177 } 178 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, 179 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 180 if (error) { 181 printf("%s: unable to allocate scheduler DMA memory, " 182 "error = %d\n", sc->sc_dev.dv_xname, error); 183 return; 184 } 185 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 186 (caddr_t *)&sc->sc_shed, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 187 if (error) { 188 printf("%s: unable to map scheduler DMA memory, error = %d\n", 189 sc->sc_dev.dv_xname, error); 190 return; 191 } 192 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, 193 NBPG, 0, BUS_DMA_NOWAIT, &sc->sc_sheddma); 194 if (error) { 195 printf("%s: unable to create scheduler DMA map, error = %d\n", 196 sc->sc_dev.dv_xname, error); 197 return; 198 } 199 error = bus_dmamap_load(sc->sc_dmat, sc->sc_sheddma, sc->sc_shed, 200 NBPG, NULL, BUS_DMA_NOWAIT); 201 if (error) { 202 printf("%s: unable to load scheduler DMA map, error = %d\n", 203 sc->sc_dev.dv_xname, error); 204 return; 205 } 206 TAILQ_INIT(&sc->free_list); 207 TAILQ_INIT(&sc->cmds); 208 /* compute number of scheduler slots */ 209 sc->sc_nshedslots = ( 210 NBPG /* memory size allocated for scheduler */ 211 - sizeof(endslot_script) /* memory needed at end of scheduler */ 212 ) / (sizeof(slot_script) - 8); 213 sc->sc_currshedslot = 0; 214 #ifdef DEBUG 215 printf("%s: script size = %d, PHY addr=0x%x, VIRT=%p nslots %d\n", 216 sc->sc_dev.dv_xname, (int)sizeof(siop_script), 217 sc->sc_scriptaddr, sc->sc_script, sc->sc_nshedslots); 218 #endif 219 220 sc->sc_link.adapter_softc = sc; 221 sc->sc_link.openings = 1; 222 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 223 sc->sc_link.scsipi_scsi.max_target = 224 (sc->features & SF_BUS_WIDE) ? 15 : 7; 225 sc->sc_link.scsipi_scsi.max_lun = 7; 226 sc->sc_link.scsipi_scsi.adapter_target = bus_space_read_1(sc->sc_rt, 227 sc->sc_rh, SIOP_SCID); 228 if (sc->sc_link.scsipi_scsi.adapter_target == 0 || 229 sc->sc_link.scsipi_scsi.adapter_target > 230 sc->sc_link.scsipi_scsi.max_target) 231 sc->sc_link.scsipi_scsi.adapter_target = SIOP_DEFAULT_TARGET; 232 sc->sc_link.type = BUS_SCSI; 233 sc->sc_link.adapter = &siop_adapter; 234 sc->sc_link.device = &siop_dev; 235 sc->sc_link.flags = 0; 236 237 for (i = 0; i < 16; i++) 238 sc->targets[i] = NULL; 239 240 /* find min/max sync period for this chip */ 241 sc->maxsync = 0; 242 sc->minsync = 255; 243 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); i++) { 244 if (sc->clock_period != scf_period[i].clock) 245 continue; 246 if (sc->maxsync < scf_period[i].period) 247 sc->maxsync = scf_period[i].period; 248 if (sc->minsync > scf_period[i].period) 249 sc->minsync = scf_period[i].period; 250 } 251 if (sc->maxsync == 255 || sc->minsync == 0) 252 panic("siop: can't find my sync parameters\n"); 253 siop_reset(sc); 254 #ifdef DUMP_SCRIPT 255 siop_dump_script(sc); 256 #endif 257 258 config_found((struct device*)sc, &sc->sc_link, scsiprint); 259 } 260 261 void 262 siop_reset(sc) 263 struct siop_softc *sc; 264 { 265 int i, j; 266 u_int32_t *scr; 267 bus_addr_t physaddr; 268 269 siop_common_reset(sc); 270 271 /* copy and patch the script */ 272 if (sc->features & SF_CHIP_RAM) { 273 bus_space_write_region_4(sc->sc_ramt, sc->sc_ramh, 0, 274 siop_script, sizeof(siop_script) / sizeof(siop_script[0])); 275 for (j = 0; j < 276 (sizeof(E_script_abs_shed_Used) / 277 sizeof(E_script_abs_shed_Used[0])); 278 j++) { 279 bus_space_write_4(sc->sc_ramt, sc->sc_ramh, 280 E_script_abs_shed_Used[j] * 4, 281 sc->sc_sheddma->dm_segs[0].ds_addr); 282 } 283 } else { 284 for (j = 0; 285 j < (sizeof(siop_script) / sizeof(siop_script[0])); j++) { 286 sc->sc_script[j] = htole32(siop_script[j]); 287 } 288 for (j = 0; j < 289 (sizeof(E_script_abs_shed_Used) / 290 sizeof(E_script_abs_shed_Used[0])); 291 j++) { 292 sc->sc_script[E_script_abs_shed_Used[j]] = 293 htole32(sc->sc_sheddma->dm_segs[0].ds_addr); 294 } 295 } 296 /* copy and init the scheduler slots script */ 297 for (i = 0; i < sc->sc_nshedslots; i++) { 298 scr = &sc->sc_shed[(Ent_nextslot / 4) * i]; 299 physaddr = sc->sc_sheddma->dm_segs[0].ds_addr + 300 Ent_nextslot * i; 301 for (j = 0; j < (sizeof(slot_script) / sizeof(slot_script[0])); 302 j++) { 303 scr[j] = htole32(slot_script[j]); 304 } 305 /* 306 * save current jump offset and patch MOVE MEMORY operands 307 * to restore it. 308 */ 309 scr[Ent_slotdata/4 + 1] = scr[Ent_slot/4 + 1]; 310 scr[E_slot_nextp_Used[0]] = htole32(physaddr + Ent_slot + 4); 311 scr[E_slot_shed_addrsrc_Used[0]] = htole32(physaddr + 312 Ent_slotdata + 4); 313 /* JUMP selected, in main script */ 314 scr[E_slot_abs_selected_Used[0]] = 315 htole32(sc->sc_scriptaddr + Ent_selected); 316 /* JUMP addr if SELECT fail */ 317 scr[E_slot_abs_reselect_Used[0]] = 318 htole32(sc->sc_scriptaddr + Ent_reselect); 319 } 320 /* Now the final JUMP */ 321 scr = &sc->sc_shed[(Ent_nextslot / 4) * sc->sc_nshedslots]; 322 for (j = 0; j < (sizeof(endslot_script) / sizeof(endslot_script[0])); 323 j++) { 324 scr[j] = htole32(endslot_script[j]); 325 } 326 scr[E_endslot_abs_reselect_Used[0]] = 327 htole32(sc->sc_scriptaddr + Ent_reselect); 328 329 /* start script */ 330 if ((sc->features & SF_CHIP_RAM) == 0) { 331 bus_dmamap_sync(sc->sc_dmat, sc->sc_scriptdma, 0, NBPG, 332 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 333 } 334 siop_shed_sync(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 335 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 336 sc->sc_scriptaddr + Ent_reselect); 337 } 338 339 #if 0 340 #define CALL_SCRIPT(ent) do {\ 341 printf ("start script DSA 0x%lx DSP 0x%lx\n", \ 342 siop_cmd->dsa, \ 343 sc->sc_scriptaddr + ent); \ 344 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \ 345 } while (0) 346 #else 347 #define CALL_SCRIPT(ent) do {\ 348 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \ 349 } while (0) 350 #endif 351 352 int 353 siop_intr(v) 354 void *v; 355 { 356 struct siop_softc *sc = v; 357 struct siop_target *siop_target; 358 struct siop_cmd *siop_cmd; 359 struct scsipi_xfer *xs; 360 int istat, sist0, sist1, sstat1, dstat, scntl1; 361 u_int32_t irqcode; 362 int need_reset = 0; 363 int offset, target, lun; 364 bus_addr_t dsa; 365 struct siop_cbd *cbdp; 366 367 istat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT); 368 if ((istat & (ISTAT_INTF | ISTAT_DIP | ISTAT_SIP)) == 0) 369 return 0; 370 INCSTAT(siop_stat_intr); 371 if (istat & ISTAT_INTF) { 372 printf("INTRF\n"); 373 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_INTF); 374 } 375 /* use DSA to find the current siop_cmd */ 376 dsa = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA); 377 for (cbdp = TAILQ_FIRST(&sc->cmds); cbdp != NULL; 378 cbdp = TAILQ_NEXT(cbdp, next)) { 379 if (dsa >= cbdp->xferdma->dm_segs[0].ds_addr && 380 dsa < cbdp->xferdma->dm_segs[0].ds_addr + NBPG) { 381 dsa -= cbdp->xferdma->dm_segs[0].ds_addr; 382 siop_cmd = &cbdp->cmds[dsa / sizeof(struct siop_xfer)]; 383 siop_table_sync(siop_cmd, 384 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 385 break; 386 } 387 } 388 if (cbdp == NULL) { 389 siop_cmd = NULL; 390 } 391 if (istat & ISTAT_DIP) { 392 u_int32_t *p; 393 dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DSTAT); 394 if (dstat & DSTAT_SSI) { 395 printf("single step dsp 0x%08x dsa 0x08%x\n", 396 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 397 sc->sc_scriptaddr), 398 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA)); 399 if ((dstat & ~(DSTAT_DFE | DSTAT_SSI)) == 0 && 400 (istat & ISTAT_SIP) == 0) { 401 bus_space_write_1(sc->sc_rt, sc->sc_rh, 402 SIOP_DCNTL, bus_space_read_1(sc->sc_rt, 403 sc->sc_rh, SIOP_DCNTL) | DCNTL_STD); 404 } 405 return 1; 406 } 407 if (dstat & ~(DSTAT_SIR | DSTAT_DFE | DSTAT_SSI)) { 408 printf("DMA IRQ:"); 409 if (dstat & DSTAT_IID) 410 printf(" Illegal instruction"); 411 if (dstat & DSTAT_ABRT) 412 printf(" abort"); 413 if (dstat & DSTAT_BF) 414 printf(" bus fault"); 415 if (dstat & DSTAT_MDPE) 416 printf(" parity"); 417 if (dstat & DSTAT_DFE) 418 printf(" dma fifo empty"); 419 printf(", DSP=0x%x DSA=0x%x: ", 420 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 421 sc->sc_scriptaddr), 422 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA)); 423 p = sc->sc_script + 424 (bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 425 sc->sc_scriptaddr - 8) / 4; 426 printf("0x%x 0x%x 0x%x 0x%x\n", le32toh(p[0]), le32toh(p[1]), 427 le32toh(p[2]), le32toh(p[3])); 428 if (siop_cmd) 429 printf("last msg_in=0x%x status=0x%x\n", 430 siop_cmd->siop_table->msg_in[0], 431 le32toh(siop_cmd->siop_table->status)); 432 else 433 printf("%s: current DSA invalid\n", 434 sc->sc_dev.dv_xname); 435 need_reset = 1; 436 } 437 } 438 if (istat & ISTAT_SIP) { 439 /* 440 * SCSI interrupt. If current command is not active, 441 * we don't need siop_cmd 442 */ 443 if (siop_cmd && siop_cmd->status != CMDST_ACTIVE && 444 siop_cmd->status != CMDST_SENSE_ACTIVE) { 445 siop_cmd = NULL; 446 } 447 if (istat & ISTAT_DIP) 448 delay(10); 449 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 450 delay(10); 451 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 452 sstat1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1); 453 #ifdef DEBUG_INTR 454 printf("scsi interrupt, sist0=0x%x sist1=0x%x sstat1=0x%x " 455 "DSA=0x%x DSP=0x%lx\n", sist0, sist1, 456 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1), 457 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA), 458 (u_long)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 459 sc->sc_scriptaddr)); 460 #endif 461 if (siop_cmd) { 462 xs = siop_cmd->xs; 463 siop_target = siop_cmd->siop_target; 464 } 465 if (sist0 & SIST0_RST) { 466 siop_handle_reset(sc); 467 siop_start(sc); 468 /* no table to flush here */ 469 return 1; 470 } 471 if (sist0 & SIST0_SGE) { 472 if (siop_cmd) 473 scsi_print_addr(xs->sc_link); 474 else 475 printf("%s:", sc->sc_dev.dv_xname); 476 printf("scsi gross error\n"); 477 goto reset; 478 } 479 if ((sist0 & SIST0_MA) && need_reset == 0) { 480 if (siop_cmd) { 481 int scratcha0; 482 dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 483 SIOP_DSTAT); 484 /* 485 * first restore DSA, in case we were in a S/G 486 * operation. 487 */ 488 bus_space_write_4(sc->sc_rt, sc->sc_rh, 489 SIOP_DSA, siop_cmd->dsa); 490 scratcha0 = bus_space_read_1(sc->sc_rt, 491 sc->sc_rh, SIOP_SCRATCHA); 492 switch (sstat1 & SSTAT1_PHASE_MASK) { 493 case SSTAT1_PHASE_STATUS: 494 /* 495 * previous phase may be aborted for any reason 496 * ( for example, the target has less data to 497 * transfer than requested). Just go to status 498 * and the command should terminate. 499 */ 500 INCSTAT(siop_stat_intr_shortxfer); 501 CALL_SCRIPT(Ent_status); 502 if ((dstat & DSTAT_DFE) == 0) 503 siop_clearfifo(sc); 504 /* no table to flush here */ 505 return 1; 506 case SSTAT1_PHASE_MSGIN: 507 /* 508 * target may be ready to disconnect 509 * Save data pointers just in case. 510 */ 511 INCSTAT(siop_stat_intr_xferdisc); 512 if (scratcha0 & A_flag_data) 513 siop_sdp(siop_cmd); 514 else if ((dstat & DSTAT_DFE) == 0) 515 siop_clearfifo(sc); 516 bus_space_write_1(sc->sc_rt, sc->sc_rh, 517 SIOP_SCRATCHA, 518 scratcha0 & ~A_flag_data); 519 siop_table_sync(siop_cmd, 520 BUS_DMASYNC_PREREAD | 521 BUS_DMASYNC_PREWRITE); 522 CALL_SCRIPT(Ent_msgin); 523 return 1; 524 } 525 printf("%s: unexpected phase mismatch %d\n", 526 sc->sc_dev.dv_xname, 527 sstat1 & SSTAT1_PHASE_MASK); 528 } else { 529 printf("%s: phase mismatch without command\n", 530 sc->sc_dev.dv_xname); 531 } 532 need_reset = 1; 533 } 534 if (sist0 & SIST0_PAR) { 535 /* parity error, reset */ 536 if (siop_cmd) 537 scsi_print_addr(xs->sc_link); 538 else 539 printf("%s:", sc->sc_dev.dv_xname); 540 printf("parity error\n"); 541 goto reset; 542 } 543 if ((sist1 & SIST1_STO) && need_reset == 0) { 544 /* selection time out, assume there's no device here */ 545 if (siop_cmd) { 546 siop_cmd->status = CMDST_DONE; 547 xs->error = XS_SELTIMEOUT; 548 goto end; 549 } else { 550 printf("%s: selection timeout without " 551 "command\n", sc->sc_dev.dv_xname); 552 need_reset = 1; 553 } 554 } 555 if (sist0 & SIST0_UDC) { 556 /* 557 * unexpected disconnect. Usually the target signals 558 * a fatal condition this way. Attempt to get sense. 559 */ 560 if (siop_cmd) 561 goto check_sense; 562 printf("%s: unexpected disconnect without " 563 "command\n", sc->sc_dev.dv_xname); 564 goto reset; 565 } 566 if (sist1 & SIST1_SBMC) { 567 /* SCSI bus mode change */ 568 if (siop_modechange(sc) == 0 || need_reset == 1) 569 goto reset; 570 if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) { 571 /* 572 * we have a script interrupt, it will 573 * restart the script. 574 */ 575 goto scintr; 576 } 577 /* 578 * else we have to restart it ourselve, at the 579 * interrupted instruction. 580 */ 581 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 582 bus_space_read_4(sc->sc_rt, sc->sc_rh, 583 SIOP_DSP) - 8); 584 return 1; 585 } 586 /* Else it's an unhandled exeption (for now). */ 587 printf("%s: unhandled scsi interrupt, sist0=0x%x sist1=0x%x " 588 "sstat1=0x%x DSA=0x%x DSP=0x%x\n", sc->sc_dev.dv_xname, 589 sist0, sist1, 590 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1), 591 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA), 592 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 593 sc->sc_scriptaddr)); 594 if (siop_cmd) { 595 siop_cmd->status = CMDST_DONE; 596 xs->error = XS_SELTIMEOUT; 597 goto end; 598 } 599 need_reset = 1; 600 } 601 if (need_reset) { 602 reset: 603 /* fatal error, reset the bus */ 604 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 605 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 606 scntl1 | SCNTL1_RST); 607 /* minimum 25 us, more time won't hurt */ 608 delay(100); 609 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 610 /* no table to flush here */ 611 return 1; 612 } 613 614 scintr: 615 if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) { /* script interrupt */ 616 irqcode = bus_space_read_4(sc->sc_rt, sc->sc_rh, 617 SIOP_DSPS); 618 #ifdef DEBUG_INTR 619 printf("script interrupt 0x%x\n", irqcode); 620 #endif 621 if (siop_cmd == NULL) { 622 printf("%s: script interrupt (0x%x) with invalid " 623 "DSA !!!\n", sc->sc_dev.dv_xname, irqcode); 624 goto reset; 625 } 626 /* 627 * an inactive command is only valid if it's a reselect 628 * interrupt: we'll change siop_cmd to point to the rigth one 629 * just here 630 */ 631 if (irqcode != A_int_resel && irqcode != A_int_reseltag && 632 siop_cmd->status != CMDST_ACTIVE && 633 siop_cmd->status != CMDST_SENSE_ACTIVE) { 634 printf("%s: Aie, no command (IRQ code 0x%x current " 635 "status %d) !\n", sc->sc_dev.dv_xname, 636 irqcode, siop_cmd->status); 637 xs = NULL; 638 } else { 639 xs = siop_cmd->xs; 640 siop_target = siop_cmd->siop_target; 641 } 642 switch(irqcode) { 643 case A_int_err: 644 printf("error, DSP=0x%x\n", 645 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, 646 SIOP_DSP) - sc->sc_scriptaddr)); 647 if (xs) { 648 xs->error = XS_SELTIMEOUT; 649 goto end; 650 } else { 651 goto reset; 652 } 653 case A_int_msgin: 654 if (siop_cmd->siop_table->msg_in[0] == 655 MSG_MESSAGE_REJECT) { 656 int msg, extmsg; 657 if (siop_cmd->siop_table->msg_out[0] & 0x80) { 658 /* 659 * message was part of a identify + 660 * something else. Identify shoudl't 661 * have been rejected. 662 */ 663 msg = siop_cmd->siop_table->msg_out[1]; 664 extmsg = 665 siop_cmd->siop_table->msg_out[3]; 666 } else { 667 msg = siop_cmd->siop_table->msg_out[0]; 668 extmsg = 669 siop_cmd->siop_table->msg_out[2]; 670 } 671 if (msg == MSG_MESSAGE_REJECT) { 672 /* MSG_REJECT for a MSG_REJECT !*/ 673 if (xs) 674 scsi_print_addr(xs->sc_link); 675 else 676 printf("%s: ", 677 sc->sc_dev.dv_xname); 678 printf("our reject message was " 679 "rejected\n"); 680 goto reset; 681 } 682 if (msg == MSG_EXTENDED && 683 extmsg == MSG_EXT_WDTR) { 684 /* WDTR rejected, initiate sync */ 685 printf("%s: target %d using 8bit " 686 "transfers\n", sc->sc_dev.dv_xname, 687 xs->sc_link->scsipi_scsi.target); 688 siop_target->status = TARST_SYNC_NEG; 689 siop_cmd->siop_table->msg_out[0] = 690 MSG_EXTENDED; 691 siop_cmd->siop_table->msg_out[1] = 692 MSG_EXT_SDTR_LEN; 693 siop_cmd->siop_table->msg_out[2] = 694 MSG_EXT_SDTR; 695 siop_cmd->siop_table->msg_out[3] = 696 sc->minsync; 697 siop_cmd->siop_table->msg_out[4] = 698 sc->maxoff; 699 siop_cmd->siop_table->t_msgout.count = 700 htole32(MSG_EXT_SDTR_LEN + 2); 701 siop_cmd->siop_table->t_msgout.addr = 702 htole32(siop_cmd->dsa); 703 siop_table_sync(siop_cmd, 704 BUS_DMASYNC_PREREAD | 705 BUS_DMASYNC_PREWRITE); 706 CALL_SCRIPT(Ent_send_msgout); 707 return 1; 708 } else if (msg == MSG_EXTENDED && 709 extmsg == MSG_EXT_SDTR) { 710 /* sync rejected */ 711 printf("%s: target %d asynchronous\n", 712 sc->sc_dev.dv_xname, 713 xs->sc_link->scsipi_scsi.target); 714 siop_cmd->siop_target->status = 715 TARST_OK; 716 /* no table to flush here */ 717 CALL_SCRIPT(Ent_msgin_ack); 718 return 1; 719 } 720 if (xs) 721 scsi_print_addr(xs->sc_link); 722 else 723 printf("%s: ", sc->sc_dev.dv_xname); 724 if (msg == MSG_EXTENDED) { 725 printf("scsi message reject, extended " 726 "message sent was 0x%x\n", extmsg); 727 } else { 728 printf("scsi message reject, message " 729 "sent was 0x%x\n", msg); 730 } 731 /* no table to flush here */ 732 CALL_SCRIPT(Ent_msgin_ack); 733 return 1; 734 } 735 if (xs) 736 scsi_print_addr(xs->sc_link); 737 else 738 printf("%s: ", sc->sc_dev.dv_xname); 739 printf("unhandled message 0x%x\n", 740 siop_cmd->siop_table->msg_in[0]); 741 siop_cmd->siop_table->t_msgout.count= htole32(1); 742 siop_cmd->siop_table->t_msgout.addr = 743 htole32(siop_cmd->dsa); 744 siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT; 745 siop_table_sync(siop_cmd, 746 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 747 CALL_SCRIPT(Ent_send_msgout); 748 return 1; 749 case A_int_extmsgin: 750 #ifdef DEBUG_INTR 751 printf("extended message: msg 0x%x len %d\n", 752 siop_cmd->siop_table->msg_in[2], 753 siop_cmd->siop_table->msg_in[1]); 754 #endif 755 if (siop_cmd->siop_table->msg_in[1] > 6) 756 printf("%s: extended message too big (%d)\n", 757 sc->sc_dev.dv_xname, 758 siop_cmd->siop_table->msg_in[1]); 759 siop_cmd->siop_table->t_extmsgdata.count = 760 htole32(siop_cmd->siop_table->msg_in[1] - 1); 761 siop_cmd->siop_table->t_extmsgdata.addr = 762 htole32( 763 le32toh(siop_cmd->siop_table->t_extmsgin.addr) 764 + 2); 765 siop_table_sync(siop_cmd, 766 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 767 CALL_SCRIPT(Ent_get_extmsgdata); 768 return 1; 769 case A_int_extmsgdata: 770 #ifdef DEBUG_INTR 771 { 772 int i; 773 printf("extended message: 0x%x, data:", 774 siop_cmd->siop_table->msg_in[2]); 775 for (i = 3; i < 2 + siop_cmd->siop_table->msg_in[1]; 776 i++) 777 printf(" 0x%x", 778 siop_cmd->siop_table->msg_in[i]); 779 printf("\n"); 780 } 781 #endif 782 if (siop_cmd->siop_table->msg_in[2] == MSG_EXT_WDTR) { 783 switch (siop_wdtr_neg(siop_cmd)) { 784 case SIOP_NEG_NOP: 785 break; 786 case SIOP_NEG_MSGOUT: 787 siop_table_sync(siop_cmd, 788 BUS_DMASYNC_PREREAD | 789 BUS_DMASYNC_PREWRITE); 790 CALL_SCRIPT(Ent_send_msgout); 791 break; 792 default: 793 panic("invalid retval from " 794 "siop_wdtr_neg()"); 795 } 796 return(1); 797 } 798 if (siop_cmd->siop_table->msg_in[2] == MSG_EXT_SDTR) { 799 switch (siop_sdtr_neg(siop_cmd)) { 800 case SIOP_NEG_NOP: 801 break; 802 case SIOP_NEG_MSGOUT: 803 siop_table_sync(siop_cmd, 804 BUS_DMASYNC_PREREAD | 805 BUS_DMASYNC_PREWRITE); 806 CALL_SCRIPT(Ent_send_msgout); 807 break; 808 case SIOP_NEG_ACK: 809 CALL_SCRIPT(Ent_msgin_ack); 810 break; 811 default: 812 panic("invalid retval from " 813 "siop_wdtr_neg()"); 814 } 815 return(1); 816 } 817 /* send a message reject */ 818 siop_cmd->siop_table->t_msgout.count = 819 htole32(1); 820 siop_cmd->siop_table->t_msgout.addr = 821 htole32(siop_cmd->dsa); 822 siop_cmd->siop_table->msg_out[0] = 823 MSG_MESSAGE_REJECT; 824 siop_table_sync(siop_cmd, 825 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 826 CALL_SCRIPT(Ent_send_msgout); 827 return 1; 828 case A_int_resel: /* reselected */ 829 case A_int_reseltag: /* reselected with tag */ 830 INCSTAT(siop_stat_intr_reselect); 831 if ((siop_cmd->siop_table->msg_in[0] & 0x80) == 0) { 832 printf("%s: reselect without identify (%d)\n", 833 sc->sc_dev.dv_xname, 834 siop_cmd->siop_table->msg_in[0]); 835 goto reset; 836 } 837 target = bus_space_read_1(sc->sc_rt, 838 sc->sc_rh, SIOP_SCRATCHA); 839 if ((target & 0x80) == 0) { 840 printf("reselect without id (%d)\n", target); 841 goto reset; 842 } 843 target &= 0x0f; 844 lun = siop_cmd->siop_table->msg_in[0] & 0x07; 845 #ifdef DEBUG_DR 846 printf("reselected by target %d lun %d\n", 847 target, lun); 848 #endif 849 siop_cmd = 850 sc->targets[target]->active_list[lun].tqh_first; 851 if (siop_cmd == NULL) { 852 printf("%s: reselected without cmd\n", 853 sc->sc_dev.dv_xname); 854 goto reset; 855 } 856 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSA, 857 siop_cmd->dsa); 858 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 859 (sc->targets[target]->id >> 24) & 0xff); 860 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 861 (sc->targets[target]->id >> 8) & 0xff); 862 /* no table to flush */ 863 CALL_SCRIPT(Ent_selected); 864 return 1; 865 case A_int_disc: 866 INCSTAT(siop_stat_intr_sdp); 867 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, 868 SIOP_SCRATCHA + 1); 869 #ifdef DEBUG_DR 870 printf("disconnect offset %d\n", offset); 871 #endif 872 if (offset > SIOP_NSG) { 873 printf("%s: bad offset for disconnect (%d)\n", 874 sc->sc_dev.dv_xname, offset); 875 goto reset; 876 } 877 /* 878 * offset == SIOP_NSG may be a valid condition if 879 * we get a sdp when the xfer is done. 880 * Don't call memmove in this case. 881 */ 882 if (offset < SIOP_NSG) { 883 memmove(&siop_cmd->siop_table->data[0], 884 &siop_cmd->siop_table->data[offset], 885 (SIOP_NSG - offset) * sizeof(scr_table_t)); 886 siop_table_sync(siop_cmd, 887 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 888 } 889 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 890 sc->sc_sheddma->dm_segs[0].ds_addr); 891 return 1; 892 case A_int_resfail: 893 printf("reselect failed\n"); 894 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 895 sc->sc_sheddma->dm_segs[0].ds_addr); 896 return 1; 897 case A_int_done: 898 if (xs == NULL) { 899 printf("%s: done without command, DSA=0x%lx\n", 900 sc->sc_dev.dv_xname, (u_long)siop_cmd->dsa); 901 siop_cmd->status = CMDST_FREE; 902 bus_space_write_4(sc->sc_rt, sc->sc_rh, 903 SIOP_DSP, 904 sc->sc_sheddma->dm_segs[0].ds_addr); 905 siop_start(sc); 906 return 1; 907 } 908 if (siop_target->status == TARST_PROBING) 909 siop_target->status = TARST_ASYNC; 910 #ifdef DEBUG_INTR 911 printf("done, DSA=0x%lx target id 0x%x last msg " 912 "in=0x%x status=0x%x\n", (u_long)siop_cmd->dsa, 913 le32toh(siop_cmd->siop_table->id), 914 siop_cmd->siop_table->msg_in[0], 915 le32toh(siop_cmd->siop_table->status)); 916 #endif 917 INCSTAT(siop_stat_intr_done); 918 if (siop_cmd->status == CMDST_SENSE_ACTIVE) 919 siop_cmd->status = CMDST_SENSE_DONE; 920 else 921 siop_cmd->status = CMDST_DONE; 922 switch(le32toh(siop_cmd->siop_table->status)) { 923 case SCSI_OK: 924 xs->error = (siop_cmd->status == CMDST_DONE) ? 925 XS_NOERROR : XS_SENSE; 926 break; 927 case SCSI_BUSY: 928 xs->error = XS_BUSY; 929 break; 930 case SCSI_CHECK: 931 check_sense: 932 if (siop_cmd->status == CMDST_SENSE_DONE) { 933 /* request sense on a request sense ? */ 934 printf("request sense failed\n"); 935 xs->error = XS_DRIVER_STUFFUP; 936 } else { 937 siop_cmd->status = CMDST_SENSE; 938 } 939 break; 940 case 0xff: 941 /* 942 * the status byte was not updated, cmd was 943 * aborted 944 */ 945 xs->error = XS_SELTIMEOUT; 946 break; 947 default: 948 xs->error = XS_DRIVER_STUFFUP; 949 } 950 goto end; 951 default: 952 printf("unknown irqcode %x\n", irqcode); 953 xs->error = XS_SELTIMEOUT; 954 goto end; 955 } 956 return 1; 957 } 958 /* We just should't get there */ 959 panic("siop_intr: I shouldn't be there !"); 960 return 1; 961 end: 962 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 963 sc->sc_sheddma->dm_segs[0].ds_addr); 964 lun = siop_cmd->xs->sc_link->scsipi_scsi.lun; 965 siop_scsicmd_end(siop_cmd); 966 if (siop_cmd->status == CMDST_FREE) { 967 TAILQ_REMOVE(&siop_target->active_list[lun], 968 siop_cmd, next); 969 TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next); 970 } 971 siop_start(sc); 972 return 1; 973 } 974 975 void 976 siop_scsicmd_end(siop_cmd) 977 struct siop_cmd *siop_cmd; 978 { 979 struct scsipi_xfer *xs = siop_cmd->xs; 980 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 981 982 if (siop_cmd->status != CMDST_SENSE_DONE && 983 xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 984 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 985 siop_cmd->dmamap_data->dm_mapsize, 986 (xs->xs_control & XS_CTL_DATA_IN) ? 987 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 988 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data); 989 } 990 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 991 if (siop_cmd->status == CMDST_SENSE) { 992 /* issue a request sense for this target */ 993 int error, i; 994 siop_cmd->rs_cmd.opcode = REQUEST_SENSE; 995 siop_cmd->rs_cmd.byte2 = xs->sc_link->scsipi_scsi.lun << 5; 996 siop_cmd->rs_cmd.unused[0] = siop_cmd->rs_cmd.unused[1] = 0; 997 siop_cmd->rs_cmd.length = sizeof(struct scsipi_sense_data); 998 siop_cmd->rs_cmd.control = 0; 999 siop_cmd->siop_table->status = htole32(0xff); /*invalid status*/ 1000 siop_cmd->siop_table->t_msgout.count= htole32(1); 1001 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 1002 siop_cmd->siop_table->msg_out[0] = 1003 MSG_IDENTIFY(xs->sc_link->scsipi_scsi.lun, 1); 1004 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd, 1005 &siop_cmd->rs_cmd, sizeof(struct scsipi_sense), 1006 NULL, BUS_DMA_NOWAIT); 1007 if (error) { 1008 printf("%s: unable to load cmd DMA map: %d", 1009 sc->sc_dev.dv_xname, error); 1010 xs->error = XS_DRIVER_STUFFUP; 1011 goto out; 1012 } 1013 siop_cmd->siop_table->cmd.count = 1014 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 1015 siop_cmd->siop_table->cmd.addr = 1016 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 1017 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data, 1018 &xs->sense.scsi_sense, sizeof(struct scsipi_sense_data), 1019 NULL, BUS_DMA_NOWAIT); 1020 if (error) { 1021 printf("%s: unable to load sense DMA map: %d", 1022 sc->sc_dev.dv_xname, error); 1023 xs->error = XS_DRIVER_STUFFUP; 1024 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1025 goto out; 1026 } 1027 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 1028 siop_cmd->siop_table->data[i].count = 1029 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 1030 siop_cmd->siop_table->data[i].addr = 1031 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 1032 } 1033 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1034 siop_cmd->dmamap_data->dm_mapsize, BUS_DMASYNC_PREREAD); 1035 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd, 0, 1036 siop_cmd->dmamap_cmd->dm_mapsize, BUS_DMASYNC_PREWRITE); 1037 siop_table_sync(siop_cmd, BUS_DMASYNC_PREWRITE); 1038 return; 1039 } else if (siop_cmd->status == CMDST_SENSE_DONE) { 1040 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1041 siop_cmd->dmamap_data->dm_mapsize, BUS_DMASYNC_POSTREAD); 1042 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data); 1043 } 1044 out: 1045 callout_stop(&siop_cmd->xs->xs_callout); 1046 siop_cmd->status = CMDST_FREE; 1047 xs->xs_status |= XS_STS_DONE; 1048 xs->resid = 0; 1049 if ((xs->xs_control & XS_CTL_POLL) == 0) 1050 scsipi_done (xs); 1051 } 1052 1053 /* 1054 * handle a bus reset: reset chip, unqueue all active commands and report 1055 * loosage to upper layer. 1056 * As the upper layer may requeue immediatly we have to first store 1057 * all active commands in a temporary queue. 1058 */ 1059 void 1060 siop_handle_reset(sc) 1061 struct siop_softc *sc; 1062 { 1063 struct cmd_list reset_list; 1064 struct siop_cmd *siop_cmd, *next_siop_cmd; 1065 int target, lun; 1066 /* 1067 * scsi bus reset. reset the chip and restart 1068 * the queue. Need to clean up all active commands 1069 */ 1070 printf("%s: scsi bus reset\n", sc->sc_dev.dv_xname); 1071 /* stop, reset and restart the chip */ 1072 siop_reset(sc); 1073 TAILQ_INIT(&reset_list); 1074 /* find all active commands */ 1075 for (target = 0; target <= sc->sc_link.scsipi_scsi.max_target; 1076 target++) { 1077 if (sc->targets[target] == NULL) 1078 continue; 1079 for (lun = 0; lun < 8; lun++) { 1080 for (siop_cmd = 1081 TAILQ_FIRST(&sc->targets[target]->active_list[lun]); 1082 siop_cmd != NULL; siop_cmd = next_siop_cmd) { 1083 next_siop_cmd = TAILQ_NEXT(siop_cmd, next); 1084 if (siop_cmd->status < CMDST_ACTIVE) 1085 continue; 1086 printf("cmd %p (target %d) in reset list\n", 1087 siop_cmd, target); 1088 TAILQ_REMOVE( 1089 &sc->targets[target]->active_list[lun], 1090 siop_cmd, next); 1091 TAILQ_INSERT_TAIL(&reset_list, siop_cmd, next); 1092 } 1093 } 1094 sc->targets[target]->status = TARST_ASYNC; 1095 sc->targets[target]->flags = ~(TARF_SYNC | TARF_WIDE); 1096 } 1097 for (siop_cmd = TAILQ_FIRST(&reset_list); siop_cmd != NULL; 1098 siop_cmd = next_siop_cmd) { 1099 next_siop_cmd = TAILQ_NEXT(siop_cmd, next); 1100 siop_cmd->xs->error = (siop_cmd->flags & CMDFL_TIMEOUT) ? 1101 XS_TIMEOUT : XS_RESET; 1102 printf("cmd %p about to be processed\n", siop_cmd); 1103 if (siop_cmd->status == CMDST_SENSE || 1104 siop_cmd->status == CMDST_SENSE_ACTIVE) 1105 siop_cmd->status = CMDST_SENSE_DONE; 1106 else 1107 siop_cmd->status = CMDST_DONE; 1108 TAILQ_REMOVE(&reset_list, siop_cmd, next); 1109 siop_scsicmd_end(siop_cmd); 1110 TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next); 1111 } 1112 } 1113 1114 int 1115 siop_scsicmd(xs) 1116 struct scsipi_xfer *xs; 1117 { 1118 struct siop_softc *sc = (struct siop_softc *)xs->sc_link->adapter_softc; 1119 struct siop_cmd *siop_cmd; 1120 int s, error, i; 1121 int target = xs->sc_link->scsipi_scsi.target; 1122 int lun = xs->sc_link->scsipi_scsi.lun; 1123 1124 s = splbio(); 1125 #ifdef DEBUG_SHED 1126 printf("starting cmd for %d:%d\n", target, lun); 1127 #endif 1128 siop_cmd = sc->free_list.tqh_first; 1129 if (siop_cmd) { 1130 TAILQ_REMOVE(&sc->free_list, siop_cmd, next); 1131 } else { 1132 if (siop_morecbd(sc) == 0) { 1133 siop_cmd = sc->free_list.tqh_first; 1134 #ifdef DIAGNOSTIC 1135 if (siop_cmd == NULL) 1136 panic("siop_morecbd succeed and does nothing"); 1137 #endif 1138 TAILQ_REMOVE(&sc->free_list, siop_cmd, next); 1139 } 1140 } 1141 splx(s); 1142 if (siop_cmd == NULL) { 1143 xs->error = XS_DRIVER_STUFFUP; 1144 return(TRY_AGAIN_LATER); 1145 } 1146 #ifdef DIAGNOSTIC 1147 if (siop_cmd->status != CMDST_FREE) 1148 panic("siop_scsicmd: new cmd not free"); 1149 #endif 1150 if (sc->targets[target] == NULL) { 1151 sc->targets[target] = 1152 malloc(sizeof(struct siop_target), M_DEVBUF, M_NOWAIT); 1153 if (sc->targets[target] == NULL) { 1154 printf("%s: can't malloc memory for target %d\n", 1155 sc->sc_dev.dv_xname, target); 1156 xs->error = XS_DRIVER_STUFFUP; 1157 return(TRY_AGAIN_LATER); 1158 } 1159 sc->targets[target]->siop_sc = sc; 1160 sc->targets[target]->status = TARST_PROBING; 1161 sc->targets[target]->flags = 0; 1162 sc->targets[target]->id = sc->clock_div << 24; /* scntl3 */ 1163 sc->targets[target]->id |= target << 16; /* id */ 1164 /* sc->targets[target]->id |= 0x0 << 8; scxfer is 0 */ 1165 for (i = 0; i < 8; i++) 1166 TAILQ_INIT(&sc->targets[target]->active_list[i]); 1167 } 1168 siop_cmd->siop_target = sc->targets[target]; 1169 siop_cmd->xs = xs; 1170 siop_cmd->siop_table->id = htole32(sc->targets[target]->id); 1171 siop_cmd->siop_table->t_msgout.count= htole32(1); 1172 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 1173 memset(siop_cmd->siop_table->msg_out, 0, 8); 1174 siop_cmd->siop_table->msg_out[0] = MSG_IDENTIFY(lun, 1); 1175 #if 0 1176 siop_cmd->siop_table->msg_out[1] = MSG_SIMPLE_Q_TAG; 1177 siop_cmd->siop_table->msg_out[2] = 0; 1178 #endif 1179 if (sc->targets[target]->status == TARST_ASYNC) { 1180 if (sc->features & SF_BUS_WIDE) { 1181 sc->targets[target]->status = TARST_WIDE_NEG; 1182 siop_cmd->siop_table->msg_out[1] = MSG_EXTENDED; 1183 siop_cmd->siop_table->msg_out[2] = MSG_EXT_WDTR_LEN; 1184 siop_cmd->siop_table->msg_out[3] = MSG_EXT_WDTR; 1185 siop_cmd->siop_table->msg_out[4] = 1186 MSG_EXT_WDTR_BUS_16_BIT; 1187 siop_cmd->siop_table->t_msgout.count= 1188 htole32(MSG_EXT_WDTR_LEN + 2 + 1); 1189 } else { 1190 sc->targets[target]->status = TARST_SYNC_NEG; 1191 siop_cmd->siop_table->msg_out[1] = MSG_EXTENDED; 1192 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR_LEN; 1193 siop_cmd->siop_table->msg_out[3] = MSG_EXT_SDTR; 1194 siop_cmd->siop_table->msg_out[4] = sc->minsync; 1195 siop_cmd->siop_table->msg_out[5] = sc->maxoff; 1196 siop_cmd->siop_table->t_msgout.count= 1197 htole32(MSG_EXT_SDTR_LEN + 2 +1); 1198 } 1199 } 1200 siop_cmd->siop_table->status = htole32(0xff); /* set invalid status */ 1201 1202 /* load the DMA maps */ 1203 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd, 1204 xs->cmd, xs->cmdlen, NULL, BUS_DMA_NOWAIT); 1205 if (error) { 1206 printf("%s: unable to load cmd DMA map: %d", 1207 sc->sc_dev.dv_xname, error); 1208 xs->error = XS_DRIVER_STUFFUP; 1209 return(TRY_AGAIN_LATER); 1210 } 1211 siop_cmd->siop_table->cmd.count = 1212 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 1213 siop_cmd->siop_table->cmd.addr = 1214 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 1215 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 1216 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data, 1217 xs->data, xs->datalen, NULL, BUS_DMA_NOWAIT); 1218 if (error) { 1219 printf("%s: unable to load cmd DMA map: %d", 1220 sc->sc_dev.dv_xname, error); 1221 xs->error = XS_DRIVER_STUFFUP; 1222 return(TRY_AGAIN_LATER); 1223 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1224 } 1225 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 1226 siop_cmd->siop_table->data[i].count = 1227 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 1228 siop_cmd->siop_table->data[i].addr = 1229 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 1230 } 1231 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1232 siop_cmd->dmamap_data->dm_mapsize, 1233 (xs->xs_control & XS_CTL_DATA_IN) ? 1234 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1235 } 1236 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd, 0, 1237 siop_cmd->dmamap_cmd->dm_mapsize, BUS_DMASYNC_PREWRITE); 1238 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1239 1240 siop_cmd->status = CMDST_READY; 1241 s = splbio(); 1242 TAILQ_INSERT_TAIL(&sc->targets[target]->active_list[lun], 1243 siop_cmd, next); 1244 siop_start(sc); 1245 if (xs->xs_control & XS_CTL_POLL) { 1246 /* poll for command completion */ 1247 while ((xs->xs_status & XS_STS_DONE) == 0) 1248 siop_intr(sc); 1249 splx(s); 1250 return (COMPLETE); 1251 } 1252 splx(s); 1253 return (SUCCESSFULLY_QUEUED); 1254 } 1255 1256 void 1257 siop_start(sc) 1258 struct siop_softc *sc; 1259 { 1260 struct siop_cmd *siop_cmd; 1261 u_int32_t *scr; 1262 u_int32_t dsa; 1263 int timeout; 1264 int target, lun, slot; 1265 int newcmd = 0; 1266 1267 /* 1268 * first make sure to read valid data 1269 */ 1270 siop_shed_sync(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1271 1272 /* 1273 * The queue management here is a bit tricky: the script always looks 1274 * at the slot from first to last, so if we always use the first 1275 * free slot commands can stay at the tail of the queue ~forever. 1276 * The algorithm used here is to restart from the head when we know 1277 * that the queue is empty, and only add commands after the last one. 1278 * When we're at the end of the queue wait for the script to clear it. 1279 * The best thing to do here would be to implement a circular queue, 1280 * but using only 53c720 features this can be "interesting". 1281 * A mid-way solution could be to implement 2 queues and swap orders. 1282 */ 1283 slot = sc->sc_currshedslot; 1284 scr = &sc->sc_shed[(Ent_nextslot / 4) * slot]; 1285 /* 1286 * if relative addr of first jump is not 0 the slot is free. As this is 1287 * the last used slot, all previous slots are free, we can restart 1288 * from 0. 1289 */ 1290 if (scr[Ent_slot / 4 + 1] != 0) { 1291 slot = sc->sc_currshedslot = 0; 1292 } else { 1293 slot++; 1294 } 1295 1296 for (target = 0; target <= sc->sc_link.scsipi_scsi.max_target; 1297 target++) { 1298 if (sc->targets[target] == NULL) 1299 continue; 1300 for (lun = 0; lun < 8; lun++) { 1301 siop_cmd = 1302 sc->targets[target]->active_list[lun].tqh_first; 1303 if (siop_cmd == NULL) 1304 continue; 1305 if (siop_cmd->status != CMDST_READY && 1306 siop_cmd->status != CMDST_SENSE) 1307 continue; 1308 /* find a free scheduler slot and load it */ 1309 for (; slot < sc->sc_nshedslots; slot++) { 1310 scr = &sc->sc_shed[(Ent_nextslot / 4) * slot]; 1311 /* 1312 * if relative addr of first jump is 0 the 1313 * slot isn't free 1314 */ 1315 if (scr[Ent_slot / 4 + 1] == 0) 1316 continue; 1317 #ifdef DEBUG_SHED 1318 printf("using slot %d for DSA 0x%lx\n", slot, 1319 (u_long)siop_cmd->dsa); 1320 #endif 1321 /* note that we started a new command */ 1322 newcmd = 1; 1323 /* mark command as active */ 1324 if (siop_cmd->status == CMDST_READY) 1325 siop_cmd->status = CMDST_ACTIVE; 1326 else if (siop_cmd->status == CMDST_SENSE) 1327 siop_cmd->status = CMDST_SENSE_ACTIVE; 1328 else 1329 panic("siop_start: bad status"); 1330 /* patch script with DSA addr */ 1331 dsa = siop_cmd->dsa; 1332 /* 1333 * 0x78000000 is a 'move data8 to reg'. data8 1334 * is the second octet, reg offset is the third. 1335 */ 1336 scr[Ent_idsa0 / 4] = 1337 htole32(0x78100000 | 1338 ((dsa & 0x000000ff) << 8)); 1339 scr[Ent_idsa1 / 4] = 1340 htole32(0x78110000 | 1341 ( dsa & 0x0000ff00 )); 1342 scr[Ent_idsa2 / 4] = 1343 htole32(0x78120000 | 1344 ((dsa & 0x00ff0000) >> 8)); 1345 scr[Ent_idsa3 / 4] = 1346 htole32(0x78130000 | 1347 ((dsa & 0xff000000) >> 16)); 1348 /* handle timeout */ 1349 if (siop_cmd->status == CMDST_ACTIVE) { 1350 if ((siop_cmd->xs->xs_control & 1351 XS_CTL_POLL) == 0) { 1352 /* start exire timer */ 1353 timeout = 1354 siop_cmd->xs->timeout * 1355 hz / 1000; 1356 if (timeout == 0) 1357 timeout = 1; 1358 callout_reset( 1359 &siop_cmd->xs->xs_callout, 1360 timeout, siop_timeout, 1361 siop_cmd); 1362 } 1363 } 1364 /* 1365 * Change jump offset so that this slot will be 1366 * handled 1367 */ 1368 scr[Ent_slot / 4 + 1] = 0; 1369 break; 1370 } 1371 /* no more free slot, no need to continue */ 1372 if (slot == sc->sc_nshedslots) { 1373 goto end; 1374 } 1375 sc->sc_currshedslot = slot; 1376 } 1377 } 1378 end: 1379 /* if nothing changed no need to flush cache and wakeup script */ 1380 if (newcmd == 0) 1381 return; 1382 /* make sure SCRIPT processor will read valid data */ 1383 siop_shed_sync(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1384 /* Signal script it has some work to do */ 1385 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SIGP); 1386 /* and wait for IRQ */ 1387 return; 1388 } 1389 1390 void 1391 siop_timeout(v) 1392 void *v; 1393 { 1394 struct siop_cmd *siop_cmd = v; 1395 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 1396 int s; 1397 u_int8_t scntl1; 1398 1399 scsi_print_addr(siop_cmd->xs->sc_link); 1400 printf("command timeout\n"); 1401 1402 s = splbio(); 1403 /* reset the scsi bus */ 1404 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 1405 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 1406 scntl1 | SCNTL1_RST); 1407 /* minimum 25 us, more time won't hurt */ 1408 delay(100); 1409 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 1410 1411 /* deactivate callout */ 1412 callout_stop(&siop_cmd->xs->xs_callout); 1413 /* mark command has being timed out; siop_intr will handle it */ 1414 /* 1415 * mark command has being timed out and just return; 1416 * the bus reset will generate an interrupt, 1417 * it will be handled in siop_intr() 1418 */ 1419 siop_cmd->flags |= CMDFL_TIMEOUT; 1420 splx(s); 1421 return; 1422 1423 } 1424 1425 void 1426 siop_dump_script(sc) 1427 struct siop_softc *sc; 1428 { 1429 int i; 1430 siop_shed_sync(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1431 for (i = 0; i < NBPG / 4; i += 2) { 1432 printf("0x%04x: 0x%08x 0x%08x", i * 4, 1433 le32toh(sc->sc_script[i]), le32toh(sc->sc_script[i+1])); 1434 if ((le32toh(sc->sc_script[i]) & 0xe0000000) == 0xc0000000) { 1435 i++; 1436 printf(" 0x%08x", le32toh(sc->sc_script[i+1])); 1437 } 1438 printf("\n"); 1439 } 1440 } 1441 1442 int 1443 siop_morecbd(sc) 1444 struct siop_softc *sc; 1445 { 1446 int error, i; 1447 bus_dma_segment_t seg; 1448 int rseg; 1449 struct siop_cbd *newcbd; 1450 1451 /* allocate a new list head */ 1452 newcbd = malloc(sizeof(struct siop_cbd), M_DEVBUF, M_NOWAIT); 1453 if (newcbd == NULL) { 1454 printf("%s: can't allocate memory for command descriptors " 1455 "head\n", sc->sc_dev.dv_xname); 1456 return ENOMEM; 1457 } 1458 1459 /* allocate cmd list */ 1460 newcbd->cmds = 1461 malloc(sizeof(struct siop_cmd) * SIOP_NCMDPB, M_DEVBUF, M_NOWAIT); 1462 if (newcbd->cmds == NULL) { 1463 printf("%s: can't allocate memory for command descriptors\n", 1464 sc->sc_dev.dv_xname); 1465 error = ENOMEM; 1466 goto bad3; 1467 } 1468 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, NBPG, 0, &seg, 1, &rseg, 1469 BUS_DMA_NOWAIT); 1470 if (error) { 1471 printf("%s: unable to allocate cbd DMA memory, error = %d\n", 1472 sc->sc_dev.dv_xname, error); 1473 goto bad2; 1474 } 1475 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 1476 (caddr_t *)&newcbd->xfers, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1477 if (error) { 1478 printf("%s: unable to map cbd DMA memory, error = %d\n", 1479 sc->sc_dev.dv_xname, error); 1480 goto bad2; 1481 } 1482 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, NBPG, 0, 1483 BUS_DMA_NOWAIT, &newcbd->xferdma); 1484 if (error) { 1485 printf("%s: unable to create cbd DMA map, error = %d\n", 1486 sc->sc_dev.dv_xname, error); 1487 goto bad1; 1488 } 1489 error = bus_dmamap_load(sc->sc_dmat, newcbd->xferdma, newcbd->xfers, 1490 NBPG, NULL, BUS_DMA_NOWAIT); 1491 if (error) { 1492 printf("%s: unable to load cbd DMA map, error = %d\n", 1493 sc->sc_dev.dv_xname, error); 1494 goto bad0; 1495 } 1496 1497 for (i = 0; i < SIOP_NCMDPB; i++) { 1498 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, SIOP_NSG, 1499 MAXPHYS, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1500 &newcbd->cmds[i].dmamap_data); 1501 if (error) { 1502 printf("%s: unable to create data DMA map for cbd: " 1503 "error %d\n", 1504 sc->sc_dev.dv_xname, error); 1505 goto bad0; 1506 } 1507 error = bus_dmamap_create(sc->sc_dmat, 1508 sizeof(struct scsipi_generic), 1, 1509 sizeof(struct scsipi_generic), 0, 1510 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1511 &newcbd->cmds[i].dmamap_cmd); 1512 if (error) { 1513 printf("%s: unable to create cmd DMA map for cbd %d\n", 1514 sc->sc_dev.dv_xname, error); 1515 goto bad0; 1516 } 1517 newcbd->cmds[i].siop_cbdp = newcbd; 1518 newcbd->cmds[i].siop_table = &newcbd->xfers[i]; 1519 memset(newcbd->cmds[i].siop_table, 0, sizeof(struct siop_xfer)); 1520 newcbd->cmds[i].dsa = newcbd->xferdma->dm_segs[0].ds_addr + 1521 i * sizeof(struct siop_xfer); 1522 newcbd->cmds[i].status = CMDST_FREE; 1523 newcbd->cmds[i].siop_table->t_msgout.count= htole32(1); 1524 newcbd->cmds[i].siop_table->t_msgout.addr = 1525 htole32(newcbd->cmds[i].dsa); 1526 newcbd->cmds[i].siop_table->t_msgin.count= htole32(1); 1527 newcbd->cmds[i].siop_table->t_msgin.addr = 1528 htole32(newcbd->cmds[i].dsa + 8); 1529 newcbd->cmds[i].siop_table->t_extmsgin.count= htole32(2); 1530 newcbd->cmds[i].siop_table->t_extmsgin.addr = htole32( 1531 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr) + 1); 1532 newcbd->cmds[i].siop_table->t_msgtag.count= htole32(2); 1533 newcbd->cmds[i].siop_table->t_msgtag.addr = htole32( 1534 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr) + 1); 1535 newcbd->cmds[i].siop_table->t_status.count= htole32(1); 1536 newcbd->cmds[i].siop_table->t_status.addr = htole32( 1537 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr) + 8); 1538 TAILQ_INSERT_TAIL(&sc->free_list, &newcbd->cmds[i], next); 1539 #ifdef DEBUG 1540 printf("tables[%d]: out=0x%x in=0x%x status=0x%x\n", i, 1541 le32toh(newcbd->cmds[i].siop_table->t_msgin.addr), 1542 le32toh(newcbd->cmds[i].siop_table->t_msgout.addr), 1543 le32toh(newcbd->cmds[i].siop_table->t_status.addr)); 1544 #endif 1545 } 1546 TAILQ_INSERT_TAIL(&sc->cmds, newcbd, next); 1547 return 0; 1548 bad0: 1549 bus_dmamap_destroy(sc->sc_dmat, newcbd->xferdma); 1550 bad1: 1551 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1552 bad2: 1553 free(newcbd->cmds, M_DEVBUF); 1554 bad3: 1555 free(newcbd, M_DEVBUF); 1556 return error; 1557 } 1558 1559 #ifdef SIOP_STATS 1560 void 1561 siop_printstats() 1562 { 1563 printf("siop_stat_intr %d\n", siop_stat_intr); 1564 printf("siop_stat_intr_shortxfer %d\n", siop_stat_intr_shortxfer); 1565 printf("siop_stat_intr_xferdisc %d\n", siop_stat_intr_xferdisc); 1566 printf("siop_stat_intr_sdp %d\n", siop_stat_intr_sdp); 1567 printf("siop_stat_intr_reselect %d\n", siop_stat_intr_reselect); 1568 printf("siop_stat_intr_done %d\n", siop_stat_intr_done); 1569 } 1570 #endif 1571
Indexes created Sun Sep 28 16:09:52 GMT 2025