siop.c revision 1.33
1 /* $NetBSD: siop.c,v 1.33 2000/10/19 07:22:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 42 #include <machine/endian.h> 43 #include <machine/bus.h> 44 45 #include <dev/microcode/siop/siop.out> 46 47 #include <dev/scsipi/scsi_all.h> 48 #include <dev/scsipi/scsi_message.h> 49 #include <dev/scsipi/scsipi_all.h> 50 51 #include <dev/scsipi/scsiconf.h> 52 53 #include <dev/ic/siopreg.h> 54 #include <dev/ic/siopvar.h> 55 #include <dev/ic/siopvar_common.h> 56 57 #undef DEBUG 58 #undef DEBUG_DR 59 #undef DEBUG_INTR 60 #undef DEBUG_SCHED 61 #undef DUMP_SCRIPT 62 63 #define SIOP_STATS 64 65 #ifndef SIOP_DEFAULT_TARGET 66 #define SIOP_DEFAULT_TARGET 7 67 #endif 68 69 /* number of cmd descriptors per block */ 70 #define SIOP_NCMDPB (NBPG / sizeof(struct siop_xfer)) 71 72 void siop_reset __P((struct siop_softc *)); 73 void siop_handle_reset __P((struct siop_softc *)); 74 int siop_handle_qtag_reject __P((struct siop_cmd *)); 75 void siop_scsicmd_end __P((struct siop_cmd *)); 76 void siop_start __P((struct siop_softc *)); 77 void siop_timeout __P((void *)); 78 int siop_scsicmd __P((struct scsipi_xfer *)); 79 void siop_dump_script __P((struct siop_softc *)); 80 int siop_morecbd __P((struct siop_softc *)); 81 struct siop_lunsw *siop_get_lunsw __P((struct siop_softc *)); 82 void siop_add_reselsw __P((struct siop_softc *, int)); 83 void siop_update_scntl3 __P((struct siop_softc *, struct siop_target *)); 84 85 struct scsipi_adapter siop_adapter = { 86 0, 87 siop_scsicmd, 88 siop_minphys, 89 siop_ioctl, 90 NULL, 91 NULL, 92 }; 93 94 struct scsipi_device siop_dev = { 95 NULL, 96 NULL, 97 NULL, 98 NULL, 99 }; 100 101 #ifdef SIOP_STATS 102 static int siop_stat_intr = 0; 103 static int siop_stat_intr_shortxfer = 0; 104 static int siop_stat_intr_sdp = 0; 105 static int siop_stat_intr_done = 0; 106 static int siop_stat_intr_xferdisc = 0; 107 void siop_printstats __P((void)); 108 #define INCSTAT(x) x++ 109 #else 110 #define INCSTAT(x) 111 #endif 112 113 static __inline__ void siop_table_sync __P((struct siop_cmd *, int)); 114 static __inline__ void 115 siop_table_sync(siop_cmd, ops) 116 struct siop_cmd *siop_cmd; 117 int ops; 118 { 119 struct siop_softc *sc = siop_cmd->siop_sc; 120 bus_addr_t offset; 121 122 offset = siop_cmd->dsa - 123 siop_cmd->siop_cbdp->xferdma->dm_segs[0].ds_addr; 124 bus_dmamap_sync(sc->sc_dmat, siop_cmd->siop_cbdp->xferdma, offset, 125 sizeof(struct siop_xfer), ops); 126 } 127 128 static __inline__ void siop_sched_sync __P((struct siop_softc *, int)); 129 static __inline__ void 130 siop_sched_sync(sc, ops) 131 struct siop_softc *sc; 132 int ops; 133 { 134 bus_dmamap_sync(sc->sc_dmat, sc->sc_scheddma, 0, NBPG, ops); 135 } 136 137 static __inline__ void siop_script_sync __P((struct siop_softc *, int)); 138 static __inline__ void 139 siop_script_sync(sc, ops) 140 struct siop_softc *sc; 141 int ops; 142 { 143 if ((sc->features & SF_CHIP_RAM) != 0) 144 bus_dmamap_sync(sc->sc_dmat, sc->sc_scriptdma, 0, NBPG, ops); 145 } 146 147 static __inline__ u_int32_t siop_script_read __P((struct siop_softc *, int)); 148 static __inline__ u_int32_t 149 siop_script_read(sc, offset) 150 struct siop_softc *sc; 151 int offset; 152 { 153 if (sc->features & SF_CHIP_RAM) { 154 return bus_space_read_4(sc->sc_ramt, sc->sc_ramh, offset * 4); 155 } else { 156 return le32toh(sc->sc_script[offset]); 157 } 158 } 159 160 static __inline__ void siop_script_write __P((struct siop_softc *, int, 161 u_int32_t)); 162 static __inline__ void 163 siop_script_write(sc, offset, val) 164 struct siop_softc *sc; 165 int offset; 166 u_int32_t val; 167 { 168 if (sc->features & SF_CHIP_RAM) { 169 bus_space_write_4(sc->sc_ramt, sc->sc_ramh, offset * 4, val); 170 } else { 171 sc->sc_script[offset] = htole32(val); 172 } 173 } 174 175 176 void 177 siop_attach(sc) 178 struct siop_softc *sc; 179 { 180 int error, i; 181 bus_dma_segment_t seg; 182 int rseg; 183 184 /* 185 * Allocate DMA-safe memory for the script and script scheduler 186 * and map it. 187 */ 188 if ((sc->features & SF_CHIP_RAM) == 0) { 189 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, 190 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 191 if (error) { 192 printf("%s: unable to allocate script DMA memory, " 193 "error = %d\n", sc->sc_dev.dv_xname, error); 194 return; 195 } 196 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 197 (caddr_t *)&sc->sc_script, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 198 if (error) { 199 printf("%s: unable to map script DMA memory, " 200 "error = %d\n", sc->sc_dev.dv_xname, error); 201 return; 202 } 203 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, 204 NBPG, 0, BUS_DMA_NOWAIT, &sc->sc_scriptdma); 205 if (error) { 206 printf("%s: unable to create script DMA map, " 207 "error = %d\n", sc->sc_dev.dv_xname, error); 208 return; 209 } 210 error = bus_dmamap_load(sc->sc_dmat, sc->sc_scriptdma, 211 sc->sc_script, NBPG, NULL, BUS_DMA_NOWAIT); 212 if (error) { 213 printf("%s: unable to load script DMA map, " 214 "error = %d\n", sc->sc_dev.dv_xname, error); 215 return; 216 } 217 sc->sc_scriptaddr = sc->sc_scriptdma->dm_segs[0].ds_addr; 218 } 219 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, 220 NBPG, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 221 if (error) { 222 printf("%s: unable to allocate scheduler DMA memory, " 223 "error = %d\n", sc->sc_dev.dv_xname, error); 224 return; 225 } 226 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 227 (caddr_t *)&sc->sc_sched, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 228 if (error) { 229 printf("%s: unable to map scheduler DMA memory, error = %d\n", 230 sc->sc_dev.dv_xname, error); 231 return; 232 } 233 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, 234 NBPG, 0, BUS_DMA_NOWAIT, &sc->sc_scheddma); 235 if (error) { 236 printf("%s: unable to create scheduler DMA map, error = %d\n", 237 sc->sc_dev.dv_xname, error); 238 return; 239 } 240 error = bus_dmamap_load(sc->sc_dmat, sc->sc_scheddma, sc->sc_sched, 241 NBPG, NULL, BUS_DMA_NOWAIT); 242 if (error) { 243 printf("%s: unable to load scheduler DMA map, error = %d\n", 244 sc->sc_dev.dv_xname, error); 245 return; 246 } 247 TAILQ_INIT(&sc->free_list); 248 TAILQ_INIT(&sc->ready_list); 249 TAILQ_INIT(&sc->cmds); 250 TAILQ_INIT(&sc->lunsw_list); 251 /* compute number of scheduler slots */ 252 sc->sc_nschedslots = ( 253 NBPG /* memory size allocated for scheduler */ 254 - sizeof(endslot_script) /* memory needed at end of scheduler */ 255 ) / (sizeof(slot_script) - 8); 256 sc->sc_currschedslot = 0; 257 #ifdef DEBUG 258 printf("%s: script size = %d, PHY addr=0x%x, VIRT=%p nslots %d\n", 259 sc->sc_dev.dv_xname, (int)sizeof(siop_script), 260 (u_int32_t)sc->sc_scriptaddr, sc->sc_script, sc->sc_nschedslots); 261 #endif 262 263 sc->sc_link.adapter_softc = sc; 264 sc->sc_link.openings = 1; 265 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 266 sc->sc_link.scsipi_scsi.max_target = 267 (sc->features & SF_BUS_WIDE) ? 15 : 7; 268 sc->sc_link.scsipi_scsi.max_lun = 7; 269 sc->sc_link.scsipi_scsi.adapter_target = bus_space_read_1(sc->sc_rt, 270 sc->sc_rh, SIOP_SCID); 271 if (sc->sc_link.scsipi_scsi.adapter_target == 0 || 272 sc->sc_link.scsipi_scsi.adapter_target > 273 sc->sc_link.scsipi_scsi.max_target) 274 sc->sc_link.scsipi_scsi.adapter_target = SIOP_DEFAULT_TARGET; 275 sc->sc_link.type = BUS_SCSI; 276 sc->sc_link.adapter = &siop_adapter; 277 sc->sc_link.device = &siop_dev; 278 sc->sc_link.flags = 0; 279 280 for (i = 0; i < 16; i++) 281 sc->targets[i] = NULL; 282 283 /* find min/max sync period for this chip */ 284 sc->maxsync = 0; 285 sc->minsync = 255; 286 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); i++) { 287 if (sc->clock_period != scf_period[i].clock) 288 continue; 289 if (sc->maxsync < scf_period[i].period) 290 sc->maxsync = scf_period[i].period; 291 if (sc->minsync > scf_period[i].period) 292 sc->minsync = scf_period[i].period; 293 } 294 if (sc->maxsync == 255 || sc->minsync == 0) 295 panic("siop: can't find my sync parameters\n"); 296 /* Do a bus reset, so that devices fall back to narrow/async */ 297 siop_resetbus(sc); 298 /* 299 * siop_reset() will reset the chip, thus clearing pending interrupts 300 */ 301 siop_reset(sc); 302 #ifdef DUMP_SCRIPT 303 siop_dump_script(sc); 304 #endif 305 306 config_found((struct device*)sc, &sc->sc_link, scsiprint); 307 } 308 309 void 310 siop_reset(sc) 311 struct siop_softc *sc; 312 { 313 int i, j; 314 u_int32_t *scr; 315 bus_addr_t physaddr; 316 struct siop_lunsw *lunsw; 317 318 siop_common_reset(sc); 319 320 /* copy and patch the script */ 321 if (sc->features & SF_CHIP_RAM) { 322 bus_space_write_region_4(sc->sc_ramt, sc->sc_ramh, 0, 323 siop_script, sizeof(siop_script) / sizeof(siop_script[0])); 324 for (j = 0; j < 325 (sizeof(E_script_abs_sched_Used) / 326 sizeof(E_script_abs_sched_Used[0])); 327 j++) { 328 bus_space_write_4(sc->sc_ramt, sc->sc_ramh, 329 E_script_abs_sched_Used[j] * 4, 330 sc->sc_scheddma->dm_segs[0].ds_addr); 331 } 332 for (j = 0; j < 333 (sizeof(E_abs_msgin_Used) / sizeof(E_abs_msgin_Used[0])); 334 j++) { 335 bus_space_write_4(sc->sc_ramt, sc->sc_ramh, 336 E_abs_msgin_Used[j] * 4, 337 sc->sc_scriptaddr + Ent_msgin_space); 338 } 339 } else { 340 for (j = 0; 341 j < (sizeof(siop_script) / sizeof(siop_script[0])); j++) { 342 sc->sc_script[j] = htole32(siop_script[j]); 343 } 344 for (j = 0; j < 345 (sizeof(E_script_abs_sched_Used) / 346 sizeof(E_script_abs_sched_Used[0])); 347 j++) { 348 sc->sc_script[E_script_abs_sched_Used[j]] = 349 htole32(sc->sc_scheddma->dm_segs[0].ds_addr); 350 } 351 for (j = 0; j < 352 (sizeof(E_abs_msgin_Used) / sizeof(E_abs_msgin_Used[0])); 353 j++) { 354 sc->sc_script[E_abs_msgin_Used[j]] = 355 htole32(sc->sc_scriptaddr + Ent_msgin_space); 356 } 357 } 358 sc->ram_free = sizeof(siop_script) / sizeof(siop_script[0]); 359 /* copy and init the scheduler slots script */ 360 for (i = 0; i < sc->sc_nschedslots; i++) { 361 scr = &sc->sc_sched[(Ent_nextslot / 4) * i]; 362 physaddr = sc->sc_scheddma->dm_segs[0].ds_addr + 363 Ent_nextslot * i; 364 for (j = 0; j < (Ent_nextslot / 4); j++) { 365 scr[j] = htole32(slot_script[j]); 366 } 367 /* 368 * save current jump offset and patch MOVE MEMORY operands 369 * to restore it. 370 */ 371 scr[(Ent_slotdata/4) + 1] = scr[(Ent_slot/4) + 1]; 372 scr[E_slot_nextp_Used[0]] = htole32(physaddr + Ent_slot + 4); 373 scr[E_slot_sched_addrsrc_Used[0]] = htole32(physaddr + 374 Ent_slotdata + 4); 375 /* JUMP selected, in main script */ 376 scr[E_slot_abs_selected_Used[0]] = 377 htole32(sc->sc_scriptaddr + Ent_selected); 378 /* JUMP addr if SELECT fail */ 379 scr[E_slot_abs_reselect_Used[0]] = 380 htole32(sc->sc_scriptaddr + Ent_reselect); 381 } 382 /* Now the final JUMP */ 383 scr = &sc->sc_sched[(Ent_nextslot / 4) * sc->sc_nschedslots]; 384 for (j = 0; j < (sizeof(endslot_script) / sizeof(endslot_script[0])); 385 j++) { 386 scr[j] = htole32(endslot_script[j]); 387 } 388 scr[E_endslot_abs_reselect_Used[0]] = 389 htole32(sc->sc_scriptaddr + Ent_reselect); 390 391 /* free used and unused lun switches */ 392 while((lunsw = TAILQ_FIRST(&sc->lunsw_list)) != NULL) { 393 #ifdef DEBUG 394 printf("%s: free lunsw at offset %d\n", 395 sc->sc_dev.dv_xname, lunsw->lunsw_off); 396 #endif 397 TAILQ_REMOVE(&sc->lunsw_list, lunsw, next); 398 free(lunsw, M_DEVBUF); 399 } 400 TAILQ_INIT(&sc->lunsw_list); 401 /* restore reselect switch */ 402 for (i = 0; i < sc->sc_link.scsipi_scsi.max_target; i++) { 403 if (sc->targets[i] == NULL) 404 continue; 405 #ifdef DEBUG 406 printf("%s: restore sw for target %d\n", 407 sc->sc_dev.dv_xname, i); 408 #endif 409 free(sc->targets[i]->lunsw, M_DEVBUF); 410 sc->targets[i]->lunsw = siop_get_lunsw(sc); 411 if (sc->targets[i]->lunsw == NULL) { 412 printf("%s: can't alloc lunsw for target %d\n", 413 sc->sc_dev.dv_xname, i); 414 break; 415 } 416 siop_add_reselsw(sc, i); 417 } 418 419 /* start script */ 420 if ((sc->features & SF_CHIP_RAM) == 0) { 421 bus_dmamap_sync(sc->sc_dmat, sc->sc_scriptdma, 0, NBPG, 422 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 423 } 424 siop_sched_sync(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 425 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 426 sc->sc_scriptaddr + Ent_reselect); 427 } 428 429 #if 0 430 #define CALL_SCRIPT(ent) do {\ 431 printf ("start script DSA 0x%lx DSP 0x%lx\n", \ 432 siop_cmd->dsa, \ 433 sc->sc_scriptaddr + ent); \ 434 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \ 435 } while (0) 436 #else 437 #define CALL_SCRIPT(ent) do {\ 438 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, sc->sc_scriptaddr + ent); \ 439 } while (0) 440 #endif 441 442 int 443 siop_intr(v) 444 void *v; 445 { 446 struct siop_softc *sc = v; 447 struct siop_target *siop_target; 448 struct siop_cmd *siop_cmd; 449 struct siop_lun *siop_lun; 450 struct scsipi_xfer *xs; 451 int istat, sist0, sist1, sstat1, dstat; 452 u_int32_t irqcode; 453 int need_reset = 0; 454 int freetarget = 0; 455 int offset, lun; 456 bus_addr_t dsa; 457 struct siop_cbd *cbdp; 458 459 istat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT); 460 if ((istat & (ISTAT_INTF | ISTAT_DIP | ISTAT_SIP)) == 0) 461 return 0; 462 INCSTAT(siop_stat_intr); 463 if (istat & ISTAT_INTF) { 464 printf("INTRF\n"); 465 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_INTF); 466 } 467 /* use DSA to find the current siop_cmd */ 468 dsa = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA); 469 for (cbdp = TAILQ_FIRST(&sc->cmds); cbdp != NULL; 470 cbdp = TAILQ_NEXT(cbdp, next)) { 471 if (dsa >= cbdp->xferdma->dm_segs[0].ds_addr && 472 dsa < cbdp->xferdma->dm_segs[0].ds_addr + NBPG) { 473 dsa -= cbdp->xferdma->dm_segs[0].ds_addr; 474 siop_cmd = &cbdp->cmds[dsa / sizeof(struct siop_xfer)]; 475 siop_table_sync(siop_cmd, 476 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 477 break; 478 } 479 } 480 if (cbdp == NULL) { 481 siop_cmd = NULL; 482 } 483 if (siop_cmd) { 484 xs = siop_cmd->xs; 485 siop_target = siop_cmd->siop_target; 486 lun = siop_cmd->xs->sc_link->scsipi_scsi.lun; 487 siop_lun = &(siop_target->siop_lun[lun]); 488 #ifdef DIAGNOSTIC 489 if (siop_cmd->status != CMDST_ACTIVE && 490 siop_cmd->status != CMDST_SENSE_ACTIVE) { 491 printf("siop_cmd (lun %d) not active (%d)\n", 492 lun, siop_cmd->status); 493 xs = NULL; 494 siop_target = NULL; 495 lun = -1; 496 siop_lun = NULL; 497 siop_cmd = NULL; 498 } else if (siop_lun->active != siop_cmd) { 499 printf("siop_cmd (lun %d) not in siop_lun active " 500 "(%p != %p)\n", lun, siop_cmd, siop_lun->active); 501 } 502 #endif 503 } else { 504 xs = NULL; 505 siop_target = NULL; 506 lun = -1; 507 siop_lun = NULL; 508 } 509 if (istat & ISTAT_DIP) { 510 u_int32_t *p; 511 dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DSTAT); 512 if (dstat & DSTAT_SSI) { 513 printf("single step dsp 0x%08x dsa 0x08%x\n", 514 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 515 sc->sc_scriptaddr), 516 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA)); 517 if ((dstat & ~(DSTAT_DFE | DSTAT_SSI)) == 0 && 518 (istat & ISTAT_SIP) == 0) { 519 bus_space_write_1(sc->sc_rt, sc->sc_rh, 520 SIOP_DCNTL, bus_space_read_1(sc->sc_rt, 521 sc->sc_rh, SIOP_DCNTL) | DCNTL_STD); 522 } 523 return 1; 524 } 525 if (dstat & ~(DSTAT_SIR | DSTAT_DFE | DSTAT_SSI)) { 526 printf("DMA IRQ:"); 527 if (dstat & DSTAT_IID) 528 printf(" Illegal instruction"); 529 if (dstat & DSTAT_ABRT) 530 printf(" abort"); 531 if (dstat & DSTAT_BF) 532 printf(" bus fault"); 533 if (dstat & DSTAT_MDPE) 534 printf(" parity"); 535 if (dstat & DSTAT_DFE) 536 printf(" dma fifo empty"); 537 printf(", DSP=0x%x DSA=0x%x: ", 538 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 539 sc->sc_scriptaddr), 540 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA)); 541 p = sc->sc_script + 542 (bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 543 sc->sc_scriptaddr - 8) / 4; 544 printf("0x%x 0x%x 0x%x 0x%x\n", le32toh(p[0]), le32toh(p[1]), 545 le32toh(p[2]), le32toh(p[3])); 546 if (siop_cmd) 547 printf("last msg_in=0x%x status=0x%x\n", 548 siop_cmd->siop_tables.msg_in[0], 549 le32toh(siop_cmd->siop_tables.status)); 550 else 551 printf("%s: current DSA invalid\n", 552 sc->sc_dev.dv_xname); 553 need_reset = 1; 554 } 555 } 556 if (istat & ISTAT_SIP) { 557 if (istat & ISTAT_DIP) 558 delay(10); 559 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 560 delay(10); 561 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 562 sstat1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1); 563 #ifdef DEBUG_INTR 564 printf("scsi interrupt, sist0=0x%x sist1=0x%x sstat1=0x%x " 565 "DSA=0x%x DSP=0x%lx\n", sist0, sist1, 566 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1), 567 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA), 568 (u_long)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 569 sc->sc_scriptaddr)); 570 #endif 571 if (sist0 & SIST0_RST) { 572 siop_handle_reset(sc); 573 siop_start(sc); 574 /* no table to flush here */ 575 return 1; 576 } 577 if (sist0 & SIST0_SGE) { 578 if (siop_cmd) 579 scsi_print_addr(xs->sc_link); 580 else 581 printf("%s:", sc->sc_dev.dv_xname); 582 printf("scsi gross error\n"); 583 goto reset; 584 } 585 if ((sist0 & SIST0_MA) && need_reset == 0) { 586 if (siop_cmd) { 587 int scratcha0; 588 dstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 589 SIOP_DSTAT); 590 /* 591 * first restore DSA, in case we were in a S/G 592 * operation. 593 */ 594 bus_space_write_4(sc->sc_rt, sc->sc_rh, 595 SIOP_DSA, siop_cmd->dsa); 596 scratcha0 = bus_space_read_1(sc->sc_rt, 597 sc->sc_rh, SIOP_SCRATCHA); 598 switch (sstat1 & SSTAT1_PHASE_MASK) { 599 case SSTAT1_PHASE_STATUS: 600 /* 601 * previous phase may be aborted for any reason 602 * ( for example, the target has less data to 603 * transfer than requested). Just go to status 604 * and the command should terminate. 605 */ 606 INCSTAT(siop_stat_intr_shortxfer); 607 if ((dstat & DSTAT_DFE) == 0) 608 siop_clearfifo(sc); 609 /* no table to flush here */ 610 CALL_SCRIPT(Ent_status); 611 return 1; 612 case SSTAT1_PHASE_MSGIN: 613 /* 614 * target may be ready to disconnect 615 * Save data pointers just in case. 616 */ 617 INCSTAT(siop_stat_intr_xferdisc); 618 if (scratcha0 & A_flag_data) 619 siop_sdp(siop_cmd); 620 else if ((dstat & DSTAT_DFE) == 0) 621 siop_clearfifo(sc); 622 bus_space_write_1(sc->sc_rt, sc->sc_rh, 623 SIOP_SCRATCHA, 624 scratcha0 & ~A_flag_data); 625 siop_table_sync(siop_cmd, 626 BUS_DMASYNC_PREREAD | 627 BUS_DMASYNC_PREWRITE); 628 CALL_SCRIPT(Ent_msgin); 629 return 1; 630 } 631 printf("%s: unexpected phase mismatch %d\n", 632 sc->sc_dev.dv_xname, 633 sstat1 & SSTAT1_PHASE_MASK); 634 } else { 635 printf("%s: phase mismatch without command\n", 636 sc->sc_dev.dv_xname); 637 } 638 need_reset = 1; 639 } 640 if (sist0 & SIST0_PAR) { 641 /* parity error, reset */ 642 if (siop_cmd) 643 scsi_print_addr(xs->sc_link); 644 else 645 printf("%s:", sc->sc_dev.dv_xname); 646 printf("parity error\n"); 647 goto reset; 648 } 649 if ((sist1 & SIST1_STO) && need_reset == 0) { 650 /* selection time out, assume there's no device here */ 651 if (siop_cmd) { 652 siop_cmd->status = CMDST_DONE; 653 xs->error = XS_SELTIMEOUT; 654 freetarget = 1; 655 goto end; 656 } else { 657 printf("%s: selection timeout without " 658 "command\n", sc->sc_dev.dv_xname); 659 need_reset = 1; 660 } 661 } 662 if (sist0 & SIST0_UDC) { 663 /* 664 * unexpected disconnect. Usually the target signals 665 * a fatal condition this way. Attempt to get sense. 666 */ 667 if (siop_cmd) 668 goto check_sense; 669 printf("%s: unexpected disconnect without " 670 "command\n", sc->sc_dev.dv_xname); 671 goto reset; 672 } 673 if (sist1 & SIST1_SBMC) { 674 /* SCSI bus mode change */ 675 if (siop_modechange(sc) == 0 || need_reset == 1) 676 goto reset; 677 if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) { 678 /* 679 * we have a script interrupt, it will 680 * restart the script. 681 */ 682 goto scintr; 683 } 684 /* 685 * else we have to restart it ourselve, at the 686 * interrupted instruction. 687 */ 688 bus_space_write_4(sc->sc_rt, sc->sc_rh, SIOP_DSP, 689 bus_space_read_4(sc->sc_rt, sc->sc_rh, 690 SIOP_DSP) - 8); 691 return 1; 692 } 693 /* Else it's an unhandled exeption (for now). */ 694 printf("%s: unhandled scsi interrupt, sist0=0x%x sist1=0x%x " 695 "sstat1=0x%x DSA=0x%x DSP=0x%x\n", sc->sc_dev.dv_xname, 696 sist0, sist1, 697 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT1), 698 bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSA), 699 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DSP) - 700 sc->sc_scriptaddr)); 701 if (siop_cmd) { 702 siop_cmd->status = CMDST_DONE; 703 xs->error = XS_SELTIMEOUT; 704 goto end; 705 } 706 need_reset = 1; 707 } 708 if (need_reset) { 709 reset: 710 /* fatal error, reset the bus */ 711 siop_resetbus(sc); 712 /* no table to flush here */ 713 return 1; 714 } 715 716 scintr: 717 if ((istat & ISTAT_DIP) && (dstat & DSTAT_SIR)) { /* script interrupt */ 718 irqcode = bus_space_read_4(sc->sc_rt, sc->sc_rh, 719 SIOP_DSPS); 720 #ifdef DEBUG_INTR 721 printf("script interrupt 0x%x\n", irqcode); 722 #endif 723 /* 724 * no command, or an inactive command is only valid for a 725 * reselect interrupt 726 */ 727 if ((irqcode & 0x80) == 0) { 728 if (siop_cmd == NULL) { 729 printf("%s: script interrupt (0x%x) with 730 invalid DSA !!!\n", sc->sc_dev.dv_xname, 731 irqcode); 732 goto reset; 733 } 734 if (siop_cmd->status != CMDST_ACTIVE && 735 siop_cmd->status != CMDST_SENSE_ACTIVE) { 736 printf("%s: command with invalid status " 737 "(IRQ code 0x%x current status %d) !\n", 738 sc->sc_dev.dv_xname, 739 irqcode, siop_cmd->status); 740 xs = NULL; 741 } 742 } 743 switch(irqcode) { 744 case A_int_err: 745 printf("error, DSP=0x%x\n", 746 (int)(bus_space_read_4(sc->sc_rt, sc->sc_rh, 747 SIOP_DSP) - sc->sc_scriptaddr)); 748 if (xs) { 749 xs->error = XS_SELTIMEOUT; 750 goto end; 751 } else { 752 goto reset; 753 } 754 case A_int_reseltarg: 755 printf("%s: reselect with invalid target\n", 756 sc->sc_dev.dv_xname); 757 goto reset; 758 case A_int_resellun: 759 printf("%s: reselect with invalid lun\n", 760 sc->sc_dev.dv_xname); 761 goto reset; 762 case A_int_reseltag: 763 printf("%s: reselect with invalid tag\n", 764 sc->sc_dev.dv_xname); 765 goto reset; 766 case A_int_msgin: 767 { 768 int msgin = bus_space_read_1(sc->sc_rt, sc->sc_rh, 769 SIOP_SFBR); 770 if (msgin == MSG_MESSAGE_REJECT) { 771 int msg, extmsg; 772 if (siop_cmd->siop_tables.msg_out[0] & 0x80) { 773 /* 774 * message was part of a identify + 775 * something else. Identify shoudl't 776 * have been rejected. 777 */ 778 msg = siop_cmd->siop_tables.msg_out[1]; 779 extmsg = 780 siop_cmd->siop_tables.msg_out[3]; 781 } else { 782 msg = siop_cmd->siop_tables.msg_out[0]; 783 extmsg = 784 siop_cmd->siop_tables.msg_out[2]; 785 } 786 if (msg == MSG_MESSAGE_REJECT) { 787 /* MSG_REJECT for a MSG_REJECT !*/ 788 if (xs) 789 scsi_print_addr(xs->sc_link); 790 else 791 printf("%s: ", 792 sc->sc_dev.dv_xname); 793 printf("our reject message was " 794 "rejected\n"); 795 goto reset; 796 } 797 if (msg == MSG_EXTENDED && 798 extmsg == MSG_EXT_WDTR) { 799 /* WDTR rejected, initiate sync */ 800 printf("%s: target %d using 8bit " 801 "transfers\n", sc->sc_dev.dv_xname, 802 xs->sc_link->scsipi_scsi.target); 803 if ((siop_target->flags & TARF_SYNC) 804 == 0) { 805 siop_target->status = TARST_OK; 806 /* no table to flush here */ 807 CALL_SCRIPT(Ent_msgin_ack); 808 return 1; 809 } 810 siop_target->status = TARST_SYNC_NEG; 811 siop_cmd->siop_tables.msg_out[0] = 812 MSG_EXTENDED; 813 siop_cmd->siop_tables.msg_out[1] = 814 MSG_EXT_SDTR_LEN; 815 siop_cmd->siop_tables.msg_out[2] = 816 MSG_EXT_SDTR; 817 siop_cmd->siop_tables.msg_out[3] = 818 sc->minsync; 819 siop_cmd->siop_tables.msg_out[4] = 820 sc->maxoff; 821 siop_cmd->siop_tables.t_msgout.count = 822 htole32(MSG_EXT_SDTR_LEN + 2); 823 siop_cmd->siop_tables.t_msgout.addr = 824 htole32(siop_cmd->dsa); 825 siop_table_sync(siop_cmd, 826 BUS_DMASYNC_PREREAD | 827 BUS_DMASYNC_PREWRITE); 828 CALL_SCRIPT(Ent_send_msgout); 829 return 1; 830 } else if (msg == MSG_EXTENDED && 831 extmsg == MSG_EXT_SDTR) { 832 /* sync rejected */ 833 printf("%s: target %d asynchronous\n", 834 sc->sc_dev.dv_xname, 835 xs->sc_link->scsipi_scsi.target); 836 siop_target->status = TARST_OK; 837 /* no table to flush here */ 838 CALL_SCRIPT(Ent_msgin_ack); 839 return 1; 840 } 841 if (xs) 842 scsi_print_addr(xs->sc_link); 843 else 844 printf("%s: ", sc->sc_dev.dv_xname); 845 if (msg == MSG_EXTENDED) { 846 printf("scsi message reject, extended " 847 "message sent was 0x%x\n", extmsg); 848 } else { 849 printf("scsi message reject, message " 850 "sent was 0x%x\n", msg); 851 if (msg == MSG_SIMPLE_Q_TAG || 852 msg == MSG_HEAD_OF_Q_TAG || 853 msg == MSG_ORDERED_Q_TAG) 854 if (siop_handle_qtag_reject( 855 siop_cmd) == -1) 856 goto reset; 857 } 858 /* no table to flush here */ 859 CALL_SCRIPT(Ent_msgin_ack); 860 return 1; 861 } 862 if (xs) 863 scsi_print_addr(xs->sc_link); 864 else 865 printf("%s: ", sc->sc_dev.dv_xname); 866 printf("unhandled message 0x%x\n", 867 siop_cmd->siop_tables.msg_in[0]); 868 siop_cmd->siop_tables.t_msgout.count= htole32(1); 869 siop_cmd->siop_tables.t_msgout.addr = 870 htole32(siop_cmd->dsa); 871 siop_cmd->siop_tables.msg_out[0] = MSG_MESSAGE_REJECT; 872 siop_table_sync(siop_cmd, 873 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 874 CALL_SCRIPT(Ent_send_msgout); 875 return 1; 876 } 877 case A_int_extmsgin: 878 #ifdef DEBUG_INTR 879 printf("extended message: msg 0x%x len %d\n", 880 siop_cmd->siop_tables.msg_in[2], 881 siop_cmd->siop_tables.msg_in[1]); 882 #endif 883 if (siop_cmd->siop_tables.msg_in[1] > 6) 884 printf("%s: extended message too big (%d)\n", 885 sc->sc_dev.dv_xname, 886 siop_cmd->siop_tables.msg_in[1]); 887 siop_cmd->siop_tables.t_extmsgdata.count = 888 htole32(siop_cmd->siop_tables.msg_in[1] - 1); 889 siop_cmd->siop_tables.t_extmsgdata.addr = 890 htole32( 891 le32toh(siop_cmd->siop_tables.t_extmsgin.addr) 892 + 2); 893 siop_table_sync(siop_cmd, 894 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 895 CALL_SCRIPT(Ent_get_extmsgdata); 896 return 1; 897 case A_int_extmsgdata: 898 #ifdef DEBUG_INTR 899 { 900 int i; 901 printf("extended message: 0x%x, data:", 902 siop_cmd->siop_tables.msg_in[2]); 903 for (i = 3; i < 2 + siop_cmd->siop_tables.msg_in[1]; 904 i++) 905 printf(" 0x%x", 906 siop_cmd->siop_tables.msg_in[i]); 907 printf("\n"); 908 } 909 #endif 910 if (siop_cmd->siop_tables.msg_in[2] == MSG_EXT_WDTR) { 911 switch (siop_wdtr_neg(siop_cmd)) { 912 case SIOP_NEG_MSGOUT: 913 siop_update_scntl3(sc, 914 siop_cmd->siop_target); 915 siop_table_sync(siop_cmd, 916 BUS_DMASYNC_PREREAD | 917 BUS_DMASYNC_PREWRITE); 918 CALL_SCRIPT(Ent_send_msgout); 919 return(1); 920 case SIOP_NEG_ACK: 921 siop_update_scntl3(sc, 922 siop_cmd->siop_target); 923 CALL_SCRIPT(Ent_msgin_ack); 924 return(1); 925 default: 926 panic("invalid retval from " 927 "siop_wdtr_neg()"); 928 } 929 return(1); 930 } 931 if (siop_cmd->siop_tables.msg_in[2] == MSG_EXT_SDTR) { 932 switch (siop_sdtr_neg(siop_cmd)) { 933 case SIOP_NEG_MSGOUT: 934 siop_update_scntl3(sc, 935 siop_cmd->siop_target); 936 siop_table_sync(siop_cmd, 937 BUS_DMASYNC_PREREAD | 938 BUS_DMASYNC_PREWRITE); 939 CALL_SCRIPT(Ent_send_msgout); 940 return(1); 941 case SIOP_NEG_ACK: 942 siop_update_scntl3(sc, 943 siop_cmd->siop_target); 944 CALL_SCRIPT(Ent_msgin_ack); 945 return(1); 946 default: 947 panic("invalid retval from " 948 "siop_wdtr_neg()"); 949 } 950 return(1); 951 } 952 /* send a message reject */ 953 siop_cmd->siop_tables.t_msgout.count = htole32(1); 954 siop_cmd->siop_tables.t_msgout.addr = 955 htole32(siop_cmd->dsa); 956 siop_cmd->siop_tables.msg_out[0] = 957 MSG_MESSAGE_REJECT; 958 siop_table_sync(siop_cmd, 959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 960 CALL_SCRIPT(Ent_send_msgout); 961 return 1; 962 case A_int_disc: 963 INCSTAT(siop_stat_intr_sdp); 964 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, 965 SIOP_SCRATCHA + 1); 966 #ifdef DEBUG_DR 967 printf("disconnect offset %d\n", offset); 968 #endif 969 if (offset > SIOP_NSG) { 970 printf("%s: bad offset for disconnect (%d)\n", 971 sc->sc_dev.dv_xname, offset); 972 goto reset; 973 } 974 /* 975 * offset == SIOP_NSG may be a valid condition if 976 * we get a sdp when the xfer is done. 977 * Don't call memmove in this case. 978 */ 979 if (offset < SIOP_NSG) { 980 memmove(&siop_cmd->siop_tables.data[0], 981 &siop_cmd->siop_tables.data[offset], 982 (SIOP_NSG - offset) * sizeof(scr_table_t)); 983 siop_table_sync(siop_cmd, 984 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 985 } 986 CALL_SCRIPT(Ent_script_sched); 987 return 1; 988 case A_int_resfail: 989 printf("reselect failed\n"); 990 CALL_SCRIPT(Ent_script_sched); 991 return 1; 992 case A_int_done: 993 if (xs == NULL) { 994 printf("%s: done without command, DSA=0x%lx\n", 995 sc->sc_dev.dv_xname, (u_long)siop_cmd->dsa); 996 siop_cmd->status = CMDST_FREE; 997 siop_start(sc); 998 CALL_SCRIPT(Ent_script_sched); 999 return 1; 1000 } 1001 if (siop_target->status == TARST_PROBING && 1002 xs->sc_link->device_softc != NULL) { 1003 siop_target->status = TARST_ASYNC; 1004 } 1005 #ifdef DEBUG_INTR 1006 printf("done, DSA=0x%lx target id 0x%x last msg " 1007 "in=0x%x status=0x%x\n", (u_long)siop_cmd->dsa, 1008 le32toh(siop_cmd->siop_tables.id), 1009 siop_cmd->siop_tables.msg_in[0], 1010 le32toh(siop_cmd->siop_tables.status)); 1011 #endif 1012 INCSTAT(siop_stat_intr_done); 1013 if (siop_cmd->status == CMDST_SENSE_ACTIVE) 1014 siop_cmd->status = CMDST_SENSE_DONE; 1015 else 1016 siop_cmd->status = CMDST_DONE; 1017 switch(le32toh(siop_cmd->siop_tables.status)) { 1018 case SCSI_OK: 1019 xs->error = (siop_cmd->status == CMDST_DONE) ? 1020 XS_NOERROR : XS_SENSE; 1021 break; 1022 case SCSI_BUSY: 1023 xs->error = XS_BUSY; 1024 break; 1025 case SCSI_CHECK: 1026 check_sense: 1027 if (siop_cmd->status == CMDST_SENSE_DONE) { 1028 /* request sense on a request sense ? */ 1029 printf("request sense failed\n"); 1030 xs->error = XS_DRIVER_STUFFUP; 1031 } else { 1032 siop_cmd->status = CMDST_SENSE; 1033 } 1034 break; 1035 case 0xff: 1036 /* 1037 * the status byte was not updated, cmd was 1038 * aborted 1039 */ 1040 xs->error = XS_SELTIMEOUT; 1041 break; 1042 default: 1043 xs->error = XS_DRIVER_STUFFUP; 1044 } 1045 goto end; 1046 default: 1047 printf("unknown irqcode %x\n", irqcode); 1048 xs->error = XS_SELTIMEOUT; 1049 goto end; 1050 } 1051 return 1; 1052 } 1053 /* We just should't get there */ 1054 panic("siop_intr: I shouldn't be there !"); 1055 return 1; 1056 end: 1057 CALL_SCRIPT(Ent_script_sched); 1058 siop_scsicmd_end(siop_cmd); 1059 siop_lun->active = NULL; 1060 if (siop_cmd->status == CMDST_FREE) { 1061 if (freetarget) { 1062 #ifdef DEBUG 1063 printf("%s: free siop_target for target %d lun %d " 1064 "lunsw offset %d\n", 1065 sc->sc_dev.dv_xname, 1066 xs->sc_link->scsipi_scsi.target, lun, 1067 sc->targets[xs->sc_link->scsipi_scsi.target]->lunsw->lunsw_off); 1068 #endif 1069 /* 1070 * nothing here, free the target struct and resel 1071 * switch entry 1072 */ 1073 siop_script_write(sc, siop_cmd->siop_target->reseloff, 1074 0x800c00ff); 1075 siop_script_sync(sc, BUS_DMASYNC_PREWRITE); 1076 TAILQ_INSERT_TAIL(&sc->lunsw_list, 1077 sc->targets[xs->sc_link->scsipi_scsi.target]->lunsw, 1078 next); 1079 free(sc->targets[xs->sc_link->scsipi_scsi.target], 1080 M_DEVBUF); 1081 sc->targets[xs->sc_link->scsipi_scsi.target] = NULL; 1082 siop_cmd->siop_target = NULL; 1083 } 1084 TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next); 1085 } 1086 siop_start(sc); 1087 return 1; 1088 } 1089 1090 void 1091 siop_scsicmd_end(siop_cmd) 1092 struct siop_cmd *siop_cmd; 1093 { 1094 struct scsipi_xfer *xs = siop_cmd->xs; 1095 struct siop_softc *sc = siop_cmd->siop_sc; 1096 1097 if (siop_cmd->status != CMDST_SENSE_DONE && 1098 xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 1099 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1100 siop_cmd->dmamap_data->dm_mapsize, 1101 (xs->xs_control & XS_CTL_DATA_IN) ? 1102 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1103 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data); 1104 } 1105 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1106 if (siop_cmd->status == CMDST_SENSE) { 1107 /* issue a request sense for this target */ 1108 int error, i; 1109 siop_cmd->rs_cmd.opcode = REQUEST_SENSE; 1110 siop_cmd->rs_cmd.byte2 = xs->sc_link->scsipi_scsi.lun << 5; 1111 siop_cmd->rs_cmd.unused[0] = siop_cmd->rs_cmd.unused[1] = 0; 1112 siop_cmd->rs_cmd.length = sizeof(struct scsipi_sense_data); 1113 siop_cmd->rs_cmd.control = 0; 1114 siop_cmd->siop_tables.status = htole32(0xff);/*invalid status*/ 1115 siop_cmd->siop_tables.t_msgout.count= htole32(1); 1116 siop_cmd->siop_tables.t_msgout.addr = htole32(siop_cmd->dsa); 1117 siop_cmd->siop_tables.msg_out[0] = 1118 MSG_IDENTIFY(xs->sc_link->scsipi_scsi.lun, 1); 1119 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd, 1120 &siop_cmd->rs_cmd, sizeof(struct scsipi_sense), 1121 NULL, BUS_DMA_NOWAIT); 1122 if (error) { 1123 printf("%s: unable to load cmd DMA map: %d", 1124 sc->sc_dev.dv_xname, error); 1125 xs->error = XS_DRIVER_STUFFUP; 1126 goto out; 1127 } 1128 siop_cmd->siop_tables.cmd.count = 1129 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 1130 siop_cmd->siop_tables.cmd.addr = 1131 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 1132 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data, 1133 &xs->sense.scsi_sense, sizeof(struct scsipi_sense_data), 1134 NULL, BUS_DMA_NOWAIT); 1135 if (error) { 1136 printf("%s: unable to load sense DMA map: %d", 1137 sc->sc_dev.dv_xname, error); 1138 xs->error = XS_DRIVER_STUFFUP; 1139 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1140 goto out; 1141 } 1142 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 1143 siop_cmd->siop_tables.data[i].count = 1144 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 1145 siop_cmd->siop_tables.data[i].addr = 1146 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 1147 } 1148 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1149 siop_cmd->dmamap_data->dm_mapsize, BUS_DMASYNC_PREREAD); 1150 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd, 0, 1151 siop_cmd->dmamap_cmd->dm_mapsize, BUS_DMASYNC_PREWRITE); 1152 siop_table_sync(siop_cmd, BUS_DMASYNC_PREWRITE); 1153 /* arrange for the cmd to be handled now */ 1154 TAILQ_INSERT_HEAD(&sc->ready_list, siop_cmd, next); 1155 return; 1156 } else if (siop_cmd->status == CMDST_SENSE_DONE) { 1157 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1158 siop_cmd->dmamap_data->dm_mapsize, BUS_DMASYNC_POSTREAD); 1159 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_data); 1160 } 1161 out: 1162 callout_stop(&siop_cmd->xs->xs_callout); 1163 siop_cmd->status = CMDST_FREE; 1164 xs->xs_status |= XS_STS_DONE; 1165 xs->resid = 0; 1166 if ((xs->xs_control & XS_CTL_POLL) == 0) 1167 scsipi_done (xs); 1168 } 1169 1170 /* 1171 * handle a rejected queue tag message: the command will run untagged, 1172 * has to adjust the reselect script. 1173 */ 1174 int 1175 siop_handle_qtag_reject(siop_cmd) 1176 struct siop_cmd *siop_cmd; 1177 { 1178 #if 0 1179 struct siop_softc *sc = siop_cmd->siop_sc; 1180 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 1181 int lun = siop_cmd->xs->sc_link->scsipi_scsi.lun; 1182 int tag = siop_cmd->siop_tables.msg_out[2]; 1183 int resel; 1184 u_int32_t *rscr; 1185 1186 for (resel = 0; resel < sc->sc_nreselslots; resel++) { 1187 rscr = &sc->sc_resel[ 1188 (Ent_res_nextld / 4) * resel]; 1189 if ((htole32(rscr[Ent_rtarget / 4]) & 0x0f) == target && 1190 (htole32(rscr[Ent_rlun / 4]) & 0x0f) == lun && 1191 (htole32(rscr[Ent_rtag / 4]) & 0xff) == tag) { 1192 rscr[Ent_rtag / 4] = htole32(0x808400ff); 1193 return 0; 1194 } 1195 } 1196 printf("%s: reselect entry not found for target %d lun %d tag %d\n", 1197 sc->sc_dev.dv_xname, target, lun, tag); 1198 return -1; 1199 #endif 1200 return 0; 1201 } 1202 1203 /* 1204 * handle a bus reset: reset chip, unqueue all active commands, free all 1205 * target struct and report loosage to upper layer. 1206 * As the upper layer may requeue immediatly we have to first store 1207 * all active commands in a temporary queue. 1208 */ 1209 void 1210 siop_handle_reset(sc) 1211 struct siop_softc *sc; 1212 { 1213 struct cmd_list reset_list; 1214 struct siop_cmd *siop_cmd, *next_siop_cmd; 1215 struct siop_lun *siop_lun; 1216 int target, lun; 1217 /* 1218 * scsi bus reset. reset the chip and restart 1219 * the queue. Need to clean up all active commands 1220 */ 1221 printf("%s: scsi bus reset\n", sc->sc_dev.dv_xname); 1222 /* stop, reset and restart the chip */ 1223 siop_reset(sc); 1224 TAILQ_INIT(&reset_list); 1225 /* find all active commands */ 1226 for (target = 0; target <= sc->sc_link.scsipi_scsi.max_target; 1227 target++) { 1228 if (sc->targets[target] == NULL) 1229 continue; 1230 for (lun = 0; lun < 8; lun++) { 1231 siop_lun = &(sc->targets[target]->siop_lun[lun]); 1232 if (siop_lun == NULL) 1233 continue; 1234 siop_cmd = siop_lun->active; 1235 if (siop_cmd == NULL) 1236 continue; 1237 printf("cmd %p (target %d:%d) in reset list\n", 1238 siop_cmd, target, lun); 1239 TAILQ_INSERT_TAIL(&reset_list, siop_cmd, next); 1240 siop_lun->active = NULL; 1241 } 1242 sc->targets[target]->status = TARST_ASYNC; 1243 sc->targets[target]->flags &= ~TARF_ISWIDE; 1244 } 1245 for (siop_cmd = TAILQ_FIRST(&sc->ready_list); siop_cmd != NULL; 1246 siop_cmd = next_siop_cmd) { 1247 next_siop_cmd = TAILQ_NEXT(siop_cmd, next); 1248 if (siop_cmd->status != CMDST_SENSE) 1249 continue; 1250 printf("cmd %p (target %d:%d) in reset list (sense)\n", 1251 siop_cmd, siop_cmd->xs->sc_link->scsipi_scsi.target, 1252 siop_cmd->xs->sc_link->scsipi_scsi.lun); 1253 TAILQ_REMOVE(&sc->ready_list, siop_cmd, next); 1254 TAILQ_INSERT_TAIL(&reset_list, siop_cmd, next); 1255 } 1256 1257 for (siop_cmd = TAILQ_FIRST(&reset_list); siop_cmd != NULL; 1258 siop_cmd = next_siop_cmd) { 1259 next_siop_cmd = TAILQ_NEXT(siop_cmd, next); 1260 siop_cmd->xs->error = (siop_cmd->flags & CMDFL_TIMEOUT) ? 1261 XS_TIMEOUT : XS_RESET; 1262 printf("cmd %p (status %d) about to be processed\n", siop_cmd, 1263 siop_cmd->status); 1264 if (siop_cmd->status == CMDST_SENSE || 1265 siop_cmd->status == CMDST_SENSE_ACTIVE) 1266 siop_cmd->status = CMDST_SENSE_DONE; 1267 else 1268 siop_cmd->status = CMDST_DONE; 1269 TAILQ_REMOVE(&reset_list, siop_cmd, next); 1270 siop_scsicmd_end(siop_cmd); 1271 TAILQ_INSERT_TAIL(&sc->free_list, siop_cmd, next); 1272 } 1273 } 1274 1275 int 1276 siop_scsicmd(xs) 1277 struct scsipi_xfer *xs; 1278 { 1279 struct siop_softc *sc = (struct siop_softc *)xs->sc_link->adapter_softc; 1280 struct siop_cmd *siop_cmd; 1281 int s, error, i; 1282 const int target = xs->sc_link->scsipi_scsi.target; 1283 const int lun = xs->sc_link->scsipi_scsi.lun; 1284 1285 s = splbio(); 1286 #ifdef DEBUG_SCHED 1287 printf("starting cmd for %d:%d\n", target, lun); 1288 #endif 1289 siop_cmd = TAILQ_FIRST(&sc->free_list); 1290 if (siop_cmd) { 1291 TAILQ_REMOVE(&sc->free_list, siop_cmd, next); 1292 } else { 1293 if (siop_morecbd(sc) == 0) { 1294 siop_cmd = TAILQ_FIRST(&sc->free_list); 1295 #ifdef DIAGNOSTIC 1296 if (siop_cmd == NULL) 1297 panic("siop_morecbd succeed and does nothing"); 1298 #endif 1299 TAILQ_REMOVE(&sc->free_list, siop_cmd, next); 1300 } 1301 } 1302 if (siop_cmd == NULL) { 1303 xs->error = XS_DRIVER_STUFFUP; 1304 splx(s); 1305 return(TRY_AGAIN_LATER); 1306 } 1307 #ifdef DIAGNOSTIC 1308 if (siop_cmd->status != CMDST_FREE) 1309 panic("siop_scsicmd: new cmd not free"); 1310 #endif 1311 if (sc->targets[target] == NULL) { 1312 #ifdef DEBUG 1313 printf("%s: alloc siop_target for target %d\n", 1314 sc->sc_dev.dv_xname, target); 1315 #endif 1316 sc->targets[target] = 1317 malloc(sizeof(struct siop_target), M_DEVBUF, M_NOWAIT); 1318 if (sc->targets[target] == NULL) { 1319 printf("%s: can't malloc memory for target %d\n", 1320 sc->sc_dev.dv_xname, target); 1321 xs->error = XS_DRIVER_STUFFUP; 1322 splx(s); 1323 return(TRY_AGAIN_LATER); 1324 } 1325 sc->targets[target]->status = TARST_PROBING; 1326 sc->targets[target]->flags = 0; 1327 sc->targets[target]->id = sc->clock_div << 24; /* scntl3 */ 1328 sc->targets[target]->id |= target << 16; /* id */ 1329 /* sc->targets[target]->id |= 0x0 << 8; scxfer is 0 */ 1330 1331 /* get a lun switch script */ 1332 sc->targets[target]->lunsw = siop_get_lunsw(sc); 1333 if (sc->targets[target]->lunsw == NULL) { 1334 printf("%s: can't alloc lunsw for target %d\n", 1335 sc->sc_dev.dv_xname, target); 1336 xs->error = XS_DRIVER_STUFFUP; 1337 splx(s); 1338 return(TRY_AGAIN_LATER); 1339 } 1340 siop_add_reselsw(sc, target); 1341 for (i=0; i < 8; i++) 1342 sc->targets[target]->siop_lun[i].active = NULL; 1343 } 1344 siop_cmd->siop_target = sc->targets[target]; 1345 siop_cmd->xs = xs; 1346 siop_cmd->flags = 0; 1347 siop_cmd->siop_tables.id = htole32(sc->targets[target]->id); 1348 siop_cmd->siop_tables.t_msgout.count= htole32(1); 1349 siop_cmd->siop_tables.t_msgout.addr = htole32(siop_cmd->dsa); 1350 memset(siop_cmd->siop_tables.msg_out, 0, 8); 1351 siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 1); 1352 if (sc->targets[target]->status == TARST_ASYNC) { 1353 if (sc->targets[target]->flags & TARF_WIDE) { 1354 sc->targets[target]->status = TARST_WIDE_NEG; 1355 siop_cmd->siop_tables.msg_out[1] = MSG_EXTENDED; 1356 siop_cmd->siop_tables.msg_out[2] = MSG_EXT_WDTR_LEN; 1357 siop_cmd->siop_tables.msg_out[3] = MSG_EXT_WDTR; 1358 siop_cmd->siop_tables.msg_out[4] = 1359 MSG_EXT_WDTR_BUS_16_BIT; 1360 siop_cmd->siop_tables.t_msgout.count= 1361 htole32(MSG_EXT_WDTR_LEN + 2 + 1); 1362 } else if (sc->targets[target]->flags & TARF_SYNC) { 1363 sc->targets[target]->status = TARST_SYNC_NEG; 1364 siop_cmd->siop_tables.msg_out[1] = MSG_EXTENDED; 1365 siop_cmd->siop_tables.msg_out[2] = MSG_EXT_SDTR_LEN; 1366 siop_cmd->siop_tables.msg_out[3] = MSG_EXT_SDTR; 1367 siop_cmd->siop_tables.msg_out[4] = sc->minsync; 1368 siop_cmd->siop_tables.msg_out[5] = sc->maxoff; 1369 siop_cmd->siop_tables.t_msgout.count= 1370 htole32(MSG_EXT_SDTR_LEN + 2 +1); 1371 } else { 1372 sc->targets[target]->status = TARST_OK; 1373 } 1374 } else if (sc->targets[target]->status == TARST_OK && 1375 (sc->targets[target]->flags & TARF_TAG)) { 1376 siop_cmd->siop_tables.msg_out[1] = MSG_SIMPLE_Q_TAG; 1377 siop_cmd->siop_tables.msg_out[2] = 0; 1378 siop_cmd->siop_tables.t_msgout.count = htole32(3); 1379 siop_cmd->flags |= CMDFL_TAG; 1380 } 1381 siop_cmd->siop_tables.status = htole32(0xff); /* set invalid status */ 1382 1383 /* load the DMA maps */ 1384 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_cmd, 1385 xs->cmd, xs->cmdlen, NULL, BUS_DMA_NOWAIT); 1386 if (error) { 1387 printf("%s: unable to load cmd DMA map: %d", 1388 sc->sc_dev.dv_xname, error); 1389 xs->error = XS_DRIVER_STUFFUP; 1390 splx(s); 1391 return(TRY_AGAIN_LATER); 1392 } 1393 siop_cmd->siop_tables.cmd.count = 1394 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 1395 siop_cmd->siop_tables.cmd.addr = 1396 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 1397 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 1398 error = bus_dmamap_load(sc->sc_dmat, siop_cmd->dmamap_data, 1399 xs->data, xs->datalen, NULL, BUS_DMA_NOWAIT); 1400 if (error) { 1401 printf("%s: unable to load cmd DMA map: %d", 1402 sc->sc_dev.dv_xname, error); 1403 xs->error = XS_DRIVER_STUFFUP; 1404 bus_dmamap_unload(sc->sc_dmat, siop_cmd->dmamap_cmd); 1405 splx(s); 1406 return(TRY_AGAIN_LATER); 1407 } 1408 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 1409 siop_cmd->siop_tables.data[i].count = 1410 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 1411 siop_cmd->siop_tables.data[i].addr = 1412 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 1413 } 1414 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_data, 0, 1415 siop_cmd->dmamap_data->dm_mapsize, 1416 (xs->xs_control & XS_CTL_DATA_IN) ? 1417 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1418 } 1419 bus_dmamap_sync(sc->sc_dmat, siop_cmd->dmamap_cmd, 0, 1420 siop_cmd->dmamap_cmd->dm_mapsize, BUS_DMASYNC_PREWRITE); 1421 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1422 1423 siop_cmd->status = CMDST_READY; 1424 TAILQ_INSERT_TAIL(&sc->ready_list, siop_cmd, next); 1425 siop_start(sc); 1426 if (xs->xs_control & XS_CTL_POLL) { 1427 /* poll for command completion */ 1428 while ((xs->xs_status & XS_STS_DONE) == 0) { 1429 delay(1000); 1430 siop_intr(sc); 1431 } 1432 splx(s); 1433 return (COMPLETE); 1434 } 1435 splx(s); 1436 return (SUCCESSFULLY_QUEUED); 1437 } 1438 1439 void 1440 siop_start(sc) 1441 struct siop_softc *sc; 1442 { 1443 struct siop_cmd *siop_cmd, *next_siop_cmd; 1444 struct siop_lun *siop_lun; 1445 u_int32_t *scr; 1446 u_int32_t dsa; 1447 int timeout; 1448 int target, lun, tag, slot; 1449 int newcmd = 0; 1450 1451 /* 1452 * first make sure to read valid data 1453 */ 1454 siop_sched_sync(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1455 1456 /* 1457 * The queue management here is a bit tricky: the script always looks 1458 * at the slot from first to last, so if we always use the first 1459 * free slot commands can stay at the tail of the queue ~forever. 1460 * The algorithm used here is to restart from the head when we know 1461 * that the queue is empty, and only add commands after the last one. 1462 * When we're at the end of the queue wait for the script to clear it. 1463 * The best thing to do here would be to implement a circular queue, 1464 * but using only 53c720 features this can be "interesting". 1465 * A mid-way solution could be to implement 2 queues and swap orders. 1466 */ 1467 slot = sc->sc_currschedslot; 1468 scr = &sc->sc_sched[(Ent_nextslot / 4) * slot]; 1469 /* 1470 * if relative addr of first jump is not 0 the slot is free. As this is 1471 * the last used slot, all previous slots are free, we can restart 1472 * from 0. 1473 */ 1474 if (scr[(Ent_slot / 4) + 1] != 0) { 1475 slot = sc->sc_currschedslot = 0; 1476 } else { 1477 slot++; 1478 } 1479 1480 for (siop_cmd = TAILQ_FIRST(&sc->ready_list); siop_cmd != NULL; 1481 siop_cmd = next_siop_cmd) { 1482 next_siop_cmd = TAILQ_NEXT(siop_cmd, next); 1483 #ifdef DIAGNOSTIC 1484 if (siop_cmd->status != CMDST_READY && 1485 siop_cmd->status != CMDST_SENSE) 1486 panic("siop: non-ready cmd in ready list"); 1487 #endif 1488 target = siop_cmd->xs->sc_link->scsipi_scsi.target; 1489 lun = siop_cmd->xs->sc_link->scsipi_scsi.lun; 1490 siop_lun = &(sc->targets[target]->siop_lun[lun]); 1491 if (siop_lun->active != NULL) 1492 continue; 1493 /* find a free scheduler slot and load it */ 1494 for (; slot < sc->sc_nschedslots; slot++) { 1495 scr = &sc->sc_sched[(Ent_nextslot / 4) * slot]; 1496 /* 1497 * if relative addr of first jump is not 0 the 1498 * slot is free 1499 */ 1500 if (scr[(Ent_slot / 4) + 1] != 0) 1501 break; 1502 } 1503 /* no more free slot, no need to continue */ 1504 if (slot == sc->sc_nschedslots) { 1505 printf("out of slot\n"); 1506 goto end; 1507 } 1508 #ifdef DEBUG_SCHED 1509 printf("using slot %d for DSA 0x%lx\n", slot, 1510 (u_long)siop_cmd->dsa); 1511 #endif 1512 /* note that we started a new command */ 1513 newcmd = 1; 1514 /* mark command as active */ 1515 if (siop_cmd->status == CMDST_READY) { 1516 siop_cmd->status = CMDST_ACTIVE; 1517 tag = (siop_cmd->flags & CMDFL_TAG) ? 1518 0x0 : 0xff; 1519 } else if (siop_cmd->status == CMDST_SENSE) { 1520 siop_cmd->status = CMDST_SENSE_ACTIVE; 1521 tag = 0xff; 1522 siop_cmd->siop_tables.t_msgout.count = htole32(1); 1523 } else 1524 panic("siop_start: bad status"); 1525 TAILQ_REMOVE(&sc->ready_list, siop_cmd, next); 1526 siop_lun->active = siop_cmd; 1527 /* patch scripts with DSA addr */ 1528 dsa = siop_cmd->dsa; 1529 /* first reselect switch */ 1530 siop_script_write(sc, siop_lun->reseloff + 1, 1531 dsa + sizeof(struct siop_xfer_common) + Ent_reload_dsa); 1532 /* then scheduler entry */ 1533 scr[E_slot_abs_loaddsa_Used[0]] = 1534 htole32(dsa + sizeof(struct siop_xfer_common)); 1535 #ifdef DEBUG_SCHED 1536 { int j; 1537 printf("dump of slot:\n"); 1538 for (j = 0; j < (sizeof(slot_script) / sizeof(slot_script[0])); 1539 j +=2) 1540 printf("0x%x 0x%x\n", scr[j], scr[j+1]); 1541 } 1542 #endif 1543 /* handle timeout */ 1544 if (siop_cmd->status == CMDST_ACTIVE) { 1545 if ((siop_cmd->xs->xs_control & 1546 XS_CTL_POLL) == 0) { 1547 /* start exire timer */ 1548 timeout = (u_int64_t) siop_cmd->xs->timeout * 1549 (u_int64_t)hz / 1000; 1550 if (timeout == 0) 1551 timeout = 1; 1552 callout_reset( &siop_cmd->xs->xs_callout, 1553 timeout, siop_timeout, siop_cmd); 1554 } 1555 } 1556 /* 1557 * Change jump offset so that this slot will be 1558 * handled 1559 */ 1560 scr[(Ent_slot / 4) + 1] = 0; 1561 sc->sc_currschedslot = slot; 1562 slot++; 1563 } 1564 end: 1565 /* if nothing changed no need to flush cache and wakeup script */ 1566 if (newcmd == 0) 1567 return; 1568 /* make sure SCRIPT processor will read valid data */ 1569 siop_sched_sync(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1570 siop_script_sync(sc, BUS_DMASYNC_PREWRITE); 1571 /* Signal script it has some work to do */ 1572 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SIGP); 1573 /* and wait for IRQ */ 1574 return; 1575 } 1576 1577 void 1578 siop_timeout(v) 1579 void *v; 1580 { 1581 struct siop_cmd *siop_cmd = v; 1582 struct siop_softc *sc = siop_cmd->siop_sc; 1583 int s; 1584 1585 scsi_print_addr(siop_cmd->xs->sc_link); 1586 printf("command timeout\n"); 1587 1588 s = splbio(); 1589 /* reset the scsi bus */ 1590 siop_resetbus(sc); 1591 1592 /* deactivate callout */ 1593 callout_stop(&siop_cmd->xs->xs_callout); 1594 /* mark command as being timed out; siop_intr will handle it */ 1595 /* 1596 * mark command has being timed out and just return; 1597 * the bus reset will generate an interrupt, 1598 * it will be handled in siop_intr() 1599 */ 1600 siop_cmd->flags |= CMDFL_TIMEOUT; 1601 splx(s); 1602 return; 1603 1604 } 1605 1606 void 1607 siop_dump_script(sc) 1608 struct siop_softc *sc; 1609 { 1610 int i; 1611 siop_sched_sync(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1612 for (i = 0; i < NBPG / 4; i += 2) { 1613 printf("0x%04x: 0x%08x 0x%08x", i * 4, 1614 le32toh(sc->sc_script[i]), le32toh(sc->sc_script[i+1])); 1615 if ((le32toh(sc->sc_script[i]) & 0xe0000000) == 0xc0000000) { 1616 i++; 1617 printf(" 0x%08x", le32toh(sc->sc_script[i+1])); 1618 } 1619 printf("\n"); 1620 } 1621 } 1622 1623 int 1624 siop_morecbd(sc) 1625 struct siop_softc *sc; 1626 { 1627 int error, i, j; 1628 bus_dma_segment_t seg; 1629 int rseg; 1630 struct siop_cbd *newcbd; 1631 bus_addr_t dsa; 1632 u_int32_t *scr; 1633 1634 /* allocate a new list head */ 1635 newcbd = malloc(sizeof(struct siop_cbd), M_DEVBUF, M_NOWAIT); 1636 if (newcbd == NULL) { 1637 printf("%s: can't allocate memory for command descriptors " 1638 "head\n", sc->sc_dev.dv_xname); 1639 return ENOMEM; 1640 } 1641 memset(newcbd, 0, sizeof(struct siop_cbd)); 1642 1643 /* allocate cmd list */ 1644 newcbd->cmds = 1645 malloc(sizeof(struct siop_cmd) * SIOP_NCMDPB, M_DEVBUF, M_NOWAIT); 1646 if (newcbd->cmds == NULL) { 1647 printf("%s: can't allocate memory for command descriptors\n", 1648 sc->sc_dev.dv_xname); 1649 error = ENOMEM; 1650 goto bad3; 1651 } 1652 memset(newcbd->cmds, 0, sizeof(struct siop_cmd) * SIOP_NCMDPB); 1653 error = bus_dmamem_alloc(sc->sc_dmat, NBPG, NBPG, 0, &seg, 1, &rseg, 1654 BUS_DMA_NOWAIT); 1655 if (error) { 1656 printf("%s: unable to allocate cbd DMA memory, error = %d\n", 1657 sc->sc_dev.dv_xname, error); 1658 goto bad2; 1659 } 1660 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, NBPG, 1661 (caddr_t *)&newcbd->xfers, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 1662 if (error) { 1663 printf("%s: unable to map cbd DMA memory, error = %d\n", 1664 sc->sc_dev.dv_xname, error); 1665 goto bad2; 1666 } 1667 error = bus_dmamap_create(sc->sc_dmat, NBPG, 1, NBPG, 0, 1668 BUS_DMA_NOWAIT, &newcbd->xferdma); 1669 if (error) { 1670 printf("%s: unable to create cbd DMA map, error = %d\n", 1671 sc->sc_dev.dv_xname, error); 1672 goto bad1; 1673 } 1674 error = bus_dmamap_load(sc->sc_dmat, newcbd->xferdma, newcbd->xfers, 1675 NBPG, NULL, BUS_DMA_NOWAIT); 1676 if (error) { 1677 printf("%s: unable to load cbd DMA map, error = %d\n", 1678 sc->sc_dev.dv_xname, error); 1679 goto bad0; 1680 } 1681 #ifdef DEBUG 1682 printf("newcdb PHY addr: 0x%lx\n", 1683 (unsigned long)newcbd->xferdma->dm_segs[0].ds_addr); 1684 #endif 1685 1686 for (i = 0; i < SIOP_NCMDPB; i++) { 1687 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, SIOP_NSG, 1688 MAXPHYS, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1689 &newcbd->cmds[i].dmamap_data); 1690 if (error) { 1691 printf("%s: unable to create data DMA map for cbd: " 1692 "error %d\n", 1693 sc->sc_dev.dv_xname, error); 1694 goto bad0; 1695 } 1696 error = bus_dmamap_create(sc->sc_dmat, 1697 sizeof(struct scsipi_generic), 1, 1698 sizeof(struct scsipi_generic), 0, 1699 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1700 &newcbd->cmds[i].dmamap_cmd); 1701 if (error) { 1702 printf("%s: unable to create cmd DMA map for cbd %d\n", 1703 sc->sc_dev.dv_xname, error); 1704 goto bad0; 1705 } 1706 newcbd->cmds[i].siop_sc = sc; 1707 newcbd->cmds[i].siop_cbdp = newcbd; 1708 newcbd->cmds[i].siop_xfer = &newcbd->xfers[i]; 1709 memset(newcbd->cmds[i].siop_xfer, 0, 1710 sizeof(struct siop_xfer)); 1711 newcbd->cmds[i].dsa = newcbd->xferdma->dm_segs[0].ds_addr + 1712 i * sizeof(struct siop_xfer); 1713 dsa = newcbd->cmds[i].dsa; 1714 newcbd->cmds[i].status = CMDST_FREE; 1715 newcbd->cmds[i].siop_tables.t_msgout.count= htole32(1); 1716 newcbd->cmds[i].siop_tables.t_msgout.addr = htole32(dsa); 1717 newcbd->cmds[i].siop_tables.t_msgin.count= htole32(1); 1718 newcbd->cmds[i].siop_tables.t_msgin.addr = htole32(dsa + 8); 1719 newcbd->cmds[i].siop_tables.t_extmsgin.count= htole32(2); 1720 newcbd->cmds[i].siop_tables.t_extmsgin.addr = htole32( 1721 le32toh(newcbd->cmds[i].siop_tables.t_msgin.addr) + 1); 1722 newcbd->cmds[i].siop_tables.t_msgtag.count= htole32(2); 1723 newcbd->cmds[i].siop_tables.t_msgtag.addr = htole32( 1724 le32toh(newcbd->cmds[i].siop_tables.t_msgin.addr) + 1); 1725 newcbd->cmds[i].siop_tables.t_status.count= htole32(1); 1726 newcbd->cmds[i].siop_tables.t_status.addr = htole32( 1727 le32toh(newcbd->cmds[i].siop_tables.t_msgin.addr) + 8); 1728 1729 /* The reselect script */ 1730 scr = &newcbd->cmds[i].siop_xfer->resel[0]; 1731 for (j = 0; j < sizeof(load_dsa) / sizeof(load_dsa[0]); j++) 1732 scr[j] = htole32(load_dsa[j]); 1733 /* 1734 * 0x78000000 is a 'move data8 to reg'. data8 is the second 1735 * octet, reg offset is the third. 1736 */ 1737 scr[Ent_rdsa0 / 4] = 1738 htole32(0x78100000 | ((dsa & 0x000000ff) << 8)); 1739 scr[Ent_rdsa1 / 4] = 1740 htole32(0x78110000 | ( dsa & 0x0000ff00 )); 1741 scr[Ent_rdsa2 / 4] = 1742 htole32(0x78120000 | ((dsa & 0x00ff0000) >> 8)); 1743 scr[Ent_rdsa3 / 4] = 1744 htole32(0x78130000 | ((dsa & 0xff000000) >> 16)); 1745 for (j = 0; 1746 j < (sizeof(E_resel_abs_reselected_Used) / 1747 sizeof(E_resel_abs_reselected_Used[0])); j++) 1748 scr[E_resel_abs_reselected_Used[j]] = 1749 htole32(sc->sc_scriptaddr + Ent_reselected); 1750 TAILQ_INSERT_TAIL(&sc->free_list, &newcbd->cmds[i], next); 1751 #ifdef DEBUG 1752 printf("tables[%d]: in=0x%x out=0x%x status=0x%x\n", i, 1753 le32toh(newcbd->cmds[i].siop_tables.t_msgin.addr), 1754 le32toh(newcbd->cmds[i].siop_tables.t_msgout.addr), 1755 le32toh(newcbd->cmds[i].siop_tables.t_status.addr)); 1756 for (j = 0; j < sizeof(load_dsa) / sizeof(load_dsa[0]); 1757 j += 2) { 1758 printf("0x%x 0x%x\n", scr[j], scr[j+1]); 1759 } 1760 #endif 1761 } 1762 TAILQ_INSERT_TAIL(&sc->cmds, newcbd, next); 1763 return 0; 1764 bad0: 1765 bus_dmamap_destroy(sc->sc_dmat, newcbd->xferdma); 1766 bad1: 1767 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 1768 bad2: 1769 free(newcbd->cmds, M_DEVBUF); 1770 bad3: 1771 free(newcbd, M_DEVBUF); 1772 return error; 1773 } 1774 1775 struct siop_lunsw * 1776 siop_get_lunsw(sc) 1777 struct siop_softc *sc; 1778 { 1779 struct siop_lunsw *lunsw; 1780 int i; 1781 1782 lunsw = TAILQ_FIRST(&sc->lunsw_list); 1783 if (lunsw != NULL) { 1784 #ifdef DEBUG 1785 printf("siop_get_lunsw got lunsw at offset %d\n", 1786 lunsw->lunsw_off); 1787 #endif 1788 TAILQ_REMOVE(&sc->lunsw_list, lunsw, next); 1789 return lunsw; 1790 } 1791 lunsw = malloc(sizeof(struct siop_lunsw), M_DEVBUF, M_NOWAIT); 1792 if (lunsw == NULL) 1793 return NULL; 1794 memset(lunsw, 0, sizeof(struct siop_lunsw)); 1795 #ifdef DEBUG 1796 printf("allocating lunsw at offset %d\n", sc->ram_free); 1797 #endif 1798 if (sc->features & SF_CHIP_RAM) { 1799 bus_space_write_region_4(sc->sc_ramt, sc->sc_ramh, 1800 sc->ram_free * 4, lun_switch, 1801 sizeof(lun_switch) / sizeof(lun_switch[0])); 1802 bus_space_write_4(sc->sc_ramt, sc->sc_ramh, 1803 (sc->ram_free + E_abs_lunsw_return_Used[0]) * 4, 1804 sc->sc_scriptaddr + Ent_lunsw_return); 1805 } else { 1806 for (i = 0; i < sizeof(lun_switch) / sizeof(lun_switch[0]); 1807 i++) 1808 sc->sc_script[sc->ram_free + i] = 1809 htole32(lun_switch[i]); 1810 sc->sc_script[sc->ram_free + E_abs_lunsw_return_Used[0]] = 1811 htole32(sc->sc_scriptaddr + Ent_lunsw_return); 1812 } 1813 lunsw->lunsw_off = sc->ram_free; 1814 sc->ram_free += sizeof(lun_switch) / sizeof(lun_switch[0]); 1815 if (sc->ram_free > 1024) 1816 printf("%s: ram_free (%d) > 1024\n", sc->sc_dev.dv_xname, 1817 sc->ram_free); 1818 siop_script_sync(sc, BUS_DMASYNC_PREWRITE); 1819 return lunsw; 1820 } 1821 1822 void 1823 siop_add_reselsw(sc, target) 1824 struct siop_softc *sc; 1825 int target; 1826 { 1827 int i; 1828 struct siop_lun *siop_lun; 1829 /* 1830 * add an entry to resel switch 1831 */ 1832 siop_script_sync(sc, BUS_DMASYNC_POSTWRITE); 1833 for (i = 0; i < 15; i++) { 1834 sc->targets[target]->reseloff = Ent_resel_targ0 / 4 + i * 2; 1835 if ((siop_script_read(sc, sc->targets[target]->reseloff) & 0xff) 1836 == 0xff) { /* it's free */ 1837 #ifdef DEBUG 1838 printf("siop: target %d slot %d offset %d\n", 1839 target, i, sc->targets[target]->reseloff); 1840 #endif 1841 /* JUMP abs_foo, IF target | 0x80; */ 1842 siop_script_write(sc, sc->targets[target]->reseloff, 1843 0x800c0080 | target); 1844 siop_script_write(sc, sc->targets[target]->reseloff + 1, 1845 sc->sc_scriptaddr + 1846 sc->targets[target]->lunsw->lunsw_off * 4 + 1847 Ent_lun_switch_entry); 1848 break; 1849 } 1850 } 1851 if (i == 15) /* no free slot, shouldn't happen */ 1852 panic("siop: resel switch full"); 1853 1854 for (i = 0; i < 8; i++) { 1855 siop_lun = &(sc->targets[target]->siop_lun[i]); 1856 siop_lun->reseloff = 1857 sc->targets[target]->lunsw->lunsw_off + 1858 (Ent_resel_lun0 / 4) + (i * 2); 1859 } 1860 siop_update_scntl3(sc, sc->targets[target]); 1861 siop_script_sync(sc, BUS_DMASYNC_PREWRITE); 1862 } 1863 1864 void 1865 siop_update_scntl3(sc, siop_target) 1866 struct siop_softc *sc; 1867 struct siop_target *siop_target; 1868 { 1869 /* MOVE target->id >> 24 TO SCNTL3 */ 1870 siop_script_write(sc, 1871 siop_target->lunsw->lunsw_off + (Ent_restore_scntl3 / 4), 1872 0x78030000 | ((siop_target->id >> 16) & 0x0000ff00)); 1873 /* MOVE target->id >> 8 TO SXFER */ 1874 siop_script_write(sc, 1875 siop_target->lunsw->lunsw_off + (Ent_restore_scntl3 / 4) + 2, 1876 0x78050000 | (siop_target->id & 0x0000ff00)); 1877 siop_script_sync(sc, BUS_DMASYNC_PREWRITE); 1878 } 1879 1880 #ifdef SIOP_STATS 1881 void 1882 siop_printstats() 1883 { 1884 printf("siop_stat_intr %d\n", siop_stat_intr); 1885 printf("siop_stat_intr_shortxfer %d\n", siop_stat_intr_shortxfer); 1886 printf("siop_stat_intr_xferdisc %d\n", siop_stat_intr_xferdisc); 1887 printf("siop_stat_intr_sdp %d\n", siop_stat_intr_sdp); 1888 printf("siop_stat_intr_done %d\n", siop_stat_intr_done); 1889 } 1890 #endif 1891
Indexes created Thu Sep 25 16:09:42 GMT 2025