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siop_common.c revision 1.2.2.1
      1  1.2.2.1  minoura /*	$NetBSD: siop_common.c,v 1.2.2.1 2000/06/22 17:06:55 minoura Exp $	*/
      2      1.1   bouyer 
      3      1.1   bouyer /*
      4      1.1   bouyer  * Copyright (c) 2000 Manuel Bouyer.
      5      1.1   bouyer  *
      6      1.1   bouyer  * Redistribution and use in source and binary forms, with or without
      7      1.1   bouyer  * modification, are permitted provided that the following conditions
      8      1.1   bouyer  * are met:
      9      1.1   bouyer  * 1. Redistributions of source code must retain the above copyright
     10      1.1   bouyer  *    notice, this list of conditions and the following disclaimer.
     11      1.1   bouyer  * 2. Redistributions in binary form must reproduce the above copyright
     12      1.1   bouyer  *    notice, this list of conditions and the following disclaimer in the
     13      1.1   bouyer  *    documentation and/or other materials provided with the distribution.
     14      1.1   bouyer  * 3. All advertising materials mentioning features or use of this software
     15      1.1   bouyer  *    must display the following acknowledgement:
     16      1.1   bouyer  *	This product includes software developed by Manuel Bouyer
     17      1.1   bouyer  * 4. The name of the author may not be used to endorse or promote products
     18      1.1   bouyer  *    derived from this software without specific prior written permission.
     19      1.1   bouyer  *
     20      1.1   bouyer  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21      1.1   bouyer  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22      1.1   bouyer  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23      1.1   bouyer  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24      1.1   bouyer  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25      1.1   bouyer  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26      1.1   bouyer  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27      1.1   bouyer  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28      1.1   bouyer  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29      1.1   bouyer  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30      1.1   bouyer  *
     31      1.1   bouyer  */
     32      1.1   bouyer 
     33      1.1   bouyer /* SYM53c7/8xx PCI-SCSI I/O Processors driver */
     34      1.1   bouyer 
     35      1.1   bouyer #include <sys/param.h>
     36      1.1   bouyer #include <sys/systm.h>
     37      1.1   bouyer #include <sys/device.h>
     38      1.1   bouyer #include <sys/malloc.h>
     39      1.1   bouyer #include <sys/buf.h>
     40      1.1   bouyer #include <sys/kernel.h>
     41      1.1   bouyer #include <sys/scsiio.h>
     42      1.1   bouyer 
     43      1.1   bouyer #include <machine/endian.h>
     44      1.1   bouyer #include <machine/bus.h>
     45      1.1   bouyer 
     46      1.1   bouyer #include <vm/vm.h>
     47      1.1   bouyer #include <vm/vm_param.h>
     48      1.1   bouyer #include <vm/vm_kern.h>
     49      1.1   bouyer 
     50      1.1   bouyer #include <dev/scsipi/scsi_all.h>
     51      1.1   bouyer #include <dev/scsipi/scsi_message.h>
     52      1.1   bouyer #include <dev/scsipi/scsipi_all.h>
     53      1.1   bouyer 
     54      1.1   bouyer #include <dev/scsipi/scsiconf.h>
     55      1.1   bouyer 
     56      1.1   bouyer #include <dev/ic/siopreg.h>
     57      1.1   bouyer #include <dev/ic/siopvar.h>
     58      1.1   bouyer #include <dev/ic/siopvar_common.h>
     59      1.1   bouyer 
     60      1.2   bouyer #undef DEBUG
     61      1.2   bouyer #undef DEBUG_DR
     62      1.1   bouyer 
     63      1.1   bouyer void
     64      1.1   bouyer siop_common_reset(sc)
     65      1.1   bouyer 	struct siop_softc *sc;
     66      1.1   bouyer {
     67      1.1   bouyer 	u_int32_t stest3;
     68      1.1   bouyer 
     69      1.1   bouyer 	/* reset the chip */
     70      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST);
     71      1.1   bouyer 	delay(1000);
     72      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0);
     73      1.1   bouyer 
     74      1.1   bouyer 	/* init registers */
     75      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0,
     76      1.1   bouyer 	    SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP);
     77      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0);
     78      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div);
     79      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 0);
     80      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff);
     81      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0,
     82      1.1   bouyer 	    0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL));
     83      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1,
     84      1.1   bouyer 	    0xff & ~(SIEN1_HTH | SIEN1_GEN));
     85      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0);
     86      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE);
     87      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0,
     88      1.1   bouyer 	    (0xb << STIME0_SEL_SHIFT));
     89      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID,
     90      1.1   bouyer 	    sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE);
     91      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0,
     92      1.1   bouyer 	    1 << sc->sc_link.scsipi_scsi.adapter_target);
     93      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
     94      1.1   bouyer 	    (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM);
     95      1.1   bouyer 
     96      1.1   bouyer 	/* enable clock doubler or quadruler if appropriate */
     97      1.1   bouyer 	if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) {
     98      1.1   bouyer 		stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3);
     99      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
    100      1.1   bouyer 		    STEST1_DBLEN);
    101      1.1   bouyer 		if (sc->features & SF_CHIP_QUAD) {
    102      1.1   bouyer 			/* wait for PPL to lock */
    103      1.1   bouyer 			while ((bus_space_read_1(sc->sc_rt, sc->sc_rh,
    104      1.1   bouyer 			    SIOP_STEST4) & STEST4_LOCK) == 0)
    105      1.1   bouyer 				delay(10);
    106      1.1   bouyer 		} else {
    107      1.1   bouyer 			/* data sheet says 20us - more won't hurt */
    108      1.1   bouyer 			delay(100);
    109      1.1   bouyer 		}
    110      1.1   bouyer 		/* halt scsi clock, select doubler/quad, restart clock */
    111      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3,
    112      1.1   bouyer 		    stest3 | STEST3_HSC);
    113      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
    114      1.1   bouyer 		    STEST1_DBLEN | STEST1_DBLSEL);
    115      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3);
    116      1.1   bouyer 	} else {
    117      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0);
    118      1.1   bouyer 	}
    119      1.1   bouyer 	if (sc->features & SF_CHIP_FIFO)
    120      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5,
    121      1.1   bouyer 		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) |
    122      1.1   bouyer 		    CTEST5_DFS);
    123      1.1   bouyer 
    124      1.1   bouyer 	sc->sc_reset(sc);
    125      1.1   bouyer }
    126      1.1   bouyer 
    127      1.1   bouyer int
    128      1.1   bouyer siop_wdtr_neg(siop_cmd)
    129      1.1   bouyer 	struct siop_cmd *siop_cmd;
    130      1.1   bouyer {
    131      1.1   bouyer 	struct siop_softc *sc = siop_cmd->siop_target->siop_sc;
    132      1.1   bouyer 	struct siop_target *siop_target = siop_cmd->siop_target;
    133      1.1   bouyer 	int target = siop_cmd->xs->sc_link->scsipi_scsi.target;
    134      1.1   bouyer 
    135      1.1   bouyer 	if (siop_target->status == TARST_WIDE_NEG) {
    136      1.1   bouyer 		/* we initiated wide negotiation */
    137      1.1   bouyer 		switch (siop_cmd->siop_table->msg_in[3]) {
    138      1.1   bouyer 		case MSG_EXT_WDTR_BUS_8_BIT:
    139      1.1   bouyer 			printf("%s: target %d using 8bit transfers\n",
    140      1.1   bouyer 			    sc->sc_dev.dv_xname, target);
    141      1.1   bouyer 			siop_target->flags &= ~SF_BUS_WIDE;
    142      1.1   bouyer 			sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
    143      1.1   bouyer 			break;
    144      1.1   bouyer 		case MSG_EXT_WDTR_BUS_16_BIT:
    145      1.1   bouyer 			if (sc->features & SF_BUS_WIDE) {
    146      1.1   bouyer 				printf("%s: target %d using 16bit transfers\n",
    147      1.1   bouyer 				    sc->sc_dev.dv_xname, target);
    148      1.1   bouyer 				siop_target->flags |= TARF_WIDE;
    149      1.1   bouyer 				sc->targets[target]->id |= (SCNTL3_EWS << 24);
    150      1.1   bouyer 				break;
    151      1.1   bouyer 			}
    152      1.1   bouyer 		/* FALLTHROUH */
    153      1.1   bouyer 		default:
    154      1.1   bouyer 			/*
    155      1.1   bouyer  			 * hum, we got more than what we can handle, shoudn't
    156      1.1   bouyer 			 * happen. Reject, and stay async
    157      1.1   bouyer 			 */
    158      1.1   bouyer 			siop_target->flags &= ~TARF_WIDE;
    159      1.1   bouyer 			siop_target->status = TARST_OK;
    160      1.1   bouyer 			printf("%s: rejecting invalid wide negotiation from "
    161      1.1   bouyer 			    "target %d (%d)\n", sc->sc_dev.dv_xname, target,
    162      1.1   bouyer 			    siop_cmd->siop_table->msg_in[3]);
    163      1.1   bouyer 			siop_cmd->siop_table->t_msgout.count= htole32(1);
    164      1.1   bouyer 			siop_cmd->siop_table->t_msgout.addr =
    165      1.1   bouyer 			    htole32(siop_cmd->dsa);
    166      1.1   bouyer 			siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT;
    167      1.1   bouyer 			return SIOP_NEG_MSGOUT;
    168      1.1   bouyer 		}
    169      1.1   bouyer 		siop_cmd->siop_table->id =
    170      1.1   bouyer 		    htole32(sc->targets[target]->id);
    171      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh,
    172      1.1   bouyer 		    SIOP_SCNTL3,
    173      1.1   bouyer 		    (sc->targets[target]->id >> 24) & 0xff);
    174      1.1   bouyer 		/* we now need to do sync */
    175      1.1   bouyer 		siop_target->status = TARST_SYNC_NEG;
    176      1.1   bouyer 		siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
    177      1.1   bouyer 		siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN;
    178      1.1   bouyer 		siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR;
    179      1.1   bouyer 		siop_cmd->siop_table->msg_out[3] = sc->minsync;
    180      1.1   bouyer 		siop_cmd->siop_table->msg_out[4] = sc->maxoff;
    181      1.1   bouyer 		siop_cmd->siop_table->t_msgout.count =
    182      1.1   bouyer 		    htole32(MSG_EXT_SDTR_LEN + 2);
    183      1.1   bouyer 		siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa);
    184      1.1   bouyer 		return SIOP_NEG_MSGOUT;
    185      1.1   bouyer 	} else {
    186      1.1   bouyer 		/* target initiated wide negotiation */
    187      1.1   bouyer 		if (siop_cmd->siop_table->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT
    188      1.1   bouyer 		    && (sc->features & SF_BUS_WIDE)) {
    189      1.1   bouyer 			printf("%s: target %d using 16bit transfers\n",
    190      1.1   bouyer 			    sc->sc_dev.dv_xname, target);
    191      1.1   bouyer 			siop_target->flags |= TARF_WIDE;
    192      1.1   bouyer 			sc->targets[target]->id |= SCNTL3_EWS << 24;
    193      1.1   bouyer 			siop_cmd->siop_table->msg_out[3] =
    194      1.1   bouyer 			    MSG_EXT_WDTR_BUS_16_BIT;
    195      1.1   bouyer 		} else {
    196      1.1   bouyer 			printf("%s: target %d using 8bit transfers\n",
    197      1.1   bouyer 			    sc->sc_dev.dv_xname, target);
    198      1.1   bouyer 			siop_target->flags &= ~SF_BUS_WIDE;
    199      1.1   bouyer 			sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
    200      1.1   bouyer 			siop_cmd->siop_table->msg_out[3] =
    201      1.1   bouyer 			    MSG_EXT_WDTR_BUS_8_BIT;
    202      1.1   bouyer 		}
    203      1.1   bouyer 		siop_cmd->siop_table->id =
    204      1.1   bouyer 		    htole32(sc->targets[target]->id);
    205      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
    206      1.1   bouyer 		    (sc->targets[target]->id >> 24) & 0xff);
    207      1.1   bouyer 		/*
    208      1.1   bouyer 		 * we did reset wide parameters, so fall back to async,
    209      1.1   bouyer 		 * but don't shedule a sync neg, target should initiate it
    210      1.1   bouyer 		 */
    211      1.1   bouyer 		siop_target->status = TARST_OK;
    212      1.1   bouyer 		siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
    213      1.1   bouyer 		siop_cmd->siop_table->msg_out[1] = MSG_EXT_WDTR_LEN;
    214      1.1   bouyer 		siop_cmd->siop_table->msg_out[2] = MSG_EXT_WDTR;
    215      1.1   bouyer 		siop_cmd->siop_table->t_msgout.count=
    216      1.1   bouyer 		    htole32(MSG_EXT_WDTR_LEN + 2);
    217      1.1   bouyer 		siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa);
    218      1.1   bouyer 		return SIOP_NEG_MSGOUT;
    219      1.1   bouyer 	}
    220      1.1   bouyer }
    221      1.1   bouyer 
    222      1.1   bouyer int
    223      1.1   bouyer siop_sdtr_neg(siop_cmd)
    224      1.1   bouyer 	struct siop_cmd *siop_cmd;
    225      1.1   bouyer {
    226      1.1   bouyer 	struct siop_softc *sc = siop_cmd->siop_target->siop_sc;
    227      1.1   bouyer 	struct siop_target *siop_target = siop_cmd->siop_target;
    228      1.1   bouyer 	int target = siop_cmd->xs->sc_link->scsipi_scsi.target;
    229      1.1   bouyer 	int sync, offset, i;
    230      1.1   bouyer 	int send_msgout = 0;
    231      1.1   bouyer 
    232      1.1   bouyer 	sync = siop_cmd->siop_table->msg_in[3];
    233      1.1   bouyer 	offset = siop_cmd->siop_table->msg_in[4];
    234      1.1   bouyer 
    235      1.1   bouyer 	if (siop_target->status == TARST_SYNC_NEG) {
    236      1.1   bouyer 		/* we initiated sync negotiation */
    237      1.1   bouyer 		siop_target->status = TARST_OK;
    238      1.1   bouyer #ifdef DEBUG
    239      1.1   bouyer 		printf("sdtr: sync %d offset %d\n", sync, offset);
    240      1.1   bouyer #endif
    241      1.1   bouyer 		if (offset > sc->maxoff || sync < sc->minsync ||
    242      1.1   bouyer 			sync > sc->maxsync)
    243      1.1   bouyer 			goto reject;
    244      1.1   bouyer 		for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
    245      1.1   bouyer 		    i++) {
    246      1.1   bouyer 			if (sc->clock_period != scf_period[i].clock)
    247      1.1   bouyer 				continue;
    248      1.1   bouyer 			if (scf_period[i].period == sync) {
    249      1.1   bouyer 				/* ok, found it. we now are sync. */
    250      1.1   bouyer 				printf("%s: target %d now synchronous at "
    251      1.1   bouyer 				    "%sMhz, offset %d\n", sc->sc_dev.dv_xname,
    252      1.1   bouyer 				    target, scf_period[i].rate, offset);
    253      1.1   bouyer 				sc->targets[target]->id &=
    254      1.1   bouyer 				    ~(SCNTL3_SCF_MASK << 24);
    255      1.1   bouyer 				sc->targets[target]->id |= scf_period[i].scf
    256      1.1   bouyer 				    << (24 + SCNTL3_SCF_SHIFT);
    257      1.1   bouyer 				if (sync < 25) /* Ultra */
    258      1.1   bouyer 					sc->targets[target]->id |=
    259      1.1   bouyer 					    SCNTL3_ULTRA << 24;
    260      1.1   bouyer 				else
    261      1.1   bouyer 					sc->targets[target]->id &=
    262      1.1   bouyer 					    ~(SCNTL3_ULTRA << 24);
    263      1.1   bouyer 				sc->targets[target]->id &=
    264      1.1   bouyer 				    ~(SCXFER_MO_MASK << 8);
    265      1.1   bouyer 				sc->targets[target]->id |=
    266      1.1   bouyer 				    (offset & SCXFER_MO_MASK) << 8;
    267      1.1   bouyer 				goto end;
    268      1.1   bouyer 			}
    269      1.1   bouyer 		}
    270      1.1   bouyer 		/*
    271      1.1   bouyer 		 * we didn't find it in our table, do async and send reject
    272      1.1   bouyer 		 * msg
    273      1.1   bouyer 		 */
    274      1.1   bouyer reject:
    275      1.1   bouyer 		send_msgout = 1;
    276      1.1   bouyer 		siop_cmd->siop_table->t_msgout.count= htole32(1);
    277      1.1   bouyer 		siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT;
    278      1.1   bouyer 		printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname,
    279      1.1   bouyer 		    target);
    280      1.1   bouyer 		sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
    281      1.1   bouyer 		sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
    282      1.1   bouyer 		sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8);
    283      1.1   bouyer 	} else { /* target initiated sync neg */
    284      1.1   bouyer #ifdef DEBUG
    285      1.1   bouyer 		printf("sdtr (target): sync %d offset %d\n", sync, offset);
    286      1.1   bouyer #endif
    287      1.1   bouyer 		if (offset == 0 || sync > sc->maxsync) { /* async */
    288      1.1   bouyer 			goto async;
    289      1.1   bouyer 		}
    290      1.1   bouyer 		if (offset > sc->maxoff)
    291      1.1   bouyer 			offset = sc->maxoff;
    292      1.1   bouyer 		if (sync < sc->minsync)
    293      1.1   bouyer 			sync = sc->minsync;
    294      1.1   bouyer 		/* look for sync period */
    295      1.1   bouyer 		for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
    296      1.1   bouyer 		    i++) {
    297      1.1   bouyer 			if (sc->clock_period != scf_period[i].clock)
    298      1.1   bouyer 				continue;
    299      1.1   bouyer 			if (scf_period[i].period == sync) {
    300      1.1   bouyer 				/* ok, found it. we now are sync. */
    301      1.1   bouyer 				printf("%s: target %d now synchronous at "
    302      1.1   bouyer 				    "%sMhz, offset %d\n", sc->sc_dev.dv_xname,
    303      1.1   bouyer 				    target, scf_period[i].rate, offset);
    304      1.1   bouyer 				sc->targets[target]->id &=
    305      1.1   bouyer 				    ~(SCNTL3_SCF_MASK << 24);
    306      1.1   bouyer 				sc->targets[target]->id |= scf_period[i].scf
    307      1.1   bouyer 				    << (24 + SCNTL3_SCF_SHIFT);
    308      1.1   bouyer 				if (sync < 25) /* Ultra */
    309      1.1   bouyer 					sc->targets[target]->id |=
    310      1.1   bouyer 					    SCNTL3_ULTRA << 24;
    311      1.1   bouyer 				else
    312      1.1   bouyer 					sc->targets[target]->id &=
    313      1.1   bouyer 					    ~(SCNTL3_ULTRA << 24);
    314      1.1   bouyer 				sc->targets[target]->id &=
    315      1.1   bouyer 				    ~(SCXFER_MO_MASK << 8);
    316      1.1   bouyer 				sc->targets[target]->id |=
    317      1.1   bouyer 				    (offset & SCXFER_MO_MASK) << 8;
    318      1.1   bouyer 				siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
    319      1.1   bouyer 				siop_cmd->siop_table->msg_out[1] =
    320      1.1   bouyer 				    MSG_EXT_SDTR_LEN;
    321      1.1   bouyer 				siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR;
    322      1.1   bouyer 				siop_cmd->siop_table->msg_out[3] = sync;
    323      1.1   bouyer 				siop_cmd->siop_table->msg_out[4] = offset;
    324      1.1   bouyer 				siop_cmd->siop_table->t_msgout.count=
    325      1.1   bouyer 				    htole32(MSG_EXT_SDTR_LEN + 2);
    326      1.1   bouyer 				send_msgout = 1;
    327      1.1   bouyer 				goto end;
    328      1.1   bouyer 			}
    329      1.1   bouyer 		}
    330      1.1   bouyer async:
    331      1.1   bouyer 		printf("%s: target %d asynchronous\n",
    332      1.1   bouyer 		    sc->sc_dev.dv_xname, target);
    333      1.1   bouyer 		sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
    334      1.1   bouyer 		sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
    335      1.1   bouyer 		sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8);
    336      1.1   bouyer 		siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
    337      1.1   bouyer 		siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN;
    338      1.1   bouyer 		siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR;
    339      1.1   bouyer 		siop_cmd->siop_table->msg_out[3] = 0;
    340      1.1   bouyer 		siop_cmd->siop_table->msg_out[4] = 0;
    341      1.1   bouyer 		siop_cmd->siop_table->t_msgout.count=
    342      1.1   bouyer 		    htole32(MSG_EXT_SDTR_LEN + 2);
    343      1.1   bouyer 		send_msgout = 1;
    344      1.1   bouyer 	}
    345      1.1   bouyer end:
    346      1.1   bouyer #ifdef DEBUG
    347      1.1   bouyer 	printf("id now 0x%x\n", sc->targets[target]->id);
    348      1.1   bouyer #endif
    349      1.1   bouyer 	siop_cmd->siop_table->id = htole32(sc->targets[target]->id);
    350      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
    351      1.1   bouyer 	    (sc->targets[target]->id >> 24) & 0xff);
    352      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER,
    353      1.1   bouyer 	    (sc->targets[target]->id >> 8) & 0xff);
    354      1.1   bouyer 	if (send_msgout) {
    355      1.1   bouyer 		siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa);
    356      1.1   bouyer 		return SIOP_NEG_MSGOUT;
    357      1.1   bouyer 	} else {
    358      1.1   bouyer 		return SIOP_NEG_ACK;
    359      1.1   bouyer 	}
    360      1.1   bouyer }
    361      1.1   bouyer 
    362      1.1   bouyer void
    363      1.1   bouyer siop_minphys(bp)
    364      1.1   bouyer 	struct buf *bp;
    365      1.1   bouyer {
    366      1.1   bouyer 	minphys(bp);
    367      1.1   bouyer }
    368      1.1   bouyer 
    369      1.1   bouyer int
    370      1.1   bouyer siop_ioctl(link, cmd, arg, flag, p)
    371      1.1   bouyer 	struct scsipi_link *link;
    372      1.1   bouyer 	u_long cmd;
    373      1.1   bouyer 	caddr_t arg;
    374      1.1   bouyer 	int flag;
    375      1.1   bouyer 	struct proc *p;
    376      1.1   bouyer {
    377      1.1   bouyer 	struct siop_softc *sc = link->adapter_softc;
    378      1.1   bouyer 	u_int8_t scntl1;
    379      1.1   bouyer 	int s;
    380      1.1   bouyer 
    381      1.1   bouyer 	switch (cmd) {
    382      1.1   bouyer 	case SCBUSIORESET:
    383      1.1   bouyer 		s = splbio();
    384      1.1   bouyer 		scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1);
    385      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1,
    386      1.1   bouyer 		    scntl1 | SCNTL1_RST);
    387      1.1   bouyer 		/* minimum 25 us, more time won't hurt */
    388      1.1   bouyer 		delay(100);
    389      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1);
    390      1.1   bouyer 		splx(s);
    391      1.1   bouyer 		return (0);
    392      1.1   bouyer 	default:
    393      1.1   bouyer 		return (ENOTTY);
    394      1.1   bouyer 	}
    395      1.1   bouyer }
    396      1.1   bouyer 
    397      1.1   bouyer void
    398      1.1   bouyer siop_sdp(siop_cmd)
    399      1.1   bouyer 	struct siop_cmd *siop_cmd;
    400      1.1   bouyer {
    401      1.1   bouyer 	/* save data pointer. Handle async only for now */
    402      1.1   bouyer 	int offset, dbc, sstat;
    403      1.1   bouyer 	struct siop_softc *sc = siop_cmd->siop_target->siop_sc;
    404      1.1   bouyer 	scr_table_t *table; /* table to patch */
    405      1.1   bouyer 
    406      1.1   bouyer 	if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN))
    407      1.1   bouyer 	    == 0)
    408      1.1   bouyer 	    return; /* no data pointers to save */
    409      1.1   bouyer 	offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1);
    410      1.1   bouyer 	if (offset >= SIOP_NSG) {
    411      1.1   bouyer 		printf("%s: bad offset in siop_sdp (%d)\n",
    412      1.1   bouyer 		    sc->sc_dev.dv_xname, offset);
    413      1.1   bouyer 		return;
    414      1.1   bouyer 	}
    415      1.1   bouyer 	table = &siop_cmd->siop_table->data[offset];
    416      1.1   bouyer #ifdef DEBUG_DR
    417      1.1   bouyer 	printf("sdp: offset %d count=%d addr=0x%x ", offset,
    418      1.1   bouyer 	    table->count, table->addr);
    419      1.1   bouyer #endif
    420      1.1   bouyer 	dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff;
    421      1.1   bouyer 	if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) {
    422      1.1   bouyer 		/* need to account stale data in FIFO */
    423      1.1   bouyer 		int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO);
    424      1.1   bouyer 		if (sc->features & SF_CHIP_FIFO) {
    425      1.1   bouyer 			dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh,
    426      1.1   bouyer 			    SIOP_CTEST5) & CTEST5_BOMASK) << 8;
    427      1.1   bouyer 			dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff;
    428      1.1   bouyer 		} else {
    429      1.1   bouyer 			dbc += (dfifo - (dbc & 0x7f)) & 0x7f;
    430      1.1   bouyer 		}
    431      1.1   bouyer 		sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0);
    432      1.1   bouyer 		if (sstat & SSTAT0_OLF)
    433      1.1   bouyer 			dbc++;
    434      1.1   bouyer 		if (sstat & SSTAT0_ORF)
    435      1.1   bouyer 			dbc++;
    436      1.1   bouyer 		if (siop_cmd->siop_target->flags & TARF_WIDE) {
    437      1.1   bouyer 			sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh,
    438      1.1   bouyer 			    SIOP_SSTAT2);
    439      1.1   bouyer 			if (sstat & SSTAT2_OLF1)
    440      1.1   bouyer 				dbc++;
    441      1.1   bouyer 			if (sstat & SSTAT2_ORF1)
    442      1.1   bouyer 				dbc++;
    443      1.1   bouyer 		}
    444      1.1   bouyer 		/* clear the FIFO */
    445      1.1   bouyer 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
    446      1.1   bouyer 		    bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
    447      1.1   bouyer 		    CTEST3_CLF);
    448      1.1   bouyer 	}
    449      1.1   bouyer 	table->addr =
    450      1.1   bouyer 	    htole32(le32toh(table->addr) + le32toh(table->count) - dbc);
    451      1.1   bouyer 	table->count = htole32(dbc);
    452      1.1   bouyer #ifdef DEBUG_DR
    453      1.1   bouyer 	printf("now count=%d addr=0x%x\n", table->count, table->addr);
    454      1.1   bouyer #endif
    455      1.1   bouyer }
    456      1.1   bouyer 
    457      1.1   bouyer void
    458      1.1   bouyer siop_clearfifo(sc)
    459      1.1   bouyer 	struct siop_softc *sc;
    460      1.1   bouyer {
    461      1.1   bouyer 	int timeout = 0;
    462      1.1   bouyer 	int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3);
    463      1.1   bouyer 
    464      1.1   bouyer #ifdef DEBUG_INTR
    465      1.1   bouyer 	printf("DMA fifo not empty !\n");
    466      1.1   bouyer #endif
    467      1.1   bouyer 	bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
    468      1.1   bouyer 	    ctest3 | CTEST3_CLF);
    469      1.1   bouyer 	while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) &
    470      1.1   bouyer 	    CTEST3_CLF) != 0) {
    471      1.1   bouyer 		delay(1);
    472      1.1   bouyer 		if (++timeout > 1000) {
    473      1.1   bouyer 			printf("clear fifo failed\n");
    474      1.1   bouyer 			bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
    475      1.1   bouyer 			    bus_space_read_1(sc->sc_rt, sc->sc_rh,
    476      1.1   bouyer 			    SIOP_CTEST3) & ~CTEST3_CLF);
    477      1.1   bouyer 			return;
    478      1.1   bouyer 		}
    479      1.1   bouyer 	}
    480  1.2.2.1  minoura }
    481  1.2.2.1  minoura 
    482  1.2.2.1  minoura int
    483  1.2.2.1  minoura siop_modechange(sc)
    484  1.2.2.1  minoura 	struct siop_softc *sc;
    485  1.2.2.1  minoura {
    486  1.2.2.1  minoura 	int retry;
    487  1.2.2.1  minoura 	int sist0, sist1, stest2, stest4;
    488  1.2.2.1  minoura 	for (retry = 0; retry < 5; retry++) {
    489  1.2.2.1  minoura 		/*
    490  1.2.2.1  minoura 		 * datasheet says to wait 100ms and re-read SIST1,
    491  1.2.2.1  minoura 		 * to check that DIFFSENSE is srable.
    492  1.2.2.1  minoura 		 * We may delay() 5 times for  100ms at interrupt time;
    493  1.2.2.1  minoura 		 * hopefully this will not happen often.
    494  1.2.2.1  minoura 		 */
    495  1.2.2.1  minoura 		delay(100000);
    496  1.2.2.1  minoura 		sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0);
    497  1.2.2.1  minoura 		sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1);
    498  1.2.2.1  minoura 		if (sist1 & SIEN1_SBMC)
    499  1.2.2.1  minoura 			continue; /* we got an irq again */
    500  1.2.2.1  minoura 		stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) &
    501  1.2.2.1  minoura 		    STEST4_MODE_MASK;
    502  1.2.2.1  minoura 		stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2);
    503  1.2.2.1  minoura 		switch(stest4) {
    504  1.2.2.1  minoura 		case STEST4_MODE_DIF:
    505  1.2.2.1  minoura 			printf("%s: switching to differential mode\n",
    506  1.2.2.1  minoura 			    sc->sc_dev.dv_xname);
    507  1.2.2.1  minoura 			bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
    508  1.2.2.1  minoura 			    stest2 | STEST2_DIF);
    509  1.2.2.1  minoura 			break;
    510  1.2.2.1  minoura 		case STEST4_MODE_SE:
    511  1.2.2.1  minoura 			printf("%s: switching to single-ended mode\n",
    512  1.2.2.1  minoura 			    sc->sc_dev.dv_xname);
    513  1.2.2.1  minoura 			bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
    514  1.2.2.1  minoura 			    stest2 & ~STEST2_DIF);
    515  1.2.2.1  minoura 			break;
    516  1.2.2.1  minoura 		case STEST4_MODE_LVD:
    517  1.2.2.1  minoura 			printf("%s: switching to LVD mode\n",
    518  1.2.2.1  minoura 			    sc->sc_dev.dv_xname);
    519  1.2.2.1  minoura 			bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
    520  1.2.2.1  minoura 			    stest2 & ~STEST2_DIF);
    521  1.2.2.1  minoura 			break;
    522  1.2.2.1  minoura 		default:
    523  1.2.2.1  minoura 			printf("%s: invalid SCSI mode 0x%x\n",
    524  1.2.2.1  minoura 			    sc->sc_dev.dv_xname, stest4);
    525  1.2.2.1  minoura 			return 0;
    526  1.2.2.1  minoura 		}
    527  1.2.2.1  minoura 		bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0,
    528  1.2.2.1  minoura 		    stest4 >> 2);
    529  1.2.2.1  minoura 		return 1;
    530  1.2.2.1  minoura 	}
    531  1.2.2.1  minoura 	printf("%s: timeout waiting for DIFFSENSE to stabilise\n",
    532  1.2.2.1  minoura 	    sc->sc_dev.dv_xname);
    533  1.2.2.1  minoura 	return 0;
    534      1.1   bouyer }
    535