siop_common.c revision 1.3.2.1 1 1.3.2.1 bouyer /* $NetBSD: siop_common.c,v 1.3.2.1 2000/07/24 16:51:38 bouyer Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*
4 1.1 bouyer * Copyright (c) 2000 Manuel Bouyer.
5 1.1 bouyer *
6 1.1 bouyer * Redistribution and use in source and binary forms, with or without
7 1.1 bouyer * modification, are permitted provided that the following conditions
8 1.1 bouyer * are met:
9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.1 bouyer * notice, this list of conditions and the following disclaimer.
11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.1 bouyer * documentation and/or other materials provided with the distribution.
14 1.1 bouyer * 3. All advertising materials mentioning features or use of this software
15 1.1 bouyer * must display the following acknowledgement:
16 1.1 bouyer * This product includes software developed by Manuel Bouyer
17 1.1 bouyer * 4. The name of the author may not be used to endorse or promote products
18 1.1 bouyer * derived from this software without specific prior written permission.
19 1.1 bouyer *
20 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.1 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 bouyer *
31 1.1 bouyer */
32 1.1 bouyer
33 1.1 bouyer /* SYM53c7/8xx PCI-SCSI I/O Processors driver */
34 1.1 bouyer
35 1.1 bouyer #include <sys/param.h>
36 1.1 bouyer #include <sys/systm.h>
37 1.1 bouyer #include <sys/device.h>
38 1.1 bouyer #include <sys/malloc.h>
39 1.1 bouyer #include <sys/buf.h>
40 1.1 bouyer #include <sys/kernel.h>
41 1.1 bouyer #include <sys/scsiio.h>
42 1.1 bouyer
43 1.1 bouyer #include <machine/endian.h>
44 1.1 bouyer #include <machine/bus.h>
45 1.1 bouyer
46 1.1 bouyer #include <vm/vm.h>
47 1.1 bouyer #include <vm/vm_param.h>
48 1.1 bouyer #include <vm/vm_kern.h>
49 1.1 bouyer
50 1.1 bouyer #include <dev/scsipi/scsi_all.h>
51 1.1 bouyer #include <dev/scsipi/scsi_message.h>
52 1.1 bouyer #include <dev/scsipi/scsipi_all.h>
53 1.1 bouyer
54 1.1 bouyer #include <dev/scsipi/scsiconf.h>
55 1.1 bouyer
56 1.1 bouyer #include <dev/ic/siopreg.h>
57 1.1 bouyer #include <dev/ic/siopvar.h>
58 1.1 bouyer #include <dev/ic/siopvar_common.h>
59 1.1 bouyer
60 1.2 bouyer #undef DEBUG
61 1.2 bouyer #undef DEBUG_DR
62 1.1 bouyer
63 1.1 bouyer void
64 1.1 bouyer siop_common_reset(sc)
65 1.1 bouyer struct siop_softc *sc;
66 1.1 bouyer {
67 1.1 bouyer u_int32_t stest3;
68 1.1 bouyer
69 1.1 bouyer /* reset the chip */
70 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST);
71 1.1 bouyer delay(1000);
72 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0);
73 1.1 bouyer
74 1.1 bouyer /* init registers */
75 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0,
76 1.1 bouyer SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP);
77 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0);
78 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div);
79 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 0);
80 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff);
81 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0,
82 1.1 bouyer 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL));
83 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1,
84 1.1 bouyer 0xff & ~(SIEN1_HTH | SIEN1_GEN));
85 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0);
86 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE);
87 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0,
88 1.1 bouyer (0xb << STIME0_SEL_SHIFT));
89 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID,
90 1.1 bouyer sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE);
91 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0,
92 1.1 bouyer 1 << sc->sc_link.scsipi_scsi.adapter_target);
93 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
94 1.1 bouyer (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM);
95 1.1 bouyer
96 1.1 bouyer /* enable clock doubler or quadruler if appropriate */
97 1.1 bouyer if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) {
98 1.1 bouyer stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3);
99 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
100 1.1 bouyer STEST1_DBLEN);
101 1.1 bouyer if (sc->features & SF_CHIP_QUAD) {
102 1.1 bouyer /* wait for PPL to lock */
103 1.1 bouyer while ((bus_space_read_1(sc->sc_rt, sc->sc_rh,
104 1.1 bouyer SIOP_STEST4) & STEST4_LOCK) == 0)
105 1.1 bouyer delay(10);
106 1.1 bouyer } else {
107 1.1 bouyer /* data sheet says 20us - more won't hurt */
108 1.1 bouyer delay(100);
109 1.1 bouyer }
110 1.1 bouyer /* halt scsi clock, select doubler/quad, restart clock */
111 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3,
112 1.1 bouyer stest3 | STEST3_HSC);
113 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
114 1.1 bouyer STEST1_DBLEN | STEST1_DBLSEL);
115 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3);
116 1.1 bouyer } else {
117 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0);
118 1.1 bouyer }
119 1.1 bouyer if (sc->features & SF_CHIP_FIFO)
120 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5,
121 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) |
122 1.1 bouyer CTEST5_DFS);
123 1.1 bouyer
124 1.1 bouyer sc->sc_reset(sc);
125 1.1 bouyer }
126 1.1 bouyer
127 1.1 bouyer int
128 1.1 bouyer siop_wdtr_neg(siop_cmd)
129 1.1 bouyer struct siop_cmd *siop_cmd;
130 1.1 bouyer {
131 1.1 bouyer struct siop_softc *sc = siop_cmd->siop_target->siop_sc;
132 1.1 bouyer struct siop_target *siop_target = siop_cmd->siop_target;
133 1.1 bouyer int target = siop_cmd->xs->sc_link->scsipi_scsi.target;
134 1.1 bouyer
135 1.1 bouyer if (siop_target->status == TARST_WIDE_NEG) {
136 1.1 bouyer /* we initiated wide negotiation */
137 1.1 bouyer switch (siop_cmd->siop_table->msg_in[3]) {
138 1.1 bouyer case MSG_EXT_WDTR_BUS_8_BIT:
139 1.1 bouyer printf("%s: target %d using 8bit transfers\n",
140 1.1 bouyer sc->sc_dev.dv_xname, target);
141 1.1 bouyer siop_target->flags &= ~SF_BUS_WIDE;
142 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
143 1.1 bouyer break;
144 1.1 bouyer case MSG_EXT_WDTR_BUS_16_BIT:
145 1.1 bouyer if (sc->features & SF_BUS_WIDE) {
146 1.1 bouyer printf("%s: target %d using 16bit transfers\n",
147 1.1 bouyer sc->sc_dev.dv_xname, target);
148 1.1 bouyer siop_target->flags |= TARF_WIDE;
149 1.1 bouyer sc->targets[target]->id |= (SCNTL3_EWS << 24);
150 1.1 bouyer break;
151 1.1 bouyer }
152 1.1 bouyer /* FALLTHROUH */
153 1.1 bouyer default:
154 1.1 bouyer /*
155 1.1 bouyer * hum, we got more than what we can handle, shoudn't
156 1.1 bouyer * happen. Reject, and stay async
157 1.1 bouyer */
158 1.1 bouyer siop_target->flags &= ~TARF_WIDE;
159 1.1 bouyer siop_target->status = TARST_OK;
160 1.1 bouyer printf("%s: rejecting invalid wide negotiation from "
161 1.1 bouyer "target %d (%d)\n", sc->sc_dev.dv_xname, target,
162 1.1 bouyer siop_cmd->siop_table->msg_in[3]);
163 1.1 bouyer siop_cmd->siop_table->t_msgout.count= htole32(1);
164 1.1 bouyer siop_cmd->siop_table->t_msgout.addr =
165 1.1 bouyer htole32(siop_cmd->dsa);
166 1.1 bouyer siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT;
167 1.1 bouyer return SIOP_NEG_MSGOUT;
168 1.1 bouyer }
169 1.1 bouyer siop_cmd->siop_table->id =
170 1.1 bouyer htole32(sc->targets[target]->id);
171 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh,
172 1.1 bouyer SIOP_SCNTL3,
173 1.1 bouyer (sc->targets[target]->id >> 24) & 0xff);
174 1.1 bouyer /* we now need to do sync */
175 1.3.2.1 bouyer if ((siop_cmd->xs->sc_link->quirks & SDEV_NOSYNC) == 0) {
176 1.3.2.1 bouyer siop_target->status = TARST_SYNC_NEG;
177 1.3.2.1 bouyer siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
178 1.3.2.1 bouyer siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN;
179 1.3.2.1 bouyer siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR;
180 1.3.2.1 bouyer siop_cmd->siop_table->msg_out[3] = sc->minsync;
181 1.3.2.1 bouyer siop_cmd->siop_table->msg_out[4] = sc->maxoff;
182 1.3.2.1 bouyer siop_cmd->siop_table->t_msgout.count =
183 1.3.2.1 bouyer htole32(MSG_EXT_SDTR_LEN + 2);
184 1.3.2.1 bouyer siop_cmd->siop_table->t_msgout.addr =
185 1.3.2.1 bouyer htole32(siop_cmd->dsa);
186 1.3.2.1 bouyer return SIOP_NEG_MSGOUT;
187 1.3.2.1 bouyer } else {
188 1.3.2.1 bouyer siop_target->status = TARST_OK;
189 1.3.2.1 bouyer return SIOP_NEG_ACK;
190 1.3.2.1 bouyer }
191 1.1 bouyer } else {
192 1.1 bouyer /* target initiated wide negotiation */
193 1.1 bouyer if (siop_cmd->siop_table->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT
194 1.1 bouyer && (sc->features & SF_BUS_WIDE)) {
195 1.1 bouyer printf("%s: target %d using 16bit transfers\n",
196 1.1 bouyer sc->sc_dev.dv_xname, target);
197 1.1 bouyer siop_target->flags |= TARF_WIDE;
198 1.1 bouyer sc->targets[target]->id |= SCNTL3_EWS << 24;
199 1.1 bouyer siop_cmd->siop_table->msg_out[3] =
200 1.1 bouyer MSG_EXT_WDTR_BUS_16_BIT;
201 1.1 bouyer } else {
202 1.1 bouyer printf("%s: target %d using 8bit transfers\n",
203 1.1 bouyer sc->sc_dev.dv_xname, target);
204 1.1 bouyer siop_target->flags &= ~SF_BUS_WIDE;
205 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
206 1.1 bouyer siop_cmd->siop_table->msg_out[3] =
207 1.1 bouyer MSG_EXT_WDTR_BUS_8_BIT;
208 1.1 bouyer }
209 1.1 bouyer siop_cmd->siop_table->id =
210 1.1 bouyer htole32(sc->targets[target]->id);
211 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
212 1.1 bouyer (sc->targets[target]->id >> 24) & 0xff);
213 1.1 bouyer /*
214 1.1 bouyer * we did reset wide parameters, so fall back to async,
215 1.1 bouyer * but don't shedule a sync neg, target should initiate it
216 1.1 bouyer */
217 1.1 bouyer siop_target->status = TARST_OK;
218 1.1 bouyer siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
219 1.1 bouyer siop_cmd->siop_table->msg_out[1] = MSG_EXT_WDTR_LEN;
220 1.1 bouyer siop_cmd->siop_table->msg_out[2] = MSG_EXT_WDTR;
221 1.1 bouyer siop_cmd->siop_table->t_msgout.count=
222 1.1 bouyer htole32(MSG_EXT_WDTR_LEN + 2);
223 1.1 bouyer siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa);
224 1.1 bouyer return SIOP_NEG_MSGOUT;
225 1.1 bouyer }
226 1.1 bouyer }
227 1.1 bouyer
228 1.1 bouyer int
229 1.1 bouyer siop_sdtr_neg(siop_cmd)
230 1.1 bouyer struct siop_cmd *siop_cmd;
231 1.1 bouyer {
232 1.1 bouyer struct siop_softc *sc = siop_cmd->siop_target->siop_sc;
233 1.1 bouyer struct siop_target *siop_target = siop_cmd->siop_target;
234 1.1 bouyer int target = siop_cmd->xs->sc_link->scsipi_scsi.target;
235 1.1 bouyer int sync, offset, i;
236 1.1 bouyer int send_msgout = 0;
237 1.1 bouyer
238 1.1 bouyer sync = siop_cmd->siop_table->msg_in[3];
239 1.1 bouyer offset = siop_cmd->siop_table->msg_in[4];
240 1.1 bouyer
241 1.1 bouyer if (siop_target->status == TARST_SYNC_NEG) {
242 1.1 bouyer /* we initiated sync negotiation */
243 1.1 bouyer siop_target->status = TARST_OK;
244 1.1 bouyer #ifdef DEBUG
245 1.1 bouyer printf("sdtr: sync %d offset %d\n", sync, offset);
246 1.1 bouyer #endif
247 1.1 bouyer if (offset > sc->maxoff || sync < sc->minsync ||
248 1.1 bouyer sync > sc->maxsync)
249 1.1 bouyer goto reject;
250 1.1 bouyer for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
251 1.1 bouyer i++) {
252 1.1 bouyer if (sc->clock_period != scf_period[i].clock)
253 1.1 bouyer continue;
254 1.1 bouyer if (scf_period[i].period == sync) {
255 1.1 bouyer /* ok, found it. we now are sync. */
256 1.1 bouyer printf("%s: target %d now synchronous at "
257 1.1 bouyer "%sMhz, offset %d\n", sc->sc_dev.dv_xname,
258 1.1 bouyer target, scf_period[i].rate, offset);
259 1.1 bouyer sc->targets[target]->id &=
260 1.1 bouyer ~(SCNTL3_SCF_MASK << 24);
261 1.1 bouyer sc->targets[target]->id |= scf_period[i].scf
262 1.1 bouyer << (24 + SCNTL3_SCF_SHIFT);
263 1.1 bouyer if (sync < 25) /* Ultra */
264 1.1 bouyer sc->targets[target]->id |=
265 1.1 bouyer SCNTL3_ULTRA << 24;
266 1.1 bouyer else
267 1.1 bouyer sc->targets[target]->id &=
268 1.1 bouyer ~(SCNTL3_ULTRA << 24);
269 1.1 bouyer sc->targets[target]->id &=
270 1.1 bouyer ~(SCXFER_MO_MASK << 8);
271 1.1 bouyer sc->targets[target]->id |=
272 1.1 bouyer (offset & SCXFER_MO_MASK) << 8;
273 1.1 bouyer goto end;
274 1.1 bouyer }
275 1.1 bouyer }
276 1.1 bouyer /*
277 1.1 bouyer * we didn't find it in our table, do async and send reject
278 1.1 bouyer * msg
279 1.1 bouyer */
280 1.1 bouyer reject:
281 1.1 bouyer send_msgout = 1;
282 1.1 bouyer siop_cmd->siop_table->t_msgout.count= htole32(1);
283 1.1 bouyer siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT;
284 1.1 bouyer printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname,
285 1.1 bouyer target);
286 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
287 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
288 1.1 bouyer sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8);
289 1.1 bouyer } else { /* target initiated sync neg */
290 1.1 bouyer #ifdef DEBUG
291 1.1 bouyer printf("sdtr (target): sync %d offset %d\n", sync, offset);
292 1.1 bouyer #endif
293 1.1 bouyer if (offset == 0 || sync > sc->maxsync) { /* async */
294 1.1 bouyer goto async;
295 1.1 bouyer }
296 1.1 bouyer if (offset > sc->maxoff)
297 1.1 bouyer offset = sc->maxoff;
298 1.1 bouyer if (sync < sc->minsync)
299 1.1 bouyer sync = sc->minsync;
300 1.1 bouyer /* look for sync period */
301 1.1 bouyer for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
302 1.1 bouyer i++) {
303 1.1 bouyer if (sc->clock_period != scf_period[i].clock)
304 1.1 bouyer continue;
305 1.1 bouyer if (scf_period[i].period == sync) {
306 1.1 bouyer /* ok, found it. we now are sync. */
307 1.1 bouyer printf("%s: target %d now synchronous at "
308 1.1 bouyer "%sMhz, offset %d\n", sc->sc_dev.dv_xname,
309 1.1 bouyer target, scf_period[i].rate, offset);
310 1.1 bouyer sc->targets[target]->id &=
311 1.1 bouyer ~(SCNTL3_SCF_MASK << 24);
312 1.1 bouyer sc->targets[target]->id |= scf_period[i].scf
313 1.1 bouyer << (24 + SCNTL3_SCF_SHIFT);
314 1.1 bouyer if (sync < 25) /* Ultra */
315 1.1 bouyer sc->targets[target]->id |=
316 1.1 bouyer SCNTL3_ULTRA << 24;
317 1.1 bouyer else
318 1.1 bouyer sc->targets[target]->id &=
319 1.1 bouyer ~(SCNTL3_ULTRA << 24);
320 1.1 bouyer sc->targets[target]->id &=
321 1.1 bouyer ~(SCXFER_MO_MASK << 8);
322 1.1 bouyer sc->targets[target]->id |=
323 1.1 bouyer (offset & SCXFER_MO_MASK) << 8;
324 1.1 bouyer siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
325 1.1 bouyer siop_cmd->siop_table->msg_out[1] =
326 1.1 bouyer MSG_EXT_SDTR_LEN;
327 1.1 bouyer siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR;
328 1.1 bouyer siop_cmd->siop_table->msg_out[3] = sync;
329 1.1 bouyer siop_cmd->siop_table->msg_out[4] = offset;
330 1.1 bouyer siop_cmd->siop_table->t_msgout.count=
331 1.1 bouyer htole32(MSG_EXT_SDTR_LEN + 2);
332 1.1 bouyer send_msgout = 1;
333 1.1 bouyer goto end;
334 1.1 bouyer }
335 1.1 bouyer }
336 1.1 bouyer async:
337 1.1 bouyer printf("%s: target %d asynchronous\n",
338 1.1 bouyer sc->sc_dev.dv_xname, target);
339 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
340 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
341 1.1 bouyer sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8);
342 1.1 bouyer siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED;
343 1.1 bouyer siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN;
344 1.1 bouyer siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR;
345 1.1 bouyer siop_cmd->siop_table->msg_out[3] = 0;
346 1.1 bouyer siop_cmd->siop_table->msg_out[4] = 0;
347 1.1 bouyer siop_cmd->siop_table->t_msgout.count=
348 1.1 bouyer htole32(MSG_EXT_SDTR_LEN + 2);
349 1.1 bouyer send_msgout = 1;
350 1.1 bouyer }
351 1.1 bouyer end:
352 1.1 bouyer #ifdef DEBUG
353 1.1 bouyer printf("id now 0x%x\n", sc->targets[target]->id);
354 1.1 bouyer #endif
355 1.1 bouyer siop_cmd->siop_table->id = htole32(sc->targets[target]->id);
356 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
357 1.1 bouyer (sc->targets[target]->id >> 24) & 0xff);
358 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER,
359 1.1 bouyer (sc->targets[target]->id >> 8) & 0xff);
360 1.1 bouyer if (send_msgout) {
361 1.1 bouyer siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa);
362 1.1 bouyer return SIOP_NEG_MSGOUT;
363 1.1 bouyer } else {
364 1.1 bouyer return SIOP_NEG_ACK;
365 1.1 bouyer }
366 1.1 bouyer }
367 1.1 bouyer
368 1.1 bouyer void
369 1.1 bouyer siop_minphys(bp)
370 1.1 bouyer struct buf *bp;
371 1.1 bouyer {
372 1.1 bouyer minphys(bp);
373 1.1 bouyer }
374 1.1 bouyer
375 1.1 bouyer int
376 1.1 bouyer siop_ioctl(link, cmd, arg, flag, p)
377 1.1 bouyer struct scsipi_link *link;
378 1.1 bouyer u_long cmd;
379 1.1 bouyer caddr_t arg;
380 1.1 bouyer int flag;
381 1.1 bouyer struct proc *p;
382 1.1 bouyer {
383 1.1 bouyer struct siop_softc *sc = link->adapter_softc;
384 1.1 bouyer u_int8_t scntl1;
385 1.1 bouyer int s;
386 1.1 bouyer
387 1.1 bouyer switch (cmd) {
388 1.1 bouyer case SCBUSIORESET:
389 1.1 bouyer s = splbio();
390 1.1 bouyer scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1);
391 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1,
392 1.1 bouyer scntl1 | SCNTL1_RST);
393 1.1 bouyer /* minimum 25 us, more time won't hurt */
394 1.1 bouyer delay(100);
395 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1);
396 1.1 bouyer splx(s);
397 1.1 bouyer return (0);
398 1.1 bouyer default:
399 1.1 bouyer return (ENOTTY);
400 1.1 bouyer }
401 1.1 bouyer }
402 1.1 bouyer
403 1.1 bouyer void
404 1.1 bouyer siop_sdp(siop_cmd)
405 1.1 bouyer struct siop_cmd *siop_cmd;
406 1.1 bouyer {
407 1.1 bouyer /* save data pointer. Handle async only for now */
408 1.1 bouyer int offset, dbc, sstat;
409 1.1 bouyer struct siop_softc *sc = siop_cmd->siop_target->siop_sc;
410 1.1 bouyer scr_table_t *table; /* table to patch */
411 1.1 bouyer
412 1.1 bouyer if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN))
413 1.1 bouyer == 0)
414 1.1 bouyer return; /* no data pointers to save */
415 1.1 bouyer offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1);
416 1.1 bouyer if (offset >= SIOP_NSG) {
417 1.1 bouyer printf("%s: bad offset in siop_sdp (%d)\n",
418 1.1 bouyer sc->sc_dev.dv_xname, offset);
419 1.1 bouyer return;
420 1.1 bouyer }
421 1.1 bouyer table = &siop_cmd->siop_table->data[offset];
422 1.1 bouyer #ifdef DEBUG_DR
423 1.1 bouyer printf("sdp: offset %d count=%d addr=0x%x ", offset,
424 1.1 bouyer table->count, table->addr);
425 1.1 bouyer #endif
426 1.1 bouyer dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff;
427 1.1 bouyer if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) {
428 1.1 bouyer /* need to account stale data in FIFO */
429 1.1 bouyer int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO);
430 1.1 bouyer if (sc->features & SF_CHIP_FIFO) {
431 1.1 bouyer dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh,
432 1.1 bouyer SIOP_CTEST5) & CTEST5_BOMASK) << 8;
433 1.1 bouyer dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff;
434 1.1 bouyer } else {
435 1.1 bouyer dbc += (dfifo - (dbc & 0x7f)) & 0x7f;
436 1.1 bouyer }
437 1.1 bouyer sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0);
438 1.1 bouyer if (sstat & SSTAT0_OLF)
439 1.1 bouyer dbc++;
440 1.1 bouyer if (sstat & SSTAT0_ORF)
441 1.1 bouyer dbc++;
442 1.1 bouyer if (siop_cmd->siop_target->flags & TARF_WIDE) {
443 1.1 bouyer sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh,
444 1.1 bouyer SIOP_SSTAT2);
445 1.1 bouyer if (sstat & SSTAT2_OLF1)
446 1.1 bouyer dbc++;
447 1.1 bouyer if (sstat & SSTAT2_ORF1)
448 1.1 bouyer dbc++;
449 1.1 bouyer }
450 1.1 bouyer /* clear the FIFO */
451 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
452 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
453 1.1 bouyer CTEST3_CLF);
454 1.1 bouyer }
455 1.1 bouyer table->addr =
456 1.1 bouyer htole32(le32toh(table->addr) + le32toh(table->count) - dbc);
457 1.1 bouyer table->count = htole32(dbc);
458 1.1 bouyer #ifdef DEBUG_DR
459 1.1 bouyer printf("now count=%d addr=0x%x\n", table->count, table->addr);
460 1.1 bouyer #endif
461 1.1 bouyer }
462 1.1 bouyer
463 1.1 bouyer void
464 1.1 bouyer siop_clearfifo(sc)
465 1.1 bouyer struct siop_softc *sc;
466 1.1 bouyer {
467 1.1 bouyer int timeout = 0;
468 1.1 bouyer int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3);
469 1.1 bouyer
470 1.1 bouyer #ifdef DEBUG_INTR
471 1.1 bouyer printf("DMA fifo not empty !\n");
472 1.1 bouyer #endif
473 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
474 1.1 bouyer ctest3 | CTEST3_CLF);
475 1.1 bouyer while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) &
476 1.1 bouyer CTEST3_CLF) != 0) {
477 1.1 bouyer delay(1);
478 1.1 bouyer if (++timeout > 1000) {
479 1.1 bouyer printf("clear fifo failed\n");
480 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
481 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh,
482 1.1 bouyer SIOP_CTEST3) & ~CTEST3_CLF);
483 1.1 bouyer return;
484 1.1 bouyer }
485 1.1 bouyer }
486 1.3 bouyer }
487 1.3 bouyer
488 1.3 bouyer int
489 1.3 bouyer siop_modechange(sc)
490 1.3 bouyer struct siop_softc *sc;
491 1.3 bouyer {
492 1.3 bouyer int retry;
493 1.3 bouyer int sist0, sist1, stest2, stest4;
494 1.3 bouyer for (retry = 0; retry < 5; retry++) {
495 1.3 bouyer /*
496 1.3 bouyer * datasheet says to wait 100ms and re-read SIST1,
497 1.3 bouyer * to check that DIFFSENSE is srable.
498 1.3 bouyer * We may delay() 5 times for 100ms at interrupt time;
499 1.3 bouyer * hopefully this will not happen often.
500 1.3 bouyer */
501 1.3 bouyer delay(100000);
502 1.3 bouyer sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0);
503 1.3 bouyer sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1);
504 1.3 bouyer if (sist1 & SIEN1_SBMC)
505 1.3 bouyer continue; /* we got an irq again */
506 1.3 bouyer stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) &
507 1.3 bouyer STEST4_MODE_MASK;
508 1.3 bouyer stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2);
509 1.3 bouyer switch(stest4) {
510 1.3 bouyer case STEST4_MODE_DIF:
511 1.3 bouyer printf("%s: switching to differential mode\n",
512 1.3 bouyer sc->sc_dev.dv_xname);
513 1.3 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
514 1.3 bouyer stest2 | STEST2_DIF);
515 1.3 bouyer break;
516 1.3 bouyer case STEST4_MODE_SE:
517 1.3 bouyer printf("%s: switching to single-ended mode\n",
518 1.3 bouyer sc->sc_dev.dv_xname);
519 1.3 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
520 1.3 bouyer stest2 & ~STEST2_DIF);
521 1.3 bouyer break;
522 1.3 bouyer case STEST4_MODE_LVD:
523 1.3 bouyer printf("%s: switching to LVD mode\n",
524 1.3 bouyer sc->sc_dev.dv_xname);
525 1.3 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
526 1.3 bouyer stest2 & ~STEST2_DIF);
527 1.3 bouyer break;
528 1.3 bouyer default:
529 1.3 bouyer printf("%s: invalid SCSI mode 0x%x\n",
530 1.3 bouyer sc->sc_dev.dv_xname, stest4);
531 1.3 bouyer return 0;
532 1.3 bouyer }
533 1.3 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0,
534 1.3 bouyer stest4 >> 2);
535 1.3 bouyer return 1;
536 1.3 bouyer }
537 1.3 bouyer printf("%s: timeout waiting for DIFFSENSE to stabilise\n",
538 1.3 bouyer sc->sc_dev.dv_xname);
539 1.3 bouyer return 0;
540 1.3.2.1 bouyer }
541 1.3.2.1 bouyer
542 1.3.2.1 bouyer void
543 1.3.2.1 bouyer siop_resetbus(sc)
544 1.3.2.1 bouyer struct siop_softc *sc;
545 1.3.2.1 bouyer {
546 1.3.2.1 bouyer int scntl1;
547 1.3.2.1 bouyer scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1);
548 1.3.2.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1,
549 1.3.2.1 bouyer scntl1 | SCNTL1_RST);
550 1.3.2.1 bouyer /* minimum 25 us, more time won't hurt */
551 1.3.2.1 bouyer delay(100);
552 1.3.2.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1);
553 1.1 bouyer }
554