siop_common.c revision 1.3.2.2 1 1.3.2.2 he /* $NetBSD: siop_common.c,v 1.3.2.2 2000/12/16 01:59:46 he Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*
4 1.1 bouyer * Copyright (c) 2000 Manuel Bouyer.
5 1.1 bouyer *
6 1.1 bouyer * Redistribution and use in source and binary forms, with or without
7 1.1 bouyer * modification, are permitted provided that the following conditions
8 1.1 bouyer * are met:
9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.1 bouyer * notice, this list of conditions and the following disclaimer.
11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.1 bouyer * documentation and/or other materials provided with the distribution.
14 1.1 bouyer * 3. All advertising materials mentioning features or use of this software
15 1.1 bouyer * must display the following acknowledgement:
16 1.1 bouyer * This product includes software developed by Manuel Bouyer
17 1.1 bouyer * 4. The name of the author may not be used to endorse or promote products
18 1.1 bouyer * derived from this software without specific prior written permission.
19 1.1 bouyer *
20 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.1 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 bouyer *
31 1.1 bouyer */
32 1.1 bouyer
33 1.1 bouyer /* SYM53c7/8xx PCI-SCSI I/O Processors driver */
34 1.1 bouyer
35 1.1 bouyer #include <sys/param.h>
36 1.1 bouyer #include <sys/systm.h>
37 1.1 bouyer #include <sys/device.h>
38 1.1 bouyer #include <sys/malloc.h>
39 1.1 bouyer #include <sys/buf.h>
40 1.1 bouyer #include <sys/kernel.h>
41 1.1 bouyer #include <sys/scsiio.h>
42 1.1 bouyer
43 1.1 bouyer #include <machine/endian.h>
44 1.1 bouyer #include <machine/bus.h>
45 1.1 bouyer
46 1.1 bouyer #include <vm/vm.h>
47 1.1 bouyer #include <vm/vm_param.h>
48 1.1 bouyer #include <vm/vm_kern.h>
49 1.1 bouyer
50 1.1 bouyer #include <dev/scsipi/scsi_all.h>
51 1.1 bouyer #include <dev/scsipi/scsi_message.h>
52 1.1 bouyer #include <dev/scsipi/scsipi_all.h>
53 1.1 bouyer
54 1.1 bouyer #include <dev/scsipi/scsiconf.h>
55 1.1 bouyer
56 1.1 bouyer #include <dev/ic/siopreg.h>
57 1.1 bouyer #include <dev/ic/siopvar.h>
58 1.1 bouyer #include <dev/ic/siopvar_common.h>
59 1.1 bouyer
60 1.2 bouyer #undef DEBUG
61 1.2 bouyer #undef DEBUG_DR
62 1.1 bouyer
63 1.1 bouyer void
64 1.1 bouyer siop_common_reset(sc)
65 1.1 bouyer struct siop_softc *sc;
66 1.1 bouyer {
67 1.1 bouyer u_int32_t stest3;
68 1.1 bouyer
69 1.1 bouyer /* reset the chip */
70 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST);
71 1.1 bouyer delay(1000);
72 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0);
73 1.1 bouyer
74 1.1 bouyer /* init registers */
75 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0,
76 1.1 bouyer SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP);
77 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0);
78 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div);
79 1.3.2.2 he bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0);
80 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff);
81 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0,
82 1.1 bouyer 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL));
83 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1,
84 1.1 bouyer 0xff & ~(SIEN1_HTH | SIEN1_GEN));
85 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0);
86 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE);
87 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0,
88 1.1 bouyer (0xb << STIME0_SEL_SHIFT));
89 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID,
90 1.1 bouyer sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE);
91 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0,
92 1.1 bouyer 1 << sc->sc_link.scsipi_scsi.adapter_target);
93 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
94 1.1 bouyer (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM);
95 1.1 bouyer
96 1.1 bouyer /* enable clock doubler or quadruler if appropriate */
97 1.1 bouyer if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) {
98 1.1 bouyer stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3);
99 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
100 1.1 bouyer STEST1_DBLEN);
101 1.1 bouyer if (sc->features & SF_CHIP_QUAD) {
102 1.1 bouyer /* wait for PPL to lock */
103 1.1 bouyer while ((bus_space_read_1(sc->sc_rt, sc->sc_rh,
104 1.1 bouyer SIOP_STEST4) & STEST4_LOCK) == 0)
105 1.1 bouyer delay(10);
106 1.1 bouyer } else {
107 1.1 bouyer /* data sheet says 20us - more won't hurt */
108 1.1 bouyer delay(100);
109 1.1 bouyer }
110 1.1 bouyer /* halt scsi clock, select doubler/quad, restart clock */
111 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3,
112 1.1 bouyer stest3 | STEST3_HSC);
113 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1,
114 1.1 bouyer STEST1_DBLEN | STEST1_DBLSEL);
115 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3);
116 1.1 bouyer } else {
117 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0);
118 1.1 bouyer }
119 1.1 bouyer if (sc->features & SF_CHIP_FIFO)
120 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5,
121 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) |
122 1.1 bouyer CTEST5_DFS);
123 1.1 bouyer
124 1.1 bouyer sc->sc_reset(sc);
125 1.1 bouyer }
126 1.1 bouyer
127 1.3.2.2 he /* prepare tables before sending a cmd */
128 1.3.2.2 he void
129 1.3.2.2 he siop_setuptables(siop_cmd)
130 1.3.2.2 he struct siop_cmd *siop_cmd;
131 1.3.2.2 he {
132 1.3.2.2 he int i;
133 1.3.2.2 he struct siop_softc *sc = siop_cmd->siop_sc;
134 1.3.2.2 he struct scsipi_xfer *xs = siop_cmd->xs;
135 1.3.2.2 he int target = xs->sc_link->scsipi_scsi.target;
136 1.3.2.2 he int lun = xs->sc_link->scsipi_scsi.lun;
137 1.3.2.2 he
138 1.3.2.2 he siop_cmd->siop_tables.id = htole32(sc->targets[target]->id);
139 1.3.2.2 he memset(siop_cmd->siop_tables.msg_out, 0, 8);
140 1.3.2.2 he siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 1);
141 1.3.2.2 he siop_cmd->siop_tables.t_msgout.count= htole32(1);
142 1.3.2.2 he if (sc->targets[target]->status == TARST_ASYNC) {
143 1.3.2.2 he if (sc->targets[target]->flags & TARF_WIDE) {
144 1.3.2.2 he sc->targets[target]->status = TARST_WIDE_NEG;
145 1.3.2.2 he siop_wdtr_msg(siop_cmd, 1, MSG_EXT_WDTR_BUS_16_BIT);
146 1.3.2.2 he } else if (sc->targets[target]->flags & TARF_SYNC) {
147 1.3.2.2 he sc->targets[target]->status = TARST_SYNC_NEG;
148 1.3.2.2 he siop_sdtr_msg(siop_cmd, 1, sc->minsync, sc->maxoff);
149 1.3.2.2 he } else {
150 1.3.2.2 he sc->targets[target]->status = TARST_OK;
151 1.3.2.2 he }
152 1.3.2.2 he } else if (sc->targets[target]->status == TARST_OK &&
153 1.3.2.2 he (sc->targets[target]->flags & TARF_TAG) &&
154 1.3.2.2 he siop_cmd->status != CMDST_SENSE) {
155 1.3.2.2 he siop_cmd->flags |= CMDFL_TAG;
156 1.3.2.2 he }
157 1.3.2.2 he siop_cmd->siop_tables.status =
158 1.3.2.2 he htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */
159 1.3.2.2 he
160 1.3.2.2 he siop_cmd->siop_tables.cmd.count =
161 1.3.2.2 he htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len);
162 1.3.2.2 he siop_cmd->siop_tables.cmd.addr =
163 1.3.2.2 he htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr);
164 1.3.2.2 he if ((xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) ||
165 1.3.2.2 he siop_cmd->status == CMDST_SENSE) {
166 1.3.2.2 he for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) {
167 1.3.2.2 he siop_cmd->siop_tables.data[i].count =
168 1.3.2.2 he htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len);
169 1.3.2.2 he siop_cmd->siop_tables.data[i].addr =
170 1.3.2.2 he htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr);
171 1.3.2.2 he }
172 1.3.2.2 he }
173 1.3.2.2 he siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
174 1.3.2.2 he }
175 1.3.2.2 he
176 1.1 bouyer int
177 1.1 bouyer siop_wdtr_neg(siop_cmd)
178 1.1 bouyer struct siop_cmd *siop_cmd;
179 1.1 bouyer {
180 1.3.2.2 he struct siop_softc *sc = siop_cmd->siop_sc;
181 1.1 bouyer struct siop_target *siop_target = siop_cmd->siop_target;
182 1.1 bouyer int target = siop_cmd->xs->sc_link->scsipi_scsi.target;
183 1.3.2.2 he struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables;
184 1.1 bouyer
185 1.1 bouyer if (siop_target->status == TARST_WIDE_NEG) {
186 1.1 bouyer /* we initiated wide negotiation */
187 1.3.2.2 he switch (tables->msg_in[3]) {
188 1.1 bouyer case MSG_EXT_WDTR_BUS_8_BIT:
189 1.1 bouyer printf("%s: target %d using 8bit transfers\n",
190 1.1 bouyer sc->sc_dev.dv_xname, target);
191 1.3.2.2 he siop_target->flags &= ~TARF_ISWIDE;
192 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
193 1.1 bouyer break;
194 1.1 bouyer case MSG_EXT_WDTR_BUS_16_BIT:
195 1.3.2.2 he if (siop_target->flags & TARF_WIDE) {
196 1.1 bouyer printf("%s: target %d using 16bit transfers\n",
197 1.1 bouyer sc->sc_dev.dv_xname, target);
198 1.3.2.2 he siop_target->flags |= TARF_ISWIDE;
199 1.1 bouyer sc->targets[target]->id |= (SCNTL3_EWS << 24);
200 1.1 bouyer break;
201 1.1 bouyer }
202 1.1 bouyer /* FALLTHROUH */
203 1.1 bouyer default:
204 1.1 bouyer /*
205 1.1 bouyer * hum, we got more than what we can handle, shoudn't
206 1.1 bouyer * happen. Reject, and stay async
207 1.1 bouyer */
208 1.3.2.2 he siop_target->flags &= ~TARF_ISWIDE;
209 1.1 bouyer siop_target->status = TARST_OK;
210 1.1 bouyer printf("%s: rejecting invalid wide negotiation from "
211 1.1 bouyer "target %d (%d)\n", sc->sc_dev.dv_xname, target,
212 1.3.2.2 he tables->msg_in[3]);
213 1.3.2.2 he tables->t_msgout.count= htole32(1);
214 1.3.2.2 he tables->msg_out[0] = MSG_MESSAGE_REJECT;
215 1.1 bouyer return SIOP_NEG_MSGOUT;
216 1.1 bouyer }
217 1.3.2.2 he tables->id = htole32(sc->targets[target]->id);
218 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh,
219 1.1 bouyer SIOP_SCNTL3,
220 1.1 bouyer (sc->targets[target]->id >> 24) & 0xff);
221 1.1 bouyer /* we now need to do sync */
222 1.3.2.2 he if (siop_target->flags & TARF_SYNC) {
223 1.3.2.1 bouyer siop_target->status = TARST_SYNC_NEG;
224 1.3.2.2 he siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff);
225 1.3.2.1 bouyer return SIOP_NEG_MSGOUT;
226 1.3.2.1 bouyer } else {
227 1.3.2.1 bouyer siop_target->status = TARST_OK;
228 1.3.2.1 bouyer return SIOP_NEG_ACK;
229 1.3.2.1 bouyer }
230 1.1 bouyer } else {
231 1.1 bouyer /* target initiated wide negotiation */
232 1.3.2.2 he if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT
233 1.3.2.2 he && (siop_target->flags & TARF_WIDE)) {
234 1.1 bouyer printf("%s: target %d using 16bit transfers\n",
235 1.1 bouyer sc->sc_dev.dv_xname, target);
236 1.3.2.2 he siop_target->flags |= TARF_ISWIDE;
237 1.1 bouyer sc->targets[target]->id |= SCNTL3_EWS << 24;
238 1.1 bouyer } else {
239 1.1 bouyer printf("%s: target %d using 8bit transfers\n",
240 1.1 bouyer sc->sc_dev.dv_xname, target);
241 1.3.2.2 he siop_target->flags &= ~TARF_ISWIDE;
242 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_EWS << 24);
243 1.1 bouyer }
244 1.3.2.2 he tables->id = htole32(sc->targets[target]->id);
245 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
246 1.1 bouyer (sc->targets[target]->id >> 24) & 0xff);
247 1.1 bouyer /*
248 1.1 bouyer * we did reset wide parameters, so fall back to async,
249 1.3.2.2 he * but don't schedule a sync neg, target should initiate it
250 1.1 bouyer */
251 1.1 bouyer siop_target->status = TARST_OK;
252 1.3.2.2 he siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ?
253 1.3.2.2 he MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT);
254 1.1 bouyer return SIOP_NEG_MSGOUT;
255 1.1 bouyer }
256 1.1 bouyer }
257 1.1 bouyer
258 1.1 bouyer int
259 1.1 bouyer siop_sdtr_neg(siop_cmd)
260 1.1 bouyer struct siop_cmd *siop_cmd;
261 1.1 bouyer {
262 1.3.2.2 he struct siop_softc *sc = siop_cmd->siop_sc;
263 1.1 bouyer struct siop_target *siop_target = siop_cmd->siop_target;
264 1.1 bouyer int target = siop_cmd->xs->sc_link->scsipi_scsi.target;
265 1.1 bouyer int sync, offset, i;
266 1.1 bouyer int send_msgout = 0;
267 1.3.2.2 he struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables;
268 1.1 bouyer
269 1.3.2.2 he sync = tables->msg_in[3];
270 1.3.2.2 he offset = tables->msg_in[4];
271 1.1 bouyer
272 1.1 bouyer if (siop_target->status == TARST_SYNC_NEG) {
273 1.1 bouyer /* we initiated sync negotiation */
274 1.1 bouyer siop_target->status = TARST_OK;
275 1.1 bouyer #ifdef DEBUG
276 1.1 bouyer printf("sdtr: sync %d offset %d\n", sync, offset);
277 1.1 bouyer #endif
278 1.1 bouyer if (offset > sc->maxoff || sync < sc->minsync ||
279 1.1 bouyer sync > sc->maxsync)
280 1.1 bouyer goto reject;
281 1.1 bouyer for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
282 1.1 bouyer i++) {
283 1.1 bouyer if (sc->clock_period != scf_period[i].clock)
284 1.1 bouyer continue;
285 1.1 bouyer if (scf_period[i].period == sync) {
286 1.1 bouyer /* ok, found it. we now are sync. */
287 1.1 bouyer printf("%s: target %d now synchronous at "
288 1.1 bouyer "%sMhz, offset %d\n", sc->sc_dev.dv_xname,
289 1.1 bouyer target, scf_period[i].rate, offset);
290 1.1 bouyer sc->targets[target]->id &=
291 1.1 bouyer ~(SCNTL3_SCF_MASK << 24);
292 1.1 bouyer sc->targets[target]->id |= scf_period[i].scf
293 1.1 bouyer << (24 + SCNTL3_SCF_SHIFT);
294 1.1 bouyer if (sync < 25) /* Ultra */
295 1.1 bouyer sc->targets[target]->id |=
296 1.1 bouyer SCNTL3_ULTRA << 24;
297 1.1 bouyer else
298 1.1 bouyer sc->targets[target]->id &=
299 1.1 bouyer ~(SCNTL3_ULTRA << 24);
300 1.1 bouyer sc->targets[target]->id &=
301 1.3.2.2 he ~(SXFER_MO_MASK << 8);
302 1.1 bouyer sc->targets[target]->id |=
303 1.3.2.2 he (offset & SXFER_MO_MASK) << 8;
304 1.1 bouyer goto end;
305 1.1 bouyer }
306 1.1 bouyer }
307 1.1 bouyer /*
308 1.1 bouyer * we didn't find it in our table, do async and send reject
309 1.1 bouyer * msg
310 1.1 bouyer */
311 1.1 bouyer reject:
312 1.1 bouyer send_msgout = 1;
313 1.3.2.2 he tables->t_msgout.count= htole32(1);
314 1.3.2.2 he tables->msg_out[0] = MSG_MESSAGE_REJECT;
315 1.1 bouyer printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname,
316 1.1 bouyer target);
317 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
318 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
319 1.3.2.2 he sc->targets[target]->id &= ~(SXFER_MO_MASK << 8);
320 1.1 bouyer } else { /* target initiated sync neg */
321 1.1 bouyer #ifdef DEBUG
322 1.1 bouyer printf("sdtr (target): sync %d offset %d\n", sync, offset);
323 1.1 bouyer #endif
324 1.1 bouyer if (offset == 0 || sync > sc->maxsync) { /* async */
325 1.1 bouyer goto async;
326 1.1 bouyer }
327 1.1 bouyer if (offset > sc->maxoff)
328 1.1 bouyer offset = sc->maxoff;
329 1.1 bouyer if (sync < sc->minsync)
330 1.1 bouyer sync = sc->minsync;
331 1.1 bouyer /* look for sync period */
332 1.1 bouyer for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]);
333 1.1 bouyer i++) {
334 1.1 bouyer if (sc->clock_period != scf_period[i].clock)
335 1.1 bouyer continue;
336 1.1 bouyer if (scf_period[i].period == sync) {
337 1.1 bouyer /* ok, found it. we now are sync. */
338 1.1 bouyer printf("%s: target %d now synchronous at "
339 1.1 bouyer "%sMhz, offset %d\n", sc->sc_dev.dv_xname,
340 1.1 bouyer target, scf_period[i].rate, offset);
341 1.1 bouyer sc->targets[target]->id &=
342 1.1 bouyer ~(SCNTL3_SCF_MASK << 24);
343 1.1 bouyer sc->targets[target]->id |= scf_period[i].scf
344 1.1 bouyer << (24 + SCNTL3_SCF_SHIFT);
345 1.1 bouyer if (sync < 25) /* Ultra */
346 1.1 bouyer sc->targets[target]->id |=
347 1.1 bouyer SCNTL3_ULTRA << 24;
348 1.1 bouyer else
349 1.1 bouyer sc->targets[target]->id &=
350 1.1 bouyer ~(SCNTL3_ULTRA << 24);
351 1.1 bouyer sc->targets[target]->id &=
352 1.3.2.2 he ~(SXFER_MO_MASK << 8);
353 1.1 bouyer sc->targets[target]->id |=
354 1.3.2.2 he (offset & SXFER_MO_MASK) << 8;
355 1.3.2.2 he siop_sdtr_msg(siop_cmd, 0, sync, offset);
356 1.1 bouyer send_msgout = 1;
357 1.1 bouyer goto end;
358 1.1 bouyer }
359 1.1 bouyer }
360 1.1 bouyer async:
361 1.1 bouyer printf("%s: target %d asynchronous\n",
362 1.1 bouyer sc->sc_dev.dv_xname, target);
363 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24);
364 1.1 bouyer sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24);
365 1.3.2.2 he sc->targets[target]->id &= ~(SXFER_MO_MASK << 8);
366 1.3.2.2 he siop_sdtr_msg(siop_cmd, 0, 0, 0);
367 1.1 bouyer send_msgout = 1;
368 1.1 bouyer }
369 1.1 bouyer end:
370 1.1 bouyer #ifdef DEBUG
371 1.1 bouyer printf("id now 0x%x\n", sc->targets[target]->id);
372 1.1 bouyer #endif
373 1.3.2.2 he tables->id = htole32(sc->targets[target]->id);
374 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3,
375 1.1 bouyer (sc->targets[target]->id >> 24) & 0xff);
376 1.3.2.2 he bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER,
377 1.1 bouyer (sc->targets[target]->id >> 8) & 0xff);
378 1.1 bouyer if (send_msgout) {
379 1.1 bouyer return SIOP_NEG_MSGOUT;
380 1.1 bouyer } else {
381 1.1 bouyer return SIOP_NEG_ACK;
382 1.1 bouyer }
383 1.1 bouyer }
384 1.1 bouyer
385 1.1 bouyer void
386 1.3.2.2 he siop_sdtr_msg(siop_cmd, offset, ssync, soff)
387 1.3.2.2 he struct siop_cmd *siop_cmd;
388 1.3.2.2 he int offset;
389 1.3.2.2 he int ssync, soff;
390 1.3.2.2 he {
391 1.3.2.2 he siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED;
392 1.3.2.2 he siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_SDTR_LEN;
393 1.3.2.2 he siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_SDTR;
394 1.3.2.2 he siop_cmd->siop_tables.msg_out[offset + 3] = ssync;
395 1.3.2.2 he siop_cmd->siop_tables.msg_out[offset + 4] = soff;
396 1.3.2.2 he siop_cmd->siop_tables.t_msgout.count =
397 1.3.2.2 he htole32(offset + MSG_EXT_SDTR_LEN + 2);
398 1.3.2.2 he }
399 1.3.2.2 he
400 1.3.2.2 he void
401 1.3.2.2 he siop_wdtr_msg(siop_cmd, offset, wide)
402 1.3.2.2 he struct siop_cmd *siop_cmd;
403 1.3.2.2 he int offset;
404 1.3.2.2 he {
405 1.3.2.2 he siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED;
406 1.3.2.2 he siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_WDTR_LEN;
407 1.3.2.2 he siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_WDTR;
408 1.3.2.2 he siop_cmd->siop_tables.msg_out[offset + 3] = wide;
409 1.3.2.2 he siop_cmd->siop_tables.t_msgout.count =
410 1.3.2.2 he htole32(offset + MSG_EXT_WDTR_LEN + 2);
411 1.3.2.2 he }
412 1.3.2.2 he
413 1.3.2.2 he void
414 1.1 bouyer siop_minphys(bp)
415 1.1 bouyer struct buf *bp;
416 1.1 bouyer {
417 1.1 bouyer minphys(bp);
418 1.1 bouyer }
419 1.1 bouyer
420 1.1 bouyer int
421 1.1 bouyer siop_ioctl(link, cmd, arg, flag, p)
422 1.1 bouyer struct scsipi_link *link;
423 1.1 bouyer u_long cmd;
424 1.1 bouyer caddr_t arg;
425 1.1 bouyer int flag;
426 1.1 bouyer struct proc *p;
427 1.1 bouyer {
428 1.1 bouyer struct siop_softc *sc = link->adapter_softc;
429 1.1 bouyer u_int8_t scntl1;
430 1.1 bouyer int s;
431 1.1 bouyer
432 1.1 bouyer switch (cmd) {
433 1.3.2.2 he case SCBUSACCEL:
434 1.3.2.2 he {
435 1.3.2.2 he struct scbusaccel_args *sp = (struct scbusaccel_args *)arg;
436 1.3.2.2 he s = splbio();
437 1.3.2.2 he if (sp->sa_lun == 0) {
438 1.3.2.2 he if (sp->sa_flags & SC_ACCEL_TAGS) {
439 1.3.2.2 he sc->targets[sp->sa_target]->flags |= TARF_TAG;
440 1.3.2.2 he printf("%s: target %d using tagged queuing\n",
441 1.3.2.2 he sc->sc_dev.dv_xname, sp->sa_target);
442 1.3.2.2 he }
443 1.3.2.2 he if ((sp->sa_flags & SC_ACCEL_WIDE) &&
444 1.3.2.2 he (sc->features & SF_BUS_WIDE))
445 1.3.2.2 he sc->targets[sp->sa_target]->flags |= TARF_WIDE;
446 1.3.2.2 he if (sp->sa_flags & SC_ACCEL_SYNC)
447 1.3.2.2 he sc->targets[sp->sa_target]->flags |= TARF_SYNC;
448 1.3.2.2 he if ((sp->sa_flags & (SC_ACCEL_SYNC | SC_ACCEL_WIDE)) ||
449 1.3.2.2 he sc->targets[sp->sa_target]->status == TARST_PROBING)
450 1.3.2.2 he sc->targets[sp->sa_target]->status =
451 1.3.2.2 he TARST_ASYNC;
452 1.3.2.2 he }
453 1.3.2.2 he
454 1.3.2.2 he /* allocate a lun sw entry for this device */
455 1.3.2.2 he siop_add_dev(sc, sp->sa_target, sp->sa_lun);
456 1.3.2.2 he /*
457 1.3.2.2 he * if we can to tagged queueing, inform upper layer
458 1.3.2.2 he * we can have NIOP_NTAG concurent commands
459 1.3.2.2 he */
460 1.3.2.2 he if (sc->targets[sp->sa_target]->flags & TARF_TAG)
461 1.3.2.2 he link->openings = SIOP_NTAG;
462 1.3.2.2 he splx(s);
463 1.3.2.2 he return 0;
464 1.3.2.2 he }
465 1.1 bouyer case SCBUSIORESET:
466 1.1 bouyer s = splbio();
467 1.1 bouyer scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1);
468 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1,
469 1.1 bouyer scntl1 | SCNTL1_RST);
470 1.1 bouyer /* minimum 25 us, more time won't hurt */
471 1.1 bouyer delay(100);
472 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1);
473 1.1 bouyer splx(s);
474 1.1 bouyer return (0);
475 1.1 bouyer default:
476 1.1 bouyer return (ENOTTY);
477 1.1 bouyer }
478 1.1 bouyer }
479 1.1 bouyer
480 1.1 bouyer void
481 1.1 bouyer siop_sdp(siop_cmd)
482 1.1 bouyer struct siop_cmd *siop_cmd;
483 1.1 bouyer {
484 1.1 bouyer /* save data pointer. Handle async only for now */
485 1.1 bouyer int offset, dbc, sstat;
486 1.3.2.2 he struct siop_softc *sc = siop_cmd->siop_sc;
487 1.1 bouyer scr_table_t *table; /* table to patch */
488 1.1 bouyer
489 1.1 bouyer if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN))
490 1.1 bouyer == 0)
491 1.1 bouyer return; /* no data pointers to save */
492 1.1 bouyer offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1);
493 1.1 bouyer if (offset >= SIOP_NSG) {
494 1.1 bouyer printf("%s: bad offset in siop_sdp (%d)\n",
495 1.1 bouyer sc->sc_dev.dv_xname, offset);
496 1.1 bouyer return;
497 1.1 bouyer }
498 1.3.2.2 he table = &siop_cmd->siop_xfer->tables.data[offset];
499 1.1 bouyer #ifdef DEBUG_DR
500 1.1 bouyer printf("sdp: offset %d count=%d addr=0x%x ", offset,
501 1.1 bouyer table->count, table->addr);
502 1.1 bouyer #endif
503 1.1 bouyer dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff;
504 1.1 bouyer if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) {
505 1.1 bouyer /* need to account stale data in FIFO */
506 1.1 bouyer int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO);
507 1.1 bouyer if (sc->features & SF_CHIP_FIFO) {
508 1.1 bouyer dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh,
509 1.1 bouyer SIOP_CTEST5) & CTEST5_BOMASK) << 8;
510 1.1 bouyer dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff;
511 1.1 bouyer } else {
512 1.1 bouyer dbc += (dfifo - (dbc & 0x7f)) & 0x7f;
513 1.1 bouyer }
514 1.1 bouyer sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0);
515 1.1 bouyer if (sstat & SSTAT0_OLF)
516 1.1 bouyer dbc++;
517 1.1 bouyer if (sstat & SSTAT0_ORF)
518 1.1 bouyer dbc++;
519 1.3.2.2 he if (siop_cmd->siop_target->flags & TARF_ISWIDE) {
520 1.1 bouyer sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh,
521 1.1 bouyer SIOP_SSTAT2);
522 1.1 bouyer if (sstat & SSTAT2_OLF1)
523 1.1 bouyer dbc++;
524 1.1 bouyer if (sstat & SSTAT2_ORF1)
525 1.1 bouyer dbc++;
526 1.1 bouyer }
527 1.1 bouyer /* clear the FIFO */
528 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
529 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
530 1.1 bouyer CTEST3_CLF);
531 1.1 bouyer }
532 1.1 bouyer table->addr =
533 1.1 bouyer htole32(le32toh(table->addr) + le32toh(table->count) - dbc);
534 1.1 bouyer table->count = htole32(dbc);
535 1.1 bouyer #ifdef DEBUG_DR
536 1.1 bouyer printf("now count=%d addr=0x%x\n", table->count, table->addr);
537 1.1 bouyer #endif
538 1.1 bouyer }
539 1.1 bouyer
540 1.1 bouyer void
541 1.1 bouyer siop_clearfifo(sc)
542 1.1 bouyer struct siop_softc *sc;
543 1.1 bouyer {
544 1.1 bouyer int timeout = 0;
545 1.1 bouyer int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3);
546 1.1 bouyer
547 1.1 bouyer #ifdef DEBUG_INTR
548 1.1 bouyer printf("DMA fifo not empty !\n");
549 1.1 bouyer #endif
550 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
551 1.1 bouyer ctest3 | CTEST3_CLF);
552 1.1 bouyer while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) &
553 1.1 bouyer CTEST3_CLF) != 0) {
554 1.1 bouyer delay(1);
555 1.1 bouyer if (++timeout > 1000) {
556 1.1 bouyer printf("clear fifo failed\n");
557 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
558 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh,
559 1.1 bouyer SIOP_CTEST3) & ~CTEST3_CLF);
560 1.1 bouyer return;
561 1.1 bouyer }
562 1.1 bouyer }
563 1.3 bouyer }
564 1.3 bouyer
565 1.3 bouyer int
566 1.3 bouyer siop_modechange(sc)
567 1.3 bouyer struct siop_softc *sc;
568 1.3 bouyer {
569 1.3 bouyer int retry;
570 1.3 bouyer int sist0, sist1, stest2, stest4;
571 1.3 bouyer for (retry = 0; retry < 5; retry++) {
572 1.3 bouyer /*
573 1.3 bouyer * datasheet says to wait 100ms and re-read SIST1,
574 1.3 bouyer * to check that DIFFSENSE is srable.
575 1.3 bouyer * We may delay() 5 times for 100ms at interrupt time;
576 1.3 bouyer * hopefully this will not happen often.
577 1.3 bouyer */
578 1.3 bouyer delay(100000);
579 1.3 bouyer sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0);
580 1.3 bouyer sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1);
581 1.3 bouyer if (sist1 & SIEN1_SBMC)
582 1.3 bouyer continue; /* we got an irq again */
583 1.3 bouyer stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) &
584 1.3 bouyer STEST4_MODE_MASK;
585 1.3 bouyer stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2);
586 1.3 bouyer switch(stest4) {
587 1.3 bouyer case STEST4_MODE_DIF:
588 1.3 bouyer printf("%s: switching to differential mode\n",
589 1.3 bouyer sc->sc_dev.dv_xname);
590 1.3 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
591 1.3 bouyer stest2 | STEST2_DIF);
592 1.3 bouyer break;
593 1.3 bouyer case STEST4_MODE_SE:
594 1.3 bouyer printf("%s: switching to single-ended mode\n",
595 1.3 bouyer sc->sc_dev.dv_xname);
596 1.3 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
597 1.3 bouyer stest2 & ~STEST2_DIF);
598 1.3 bouyer break;
599 1.3 bouyer case STEST4_MODE_LVD:
600 1.3 bouyer printf("%s: switching to LVD mode\n",
601 1.3 bouyer sc->sc_dev.dv_xname);
602 1.3 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2,
603 1.3 bouyer stest2 & ~STEST2_DIF);
604 1.3 bouyer break;
605 1.3 bouyer default:
606 1.3 bouyer printf("%s: invalid SCSI mode 0x%x\n",
607 1.3 bouyer sc->sc_dev.dv_xname, stest4);
608 1.3 bouyer return 0;
609 1.3 bouyer }
610 1.3 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0,
611 1.3 bouyer stest4 >> 2);
612 1.3 bouyer return 1;
613 1.3 bouyer }
614 1.3 bouyer printf("%s: timeout waiting for DIFFSENSE to stabilise\n",
615 1.3 bouyer sc->sc_dev.dv_xname);
616 1.3 bouyer return 0;
617 1.3.2.1 bouyer }
618 1.3.2.1 bouyer
619 1.3.2.1 bouyer void
620 1.3.2.1 bouyer siop_resetbus(sc)
621 1.3.2.1 bouyer struct siop_softc *sc;
622 1.3.2.1 bouyer {
623 1.3.2.1 bouyer int scntl1;
624 1.3.2.1 bouyer scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1);
625 1.3.2.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1,
626 1.3.2.1 bouyer scntl1 | SCNTL1_RST);
627 1.3.2.1 bouyer /* minimum 25 us, more time won't hurt */
628 1.3.2.1 bouyer delay(100);
629 1.3.2.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1);
630 1.1 bouyer }
631