siop_common.c revision 1.1
1 /* $NetBSD: siop_common.c,v 1.1 2000/05/15 07:48:25 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_param.h> 48 #include <vm/vm_kern.h> 49 50 #include <dev/scsipi/scsi_all.h> 51 #include <dev/scsipi/scsi_message.h> 52 #include <dev/scsipi/scsipi_all.h> 53 54 #include <dev/scsipi/scsiconf.h> 55 56 #include <dev/ic/siopreg.h> 57 #include <dev/ic/siopvar.h> 58 #include <dev/ic/siopvar_common.h> 59 60 #define DEBUG 61 62 void 63 siop_common_reset(sc) 64 struct siop_softc *sc; 65 { 66 u_int32_t stest3; 67 68 /* reset the chip */ 69 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 70 delay(1000); 71 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 72 73 /* init registers */ 74 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 75 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 76 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 78 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 0); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 80 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 81 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 82 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 83 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 84 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 86 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 87 (0xb << STIME0_SEL_SHIFT)); 88 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 89 sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE); 90 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 91 1 << sc->sc_link.scsipi_scsi.adapter_target); 92 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 93 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 94 95 /* enable clock doubler or quadruler if appropriate */ 96 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 97 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 98 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 99 STEST1_DBLEN); 100 if (sc->features & SF_CHIP_QUAD) { 101 /* wait for PPL to lock */ 102 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 103 SIOP_STEST4) & STEST4_LOCK) == 0) 104 delay(10); 105 } else { 106 /* data sheet says 20us - more won't hurt */ 107 delay(100); 108 } 109 /* halt scsi clock, select doubler/quad, restart clock */ 110 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 111 stest3 | STEST3_HSC); 112 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 113 STEST1_DBLEN | STEST1_DBLSEL); 114 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 115 } else { 116 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 117 } 118 if (sc->features & SF_CHIP_FIFO) 119 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 120 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 121 CTEST5_DFS); 122 123 sc->sc_reset(sc); 124 } 125 126 int 127 siop_wdtr_neg(siop_cmd) 128 struct siop_cmd *siop_cmd; 129 { 130 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 131 struct siop_target *siop_target = siop_cmd->siop_target; 132 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 133 134 if (siop_target->status == TARST_WIDE_NEG) { 135 /* we initiated wide negotiation */ 136 switch (siop_cmd->siop_table->msg_in[3]) { 137 case MSG_EXT_WDTR_BUS_8_BIT: 138 printf("%s: target %d using 8bit transfers\n", 139 sc->sc_dev.dv_xname, target); 140 siop_target->flags &= ~SF_BUS_WIDE; 141 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 142 break; 143 case MSG_EXT_WDTR_BUS_16_BIT: 144 if (sc->features & SF_BUS_WIDE) { 145 printf("%s: target %d using 16bit transfers\n", 146 sc->sc_dev.dv_xname, target); 147 siop_target->flags |= TARF_WIDE; 148 sc->targets[target]->id |= (SCNTL3_EWS << 24); 149 break; 150 } 151 /* FALLTHROUH */ 152 default: 153 /* 154 * hum, we got more than what we can handle, shoudn't 155 * happen. Reject, and stay async 156 */ 157 siop_target->flags &= ~TARF_WIDE; 158 siop_target->status = TARST_OK; 159 printf("%s: rejecting invalid wide negotiation from " 160 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 161 siop_cmd->siop_table->msg_in[3]); 162 siop_cmd->siop_table->t_msgout.count= htole32(1); 163 siop_cmd->siop_table->t_msgout.addr = 164 htole32(siop_cmd->dsa); 165 siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT; 166 return SIOP_NEG_MSGOUT; 167 } 168 siop_cmd->siop_table->id = 169 htole32(sc->targets[target]->id); 170 bus_space_write_1(sc->sc_rt, sc->sc_rh, 171 SIOP_SCNTL3, 172 (sc->targets[target]->id >> 24) & 0xff); 173 /* we now need to do sync */ 174 siop_target->status = TARST_SYNC_NEG; 175 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 176 siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN; 177 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR; 178 siop_cmd->siop_table->msg_out[3] = sc->minsync; 179 siop_cmd->siop_table->msg_out[4] = sc->maxoff; 180 siop_cmd->siop_table->t_msgout.count = 181 htole32(MSG_EXT_SDTR_LEN + 2); 182 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 183 return SIOP_NEG_MSGOUT; 184 } else { 185 /* target initiated wide negotiation */ 186 if (siop_cmd->siop_table->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 187 && (sc->features & SF_BUS_WIDE)) { 188 printf("%s: target %d using 16bit transfers\n", 189 sc->sc_dev.dv_xname, target); 190 siop_target->flags |= TARF_WIDE; 191 sc->targets[target]->id |= SCNTL3_EWS << 24; 192 siop_cmd->siop_table->msg_out[3] = 193 MSG_EXT_WDTR_BUS_16_BIT; 194 } else { 195 printf("%s: target %d using 8bit transfers\n", 196 sc->sc_dev.dv_xname, target); 197 siop_target->flags &= ~SF_BUS_WIDE; 198 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 199 siop_cmd->siop_table->msg_out[3] = 200 MSG_EXT_WDTR_BUS_8_BIT; 201 } 202 siop_cmd->siop_table->id = 203 htole32(sc->targets[target]->id); 204 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 205 (sc->targets[target]->id >> 24) & 0xff); 206 /* 207 * we did reset wide parameters, so fall back to async, 208 * but don't shedule a sync neg, target should initiate it 209 */ 210 siop_target->status = TARST_OK; 211 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 212 siop_cmd->siop_table->msg_out[1] = MSG_EXT_WDTR_LEN; 213 siop_cmd->siop_table->msg_out[2] = MSG_EXT_WDTR; 214 siop_cmd->siop_table->t_msgout.count= 215 htole32(MSG_EXT_WDTR_LEN + 2); 216 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 217 return SIOP_NEG_MSGOUT; 218 } 219 } 220 221 int 222 siop_sdtr_neg(siop_cmd) 223 struct siop_cmd *siop_cmd; 224 { 225 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 226 struct siop_target *siop_target = siop_cmd->siop_target; 227 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 228 int sync, offset, i; 229 int send_msgout = 0; 230 231 sync = siop_cmd->siop_table->msg_in[3]; 232 offset = siop_cmd->siop_table->msg_in[4]; 233 234 if (siop_target->status == TARST_SYNC_NEG) { 235 /* we initiated sync negotiation */ 236 siop_target->status = TARST_OK; 237 #ifdef DEBUG 238 printf("sdtr: sync %d offset %d\n", sync, offset); 239 #endif 240 if (offset > sc->maxoff || sync < sc->minsync || 241 sync > sc->maxsync) 242 goto reject; 243 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 244 i++) { 245 if (sc->clock_period != scf_period[i].clock) 246 continue; 247 if (scf_period[i].period == sync) { 248 /* ok, found it. we now are sync. */ 249 printf("%s: target %d now synchronous at " 250 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 251 target, scf_period[i].rate, offset); 252 sc->targets[target]->id &= 253 ~(SCNTL3_SCF_MASK << 24); 254 sc->targets[target]->id |= scf_period[i].scf 255 << (24 + SCNTL3_SCF_SHIFT); 256 if (sync < 25) /* Ultra */ 257 sc->targets[target]->id |= 258 SCNTL3_ULTRA << 24; 259 else 260 sc->targets[target]->id &= 261 ~(SCNTL3_ULTRA << 24); 262 sc->targets[target]->id &= 263 ~(SCXFER_MO_MASK << 8); 264 sc->targets[target]->id |= 265 (offset & SCXFER_MO_MASK) << 8; 266 goto end; 267 } 268 } 269 /* 270 * we didn't find it in our table, do async and send reject 271 * msg 272 */ 273 reject: 274 send_msgout = 1; 275 siop_cmd->siop_table->t_msgout.count= htole32(1); 276 siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT; 277 printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname, 278 target); 279 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 280 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 281 sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8); 282 } else { /* target initiated sync neg */ 283 #ifdef DEBUG 284 printf("sdtr (target): sync %d offset %d\n", sync, offset); 285 #endif 286 if (offset == 0 || sync > sc->maxsync) { /* async */ 287 goto async; 288 } 289 if (offset > sc->maxoff) 290 offset = sc->maxoff; 291 if (sync < sc->minsync) 292 sync = sc->minsync; 293 /* look for sync period */ 294 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 295 i++) { 296 if (sc->clock_period != scf_period[i].clock) 297 continue; 298 if (scf_period[i].period == sync) { 299 /* ok, found it. we now are sync. */ 300 printf("%s: target %d now synchronous at " 301 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 302 target, scf_period[i].rate, offset); 303 sc->targets[target]->id &= 304 ~(SCNTL3_SCF_MASK << 24); 305 sc->targets[target]->id |= scf_period[i].scf 306 << (24 + SCNTL3_SCF_SHIFT); 307 if (sync < 25) /* Ultra */ 308 sc->targets[target]->id |= 309 SCNTL3_ULTRA << 24; 310 else 311 sc->targets[target]->id &= 312 ~(SCNTL3_ULTRA << 24); 313 sc->targets[target]->id &= 314 ~(SCXFER_MO_MASK << 8); 315 sc->targets[target]->id |= 316 (offset & SCXFER_MO_MASK) << 8; 317 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 318 siop_cmd->siop_table->msg_out[1] = 319 MSG_EXT_SDTR_LEN; 320 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR; 321 siop_cmd->siop_table->msg_out[3] = sync; 322 siop_cmd->siop_table->msg_out[4] = offset; 323 siop_cmd->siop_table->t_msgout.count= 324 htole32(MSG_EXT_SDTR_LEN + 2); 325 send_msgout = 1; 326 goto end; 327 } 328 } 329 async: 330 printf("%s: target %d asynchronous\n", 331 sc->sc_dev.dv_xname, target); 332 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 333 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 334 sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8); 335 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 336 siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN; 337 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR; 338 siop_cmd->siop_table->msg_out[3] = 0; 339 siop_cmd->siop_table->msg_out[4] = 0; 340 siop_cmd->siop_table->t_msgout.count= 341 htole32(MSG_EXT_SDTR_LEN + 2); 342 send_msgout = 1; 343 } 344 end: 345 #ifdef DEBUG 346 printf("id now 0x%x\n", sc->targets[target]->id); 347 #endif 348 siop_cmd->siop_table->id = htole32(sc->targets[target]->id); 349 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 350 (sc->targets[target]->id >> 24) & 0xff); 351 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 352 (sc->targets[target]->id >> 8) & 0xff); 353 if (send_msgout) { 354 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 355 return SIOP_NEG_MSGOUT; 356 } else { 357 return SIOP_NEG_ACK; 358 } 359 } 360 361 void 362 siop_minphys(bp) 363 struct buf *bp; 364 { 365 minphys(bp); 366 } 367 368 int 369 siop_ioctl(link, cmd, arg, flag, p) 370 struct scsipi_link *link; 371 u_long cmd; 372 caddr_t arg; 373 int flag; 374 struct proc *p; 375 { 376 struct siop_softc *sc = link->adapter_softc; 377 u_int8_t scntl1; 378 int s; 379 380 switch (cmd) { 381 case SCBUSIORESET: 382 s = splbio(); 383 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 384 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 385 scntl1 | SCNTL1_RST); 386 /* minimum 25 us, more time won't hurt */ 387 delay(100); 388 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 389 splx(s); 390 return (0); 391 default: 392 return (ENOTTY); 393 } 394 } 395 396 void 397 siop_sdp(siop_cmd) 398 struct siop_cmd *siop_cmd; 399 { 400 /* save data pointer. Handle async only for now */ 401 int offset, dbc, sstat; 402 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 403 scr_table_t *table; /* table to patch */ 404 405 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 406 == 0) 407 return; /* no data pointers to save */ 408 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 409 if (offset >= SIOP_NSG) { 410 printf("%s: bad offset in siop_sdp (%d)\n", 411 sc->sc_dev.dv_xname, offset); 412 return; 413 } 414 table = &siop_cmd->siop_table->data[offset]; 415 #ifdef DEBUG_DR 416 printf("sdp: offset %d count=%d addr=0x%x ", offset, 417 table->count, table->addr); 418 #endif 419 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 420 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 421 /* need to account stale data in FIFO */ 422 int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 423 if (sc->features & SF_CHIP_FIFO) { 424 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 425 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 426 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 427 } else { 428 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 429 } 430 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 431 if (sstat & SSTAT0_OLF) 432 dbc++; 433 if (sstat & SSTAT0_ORF) 434 dbc++; 435 if (siop_cmd->siop_target->flags & TARF_WIDE) { 436 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 437 SIOP_SSTAT2); 438 if (sstat & SSTAT2_OLF1) 439 dbc++; 440 if (sstat & SSTAT2_ORF1) 441 dbc++; 442 } 443 /* clear the FIFO */ 444 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 445 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 446 CTEST3_CLF); 447 } 448 table->addr = 449 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 450 table->count = htole32(dbc); 451 #ifdef DEBUG_DR 452 printf("now count=%d addr=0x%x\n", table->count, table->addr); 453 #endif 454 } 455 456 void 457 siop_clearfifo(sc) 458 struct siop_softc *sc; 459 { 460 int timeout = 0; 461 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 462 463 #ifdef DEBUG_INTR 464 printf("DMA fifo not empty !\n"); 465 #endif 466 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 467 ctest3 | CTEST3_CLF); 468 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 469 CTEST3_CLF) != 0) { 470 delay(1); 471 if (++timeout > 1000) { 472 printf("clear fifo failed\n"); 473 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 474 bus_space_read_1(sc->sc_rt, sc->sc_rh, 475 SIOP_CTEST3) & ~CTEST3_CLF); 476 return; 477 } 478 } 479 } 480
Indexes created Tue Sep 23 20:09:58 GMT 2025