siop_common.c revision 1.11
1 /* $NetBSD: siop_common.c,v 1.11 2000/10/23 23:18:10 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsi_message.h> 48 #include <dev/scsipi/scsipi_all.h> 49 50 #include <dev/scsipi/scsiconf.h> 51 52 #include <dev/ic/siopreg.h> 53 #include <dev/ic/siopvar.h> 54 #include <dev/ic/siopvar_common.h> 55 56 #undef DEBUG 57 #undef DEBUG_DR 58 59 void 60 siop_common_reset(sc) 61 struct siop_softc *sc; 62 { 63 u_int32_t stest3; 64 65 /* reset the chip */ 66 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 67 delay(1000); 68 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 69 70 /* init registers */ 71 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 72 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 73 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 74 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 76 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 78 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 80 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 82 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 84 (0xb << STIME0_SEL_SHIFT)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 86 sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 88 1 << sc->sc_link.scsipi_scsi.adapter_target); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 90 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 91 92 /* enable clock doubler or quadruler if appropriate */ 93 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 94 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 95 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 96 STEST1_DBLEN); 97 if (sc->features & SF_CHIP_QUAD) { 98 /* wait for PPL to lock */ 99 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 100 SIOP_STEST4) & STEST4_LOCK) == 0) 101 delay(10); 102 } else { 103 /* data sheet says 20us - more won't hurt */ 104 delay(100); 105 } 106 /* halt scsi clock, select doubler/quad, restart clock */ 107 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 108 stest3 | STEST3_HSC); 109 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 110 STEST1_DBLEN | STEST1_DBLSEL); 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 112 } else { 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 114 } 115 if (sc->features & SF_CHIP_FIFO) 116 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 117 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 118 CTEST5_DFS); 119 120 sc->sc_reset(sc); 121 } 122 123 /* prepare tables before sending a cmd */ 124 void 125 siop_setuptables(siop_cmd) 126 struct siop_cmd *siop_cmd; 127 { 128 int i; 129 struct siop_softc *sc = siop_cmd->siop_sc; 130 struct scsipi_xfer *xs = siop_cmd->xs; 131 int target = xs->sc_link->scsipi_scsi.target; 132 int lun = xs->sc_link->scsipi_scsi.lun; 133 134 siop_cmd->siop_tables.id = htole32(sc->targets[target]->id); 135 memset(siop_cmd->siop_tables.msg_out, 0, 8); 136 siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 1); 137 siop_cmd->siop_tables.t_msgout.count= htole32(1); 138 if (sc->targets[target]->status == TARST_ASYNC) { 139 if (sc->targets[target]->flags & TARF_WIDE) { 140 sc->targets[target]->status = TARST_WIDE_NEG; 141 siop_wdtr_msg(siop_cmd, 1, MSG_EXT_WDTR_BUS_16_BIT); 142 } else if (sc->targets[target]->flags & TARF_SYNC) { 143 sc->targets[target]->status = TARST_SYNC_NEG; 144 siop_sdtr_msg(siop_cmd, 1, sc->minsync, sc->maxoff); 145 } else { 146 sc->targets[target]->status = TARST_OK; 147 } 148 } else if (sc->targets[target]->status == TARST_OK && 149 (sc->targets[target]->flags & TARF_TAG) && 150 siop_cmd->status != CMDST_SENSE) { 151 siop_cmd->flags |= CMDFL_TAG; 152 } 153 siop_cmd->siop_tables.status = 154 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 155 156 siop_cmd->siop_tables.cmd.count = 157 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 158 siop_cmd->siop_tables.cmd.addr = 159 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 160 if ((xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) || 161 siop_cmd->status == CMDST_SENSE) { 162 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 163 siop_cmd->siop_tables.data[i].count = 164 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 165 siop_cmd->siop_tables.data[i].addr = 166 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 167 } 168 } 169 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 170 } 171 172 int 173 siop_wdtr_neg(siop_cmd) 174 struct siop_cmd *siop_cmd; 175 { 176 struct siop_softc *sc = siop_cmd->siop_sc; 177 struct siop_target *siop_target = siop_cmd->siop_target; 178 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 179 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 180 181 if (siop_target->status == TARST_WIDE_NEG) { 182 /* we initiated wide negotiation */ 183 switch (tables->msg_in[3]) { 184 case MSG_EXT_WDTR_BUS_8_BIT: 185 printf("%s: target %d using 8bit transfers\n", 186 sc->sc_dev.dv_xname, target); 187 siop_target->flags &= ~TARF_ISWIDE; 188 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 189 break; 190 case MSG_EXT_WDTR_BUS_16_BIT: 191 if (siop_target->flags & TARF_WIDE) { 192 printf("%s: target %d using 16bit transfers\n", 193 sc->sc_dev.dv_xname, target); 194 siop_target->flags |= TARF_ISWIDE; 195 sc->targets[target]->id |= (SCNTL3_EWS << 24); 196 break; 197 } 198 /* FALLTHROUH */ 199 default: 200 /* 201 * hum, we got more than what we can handle, shoudn't 202 * happen. Reject, and stay async 203 */ 204 siop_target->flags &= ~TARF_ISWIDE; 205 siop_target->status = TARST_OK; 206 printf("%s: rejecting invalid wide negotiation from " 207 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 208 tables->msg_in[3]); 209 tables->t_msgout.count= htole32(1); 210 tables->msg_out[0] = MSG_MESSAGE_REJECT; 211 return SIOP_NEG_MSGOUT; 212 } 213 tables->id = htole32(sc->targets[target]->id); 214 bus_space_write_1(sc->sc_rt, sc->sc_rh, 215 SIOP_SCNTL3, 216 (sc->targets[target]->id >> 24) & 0xff); 217 /* we now need to do sync */ 218 if (siop_target->flags & TARF_SYNC) { 219 siop_target->status = TARST_SYNC_NEG; 220 siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff); 221 return SIOP_NEG_MSGOUT; 222 } else { 223 siop_target->status = TARST_OK; 224 return SIOP_NEG_ACK; 225 } 226 } else { 227 /* target initiated wide negotiation */ 228 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 229 && (siop_target->flags & TARF_WIDE)) { 230 printf("%s: target %d using 16bit transfers\n", 231 sc->sc_dev.dv_xname, target); 232 siop_target->flags |= TARF_ISWIDE; 233 sc->targets[target]->id |= SCNTL3_EWS << 24; 234 } else { 235 printf("%s: target %d using 8bit transfers\n", 236 sc->sc_dev.dv_xname, target); 237 siop_target->flags &= ~TARF_ISWIDE; 238 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 239 } 240 tables->id = htole32(sc->targets[target]->id); 241 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 242 (sc->targets[target]->id >> 24) & 0xff); 243 /* 244 * we did reset wide parameters, so fall back to async, 245 * but don't schedule a sync neg, target should initiate it 246 */ 247 siop_target->status = TARST_OK; 248 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 249 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 250 return SIOP_NEG_MSGOUT; 251 } 252 } 253 254 int 255 siop_sdtr_neg(siop_cmd) 256 struct siop_cmd *siop_cmd; 257 { 258 struct siop_softc *sc = siop_cmd->siop_sc; 259 struct siop_target *siop_target = siop_cmd->siop_target; 260 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 261 int sync, offset, i; 262 int send_msgout = 0; 263 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 264 265 sync = tables->msg_in[3]; 266 offset = tables->msg_in[4]; 267 268 if (siop_target->status == TARST_SYNC_NEG) { 269 /* we initiated sync negotiation */ 270 siop_target->status = TARST_OK; 271 #ifdef DEBUG 272 printf("sdtr: sync %d offset %d\n", sync, offset); 273 #endif 274 if (offset > sc->maxoff || sync < sc->minsync || 275 sync > sc->maxsync) 276 goto reject; 277 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 278 i++) { 279 if (sc->clock_period != scf_period[i].clock) 280 continue; 281 if (scf_period[i].period == sync) { 282 /* ok, found it. we now are sync. */ 283 printf("%s: target %d now synchronous at " 284 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 285 target, scf_period[i].rate, offset); 286 sc->targets[target]->id &= 287 ~(SCNTL3_SCF_MASK << 24); 288 sc->targets[target]->id |= scf_period[i].scf 289 << (24 + SCNTL3_SCF_SHIFT); 290 if (sync < 25) /* Ultra */ 291 sc->targets[target]->id |= 292 SCNTL3_ULTRA << 24; 293 else 294 sc->targets[target]->id &= 295 ~(SCNTL3_ULTRA << 24); 296 sc->targets[target]->id &= 297 ~(SXFER_MO_MASK << 8); 298 sc->targets[target]->id |= 299 (offset & SXFER_MO_MASK) << 8; 300 goto end; 301 } 302 } 303 /* 304 * we didn't find it in our table, do async and send reject 305 * msg 306 */ 307 reject: 308 send_msgout = 1; 309 tables->t_msgout.count= htole32(1); 310 tables->msg_out[0] = MSG_MESSAGE_REJECT; 311 printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname, 312 target); 313 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 314 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 315 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 316 } else { /* target initiated sync neg */ 317 #ifdef DEBUG 318 printf("sdtr (target): sync %d offset %d\n", sync, offset); 319 #endif 320 if (offset == 0 || sync > sc->maxsync) { /* async */ 321 goto async; 322 } 323 if (offset > sc->maxoff) 324 offset = sc->maxoff; 325 if (sync < sc->minsync) 326 sync = sc->minsync; 327 /* look for sync period */ 328 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 329 i++) { 330 if (sc->clock_period != scf_period[i].clock) 331 continue; 332 if (scf_period[i].period == sync) { 333 /* ok, found it. we now are sync. */ 334 printf("%s: target %d now synchronous at " 335 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 336 target, scf_period[i].rate, offset); 337 sc->targets[target]->id &= 338 ~(SCNTL3_SCF_MASK << 24); 339 sc->targets[target]->id |= scf_period[i].scf 340 << (24 + SCNTL3_SCF_SHIFT); 341 if (sync < 25) /* Ultra */ 342 sc->targets[target]->id |= 343 SCNTL3_ULTRA << 24; 344 else 345 sc->targets[target]->id &= 346 ~(SCNTL3_ULTRA << 24); 347 sc->targets[target]->id &= 348 ~(SXFER_MO_MASK << 8); 349 sc->targets[target]->id |= 350 (offset & SXFER_MO_MASK) << 8; 351 siop_sdtr_msg(siop_cmd, 0, sync, offset); 352 send_msgout = 1; 353 goto end; 354 } 355 } 356 async: 357 printf("%s: target %d asynchronous\n", 358 sc->sc_dev.dv_xname, target); 359 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 360 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 361 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 362 siop_sdtr_msg(siop_cmd, 0, 0, 0); 363 send_msgout = 1; 364 } 365 end: 366 #ifdef DEBUG 367 printf("id now 0x%x\n", sc->targets[target]->id); 368 #endif 369 tables->id = htole32(sc->targets[target]->id); 370 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 371 (sc->targets[target]->id >> 24) & 0xff); 372 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 373 (sc->targets[target]->id >> 8) & 0xff); 374 if (send_msgout) { 375 return SIOP_NEG_MSGOUT; 376 } else { 377 return SIOP_NEG_ACK; 378 } 379 } 380 381 void 382 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 383 struct siop_cmd *siop_cmd; 384 int offset; 385 int ssync, soff; 386 { 387 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 388 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 389 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_SDTR; 390 siop_cmd->siop_tables.msg_out[offset + 3] = ssync; 391 siop_cmd->siop_tables.msg_out[offset + 4] = soff; 392 siop_cmd->siop_tables.t_msgout.count = 393 htole32(offset + MSG_EXT_SDTR_LEN + 2); 394 } 395 396 void 397 siop_wdtr_msg(siop_cmd, offset, wide) 398 struct siop_cmd *siop_cmd; 399 int offset; 400 { 401 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 402 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 403 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_WDTR; 404 siop_cmd->siop_tables.msg_out[offset + 3] = wide; 405 siop_cmd->siop_tables.t_msgout.count = 406 htole32(offset + MSG_EXT_WDTR_LEN + 2); 407 } 408 409 void 410 siop_minphys(bp) 411 struct buf *bp; 412 { 413 minphys(bp); 414 } 415 416 int 417 siop_ioctl(link, cmd, arg, flag, p) 418 struct scsipi_link *link; 419 u_long cmd; 420 caddr_t arg; 421 int flag; 422 struct proc *p; 423 { 424 struct siop_softc *sc = link->adapter_softc; 425 u_int8_t scntl1; 426 int s; 427 428 switch (cmd) { 429 case SCBUSACCEL: 430 { 431 struct scbusaccel_args *sp = (struct scbusaccel_args *)arg; 432 s = splbio(); 433 if (sp->sa_lun == 0) { 434 if (sp->sa_flags & SC_ACCEL_TAGS) { 435 sc->targets[sp->sa_target]->flags |= TARF_TAG; 436 printf("%s: target %d using tagged queuing\n", 437 sc->sc_dev.dv_xname, sp->sa_target); 438 } 439 if ((sp->sa_flags & SC_ACCEL_WIDE) && 440 (sc->features & SF_BUS_WIDE)) 441 sc->targets[sp->sa_target]->flags |= TARF_WIDE; 442 if (sp->sa_flags & SC_ACCEL_SYNC) 443 sc->targets[sp->sa_target]->flags |= TARF_SYNC; 444 if ((sp->sa_flags & (SC_ACCEL_SYNC | SC_ACCEL_WIDE)) || 445 sc->targets[sp->sa_target]->status == TARST_PROBING) 446 sc->targets[sp->sa_target]->status = 447 TARST_ASYNC; 448 } 449 450 /* allocate a lun sw entry for this device */ 451 siop_add_dev(sc, sp->sa_target, sp->sa_lun); 452 /* 453 * if we can to tagged queueing, inform upper layer 454 * we can have NIOP_NTAG concurent commands 455 */ 456 if (sc->targets[sp->sa_target]->flags & TARF_TAG) 457 link->openings = SIOP_NTAG; 458 splx(s); 459 return 0; 460 } 461 case SCBUSIORESET: 462 s = splbio(); 463 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 464 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 465 scntl1 | SCNTL1_RST); 466 /* minimum 25 us, more time won't hurt */ 467 delay(100); 468 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 469 splx(s); 470 return (0); 471 default: 472 return (ENOTTY); 473 } 474 } 475 476 void 477 siop_sdp(siop_cmd) 478 struct siop_cmd *siop_cmd; 479 { 480 /* save data pointer. Handle async only for now */ 481 int offset, dbc, sstat; 482 struct siop_softc *sc = siop_cmd->siop_sc; 483 scr_table_t *table; /* table to patch */ 484 485 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 486 == 0) 487 return; /* no data pointers to save */ 488 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 489 if (offset >= SIOP_NSG) { 490 printf("%s: bad offset in siop_sdp (%d)\n", 491 sc->sc_dev.dv_xname, offset); 492 return; 493 } 494 table = &siop_cmd->siop_xfer->tables.data[offset]; 495 #ifdef DEBUG_DR 496 printf("sdp: offset %d count=%d addr=0x%x ", offset, 497 table->count, table->addr); 498 #endif 499 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 500 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 501 /* need to account stale data in FIFO */ 502 int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 503 if (sc->features & SF_CHIP_FIFO) { 504 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 505 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 506 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 507 } else { 508 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 509 } 510 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 511 if (sstat & SSTAT0_OLF) 512 dbc++; 513 if (sstat & SSTAT0_ORF) 514 dbc++; 515 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 516 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 517 SIOP_SSTAT2); 518 if (sstat & SSTAT2_OLF1) 519 dbc++; 520 if (sstat & SSTAT2_ORF1) 521 dbc++; 522 } 523 /* clear the FIFO */ 524 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 525 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 526 CTEST3_CLF); 527 } 528 table->addr = 529 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 530 table->count = htole32(dbc); 531 #ifdef DEBUG_DR 532 printf("now count=%d addr=0x%x\n", table->count, table->addr); 533 #endif 534 } 535 536 void 537 siop_clearfifo(sc) 538 struct siop_softc *sc; 539 { 540 int timeout = 0; 541 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 542 543 #ifdef DEBUG_INTR 544 printf("DMA fifo not empty !\n"); 545 #endif 546 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 547 ctest3 | CTEST3_CLF); 548 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 549 CTEST3_CLF) != 0) { 550 delay(1); 551 if (++timeout > 1000) { 552 printf("clear fifo failed\n"); 553 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 554 bus_space_read_1(sc->sc_rt, sc->sc_rh, 555 SIOP_CTEST3) & ~CTEST3_CLF); 556 return; 557 } 558 } 559 } 560 561 int 562 siop_modechange(sc) 563 struct siop_softc *sc; 564 { 565 int retry; 566 int sist0, sist1, stest2, stest4; 567 for (retry = 0; retry < 5; retry++) { 568 /* 569 * datasheet says to wait 100ms and re-read SIST1, 570 * to check that DIFFSENSE is srable. 571 * We may delay() 5 times for 100ms at interrupt time; 572 * hopefully this will not happen often. 573 */ 574 delay(100000); 575 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 576 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 577 if (sist1 & SIEN1_SBMC) 578 continue; /* we got an irq again */ 579 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 580 STEST4_MODE_MASK; 581 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 582 switch(stest4) { 583 case STEST4_MODE_DIF: 584 printf("%s: switching to differential mode\n", 585 sc->sc_dev.dv_xname); 586 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 587 stest2 | STEST2_DIF); 588 break; 589 case STEST4_MODE_SE: 590 printf("%s: switching to single-ended mode\n", 591 sc->sc_dev.dv_xname); 592 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 593 stest2 & ~STEST2_DIF); 594 break; 595 case STEST4_MODE_LVD: 596 printf("%s: switching to LVD mode\n", 597 sc->sc_dev.dv_xname); 598 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 599 stest2 & ~STEST2_DIF); 600 break; 601 default: 602 printf("%s: invalid SCSI mode 0x%x\n", 603 sc->sc_dev.dv_xname, stest4); 604 return 0; 605 } 606 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 607 stest4 >> 2); 608 return 1; 609 } 610 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 611 sc->sc_dev.dv_xname); 612 return 0; 613 } 614 615 void 616 siop_resetbus(sc) 617 struct siop_softc *sc; 618 { 619 int scntl1; 620 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 621 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 622 scntl1 | SCNTL1_RST); 623 /* minimum 25 us, more time won't hurt */ 624 delay(100); 625 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 626 } 627
Indexes created Wed Sep 24 02:09:48 GMT 2025