siop_common.c revision 1.11.2.4
1 /* $NetBSD: siop_common.c,v 1.11.2.4 2000/12/15 07:48:33 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsi_message.h> 48 #include <dev/scsipi/scsipi_all.h> 49 50 #include <dev/scsipi/scsiconf.h> 51 52 #include <dev/ic/siopreg.h> 53 #include <dev/ic/siopvar.h> 54 #include <dev/ic/siopvar_common.h> 55 56 #undef DEBUG 57 #undef DEBUG_DR 58 59 void 60 siop_common_reset(sc) 61 struct siop_softc *sc; 62 { 63 u_int32_t stest3; 64 65 /* reset the chip */ 66 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 67 delay(1000); 68 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 69 70 /* init registers */ 71 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 72 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 73 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 74 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 76 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 78 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 80 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 82 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 84 (0xb << STIME0_SEL_SHIFT)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 86 sc->sc_chan.chan_id | SCID_RRE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 88 1 << sc->sc_chan.chan_id); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 90 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 91 92 /* enable clock doubler or quadruler if appropriate */ 93 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 94 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 95 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 96 STEST1_DBLEN); 97 if (sc->features & SF_CHIP_QUAD) { 98 /* wait for PPL to lock */ 99 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 100 SIOP_STEST4) & STEST4_LOCK) == 0) 101 delay(10); 102 } else { 103 /* data sheet says 20us - more won't hurt */ 104 delay(100); 105 } 106 /* halt scsi clock, select doubler/quad, restart clock */ 107 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 108 stest3 | STEST3_HSC); 109 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 110 STEST1_DBLEN | STEST1_DBLSEL); 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 112 } else { 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 114 } 115 if (sc->features & SF_CHIP_FIFO) 116 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 117 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 118 CTEST5_DFS); 119 120 sc->sc_reset(sc); 121 } 122 123 /* prepare tables before sending a cmd */ 124 void 125 siop_setuptables(siop_cmd) 126 struct siop_cmd *siop_cmd; 127 { 128 int i; 129 struct siop_softc *sc = siop_cmd->siop_sc; 130 struct scsipi_xfer *xs = siop_cmd->xs; 131 int target = xs->xs_periph->periph_target; 132 int lun = xs->xs_periph->periph_lun; 133 134 siop_cmd->siop_tables.id = htole32(sc->targets[target]->id); 135 memset(siop_cmd->siop_tables.msg_out, 0, 8); 136 siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 1); 137 siop_cmd->siop_tables.t_msgout.count= htole32(1); 138 if (sc->targets[target]->status == TARST_ASYNC) { 139 if (sc->targets[target]->flags & TARF_WIDE) { 140 sc->targets[target]->status = TARST_WIDE_NEG; 141 siop_wdtr_msg(siop_cmd, 1, MSG_EXT_WDTR_BUS_16_BIT); 142 } else if (sc->targets[target]->flags & TARF_SYNC) { 143 sc->targets[target]->status = TARST_SYNC_NEG; 144 siop_sdtr_msg(siop_cmd, 1, sc->minsync, sc->maxoff); 145 } else { 146 sc->targets[target]->status = TARST_OK; 147 siop_update_xfer_mode(sc, target); 148 } 149 } else if (sc->targets[target]->status == TARST_OK && 150 (sc->targets[target]->flags & TARF_TAG) && 151 siop_cmd->status != CMDST_SENSE && xs->xs_tag_type != 0) { 152 siop_cmd->flags |= CMDFL_TAG; 153 } 154 siop_cmd->siop_tables.status = 155 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 156 157 siop_cmd->siop_tables.cmd.count = 158 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 159 siop_cmd->siop_tables.cmd.addr = 160 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 161 if ((xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) || 162 siop_cmd->status == CMDST_SENSE) { 163 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 164 siop_cmd->siop_tables.data[i].count = 165 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 166 siop_cmd->siop_tables.data[i].addr = 167 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 168 } 169 } 170 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 171 } 172 173 int 174 siop_wdtr_neg(siop_cmd) 175 struct siop_cmd *siop_cmd; 176 { 177 struct siop_softc *sc = siop_cmd->siop_sc; 178 struct siop_target *siop_target = siop_cmd->siop_target; 179 int target = siop_cmd->xs->xs_periph->periph_target; 180 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 181 182 if (siop_target->status == TARST_WIDE_NEG) { 183 /* we initiated wide negotiation */ 184 switch (tables->msg_in[3]) { 185 case MSG_EXT_WDTR_BUS_8_BIT: 186 siop_target->flags &= ~TARF_ISWIDE; 187 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 188 break; 189 case MSG_EXT_WDTR_BUS_16_BIT: 190 if (siop_target->flags & TARF_WIDE) { 191 siop_target->flags |= TARF_ISWIDE; 192 sc->targets[target]->id |= (SCNTL3_EWS << 24); 193 break; 194 } 195 /* FALLTHROUH */ 196 default: 197 /* 198 * hum, we got more than what we can handle, shoudn't 199 * happen. Reject, and stay async 200 */ 201 siop_target->flags &= ~TARF_ISWIDE; 202 siop_target->status = TARST_OK; 203 siop_target->offset = siop_target->period = 0; 204 siop_update_xfer_mode(sc, target); 205 printf("%s: rejecting invalid wide negotiation from " 206 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 207 tables->msg_in[3]); 208 tables->t_msgout.count= htole32(1); 209 tables->msg_out[0] = MSG_MESSAGE_REJECT; 210 return SIOP_NEG_MSGOUT; 211 } 212 tables->id = htole32(sc->targets[target]->id); 213 bus_space_write_1(sc->sc_rt, sc->sc_rh, 214 SIOP_SCNTL3, 215 (sc->targets[target]->id >> 24) & 0xff); 216 /* we now need to do sync */ 217 if (siop_target->flags & TARF_SYNC) { 218 siop_target->status = TARST_SYNC_NEG; 219 siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff); 220 return SIOP_NEG_MSGOUT; 221 } else { 222 siop_target->status = TARST_OK; 223 siop_update_xfer_mode(sc, target); 224 return SIOP_NEG_ACK; 225 } 226 } else { 227 /* target initiated wide negotiation */ 228 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 229 && (siop_target->flags & TARF_WIDE)) { 230 siop_target->flags |= TARF_ISWIDE; 231 sc->targets[target]->id |= SCNTL3_EWS << 24; 232 } else { 233 siop_target->flags &= ~TARF_ISWIDE; 234 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 235 } 236 tables->id = htole32(sc->targets[target]->id); 237 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 238 (sc->targets[target]->id >> 24) & 0xff); 239 /* 240 * we did reset wide parameters, so fall back to async, 241 * but don't schedule a sync neg, target should initiate it 242 */ 243 siop_target->status = TARST_OK; 244 siop_target->offset = siop_target->period = 0; 245 siop_update_xfer_mode(sc, target); 246 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 247 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 248 return SIOP_NEG_MSGOUT; 249 } 250 } 251 252 int 253 siop_sdtr_neg(siop_cmd) 254 struct siop_cmd *siop_cmd; 255 { 256 struct siop_softc *sc = siop_cmd->siop_sc; 257 struct siop_target *siop_target = siop_cmd->siop_target; 258 int target = siop_cmd->xs->xs_periph->periph_target; 259 int sync, offset, i; 260 int send_msgout = 0; 261 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 262 263 sync = tables->msg_in[3]; 264 offset = tables->msg_in[4]; 265 266 if (siop_target->status == TARST_SYNC_NEG) { 267 /* we initiated sync negotiation */ 268 siop_target->status = TARST_OK; 269 #ifdef DEBUG 270 printf("sdtr: sync %d offset %d\n", sync, offset); 271 #endif 272 if (offset > sc->maxoff || sync < sc->minsync || 273 sync > sc->maxsync) 274 goto reject; 275 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 276 i++) { 277 if (sc->clock_period != scf_period[i].clock) 278 continue; 279 if (scf_period[i].period == sync) { 280 /* ok, found it. we now are sync. */ 281 siop_target->offset = offset; 282 siop_target->period = sync; 283 sc->targets[target]->id &= 284 ~(SCNTL3_SCF_MASK << 24); 285 sc->targets[target]->id |= scf_period[i].scf 286 << (24 + SCNTL3_SCF_SHIFT); 287 if (sync < 25) /* Ultra */ 288 sc->targets[target]->id |= 289 SCNTL3_ULTRA << 24; 290 else 291 sc->targets[target]->id &= 292 ~(SCNTL3_ULTRA << 24); 293 sc->targets[target]->id &= 294 ~(SXFER_MO_MASK << 8); 295 sc->targets[target]->id |= 296 (offset & SXFER_MO_MASK) << 8; 297 goto end; 298 } 299 } 300 /* 301 * we didn't find it in our table, do async and send reject 302 * msg 303 */ 304 reject: 305 send_msgout = 1; 306 tables->t_msgout.count= htole32(1); 307 tables->msg_out[0] = MSG_MESSAGE_REJECT; 308 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 309 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 310 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 311 siop_target->offset = siop_target->period = 0; 312 } else { /* target initiated sync neg */ 313 #ifdef DEBUG 314 printf("sdtr (target): sync %d offset %d\n", sync, offset); 315 #endif 316 if (offset == 0 || sync > sc->maxsync) { /* async */ 317 goto async; 318 } 319 if (offset > sc->maxoff) 320 offset = sc->maxoff; 321 if (sync < sc->minsync) 322 sync = sc->minsync; 323 /* look for sync period */ 324 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 325 i++) { 326 if (sc->clock_period != scf_period[i].clock) 327 continue; 328 if (scf_period[i].period == sync) { 329 /* ok, found it. we now are sync. */ 330 siop_target->offset = offset; 331 siop_target->period = sync; 332 sc->targets[target]->id &= 333 ~(SCNTL3_SCF_MASK << 24); 334 sc->targets[target]->id |= scf_period[i].scf 335 << (24 + SCNTL3_SCF_SHIFT); 336 if (sync < 25) /* Ultra */ 337 sc->targets[target]->id |= 338 SCNTL3_ULTRA << 24; 339 else 340 sc->targets[target]->id &= 341 ~(SCNTL3_ULTRA << 24); 342 sc->targets[target]->id &= 343 ~(SXFER_MO_MASK << 8); 344 sc->targets[target]->id |= 345 (offset & SXFER_MO_MASK) << 8; 346 siop_sdtr_msg(siop_cmd, 0, sync, offset); 347 send_msgout = 1; 348 goto end; 349 } 350 } 351 async: 352 siop_target->offset = siop_target->period = 0; 353 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 354 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 355 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 356 siop_sdtr_msg(siop_cmd, 0, 0, 0); 357 send_msgout = 1; 358 } 359 end: 360 if (siop_target->status == TARST_OK) 361 siop_update_xfer_mode(sc, target); 362 #ifdef DEBUG 363 printf("id now 0x%x\n", sc->targets[target]->id); 364 #endif 365 tables->id = htole32(sc->targets[target]->id); 366 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 367 (sc->targets[target]->id >> 24) & 0xff); 368 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 369 (sc->targets[target]->id >> 8) & 0xff); 370 if (send_msgout) { 371 return SIOP_NEG_MSGOUT; 372 } else { 373 return SIOP_NEG_ACK; 374 } 375 } 376 377 void 378 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 379 struct siop_cmd *siop_cmd; 380 int offset; 381 int ssync, soff; 382 { 383 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 384 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 385 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_SDTR; 386 siop_cmd->siop_tables.msg_out[offset + 3] = ssync; 387 siop_cmd->siop_tables.msg_out[offset + 4] = soff; 388 siop_cmd->siop_tables.t_msgout.count = 389 htole32(offset + MSG_EXT_SDTR_LEN + 2); 390 } 391 392 void 393 siop_wdtr_msg(siop_cmd, offset, wide) 394 struct siop_cmd *siop_cmd; 395 int offset; 396 { 397 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 398 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 399 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_WDTR; 400 siop_cmd->siop_tables.msg_out[offset + 3] = wide; 401 siop_cmd->siop_tables.t_msgout.count = 402 htole32(offset + MSG_EXT_WDTR_LEN + 2); 403 } 404 405 void 406 siop_minphys(bp) 407 struct buf *bp; 408 { 409 minphys(bp); 410 } 411 412 int 413 siop_ioctl(chan, cmd, arg, flag, p) 414 struct scsipi_channel *chan; 415 u_long cmd; 416 caddr_t arg; 417 int flag; 418 struct proc *p; 419 { 420 struct siop_softc *sc = (void *)chan->chan_adapter->adapt_dev; 421 u_int8_t scntl1; 422 int s; 423 424 switch (cmd) { 425 case SCBUSIORESET: 426 s = splbio(); 427 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 428 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 429 scntl1 | SCNTL1_RST); 430 /* minimum 25 us, more time won't hurt */ 431 delay(100); 432 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 433 splx(s); 434 return (0); 435 default: 436 return (ENOTTY); 437 } 438 } 439 440 void 441 siop_sdp(siop_cmd) 442 struct siop_cmd *siop_cmd; 443 { 444 /* save data pointer. Handle async only for now */ 445 int offset, dbc, sstat; 446 struct siop_softc *sc = siop_cmd->siop_sc; 447 scr_table_t *table; /* table to patch */ 448 449 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 450 == 0) 451 return; /* no data pointers to save */ 452 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 453 if (offset >= SIOP_NSG) { 454 printf("%s: bad offset in siop_sdp (%d)\n", 455 sc->sc_dev.dv_xname, offset); 456 return; 457 } 458 table = &siop_cmd->siop_xfer->tables.data[offset]; 459 #ifdef DEBUG_DR 460 printf("sdp: offset %d count=%d addr=0x%x ", offset, 461 table->count, table->addr); 462 #endif 463 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 464 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 465 /* need to account stale data in FIFO */ 466 int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 467 if (sc->features & SF_CHIP_FIFO) { 468 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 469 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 470 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 471 } else { 472 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 473 } 474 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 475 if (sstat & SSTAT0_OLF) 476 dbc++; 477 if (sstat & SSTAT0_ORF) 478 dbc++; 479 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 480 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 481 SIOP_SSTAT2); 482 if (sstat & SSTAT2_OLF1) 483 dbc++; 484 if (sstat & SSTAT2_ORF1) 485 dbc++; 486 } 487 /* clear the FIFO */ 488 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 489 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 490 CTEST3_CLF); 491 } 492 table->addr = 493 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 494 table->count = htole32(dbc); 495 #ifdef DEBUG_DR 496 printf("now count=%d addr=0x%x\n", table->count, table->addr); 497 #endif 498 } 499 500 void 501 siop_clearfifo(sc) 502 struct siop_softc *sc; 503 { 504 int timeout = 0; 505 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 506 507 #ifdef DEBUG_INTR 508 printf("DMA fifo not empty !\n"); 509 #endif 510 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 511 ctest3 | CTEST3_CLF); 512 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 513 CTEST3_CLF) != 0) { 514 delay(1); 515 if (++timeout > 1000) { 516 printf("clear fifo failed\n"); 517 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 518 bus_space_read_1(sc->sc_rt, sc->sc_rh, 519 SIOP_CTEST3) & ~CTEST3_CLF); 520 return; 521 } 522 } 523 } 524 525 int 526 siop_modechange(sc) 527 struct siop_softc *sc; 528 { 529 int retry; 530 int sist0, sist1, stest2, stest4; 531 for (retry = 0; retry < 5; retry++) { 532 /* 533 * datasheet says to wait 100ms and re-read SIST1, 534 * to check that DIFFSENSE is srable. 535 * We may delay() 5 times for 100ms at interrupt time; 536 * hopefully this will not happen often. 537 */ 538 delay(100000); 539 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 540 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 541 if (sist1 & SIEN1_SBMC) 542 continue; /* we got an irq again */ 543 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 544 STEST4_MODE_MASK; 545 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 546 switch(stest4) { 547 case STEST4_MODE_DIF: 548 printf("%s: switching to differential mode\n", 549 sc->sc_dev.dv_xname); 550 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 551 stest2 | STEST2_DIF); 552 break; 553 case STEST4_MODE_SE: 554 printf("%s: switching to single-ended mode\n", 555 sc->sc_dev.dv_xname); 556 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 557 stest2 & ~STEST2_DIF); 558 break; 559 case STEST4_MODE_LVD: 560 printf("%s: switching to LVD mode\n", 561 sc->sc_dev.dv_xname); 562 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 563 stest2 & ~STEST2_DIF); 564 break; 565 default: 566 printf("%s: invalid SCSI mode 0x%x\n", 567 sc->sc_dev.dv_xname, stest4); 568 return 0; 569 } 570 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 571 stest4 >> 2); 572 return 1; 573 } 574 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 575 sc->sc_dev.dv_xname); 576 return 0; 577 } 578 579 void 580 siop_resetbus(sc) 581 struct siop_softc *sc; 582 { 583 int scntl1; 584 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 585 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 586 scntl1 | SCNTL1_RST); 587 /* minimum 25 us, more time won't hurt */ 588 delay(100); 589 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 590 } 591
Indexes created Sun Oct 12 05:10:08 GMT 2025