siop_common.c revision 1.11.2.5
1 /* $NetBSD: siop_common.c,v 1.11.2.5 2001/01/15 09:26:26 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsi_message.h> 48 #include <dev/scsipi/scsipi_all.h> 49 50 #include <dev/scsipi/scsiconf.h> 51 52 #include <dev/ic/siopreg.h> 53 #include <dev/ic/siopvar.h> 54 #include <dev/ic/siopvar_common.h> 55 56 #undef DEBUG 57 #undef DEBUG_DR 58 59 void 60 siop_common_reset(sc) 61 struct siop_softc *sc; 62 { 63 u_int32_t stest3; 64 65 /* reset the chip */ 66 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 67 delay(1000); 68 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 69 70 /* init registers */ 71 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 72 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 73 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 74 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 76 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 78 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 80 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 82 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 84 (0xb << STIME0_SEL_SHIFT)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 86 sc->sc_chan.chan_id | SCID_RRE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 88 1 << sc->sc_chan.chan_id); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 90 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 91 92 /* enable clock doubler or quadruler if appropriate */ 93 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 94 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 95 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 96 STEST1_DBLEN); 97 if (sc->features & SF_CHIP_QUAD) { 98 /* wait for PPL to lock */ 99 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 100 SIOP_STEST4) & STEST4_LOCK) == 0) 101 delay(10); 102 } else { 103 /* data sheet says 20us - more won't hurt */ 104 delay(100); 105 } 106 /* halt scsi clock, select doubler/quad, restart clock */ 107 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 108 stest3 | STEST3_HSC); 109 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 110 STEST1_DBLEN | STEST1_DBLSEL); 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 112 } else { 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 114 } 115 if (sc->features & SF_CHIP_FIFO) 116 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 117 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 118 CTEST5_DFS); 119 120 sc->sc_reset(sc); 121 } 122 123 /* prepare tables before sending a cmd */ 124 void 125 siop_setuptables(siop_cmd) 126 struct siop_cmd *siop_cmd; 127 { 128 int i; 129 struct siop_softc *sc = siop_cmd->siop_sc; 130 struct scsipi_xfer *xs = siop_cmd->xs; 131 int target = xs->xs_periph->periph_target; 132 int lun = xs->xs_periph->periph_lun; 133 134 siop_cmd->siop_tables.id = htole32(sc->targets[target]->id); 135 memset(siop_cmd->siop_tables.msg_out, 0, 8); 136 siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 1); 137 siop_cmd->siop_tables.t_msgout.count= htole32(1); 138 if (sc->targets[target]->status == TARST_ASYNC) { 139 if (sc->targets[target]->flags & TARF_WIDE) { 140 sc->targets[target]->status = TARST_WIDE_NEG; 141 siop_wdtr_msg(siop_cmd, 1, MSG_EXT_WDTR_BUS_16_BIT); 142 } else if (sc->targets[target]->flags & TARF_SYNC) { 143 sc->targets[target]->status = TARST_SYNC_NEG; 144 siop_sdtr_msg(siop_cmd, 1, sc->minsync, sc->maxoff); 145 } else { 146 sc->targets[target]->status = TARST_OK; 147 siop_update_xfer_mode(sc, target); 148 } 149 } else if (sc->targets[target]->status == TARST_OK && 150 (sc->targets[target]->flags & TARF_TAG) && xs->xs_tag_type != 0) { 151 siop_cmd->flags |= CMDFL_TAG; 152 } 153 siop_cmd->siop_tables.status = 154 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 155 156 siop_cmd->siop_tables.cmd.count = 157 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 158 siop_cmd->siop_tables.cmd.addr = 159 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 160 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 161 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 162 siop_cmd->siop_tables.data[i].count = 163 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 164 siop_cmd->siop_tables.data[i].addr = 165 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 166 } 167 } 168 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 169 } 170 171 int 172 siop_wdtr_neg(siop_cmd) 173 struct siop_cmd *siop_cmd; 174 { 175 struct siop_softc *sc = siop_cmd->siop_sc; 176 struct siop_target *siop_target = siop_cmd->siop_target; 177 int target = siop_cmd->xs->xs_periph->periph_target; 178 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 179 180 if (siop_target->status == TARST_WIDE_NEG) { 181 /* we initiated wide negotiation */ 182 switch (tables->msg_in[3]) { 183 case MSG_EXT_WDTR_BUS_8_BIT: 184 siop_target->flags &= ~TARF_ISWIDE; 185 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 186 break; 187 case MSG_EXT_WDTR_BUS_16_BIT: 188 if (siop_target->flags & TARF_WIDE) { 189 siop_target->flags |= TARF_ISWIDE; 190 sc->targets[target]->id |= (SCNTL3_EWS << 24); 191 break; 192 } 193 /* FALLTHROUH */ 194 default: 195 /* 196 * hum, we got more than what we can handle, shoudn't 197 * happen. Reject, and stay async 198 */ 199 siop_target->flags &= ~TARF_ISWIDE; 200 siop_target->status = TARST_OK; 201 siop_target->offset = siop_target->period = 0; 202 siop_update_xfer_mode(sc, target); 203 printf("%s: rejecting invalid wide negotiation from " 204 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 205 tables->msg_in[3]); 206 tables->t_msgout.count= htole32(1); 207 tables->msg_out[0] = MSG_MESSAGE_REJECT; 208 return SIOP_NEG_MSGOUT; 209 } 210 tables->id = htole32(sc->targets[target]->id); 211 bus_space_write_1(sc->sc_rt, sc->sc_rh, 212 SIOP_SCNTL3, 213 (sc->targets[target]->id >> 24) & 0xff); 214 /* we now need to do sync */ 215 if (siop_target->flags & TARF_SYNC) { 216 siop_target->status = TARST_SYNC_NEG; 217 siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff); 218 return SIOP_NEG_MSGOUT; 219 } else { 220 siop_target->status = TARST_OK; 221 siop_update_xfer_mode(sc, target); 222 return SIOP_NEG_ACK; 223 } 224 } else { 225 /* target initiated wide negotiation */ 226 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 227 && (siop_target->flags & TARF_WIDE)) { 228 siop_target->flags |= TARF_ISWIDE; 229 sc->targets[target]->id |= SCNTL3_EWS << 24; 230 } else { 231 siop_target->flags &= ~TARF_ISWIDE; 232 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 233 } 234 tables->id = htole32(sc->targets[target]->id); 235 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 236 (sc->targets[target]->id >> 24) & 0xff); 237 /* 238 * we did reset wide parameters, so fall back to async, 239 * but don't schedule a sync neg, target should initiate it 240 */ 241 siop_target->status = TARST_OK; 242 siop_target->offset = siop_target->period = 0; 243 siop_update_xfer_mode(sc, target); 244 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 245 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 246 return SIOP_NEG_MSGOUT; 247 } 248 } 249 250 int 251 siop_sdtr_neg(siop_cmd) 252 struct siop_cmd *siop_cmd; 253 { 254 struct siop_softc *sc = siop_cmd->siop_sc; 255 struct siop_target *siop_target = siop_cmd->siop_target; 256 int target = siop_cmd->xs->xs_periph->periph_target; 257 int sync, offset, i; 258 int send_msgout = 0; 259 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 260 261 sync = tables->msg_in[3]; 262 offset = tables->msg_in[4]; 263 264 if (siop_target->status == TARST_SYNC_NEG) { 265 /* we initiated sync negotiation */ 266 siop_target->status = TARST_OK; 267 #ifdef DEBUG 268 printf("sdtr: sync %d offset %d\n", sync, offset); 269 #endif 270 if (offset > sc->maxoff || sync < sc->minsync || 271 sync > sc->maxsync) 272 goto reject; 273 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 274 i++) { 275 if (sc->clock_period != scf_period[i].clock) 276 continue; 277 if (scf_period[i].period == sync) { 278 /* ok, found it. we now are sync. */ 279 siop_target->offset = offset; 280 siop_target->period = sync; 281 sc->targets[target]->id &= 282 ~(SCNTL3_SCF_MASK << 24); 283 sc->targets[target]->id |= scf_period[i].scf 284 << (24 + SCNTL3_SCF_SHIFT); 285 if (sync < 25) /* Ultra */ 286 sc->targets[target]->id |= 287 SCNTL3_ULTRA << 24; 288 else 289 sc->targets[target]->id &= 290 ~(SCNTL3_ULTRA << 24); 291 sc->targets[target]->id &= 292 ~(SXFER_MO_MASK << 8); 293 sc->targets[target]->id |= 294 (offset & SXFER_MO_MASK) << 8; 295 goto end; 296 } 297 } 298 /* 299 * we didn't find it in our table, do async and send reject 300 * msg 301 */ 302 reject: 303 send_msgout = 1; 304 tables->t_msgout.count= htole32(1); 305 tables->msg_out[0] = MSG_MESSAGE_REJECT; 306 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 307 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 308 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 309 siop_target->offset = siop_target->period = 0; 310 } else { /* target initiated sync neg */ 311 #ifdef DEBUG 312 printf("sdtr (target): sync %d offset %d\n", sync, offset); 313 #endif 314 if (offset == 0 || sync > sc->maxsync) { /* async */ 315 goto async; 316 } 317 if (offset > sc->maxoff) 318 offset = sc->maxoff; 319 if (sync < sc->minsync) 320 sync = sc->minsync; 321 /* look for sync period */ 322 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 323 i++) { 324 if (sc->clock_period != scf_period[i].clock) 325 continue; 326 if (scf_period[i].period == sync) { 327 /* ok, found it. we now are sync. */ 328 siop_target->offset = offset; 329 siop_target->period = sync; 330 sc->targets[target]->id &= 331 ~(SCNTL3_SCF_MASK << 24); 332 sc->targets[target]->id |= scf_period[i].scf 333 << (24 + SCNTL3_SCF_SHIFT); 334 if (sync < 25) /* Ultra */ 335 sc->targets[target]->id |= 336 SCNTL3_ULTRA << 24; 337 else 338 sc->targets[target]->id &= 339 ~(SCNTL3_ULTRA << 24); 340 sc->targets[target]->id &= 341 ~(SXFER_MO_MASK << 8); 342 sc->targets[target]->id |= 343 (offset & SXFER_MO_MASK) << 8; 344 siop_sdtr_msg(siop_cmd, 0, sync, offset); 345 send_msgout = 1; 346 goto end; 347 } 348 } 349 async: 350 siop_target->offset = siop_target->period = 0; 351 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 352 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 353 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 354 siop_sdtr_msg(siop_cmd, 0, 0, 0); 355 send_msgout = 1; 356 } 357 end: 358 if (siop_target->status == TARST_OK) 359 siop_update_xfer_mode(sc, target); 360 #ifdef DEBUG 361 printf("id now 0x%x\n", sc->targets[target]->id); 362 #endif 363 tables->id = htole32(sc->targets[target]->id); 364 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 365 (sc->targets[target]->id >> 24) & 0xff); 366 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 367 (sc->targets[target]->id >> 8) & 0xff); 368 if (send_msgout) { 369 return SIOP_NEG_MSGOUT; 370 } else { 371 return SIOP_NEG_ACK; 372 } 373 } 374 375 void 376 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 377 struct siop_cmd *siop_cmd; 378 int offset; 379 int ssync, soff; 380 { 381 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 382 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 383 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_SDTR; 384 siop_cmd->siop_tables.msg_out[offset + 3] = ssync; 385 siop_cmd->siop_tables.msg_out[offset + 4] = soff; 386 siop_cmd->siop_tables.t_msgout.count = 387 htole32(offset + MSG_EXT_SDTR_LEN + 2); 388 } 389 390 void 391 siop_wdtr_msg(siop_cmd, offset, wide) 392 struct siop_cmd *siop_cmd; 393 int offset; 394 { 395 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 396 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 397 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_WDTR; 398 siop_cmd->siop_tables.msg_out[offset + 3] = wide; 399 siop_cmd->siop_tables.t_msgout.count = 400 htole32(offset + MSG_EXT_WDTR_LEN + 2); 401 } 402 403 void 404 siop_minphys(bp) 405 struct buf *bp; 406 { 407 minphys(bp); 408 } 409 410 int 411 siop_ioctl(chan, cmd, arg, flag, p) 412 struct scsipi_channel *chan; 413 u_long cmd; 414 caddr_t arg; 415 int flag; 416 struct proc *p; 417 { 418 struct siop_softc *sc = (void *)chan->chan_adapter->adapt_dev; 419 u_int8_t scntl1; 420 int s; 421 422 switch (cmd) { 423 case SCBUSIORESET: 424 s = splbio(); 425 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 426 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 427 scntl1 | SCNTL1_RST); 428 /* minimum 25 us, more time won't hurt */ 429 delay(100); 430 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 431 splx(s); 432 return (0); 433 default: 434 return (ENOTTY); 435 } 436 } 437 438 void 439 siop_sdp(siop_cmd) 440 struct siop_cmd *siop_cmd; 441 { 442 /* save data pointer. Handle async only for now */ 443 int offset, dbc, sstat; 444 struct siop_softc *sc = siop_cmd->siop_sc; 445 scr_table_t *table; /* table to patch */ 446 447 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 448 == 0) 449 return; /* no data pointers to save */ 450 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 451 if (offset >= SIOP_NSG) { 452 printf("%s: bad offset in siop_sdp (%d)\n", 453 sc->sc_dev.dv_xname, offset); 454 return; 455 } 456 table = &siop_cmd->siop_xfer->tables.data[offset]; 457 #ifdef DEBUG_DR 458 printf("sdp: offset %d count=%d addr=0x%x ", offset, 459 table->count, table->addr); 460 #endif 461 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 462 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 463 /* need to account stale data in FIFO */ 464 int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 465 if (sc->features & SF_CHIP_FIFO) { 466 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 467 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 468 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 469 } else { 470 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 471 } 472 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 473 if (sstat & SSTAT0_OLF) 474 dbc++; 475 if (sstat & SSTAT0_ORF) 476 dbc++; 477 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 478 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 479 SIOP_SSTAT2); 480 if (sstat & SSTAT2_OLF1) 481 dbc++; 482 if (sstat & SSTAT2_ORF1) 483 dbc++; 484 } 485 /* clear the FIFO */ 486 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 487 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 488 CTEST3_CLF); 489 } 490 table->addr = 491 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 492 table->count = htole32(dbc); 493 #ifdef DEBUG_DR 494 printf("now count=%d addr=0x%x\n", table->count, table->addr); 495 #endif 496 } 497 498 void 499 siop_clearfifo(sc) 500 struct siop_softc *sc; 501 { 502 int timeout = 0; 503 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 504 505 #ifdef DEBUG_INTR 506 printf("DMA fifo not empty !\n"); 507 #endif 508 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 509 ctest3 | CTEST3_CLF); 510 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 511 CTEST3_CLF) != 0) { 512 delay(1); 513 if (++timeout > 1000) { 514 printf("clear fifo failed\n"); 515 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 516 bus_space_read_1(sc->sc_rt, sc->sc_rh, 517 SIOP_CTEST3) & ~CTEST3_CLF); 518 return; 519 } 520 } 521 } 522 523 int 524 siop_modechange(sc) 525 struct siop_softc *sc; 526 { 527 int retry; 528 int sist0, sist1, stest2, stest4; 529 for (retry = 0; retry < 5; retry++) { 530 /* 531 * datasheet says to wait 100ms and re-read SIST1, 532 * to check that DIFFSENSE is stable. 533 * We may delay() 5 times for 100ms at interrupt time; 534 * hopefully this will not happen often. 535 */ 536 delay(100000); 537 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 538 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 539 if (sist1 & SIEN1_SBMC) 540 continue; /* we got an irq again */ 541 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 542 STEST4_MODE_MASK; 543 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 544 switch(stest4) { 545 case STEST4_MODE_DIF: 546 printf("%s: switching to differential mode\n", 547 sc->sc_dev.dv_xname); 548 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 549 stest2 | STEST2_DIF); 550 break; 551 case STEST4_MODE_SE: 552 printf("%s: switching to single-ended mode\n", 553 sc->sc_dev.dv_xname); 554 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 555 stest2 & ~STEST2_DIF); 556 break; 557 case STEST4_MODE_LVD: 558 printf("%s: switching to LVD mode\n", 559 sc->sc_dev.dv_xname); 560 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 561 stest2 & ~STEST2_DIF); 562 break; 563 default: 564 printf("%s: invalid SCSI mode 0x%x\n", 565 sc->sc_dev.dv_xname, stest4); 566 return 0; 567 } 568 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 569 stest4 >> 2); 570 return 1; 571 } 572 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 573 sc->sc_dev.dv_xname); 574 return 0; 575 } 576 577 void 578 siop_resetbus(sc) 579 struct siop_softc *sc; 580 { 581 int scntl1; 582 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 583 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 584 scntl1 | SCNTL1_RST); 585 /* minimum 25 us, more time won't hurt */ 586 delay(100); 587 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 588 } 589
Indexes created Sun Oct 12 05:10:08 GMT 2025