siop_common.c revision 1.11.2.6
1 /* $NetBSD: siop_common.c,v 1.11.2.6 2001/01/22 17:46:32 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsi_message.h> 48 #include <dev/scsipi/scsipi_all.h> 49 50 #include <dev/scsipi/scsiconf.h> 51 52 #include <dev/ic/siopreg.h> 53 #include <dev/ic/siopvar.h> 54 #include <dev/ic/siopvar_common.h> 55 56 #undef DEBUG 57 #undef DEBUG_DR 58 59 void 60 siop_common_reset(sc) 61 struct siop_softc *sc; 62 { 63 u_int32_t stest3; 64 65 /* reset the chip */ 66 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 67 delay(1000); 68 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 69 70 /* init registers */ 71 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 72 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 73 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 74 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 76 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 78 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 80 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 82 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 84 (0xb << STIME0_SEL_SHIFT)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 86 sc->sc_chan.chan_id | SCID_RRE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 88 1 << sc->sc_chan.chan_id); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 90 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 91 92 /* enable clock doubler or quadruler if appropriate */ 93 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 94 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 95 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 96 STEST1_DBLEN); 97 if (sc->features & SF_CHIP_QUAD) { 98 /* wait for PPL to lock */ 99 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 100 SIOP_STEST4) & STEST4_LOCK) == 0) 101 delay(10); 102 } else { 103 /* data sheet says 20us - more won't hurt */ 104 delay(100); 105 } 106 /* halt scsi clock, select doubler/quad, restart clock */ 107 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 108 stest3 | STEST3_HSC); 109 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 110 STEST1_DBLEN | STEST1_DBLSEL); 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 112 } else { 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 114 } 115 if (sc->features & SF_CHIP_FIFO) 116 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 117 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 118 CTEST5_DFS); 119 120 sc->sc_reset(sc); 121 } 122 123 /* prepare tables before sending a cmd */ 124 void 125 siop_setuptables(siop_cmd) 126 struct siop_cmd *siop_cmd; 127 { 128 int i; 129 struct siop_softc *sc = siop_cmd->siop_sc; 130 struct scsipi_xfer *xs = siop_cmd->xs; 131 int target = xs->xs_periph->periph_target; 132 int lun = xs->xs_periph->periph_lun; 133 134 siop_cmd->siop_tables.id = htole32(sc->targets[target]->id); 135 memset(siop_cmd->siop_tables.msg_out, 0, 8); 136 /* request sense doesn't disconnect */ 137 if (xs->xs_control & XS_CTL_REQSENSE) 138 siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 0); 139 else 140 siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 1); 141 siop_cmd->siop_tables.t_msgout.count= htole32(1); 142 if (sc->targets[target]->status == TARST_ASYNC) { 143 if (sc->targets[target]->flags & TARF_WIDE) { 144 sc->targets[target]->status = TARST_WIDE_NEG; 145 siop_wdtr_msg(siop_cmd, 1, MSG_EXT_WDTR_BUS_16_BIT); 146 } else if (sc->targets[target]->flags & TARF_SYNC) { 147 sc->targets[target]->status = TARST_SYNC_NEG; 148 siop_sdtr_msg(siop_cmd, 1, sc->minsync, sc->maxoff); 149 } else { 150 sc->targets[target]->status = TARST_OK; 151 siop_update_xfer_mode(sc, target); 152 } 153 } else if (sc->targets[target]->status == TARST_OK && 154 (sc->targets[target]->flags & TARF_TAG) && xs->xs_tag_type != 0) { 155 siop_cmd->flags |= CMDFL_TAG; 156 } 157 siop_cmd->siop_tables.status = 158 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 159 160 siop_cmd->siop_tables.cmd.count = 161 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 162 siop_cmd->siop_tables.cmd.addr = 163 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 164 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 165 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 166 siop_cmd->siop_tables.data[i].count = 167 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 168 siop_cmd->siop_tables.data[i].addr = 169 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 170 } 171 } 172 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 173 } 174 175 int 176 siop_wdtr_neg(siop_cmd) 177 struct siop_cmd *siop_cmd; 178 { 179 struct siop_softc *sc = siop_cmd->siop_sc; 180 struct siop_target *siop_target = siop_cmd->siop_target; 181 int target = siop_cmd->xs->xs_periph->periph_target; 182 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 183 184 if (siop_target->status == TARST_WIDE_NEG) { 185 /* we initiated wide negotiation */ 186 switch (tables->msg_in[3]) { 187 case MSG_EXT_WDTR_BUS_8_BIT: 188 siop_target->flags &= ~TARF_ISWIDE; 189 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 190 break; 191 case MSG_EXT_WDTR_BUS_16_BIT: 192 if (siop_target->flags & TARF_WIDE) { 193 siop_target->flags |= TARF_ISWIDE; 194 sc->targets[target]->id |= (SCNTL3_EWS << 24); 195 break; 196 } 197 /* FALLTHROUH */ 198 default: 199 /* 200 * hum, we got more than what we can handle, shoudn't 201 * happen. Reject, and stay async 202 */ 203 siop_target->flags &= ~TARF_ISWIDE; 204 siop_target->status = TARST_OK; 205 siop_target->offset = siop_target->period = 0; 206 siop_update_xfer_mode(sc, target); 207 printf("%s: rejecting invalid wide negotiation from " 208 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 209 tables->msg_in[3]); 210 tables->t_msgout.count= htole32(1); 211 tables->msg_out[0] = MSG_MESSAGE_REJECT; 212 return SIOP_NEG_MSGOUT; 213 } 214 tables->id = htole32(sc->targets[target]->id); 215 bus_space_write_1(sc->sc_rt, sc->sc_rh, 216 SIOP_SCNTL3, 217 (sc->targets[target]->id >> 24) & 0xff); 218 /* we now need to do sync */ 219 if (siop_target->flags & TARF_SYNC) { 220 siop_target->status = TARST_SYNC_NEG; 221 siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff); 222 return SIOP_NEG_MSGOUT; 223 } else { 224 siop_target->status = TARST_OK; 225 siop_update_xfer_mode(sc, target); 226 return SIOP_NEG_ACK; 227 } 228 } else { 229 /* target initiated wide negotiation */ 230 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 231 && (siop_target->flags & TARF_WIDE)) { 232 siop_target->flags |= TARF_ISWIDE; 233 sc->targets[target]->id |= SCNTL3_EWS << 24; 234 } else { 235 siop_target->flags &= ~TARF_ISWIDE; 236 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 237 } 238 tables->id = htole32(sc->targets[target]->id); 239 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 240 (sc->targets[target]->id >> 24) & 0xff); 241 /* 242 * we did reset wide parameters, so fall back to async, 243 * but don't schedule a sync neg, target should initiate it 244 */ 245 siop_target->status = TARST_OK; 246 siop_target->offset = siop_target->period = 0; 247 siop_update_xfer_mode(sc, target); 248 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 249 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 250 return SIOP_NEG_MSGOUT; 251 } 252 } 253 254 int 255 siop_sdtr_neg(siop_cmd) 256 struct siop_cmd *siop_cmd; 257 { 258 struct siop_softc *sc = siop_cmd->siop_sc; 259 struct siop_target *siop_target = siop_cmd->siop_target; 260 int target = siop_cmd->xs->xs_periph->periph_target; 261 int sync, offset, i; 262 int send_msgout = 0; 263 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 264 265 sync = tables->msg_in[3]; 266 offset = tables->msg_in[4]; 267 268 if (siop_target->status == TARST_SYNC_NEG) { 269 /* we initiated sync negotiation */ 270 siop_target->status = TARST_OK; 271 #ifdef DEBUG 272 printf("sdtr: sync %d offset %d\n", sync, offset); 273 #endif 274 if (offset > sc->maxoff || sync < sc->minsync || 275 sync > sc->maxsync) 276 goto reject; 277 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 278 i++) { 279 if (sc->clock_period != scf_period[i].clock) 280 continue; 281 if (scf_period[i].period == sync) { 282 /* ok, found it. we now are sync. */ 283 siop_target->offset = offset; 284 siop_target->period = sync; 285 sc->targets[target]->id &= 286 ~(SCNTL3_SCF_MASK << 24); 287 sc->targets[target]->id |= scf_period[i].scf 288 << (24 + SCNTL3_SCF_SHIFT); 289 if (sync < 25) /* Ultra */ 290 sc->targets[target]->id |= 291 SCNTL3_ULTRA << 24; 292 else 293 sc->targets[target]->id &= 294 ~(SCNTL3_ULTRA << 24); 295 sc->targets[target]->id &= 296 ~(SXFER_MO_MASK << 8); 297 sc->targets[target]->id |= 298 (offset & SXFER_MO_MASK) << 8; 299 goto end; 300 } 301 } 302 /* 303 * we didn't find it in our table, do async and send reject 304 * msg 305 */ 306 reject: 307 send_msgout = 1; 308 tables->t_msgout.count= htole32(1); 309 tables->msg_out[0] = MSG_MESSAGE_REJECT; 310 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 311 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 312 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 313 siop_target->offset = siop_target->period = 0; 314 } else { /* target initiated sync neg */ 315 #ifdef DEBUG 316 printf("sdtr (target): sync %d offset %d\n", sync, offset); 317 #endif 318 if (offset == 0 || sync > sc->maxsync) { /* async */ 319 goto async; 320 } 321 if (offset > sc->maxoff) 322 offset = sc->maxoff; 323 if (sync < sc->minsync) 324 sync = sc->minsync; 325 /* look for sync period */ 326 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 327 i++) { 328 if (sc->clock_period != scf_period[i].clock) 329 continue; 330 if (scf_period[i].period == sync) { 331 /* ok, found it. we now are sync. */ 332 siop_target->offset = offset; 333 siop_target->period = sync; 334 sc->targets[target]->id &= 335 ~(SCNTL3_SCF_MASK << 24); 336 sc->targets[target]->id |= scf_period[i].scf 337 << (24 + SCNTL3_SCF_SHIFT); 338 if (sync < 25) /* Ultra */ 339 sc->targets[target]->id |= 340 SCNTL3_ULTRA << 24; 341 else 342 sc->targets[target]->id &= 343 ~(SCNTL3_ULTRA << 24); 344 sc->targets[target]->id &= 345 ~(SXFER_MO_MASK << 8); 346 sc->targets[target]->id |= 347 (offset & SXFER_MO_MASK) << 8; 348 siop_sdtr_msg(siop_cmd, 0, sync, offset); 349 send_msgout = 1; 350 goto end; 351 } 352 } 353 async: 354 siop_target->offset = siop_target->period = 0; 355 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 356 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 357 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 358 siop_sdtr_msg(siop_cmd, 0, 0, 0); 359 send_msgout = 1; 360 } 361 end: 362 if (siop_target->status == TARST_OK) 363 siop_update_xfer_mode(sc, target); 364 #ifdef DEBUG 365 printf("id now 0x%x\n", sc->targets[target]->id); 366 #endif 367 tables->id = htole32(sc->targets[target]->id); 368 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 369 (sc->targets[target]->id >> 24) & 0xff); 370 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 371 (sc->targets[target]->id >> 8) & 0xff); 372 if (send_msgout) { 373 return SIOP_NEG_MSGOUT; 374 } else { 375 return SIOP_NEG_ACK; 376 } 377 } 378 379 void 380 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 381 struct siop_cmd *siop_cmd; 382 int offset; 383 int ssync, soff; 384 { 385 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 386 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 387 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_SDTR; 388 siop_cmd->siop_tables.msg_out[offset + 3] = ssync; 389 siop_cmd->siop_tables.msg_out[offset + 4] = soff; 390 siop_cmd->siop_tables.t_msgout.count = 391 htole32(offset + MSG_EXT_SDTR_LEN + 2); 392 } 393 394 void 395 siop_wdtr_msg(siop_cmd, offset, wide) 396 struct siop_cmd *siop_cmd; 397 int offset; 398 { 399 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 400 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 401 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_WDTR; 402 siop_cmd->siop_tables.msg_out[offset + 3] = wide; 403 siop_cmd->siop_tables.t_msgout.count = 404 htole32(offset + MSG_EXT_WDTR_LEN + 2); 405 } 406 407 void 408 siop_minphys(bp) 409 struct buf *bp; 410 { 411 minphys(bp); 412 } 413 414 int 415 siop_ioctl(chan, cmd, arg, flag, p) 416 struct scsipi_channel *chan; 417 u_long cmd; 418 caddr_t arg; 419 int flag; 420 struct proc *p; 421 { 422 struct siop_softc *sc = (void *)chan->chan_adapter->adapt_dev; 423 u_int8_t scntl1; 424 int s; 425 426 switch (cmd) { 427 case SCBUSIORESET: 428 s = splbio(); 429 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 430 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 431 scntl1 | SCNTL1_RST); 432 /* minimum 25 us, more time won't hurt */ 433 delay(100); 434 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 435 splx(s); 436 return (0); 437 default: 438 return (ENOTTY); 439 } 440 } 441 442 void 443 siop_sdp(siop_cmd) 444 struct siop_cmd *siop_cmd; 445 { 446 /* save data pointer. Handle async only for now */ 447 int offset, dbc, sstat; 448 struct siop_softc *sc = siop_cmd->siop_sc; 449 scr_table_t *table; /* table to patch */ 450 451 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 452 == 0) 453 return; /* no data pointers to save */ 454 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 455 if (offset >= SIOP_NSG) { 456 printf("%s: bad offset in siop_sdp (%d)\n", 457 sc->sc_dev.dv_xname, offset); 458 return; 459 } 460 table = &siop_cmd->siop_xfer->tables.data[offset]; 461 #ifdef DEBUG_DR 462 printf("sdp: offset %d count=%d addr=0x%x ", offset, 463 table->count, table->addr); 464 #endif 465 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 466 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 467 /* need to account stale data in FIFO */ 468 int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 469 if (sc->features & SF_CHIP_FIFO) { 470 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 471 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 472 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 473 } else { 474 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 475 } 476 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 477 if (sstat & SSTAT0_OLF) 478 dbc++; 479 if (sstat & SSTAT0_ORF) 480 dbc++; 481 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 482 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 483 SIOP_SSTAT2); 484 if (sstat & SSTAT2_OLF1) 485 dbc++; 486 if (sstat & SSTAT2_ORF1) 487 dbc++; 488 } 489 /* clear the FIFO */ 490 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 491 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 492 CTEST3_CLF); 493 } 494 table->addr = 495 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 496 table->count = htole32(dbc); 497 #ifdef DEBUG_DR 498 printf("now count=%d addr=0x%x\n", table->count, table->addr); 499 #endif 500 } 501 502 void 503 siop_clearfifo(sc) 504 struct siop_softc *sc; 505 { 506 int timeout = 0; 507 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 508 509 #ifdef DEBUG_INTR 510 printf("DMA fifo not empty !\n"); 511 #endif 512 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 513 ctest3 | CTEST3_CLF); 514 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 515 CTEST3_CLF) != 0) { 516 delay(1); 517 if (++timeout > 1000) { 518 printf("clear fifo failed\n"); 519 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 520 bus_space_read_1(sc->sc_rt, sc->sc_rh, 521 SIOP_CTEST3) & ~CTEST3_CLF); 522 return; 523 } 524 } 525 } 526 527 int 528 siop_modechange(sc) 529 struct siop_softc *sc; 530 { 531 int retry; 532 int sist0, sist1, stest2, stest4; 533 for (retry = 0; retry < 5; retry++) { 534 /* 535 * datasheet says to wait 100ms and re-read SIST1, 536 * to check that DIFFSENSE is stable. 537 * We may delay() 5 times for 100ms at interrupt time; 538 * hopefully this will not happen often. 539 */ 540 delay(100000); 541 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 542 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 543 if (sist1 & SIEN1_SBMC) 544 continue; /* we got an irq again */ 545 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 546 STEST4_MODE_MASK; 547 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 548 switch(stest4) { 549 case STEST4_MODE_DIF: 550 printf("%s: switching to differential mode\n", 551 sc->sc_dev.dv_xname); 552 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 553 stest2 | STEST2_DIF); 554 break; 555 case STEST4_MODE_SE: 556 printf("%s: switching to single-ended mode\n", 557 sc->sc_dev.dv_xname); 558 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 559 stest2 & ~STEST2_DIF); 560 break; 561 case STEST4_MODE_LVD: 562 printf("%s: switching to LVD mode\n", 563 sc->sc_dev.dv_xname); 564 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 565 stest2 & ~STEST2_DIF); 566 break; 567 default: 568 printf("%s: invalid SCSI mode 0x%x\n", 569 sc->sc_dev.dv_xname, stest4); 570 return 0; 571 } 572 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 573 stest4 >> 2); 574 return 1; 575 } 576 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 577 sc->sc_dev.dv_xname); 578 return 0; 579 } 580 581 void 582 siop_resetbus(sc) 583 struct siop_softc *sc; 584 { 585 int scntl1; 586 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 587 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 588 scntl1 | SCNTL1_RST); 589 /* minimum 25 us, more time won't hurt */ 590 delay(100); 591 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 592 } 593
Indexes created Sun Oct 12 05:10:08 GMT 2025