siop_common.c revision 1.13
1 /* $NetBSD: siop_common.c,v 1.13 2001/03/12 10:00:50 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsi_message.h> 48 #include <dev/scsipi/scsipi_all.h> 49 50 #include <dev/scsipi/scsiconf.h> 51 52 #include <dev/ic/siopreg.h> 53 #include <dev/ic/siopvar.h> 54 #include <dev/ic/siopvar_common.h> 55 56 #undef DEBUG 57 #undef DEBUG_DR 58 59 void 60 siop_common_reset(sc) 61 struct siop_softc *sc; 62 { 63 u_int32_t stest3; 64 65 /* reset the chip */ 66 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 67 delay(1000); 68 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 69 70 /* init registers */ 71 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 72 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 73 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 74 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 76 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 78 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 80 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 82 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 84 (0xb << STIME0_SEL_SHIFT)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 86 sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 88 1 << sc->sc_link.scsipi_scsi.adapter_target); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 90 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 91 92 /* enable clock doubler or quadruler if appropriate */ 93 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 94 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 95 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 96 STEST1_DBLEN); 97 if (sc->features & SF_CHIP_QUAD) { 98 /* wait for PPL to lock */ 99 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 100 SIOP_STEST4) & STEST4_LOCK) == 0) 101 delay(10); 102 } else { 103 /* data sheet says 20us - more won't hurt */ 104 delay(100); 105 } 106 /* halt scsi clock, select doubler/quad, restart clock */ 107 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 108 stest3 | STEST3_HSC); 109 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 110 STEST1_DBLEN | STEST1_DBLSEL); 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 112 } else { 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 114 } 115 if (sc->features & SF_CHIP_FIFO) 116 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 117 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 118 CTEST5_DFS); 119 120 sc->sc_reset(sc); 121 } 122 123 /* prepare tables before sending a cmd */ 124 void 125 siop_setuptables(siop_cmd) 126 struct siop_cmd *siop_cmd; 127 { 128 int i; 129 struct siop_softc *sc = siop_cmd->siop_sc; 130 struct scsipi_xfer *xs = siop_cmd->xs; 131 int target = xs->sc_link->scsipi_scsi.target; 132 int lun = xs->sc_link->scsipi_scsi.lun; 133 134 siop_cmd->siop_tables.id = htole32(sc->targets[target]->id); 135 memset(siop_cmd->siop_tables.msg_out, 0, 8); 136 if (siop_cmd->status != CMDST_SENSE) 137 siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 1); 138 else 139 siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 0); 140 siop_cmd->siop_tables.t_msgout.count= htole32(1); 141 if (sc->targets[target]->status == TARST_ASYNC) { 142 if (sc->targets[target]->flags & TARF_WIDE) { 143 sc->targets[target]->status = TARST_WIDE_NEG; 144 siop_wdtr_msg(siop_cmd, 1, MSG_EXT_WDTR_BUS_16_BIT); 145 } else if (sc->targets[target]->flags & TARF_SYNC) { 146 sc->targets[target]->status = TARST_SYNC_NEG; 147 siop_sdtr_msg(siop_cmd, 1, sc->minsync, sc->maxoff); 148 } else { 149 sc->targets[target]->status = TARST_OK; 150 } 151 } else if (sc->targets[target]->status == TARST_OK && 152 (sc->targets[target]->flags & TARF_TAG) && 153 siop_cmd->status != CMDST_SENSE) { 154 siop_cmd->flags |= CMDFL_TAG; 155 } 156 siop_cmd->siop_tables.status = 157 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 158 159 siop_cmd->siop_tables.cmd.count = 160 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 161 siop_cmd->siop_tables.cmd.addr = 162 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 163 if ((xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) || 164 siop_cmd->status == CMDST_SENSE) { 165 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 166 siop_cmd->siop_tables.data[i].count = 167 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 168 siop_cmd->siop_tables.data[i].addr = 169 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 170 } 171 } 172 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 173 } 174 175 int 176 siop_wdtr_neg(siop_cmd) 177 struct siop_cmd *siop_cmd; 178 { 179 struct siop_softc *sc = siop_cmd->siop_sc; 180 struct siop_target *siop_target = siop_cmd->siop_target; 181 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 182 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 183 184 if (siop_target->status == TARST_WIDE_NEG) { 185 /* we initiated wide negotiation */ 186 switch (tables->msg_in[3]) { 187 case MSG_EXT_WDTR_BUS_8_BIT: 188 printf("%s: target %d using 8bit transfers\n", 189 sc->sc_dev.dv_xname, target); 190 siop_target->flags &= ~TARF_ISWIDE; 191 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 192 break; 193 case MSG_EXT_WDTR_BUS_16_BIT: 194 if (siop_target->flags & TARF_WIDE) { 195 printf("%s: target %d using 16bit transfers\n", 196 sc->sc_dev.dv_xname, target); 197 siop_target->flags |= TARF_ISWIDE; 198 sc->targets[target]->id |= (SCNTL3_EWS << 24); 199 break; 200 } 201 /* FALLTHROUH */ 202 default: 203 /* 204 * hum, we got more than what we can handle, shoudn't 205 * happen. Reject, and stay async 206 */ 207 siop_target->flags &= ~TARF_ISWIDE; 208 siop_target->status = TARST_OK; 209 printf("%s: rejecting invalid wide negotiation from " 210 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 211 tables->msg_in[3]); 212 tables->t_msgout.count= htole32(1); 213 tables->msg_out[0] = MSG_MESSAGE_REJECT; 214 return SIOP_NEG_MSGOUT; 215 } 216 tables->id = htole32(sc->targets[target]->id); 217 bus_space_write_1(sc->sc_rt, sc->sc_rh, 218 SIOP_SCNTL3, 219 (sc->targets[target]->id >> 24) & 0xff); 220 /* we now need to do sync */ 221 if (siop_target->flags & TARF_SYNC) { 222 siop_target->status = TARST_SYNC_NEG; 223 siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff); 224 return SIOP_NEG_MSGOUT; 225 } else { 226 siop_target->status = TARST_OK; 227 return SIOP_NEG_ACK; 228 } 229 } else { 230 /* target initiated wide negotiation */ 231 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 232 && (siop_target->flags & TARF_WIDE)) { 233 printf("%s: target %d using 16bit transfers\n", 234 sc->sc_dev.dv_xname, target); 235 siop_target->flags |= TARF_ISWIDE; 236 sc->targets[target]->id |= SCNTL3_EWS << 24; 237 } else { 238 printf("%s: target %d using 8bit transfers\n", 239 sc->sc_dev.dv_xname, target); 240 siop_target->flags &= ~TARF_ISWIDE; 241 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 242 } 243 tables->id = htole32(sc->targets[target]->id); 244 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 245 (sc->targets[target]->id >> 24) & 0xff); 246 /* 247 * we did reset wide parameters, so fall back to async, 248 * but don't schedule a sync neg, target should initiate it 249 */ 250 siop_target->status = TARST_OK; 251 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 252 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 253 return SIOP_NEG_MSGOUT; 254 } 255 } 256 257 int 258 siop_sdtr_neg(siop_cmd) 259 struct siop_cmd *siop_cmd; 260 { 261 struct siop_softc *sc = siop_cmd->siop_sc; 262 struct siop_target *siop_target = siop_cmd->siop_target; 263 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 264 int sync, offset, i; 265 int send_msgout = 0; 266 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 267 268 sync = tables->msg_in[3]; 269 offset = tables->msg_in[4]; 270 271 if (siop_target->status == TARST_SYNC_NEG) { 272 /* we initiated sync negotiation */ 273 siop_target->status = TARST_OK; 274 #ifdef DEBUG 275 printf("sdtr: sync %d offset %d\n", sync, offset); 276 #endif 277 if (offset > sc->maxoff || sync < sc->minsync || 278 sync > sc->maxsync) 279 goto reject; 280 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 281 i++) { 282 if (sc->clock_period != scf_period[i].clock) 283 continue; 284 if (scf_period[i].period == sync) { 285 /* ok, found it. we now are sync. */ 286 printf("%s: target %d now synchronous at " 287 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 288 target, scf_period[i].rate, offset); 289 sc->targets[target]->id &= 290 ~(SCNTL3_SCF_MASK << 24); 291 sc->targets[target]->id |= scf_period[i].scf 292 << (24 + SCNTL3_SCF_SHIFT); 293 if (sync < 25) /* Ultra */ 294 sc->targets[target]->id |= 295 SCNTL3_ULTRA << 24; 296 else 297 sc->targets[target]->id &= 298 ~(SCNTL3_ULTRA << 24); 299 sc->targets[target]->id &= 300 ~(SXFER_MO_MASK << 8); 301 sc->targets[target]->id |= 302 (offset & SXFER_MO_MASK) << 8; 303 goto end; 304 } 305 } 306 /* 307 * we didn't find it in our table, do async and send reject 308 * msg 309 */ 310 reject: 311 send_msgout = 1; 312 tables->t_msgout.count= htole32(1); 313 tables->msg_out[0] = MSG_MESSAGE_REJECT; 314 printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname, 315 target); 316 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 317 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 318 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 319 } else { /* target initiated sync neg */ 320 #ifdef DEBUG 321 printf("sdtr (target): sync %d offset %d\n", sync, offset); 322 #endif 323 if (offset == 0 || sync > sc->maxsync) { /* async */ 324 goto async; 325 } 326 if (offset > sc->maxoff) 327 offset = sc->maxoff; 328 if (sync < sc->minsync) 329 sync = sc->minsync; 330 /* look for sync period */ 331 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 332 i++) { 333 if (sc->clock_period != scf_period[i].clock) 334 continue; 335 if (scf_period[i].period == sync) { 336 /* ok, found it. we now are sync. */ 337 printf("%s: target %d now synchronous at " 338 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 339 target, scf_period[i].rate, offset); 340 sc->targets[target]->id &= 341 ~(SCNTL3_SCF_MASK << 24); 342 sc->targets[target]->id |= scf_period[i].scf 343 << (24 + SCNTL3_SCF_SHIFT); 344 if (sync < 25) /* Ultra */ 345 sc->targets[target]->id |= 346 SCNTL3_ULTRA << 24; 347 else 348 sc->targets[target]->id &= 349 ~(SCNTL3_ULTRA << 24); 350 sc->targets[target]->id &= 351 ~(SXFER_MO_MASK << 8); 352 sc->targets[target]->id |= 353 (offset & SXFER_MO_MASK) << 8; 354 siop_sdtr_msg(siop_cmd, 0, sync, offset); 355 send_msgout = 1; 356 goto end; 357 } 358 } 359 async: 360 printf("%s: target %d asynchronous\n", 361 sc->sc_dev.dv_xname, target); 362 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 363 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 364 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 365 siop_sdtr_msg(siop_cmd, 0, 0, 0); 366 send_msgout = 1; 367 } 368 end: 369 #ifdef DEBUG 370 printf("id now 0x%x\n", sc->targets[target]->id); 371 #endif 372 tables->id = htole32(sc->targets[target]->id); 373 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 374 (sc->targets[target]->id >> 24) & 0xff); 375 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 376 (sc->targets[target]->id >> 8) & 0xff); 377 if (send_msgout) { 378 return SIOP_NEG_MSGOUT; 379 } else { 380 return SIOP_NEG_ACK; 381 } 382 } 383 384 void 385 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 386 struct siop_cmd *siop_cmd; 387 int offset; 388 int ssync, soff; 389 { 390 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 391 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 392 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_SDTR; 393 siop_cmd->siop_tables.msg_out[offset + 3] = ssync; 394 siop_cmd->siop_tables.msg_out[offset + 4] = soff; 395 siop_cmd->siop_tables.t_msgout.count = 396 htole32(offset + MSG_EXT_SDTR_LEN + 2); 397 } 398 399 void 400 siop_wdtr_msg(siop_cmd, offset, wide) 401 struct siop_cmd *siop_cmd; 402 int offset; 403 { 404 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 405 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 406 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_WDTR; 407 siop_cmd->siop_tables.msg_out[offset + 3] = wide; 408 siop_cmd->siop_tables.t_msgout.count = 409 htole32(offset + MSG_EXT_WDTR_LEN + 2); 410 } 411 412 void 413 siop_minphys(bp) 414 struct buf *bp; 415 { 416 minphys(bp); 417 } 418 419 int 420 siop_ioctl(link, cmd, arg, flag, p) 421 struct scsipi_link *link; 422 u_long cmd; 423 caddr_t arg; 424 int flag; 425 struct proc *p; 426 { 427 struct siop_softc *sc = link->adapter_softc; 428 u_int8_t scntl1; 429 int s; 430 431 switch (cmd) { 432 case SCBUSACCEL: 433 { 434 struct scbusaccel_args *sp = (struct scbusaccel_args *)arg; 435 s = splbio(); 436 if (sp->sa_lun == 0) { 437 if (sp->sa_flags & SC_ACCEL_TAGS) { 438 sc->targets[sp->sa_target]->flags |= TARF_TAG; 439 printf("%s: target %d using tagged queuing\n", 440 sc->sc_dev.dv_xname, sp->sa_target); 441 } 442 if ((sp->sa_flags & SC_ACCEL_WIDE) && 443 (sc->features & SF_BUS_WIDE)) 444 sc->targets[sp->sa_target]->flags |= TARF_WIDE; 445 if (sp->sa_flags & SC_ACCEL_SYNC) 446 sc->targets[sp->sa_target]->flags |= TARF_SYNC; 447 if ((sp->sa_flags & (SC_ACCEL_SYNC | SC_ACCEL_WIDE)) || 448 sc->targets[sp->sa_target]->status == TARST_PROBING) 449 sc->targets[sp->sa_target]->status = 450 TARST_ASYNC; 451 } 452 453 /* allocate a lun sw entry for this device */ 454 siop_add_dev(sc, sp->sa_target, sp->sa_lun); 455 /* 456 * if we can to tagged queueing, inform upper layer 457 * we can have NIOP_NTAG concurent commands 458 */ 459 if (sc->targets[sp->sa_target]->flags & TARF_TAG) 460 link->openings = SIOP_NTAG; 461 splx(s); 462 return 0; 463 } 464 case SCBUSIORESET: 465 s = splbio(); 466 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 467 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 468 scntl1 | SCNTL1_RST); 469 /* minimum 25 us, more time won't hurt */ 470 delay(100); 471 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 472 splx(s); 473 return (0); 474 default: 475 return (ENOTTY); 476 } 477 } 478 479 void 480 siop_sdp(siop_cmd) 481 struct siop_cmd *siop_cmd; 482 { 483 /* save data pointer. Handle async only for now */ 484 int offset, dbc, sstat; 485 struct siop_softc *sc = siop_cmd->siop_sc; 486 scr_table_t *table; /* table to patch */ 487 488 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 489 == 0) 490 return; /* no data pointers to save */ 491 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 492 if (offset >= SIOP_NSG) { 493 printf("%s: bad offset in siop_sdp (%d)\n", 494 sc->sc_dev.dv_xname, offset); 495 return; 496 } 497 table = &siop_cmd->siop_xfer->tables.data[offset]; 498 #ifdef DEBUG_DR 499 printf("sdp: offset %d count=%d addr=0x%x ", offset, 500 table->count, table->addr); 501 #endif 502 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 503 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 504 if (sc->features & SF_CHIP_DFBC) { 505 dbc += 506 bus_space_read_2(sc->sc_rt, sc->sc_rh, SIOP_DFBC); 507 } else { 508 /* need to account stale data in FIFO */ 509 int dfifo = 510 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 511 if (sc->features & SF_CHIP_FIFO) { 512 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 513 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 514 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 515 } else { 516 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 517 } 518 } 519 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 520 if (sstat & SSTAT0_OLF) 521 dbc++; 522 if ((sstat & SSTAT0_ORF) && (sc->features & SF_CHIP_DFBC) == 0) 523 dbc++; 524 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 525 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 526 SIOP_SSTAT2); 527 if (sstat & SSTAT2_OLF1) 528 dbc++; 529 if ((sstat & SSTAT2_ORF1) && 530 (sc->features & SF_CHIP_DFBC) == 0) 531 dbc++; 532 } 533 /* clear the FIFO */ 534 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 535 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 536 CTEST3_CLF); 537 } 538 table->addr = 539 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 540 table->count = htole32(dbc); 541 #ifdef DEBUG_DR 542 printf("now count=%d addr=0x%x\n", table->count, table->addr); 543 #endif 544 } 545 546 void 547 siop_clearfifo(sc) 548 struct siop_softc *sc; 549 { 550 int timeout = 0; 551 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 552 553 #ifdef DEBUG_INTR 554 printf("DMA fifo not empty !\n"); 555 #endif 556 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 557 ctest3 | CTEST3_CLF); 558 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 559 CTEST3_CLF) != 0) { 560 delay(1); 561 if (++timeout > 1000) { 562 printf("clear fifo failed\n"); 563 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 564 bus_space_read_1(sc->sc_rt, sc->sc_rh, 565 SIOP_CTEST3) & ~CTEST3_CLF); 566 return; 567 } 568 } 569 } 570 571 int 572 siop_modechange(sc) 573 struct siop_softc *sc; 574 { 575 int retry; 576 int sist0, sist1, stest2, stest4; 577 for (retry = 0; retry < 5; retry++) { 578 /* 579 * datasheet says to wait 100ms and re-read SIST1, 580 * to check that DIFFSENSE is srable. 581 * We may delay() 5 times for 100ms at interrupt time; 582 * hopefully this will not happen often. 583 */ 584 delay(100000); 585 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 586 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 587 if (sist1 & SIEN1_SBMC) 588 continue; /* we got an irq again */ 589 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 590 STEST4_MODE_MASK; 591 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 592 switch(stest4) { 593 case STEST4_MODE_DIF: 594 printf("%s: switching to differential mode\n", 595 sc->sc_dev.dv_xname); 596 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 597 stest2 | STEST2_DIF); 598 break; 599 case STEST4_MODE_SE: 600 printf("%s: switching to single-ended mode\n", 601 sc->sc_dev.dv_xname); 602 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 603 stest2 & ~STEST2_DIF); 604 break; 605 case STEST4_MODE_LVD: 606 printf("%s: switching to LVD mode\n", 607 sc->sc_dev.dv_xname); 608 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 609 stest2 & ~STEST2_DIF); 610 break; 611 default: 612 printf("%s: invalid SCSI mode 0x%x\n", 613 sc->sc_dev.dv_xname, stest4); 614 return 0; 615 } 616 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 617 stest4 >> 2); 618 return 1; 619 } 620 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 621 sc->sc_dev.dv_xname); 622 return 0; 623 } 624 625 void 626 siop_resetbus(sc) 627 struct siop_softc *sc; 628 { 629 int scntl1; 630 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 631 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 632 scntl1 | SCNTL1_RST); 633 /* minimum 25 us, more time won't hurt */ 634 delay(100); 635 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 636 } 637
Indexes created Wed Sep 24 02:09:48 GMT 2025