siop_common.c revision 1.18
1 /* $NetBSD: siop_common.c,v 1.18 2002/04/22 09:43:44 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: siop_common.c,v 1.18 2002/04/22 09:43:44 bouyer Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/buf.h> 43 #include <sys/kernel.h> 44 #include <sys/scsiio.h> 45 46 #include <machine/endian.h> 47 #include <machine/bus.h> 48 49 #include <dev/scsipi/scsi_all.h> 50 #include <dev/scsipi/scsi_message.h> 51 #include <dev/scsipi/scsipi_all.h> 52 53 #include <dev/scsipi/scsiconf.h> 54 55 #include <dev/ic/siopreg.h> 56 #include <dev/ic/siopvar_common.h> 57 58 #include "opt_siop.h" 59 60 #undef DEBUG 61 #undef DEBUG_DR 62 63 void 64 siop_common_reset(sc) 65 struct siop_common_softc *sc; 66 { 67 u_int32_t stest3; 68 69 /* reset the chip */ 70 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 71 delay(1000); 72 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 73 74 /* init registers */ 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 76 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 78 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 80 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 82 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 84 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 86 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 88 (0xb << STIME0_SEL_SHIFT)); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 90 sc->sc_chan.chan_id | SCID_RRE); 91 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 92 1 << sc->sc_chan.chan_id); 93 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 94 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 95 96 /* enable clock doubler or quadruler if appropriate */ 97 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 98 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 99 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 100 STEST1_DBLEN); 101 if (sc->features & SF_CHIP_QUAD) { 102 /* wait for PPL to lock */ 103 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 104 SIOP_STEST4) & STEST4_LOCK) == 0) 105 delay(10); 106 } else { 107 /* data sheet says 20us - more won't hurt */ 108 delay(100); 109 } 110 /* halt scsi clock, select doubler/quad, restart clock */ 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 112 stest3 | STEST3_HSC); 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 114 STEST1_DBLEN | STEST1_DBLSEL); 115 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 116 } else { 117 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 118 } 119 if (sc->features & SF_CHIP_FIFO) 120 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 121 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 122 CTEST5_DFS); 123 #ifdef SIOP_SYMLED 124 /* Set GPIO0 as output if software LED control is required */ 125 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL, 126 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL) & 0xfe); 127 #endif 128 129 sc->sc_reset(sc); 130 } 131 132 /* prepare tables before sending a cmd */ 133 void 134 siop_setuptables(siop_cmd) 135 struct siop_common_cmd *siop_cmd; 136 { 137 int i; 138 struct siop_common_softc *sc = siop_cmd->siop_sc; 139 struct scsipi_xfer *xs = siop_cmd->xs; 140 int target = xs->xs_periph->periph_target; 141 int lun = xs->xs_periph->periph_lun; 142 int msgoffset = 1; 143 144 siop_cmd->siop_tables->id = htole32(sc->targets[target]->id); 145 memset(siop_cmd->siop_tables->msg_out, 0, 8); 146 /* request sense doesn't disconnect */ 147 if (xs->xs_control & XS_CTL_REQSENSE) 148 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 0); 149 else 150 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 1); 151 siop_cmd->siop_tables->t_msgout.count= htole32(1); 152 if (xs->xs_tag_type != 0) { 153 if ((sc->targets[target]->flags & TARF_TAG) == 0) { 154 scsipi_printaddr(xs->xs_periph); 155 printf(": tagged command type %d id %d\n", 156 siop_cmd->xs->xs_tag_type, siop_cmd->xs->xs_tag_id); 157 panic("tagged command for non-tagging device\n"); 158 } 159 siop_cmd->flags |= CMDFL_TAG; 160 siop_cmd->siop_tables->msg_out[1] = siop_cmd->xs->xs_tag_type; 161 siop_cmd->siop_tables->msg_out[2] = siop_cmd->xs->xs_tag_id + 1; 162 siop_cmd->siop_tables->t_msgout.count = htole32(3); 163 msgoffset = 3; 164 siop_cmd->tag = siop_cmd->xs->xs_tag_id; 165 } else 166 siop_cmd->tag = 0; 167 if (sc->targets[target]->status == TARST_ASYNC) { 168 if (sc->targets[target]->flags & TARF_WIDE) { 169 sc->targets[target]->status = TARST_WIDE_NEG; 170 siop_wdtr_msg(siop_cmd, msgoffset, 171 MSG_EXT_WDTR_BUS_16_BIT); 172 } else if (sc->targets[target]->flags & TARF_SYNC) { 173 sc->targets[target]->status = TARST_SYNC_NEG; 174 siop_sdtr_msg(siop_cmd, msgoffset, 175 sc->minsync, sc->maxoff); 176 } else { 177 sc->targets[target]->status = TARST_OK; 178 siop_update_xfer_mode(sc, target); 179 } 180 } 181 if (xs->xs_tag_type != 0 && (siop_cmd->flags & CMDFL_TAG) == 0) 182 printf("siop_setuptables: tagged CMD type 0x%x for target %d lun %d runs untagged, status 0x%x flags 0x%x\n", xs->xs_tag_type, target, lun, sc->targets[target]->status, sc->targets[target]->flags); 183 siop_cmd->siop_tables->status = 184 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 185 186 siop_cmd->siop_tables->cmd.count = 187 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 188 siop_cmd->siop_tables->cmd.addr = 189 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 190 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 191 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 192 siop_cmd->siop_tables->data[i].count = 193 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 194 siop_cmd->siop_tables->data[i].addr = 195 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 196 } 197 } 198 } 199 200 int 201 siop_wdtr_neg(siop_cmd) 202 struct siop_common_cmd *siop_cmd; 203 { 204 struct siop_common_softc *sc = siop_cmd->siop_sc; 205 struct siop_common_target *siop_target = siop_cmd->siop_target; 206 int target = siop_cmd->xs->xs_periph->periph_target; 207 struct siop_common_xfer *tables = siop_cmd->siop_tables; 208 209 if (siop_target->status == TARST_WIDE_NEG) { 210 /* we initiated wide negotiation */ 211 switch (tables->msg_in[3]) { 212 case MSG_EXT_WDTR_BUS_8_BIT: 213 siop_target->flags &= ~TARF_ISWIDE; 214 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 215 break; 216 case MSG_EXT_WDTR_BUS_16_BIT: 217 if (siop_target->flags & TARF_WIDE) { 218 siop_target->flags |= TARF_ISWIDE; 219 sc->targets[target]->id |= (SCNTL3_EWS << 24); 220 break; 221 } 222 /* FALLTHROUH */ 223 default: 224 /* 225 * hum, we got more than what we can handle, shoudn't 226 * happen. Reject, and stay async 227 */ 228 siop_target->flags &= ~TARF_ISWIDE; 229 siop_target->status = TARST_OK; 230 siop_target->offset = siop_target->period = 0; 231 siop_update_xfer_mode(sc, target); 232 printf("%s: rejecting invalid wide negotiation from " 233 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 234 tables->msg_in[3]); 235 tables->t_msgout.count= htole32(1); 236 tables->msg_out[0] = MSG_MESSAGE_REJECT; 237 return SIOP_NEG_MSGOUT; 238 } 239 tables->id = htole32(sc->targets[target]->id); 240 bus_space_write_1(sc->sc_rt, sc->sc_rh, 241 SIOP_SCNTL3, 242 (sc->targets[target]->id >> 24) & 0xff); 243 /* we now need to do sync */ 244 if (siop_target->flags & TARF_SYNC) { 245 siop_target->status = TARST_SYNC_NEG; 246 siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff); 247 return SIOP_NEG_MSGOUT; 248 } else { 249 siop_target->status = TARST_OK; 250 siop_update_xfer_mode(sc, target); 251 return SIOP_NEG_ACK; 252 } 253 } else { 254 /* target initiated wide negotiation */ 255 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 256 && (siop_target->flags & TARF_WIDE)) { 257 siop_target->flags |= TARF_ISWIDE; 258 sc->targets[target]->id |= SCNTL3_EWS << 24; 259 } else { 260 siop_target->flags &= ~TARF_ISWIDE; 261 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 262 } 263 tables->id = htole32(sc->targets[target]->id); 264 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 265 (sc->targets[target]->id >> 24) & 0xff); 266 /* 267 * we did reset wide parameters, so fall back to async, 268 * but don't schedule a sync neg, target should initiate it 269 */ 270 siop_target->status = TARST_OK; 271 siop_target->offset = siop_target->period = 0; 272 siop_update_xfer_mode(sc, target); 273 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 274 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 275 return SIOP_NEG_MSGOUT; 276 } 277 } 278 279 int 280 siop_sdtr_neg(siop_cmd) 281 struct siop_common_cmd *siop_cmd; 282 { 283 struct siop_common_softc *sc = siop_cmd->siop_sc; 284 struct siop_common_target *siop_target = siop_cmd->siop_target; 285 int target = siop_cmd->xs->xs_periph->periph_target; 286 int sync, offset, i; 287 int send_msgout = 0; 288 struct siop_common_xfer *tables = siop_cmd->siop_tables; 289 290 sync = tables->msg_in[3]; 291 offset = tables->msg_in[4]; 292 293 if (siop_target->status == TARST_SYNC_NEG) { 294 /* we initiated sync negotiation */ 295 siop_target->status = TARST_OK; 296 #ifdef DEBUG 297 printf("sdtr: sync %d offset %d\n", sync, offset); 298 #endif 299 if (offset > sc->maxoff || sync < sc->minsync || 300 sync > sc->maxsync) 301 goto reject; 302 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 303 i++) { 304 if (sc->clock_period != scf_period[i].clock) 305 continue; 306 if (scf_period[i].period == sync) { 307 /* ok, found it. we now are sync. */ 308 siop_target->offset = offset; 309 siop_target->period = sync; 310 sc->targets[target]->id &= 311 ~(SCNTL3_SCF_MASK << 24); 312 sc->targets[target]->id |= scf_period[i].scf 313 << (24 + SCNTL3_SCF_SHIFT); 314 if (sync < 25) /* Ultra */ 315 sc->targets[target]->id |= 316 SCNTL3_ULTRA << 24; 317 else 318 sc->targets[target]->id &= 319 ~(SCNTL3_ULTRA << 24); 320 sc->targets[target]->id &= 321 ~(SXFER_MO_MASK << 8); 322 sc->targets[target]->id |= 323 (offset & SXFER_MO_MASK) << 8; 324 goto end; 325 } 326 } 327 /* 328 * we didn't find it in our table, do async and send reject 329 * msg 330 */ 331 reject: 332 send_msgout = 1; 333 tables->t_msgout.count= htole32(1); 334 tables->msg_out[0] = MSG_MESSAGE_REJECT; 335 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 336 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 337 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 338 siop_target->offset = siop_target->period = 0; 339 } else { /* target initiated sync neg */ 340 #ifdef DEBUG 341 printf("sdtr (target): sync %d offset %d\n", sync, offset); 342 #endif 343 if (offset == 0 || sync > sc->maxsync) { /* async */ 344 goto async; 345 } 346 if (offset > sc->maxoff) 347 offset = sc->maxoff; 348 if (sync < sc->minsync) 349 sync = sc->minsync; 350 /* look for sync period */ 351 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 352 i++) { 353 if (sc->clock_period != scf_period[i].clock) 354 continue; 355 if (scf_period[i].period == sync) { 356 /* ok, found it. we now are sync. */ 357 siop_target->offset = offset; 358 siop_target->period = sync; 359 sc->targets[target]->id &= 360 ~(SCNTL3_SCF_MASK << 24); 361 sc->targets[target]->id |= scf_period[i].scf 362 << (24 + SCNTL3_SCF_SHIFT); 363 if (sync < 25) /* Ultra */ 364 sc->targets[target]->id |= 365 SCNTL3_ULTRA << 24; 366 else 367 sc->targets[target]->id &= 368 ~(SCNTL3_ULTRA << 24); 369 sc->targets[target]->id &= 370 ~(SXFER_MO_MASK << 8); 371 sc->targets[target]->id |= 372 (offset & SXFER_MO_MASK) << 8; 373 siop_sdtr_msg(siop_cmd, 0, sync, offset); 374 send_msgout = 1; 375 goto end; 376 } 377 } 378 async: 379 siop_target->offset = siop_target->period = 0; 380 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 381 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 382 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 383 siop_sdtr_msg(siop_cmd, 0, 0, 0); 384 send_msgout = 1; 385 } 386 end: 387 if (siop_target->status == TARST_OK) 388 siop_update_xfer_mode(sc, target); 389 #ifdef DEBUG 390 printf("id now 0x%x\n", sc->targets[target]->id); 391 #endif 392 tables->id = htole32(sc->targets[target]->id); 393 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 394 (sc->targets[target]->id >> 24) & 0xff); 395 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 396 (sc->targets[target]->id >> 8) & 0xff); 397 if (send_msgout) { 398 return SIOP_NEG_MSGOUT; 399 } else { 400 return SIOP_NEG_ACK; 401 } 402 } 403 404 void 405 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 406 struct siop_common_cmd *siop_cmd; 407 int offset; 408 int ssync, soff; 409 { 410 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 411 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 412 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_SDTR; 413 siop_cmd->siop_tables->msg_out[offset + 3] = ssync; 414 siop_cmd->siop_tables->msg_out[offset + 4] = soff; 415 siop_cmd->siop_tables->t_msgout.count = 416 htole32(offset + MSG_EXT_SDTR_LEN + 2); 417 } 418 419 void 420 siop_wdtr_msg(siop_cmd, offset, wide) 421 struct siop_common_cmd *siop_cmd; 422 int offset; 423 { 424 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 425 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 426 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_WDTR; 427 siop_cmd->siop_tables->msg_out[offset + 3] = wide; 428 siop_cmd->siop_tables->t_msgout.count = 429 htole32(offset + MSG_EXT_WDTR_LEN + 2); 430 } 431 432 void 433 siop_minphys(bp) 434 struct buf *bp; 435 { 436 minphys(bp); 437 } 438 439 int 440 siop_ioctl(chan, cmd, arg, flag, p) 441 struct scsipi_channel *chan; 442 u_long cmd; 443 caddr_t arg; 444 int flag; 445 struct proc *p; 446 { 447 struct siop_common_softc *sc = (void *)chan->chan_adapter->adapt_dev; 448 u_int8_t scntl1; 449 int s; 450 451 switch (cmd) { 452 case SCBUSIORESET: 453 s = splbio(); 454 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 455 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 456 scntl1 | SCNTL1_RST); 457 /* minimum 25 us, more time won't hurt */ 458 delay(100); 459 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 460 splx(s); 461 return (0); 462 default: 463 return (ENOTTY); 464 } 465 } 466 467 void 468 siop_sdp(siop_cmd) 469 struct siop_common_cmd *siop_cmd; 470 { 471 /* save data pointer. Handle async only for now */ 472 int offset, dbc, sstat; 473 struct siop_common_softc *sc = siop_cmd->siop_sc; 474 scr_table_t *table; /* table to patch */ 475 476 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 477 == 0) 478 return; /* no data pointers to save */ 479 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 480 if (offset >= SIOP_NSG) { 481 printf("%s: bad offset in siop_sdp (%d)\n", 482 sc->sc_dev.dv_xname, offset); 483 return; 484 } 485 table = &siop_cmd->siop_tables->data[offset]; 486 #ifdef DEBUG_DR 487 printf("sdp: offset %d count=%d addr=0x%x ", offset, 488 table->count, table->addr); 489 #endif 490 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 491 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 492 if (sc->features & SF_CHIP_DFBC) { 493 dbc += 494 bus_space_read_2(sc->sc_rt, sc->sc_rh, SIOP_DFBC); 495 } else { 496 /* need to account stale data in FIFO */ 497 int dfifo = 498 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 499 if (sc->features & SF_CHIP_FIFO) { 500 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 501 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 502 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 503 } else { 504 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 505 } 506 } 507 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 508 if (sstat & SSTAT0_OLF) 509 dbc++; 510 if ((sstat & SSTAT0_ORF) && (sc->features & SF_CHIP_DFBC) == 0) 511 dbc++; 512 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 513 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 514 SIOP_SSTAT2); 515 if (sstat & SSTAT2_OLF1) 516 dbc++; 517 if ((sstat & SSTAT2_ORF1) && 518 (sc->features & SF_CHIP_DFBC) == 0) 519 dbc++; 520 } 521 /* clear the FIFO */ 522 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 523 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 524 CTEST3_CLF); 525 } 526 table->addr = 527 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 528 table->count = htole32(dbc); 529 #ifdef DEBUG_DR 530 printf("now count=%d addr=0x%x\n", table->count, table->addr); 531 #endif 532 } 533 534 void 535 siop_clearfifo(sc) 536 struct siop_common_softc *sc; 537 { 538 int timeout = 0; 539 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 540 541 #ifdef DEBUG_INTR 542 printf("DMA fifo not empty !\n"); 543 #endif 544 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 545 ctest3 | CTEST3_CLF); 546 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 547 CTEST3_CLF) != 0) { 548 delay(1); 549 if (++timeout > 1000) { 550 printf("clear fifo failed\n"); 551 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 552 bus_space_read_1(sc->sc_rt, sc->sc_rh, 553 SIOP_CTEST3) & ~CTEST3_CLF); 554 return; 555 } 556 } 557 } 558 559 int 560 siop_modechange(sc) 561 struct siop_common_softc *sc; 562 { 563 int retry; 564 int sist0, sist1, stest2, stest4; 565 for (retry = 0; retry < 5; retry++) { 566 /* 567 * datasheet says to wait 100ms and re-read SIST1, 568 * to check that DIFFSENSE is stable. 569 * We may delay() 5 times for 100ms at interrupt time; 570 * hopefully this will not happen often. 571 */ 572 delay(100000); 573 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 574 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 575 if (sist1 & SIEN1_SBMC) 576 continue; /* we got an irq again */ 577 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 578 STEST4_MODE_MASK; 579 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 580 switch(stest4) { 581 case STEST4_MODE_DIF: 582 printf("%s: switching to differential mode\n", 583 sc->sc_dev.dv_xname); 584 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 585 stest2 | STEST2_DIF); 586 break; 587 case STEST4_MODE_SE: 588 printf("%s: switching to single-ended mode\n", 589 sc->sc_dev.dv_xname); 590 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 591 stest2 & ~STEST2_DIF); 592 break; 593 case STEST4_MODE_LVD: 594 printf("%s: switching to LVD mode\n", 595 sc->sc_dev.dv_xname); 596 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 597 stest2 & ~STEST2_DIF); 598 break; 599 default: 600 printf("%s: invalid SCSI mode 0x%x\n", 601 sc->sc_dev.dv_xname, stest4); 602 return 0; 603 } 604 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 605 stest4 >> 2); 606 return 1; 607 } 608 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 609 sc->sc_dev.dv_xname); 610 return 0; 611 } 612 613 void 614 siop_resetbus(sc) 615 struct siop_common_softc *sc; 616 { 617 int scntl1; 618 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 619 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 620 scntl1 | SCNTL1_RST); 621 /* minimum 25 us, more time won't hurt */ 622 delay(100); 623 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 624 } 625 626 void 627 siop_update_xfer_mode(sc, target) 628 struct siop_common_softc *sc; 629 int target; 630 { 631 struct siop_common_target *siop_target = sc->targets[target]; 632 struct scsipi_xfer_mode xm; 633 634 xm.xm_target = target; 635 xm.xm_mode = 0; 636 xm.xm_period = 0; 637 xm.xm_offset = 0; 638 639 if (siop_target->flags & TARF_ISWIDE) 640 xm.xm_mode |= PERIPH_CAP_WIDE16; 641 if (siop_target->period) { 642 xm.xm_period = siop_target->period; 643 xm.xm_offset = siop_target->offset; 644 xm.xm_mode |= PERIPH_CAP_SYNC; 645 } 646 if (siop_target->flags & TARF_TAG) 647 xm.xm_mode |= PERIPH_CAP_TQING; 648 scsipi_async_event(&sc->sc_chan, ASYNC_EVENT_XFER_MODE, &xm); 649 } 650
Indexes created Sun Oct 12 05:10:08 GMT 2025