siop_common.c revision 1.19
1 /* $NetBSD: siop_common.c,v 1.19 2002/04/22 15:48:56 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: siop_common.c,v 1.19 2002/04/22 15:48:56 bouyer Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/buf.h> 43 #include <sys/kernel.h> 44 #include <sys/scsiio.h> 45 46 #include <machine/endian.h> 47 #include <machine/bus.h> 48 49 #include <dev/scsipi/scsi_all.h> 50 #include <dev/scsipi/scsi_message.h> 51 #include <dev/scsipi/scsipi_all.h> 52 53 #include <dev/scsipi/scsiconf.h> 54 55 #include <dev/ic/siopreg.h> 56 #include <dev/ic/siopvar_common.h> 57 58 #include "opt_siop.h" 59 60 #undef DEBUG 61 #undef DEBUG_DR 62 63 void 64 siop_common_reset(sc) 65 struct siop_common_softc *sc; 66 { 67 u_int32_t stest3; 68 69 /* reset the chip */ 70 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 71 delay(1000); 72 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 73 74 /* init registers */ 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 76 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 78 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 80 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 82 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 84 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 86 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 88 (0xb << STIME0_SEL_SHIFT)); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 90 sc->sc_chan.chan_id | SCID_RRE); 91 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 92 1 << sc->sc_chan.chan_id); 93 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 94 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 95 96 /* enable clock doubler or quadruler if appropriate */ 97 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 98 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 99 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 100 STEST1_DBLEN); 101 if (sc->features & SF_CHIP_QUAD) { 102 /* wait for PPL to lock */ 103 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 104 SIOP_STEST4) & STEST4_LOCK) == 0) 105 delay(10); 106 } else { 107 /* data sheet says 20us - more won't hurt */ 108 delay(100); 109 } 110 /* halt scsi clock, select doubler/quad, restart clock */ 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 112 stest3 | STEST3_HSC); 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 114 STEST1_DBLEN | STEST1_DBLSEL); 115 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 116 } else { 117 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 118 } 119 if (sc->features & SF_CHIP_FIFO) 120 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 121 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 122 CTEST5_DFS); 123 #ifdef SIOP_SYMLED 124 /* Set GPIO0 as output if software LED control is required */ 125 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL, 126 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL) & 0xfe); 127 #endif 128 129 sc->sc_reset(sc); 130 } 131 132 /* prepare tables before sending a cmd */ 133 void 134 siop_setuptables(siop_cmd) 135 struct siop_common_cmd *siop_cmd; 136 { 137 int i; 138 struct siop_common_softc *sc = siop_cmd->siop_sc; 139 struct scsipi_xfer *xs = siop_cmd->xs; 140 int target = xs->xs_periph->periph_target; 141 int lun = xs->xs_periph->periph_lun; 142 int msgoffset = 1; 143 144 siop_cmd->siop_tables->id = htole32(sc->targets[target]->id); 145 memset(siop_cmd->siop_tables->msg_out, 0, 8); 146 /* request sense doesn't disconnect */ 147 if (xs->xs_control & XS_CTL_REQSENSE) 148 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 0); 149 else 150 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 1); 151 siop_cmd->siop_tables->t_msgout.count= htole32(1); 152 if (xs->xs_tag_type != 0) { 153 if ((sc->targets[target]->flags & TARF_TAG) == 0) { 154 scsipi_printaddr(xs->xs_periph); 155 printf(": tagged command type %d id %d\n", 156 siop_cmd->xs->xs_tag_type, siop_cmd->xs->xs_tag_id); 157 panic("tagged command for non-tagging device\n"); 158 } 159 siop_cmd->flags |= CMDFL_TAG; 160 siop_cmd->siop_tables->msg_out[1] = siop_cmd->xs->xs_tag_type; 161 /* 162 * use siop_cmd->tag not xs->xs_tag_id, caller may want a 163 * different one 164 */ 165 siop_cmd->siop_tables->msg_out[2] = siop_cmd->tag; 166 siop_cmd->siop_tables->t_msgout.count = htole32(3); 167 msgoffset = 3; 168 } else 169 siop_cmd->tag = 0; 170 if (sc->targets[target]->status == TARST_ASYNC) { 171 if (sc->targets[target]->flags & TARF_WIDE) { 172 sc->targets[target]->status = TARST_WIDE_NEG; 173 siop_wdtr_msg(siop_cmd, msgoffset, 174 MSG_EXT_WDTR_BUS_16_BIT); 175 } else if (sc->targets[target]->flags & TARF_SYNC) { 176 sc->targets[target]->status = TARST_SYNC_NEG; 177 siop_sdtr_msg(siop_cmd, msgoffset, 178 sc->minsync, sc->maxoff); 179 } else { 180 sc->targets[target]->status = TARST_OK; 181 siop_update_xfer_mode(sc, target); 182 } 183 } 184 if (xs->xs_tag_type != 0 && (siop_cmd->flags & CMDFL_TAG) == 0) 185 printf("siop_setuptables: tagged CMD type 0x%x for target %d lun %d runs untagged, status 0x%x flags 0x%x\n", xs->xs_tag_type, target, lun, sc->targets[target]->status, sc->targets[target]->flags); 186 siop_cmd->siop_tables->status = 187 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 188 189 siop_cmd->siop_tables->cmd.count = 190 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 191 siop_cmd->siop_tables->cmd.addr = 192 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 193 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 194 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 195 siop_cmd->siop_tables->data[i].count = 196 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 197 siop_cmd->siop_tables->data[i].addr = 198 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 199 } 200 } 201 } 202 203 int 204 siop_wdtr_neg(siop_cmd) 205 struct siop_common_cmd *siop_cmd; 206 { 207 struct siop_common_softc *sc = siop_cmd->siop_sc; 208 struct siop_common_target *siop_target = siop_cmd->siop_target; 209 int target = siop_cmd->xs->xs_periph->periph_target; 210 struct siop_common_xfer *tables = siop_cmd->siop_tables; 211 212 if (siop_target->status == TARST_WIDE_NEG) { 213 /* we initiated wide negotiation */ 214 switch (tables->msg_in[3]) { 215 case MSG_EXT_WDTR_BUS_8_BIT: 216 siop_target->flags &= ~TARF_ISWIDE; 217 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 218 break; 219 case MSG_EXT_WDTR_BUS_16_BIT: 220 if (siop_target->flags & TARF_WIDE) { 221 siop_target->flags |= TARF_ISWIDE; 222 sc->targets[target]->id |= (SCNTL3_EWS << 24); 223 break; 224 } 225 /* FALLTHROUH */ 226 default: 227 /* 228 * hum, we got more than what we can handle, shoudn't 229 * happen. Reject, and stay async 230 */ 231 siop_target->flags &= ~TARF_ISWIDE; 232 siop_target->status = TARST_OK; 233 siop_target->offset = siop_target->period = 0; 234 siop_update_xfer_mode(sc, target); 235 printf("%s: rejecting invalid wide negotiation from " 236 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 237 tables->msg_in[3]); 238 tables->t_msgout.count= htole32(1); 239 tables->msg_out[0] = MSG_MESSAGE_REJECT; 240 return SIOP_NEG_MSGOUT; 241 } 242 tables->id = htole32(sc->targets[target]->id); 243 bus_space_write_1(sc->sc_rt, sc->sc_rh, 244 SIOP_SCNTL3, 245 (sc->targets[target]->id >> 24) & 0xff); 246 /* we now need to do sync */ 247 if (siop_target->flags & TARF_SYNC) { 248 siop_target->status = TARST_SYNC_NEG; 249 siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff); 250 return SIOP_NEG_MSGOUT; 251 } else { 252 siop_target->status = TARST_OK; 253 siop_update_xfer_mode(sc, target); 254 return SIOP_NEG_ACK; 255 } 256 } else { 257 /* target initiated wide negotiation */ 258 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 259 && (siop_target->flags & TARF_WIDE)) { 260 siop_target->flags |= TARF_ISWIDE; 261 sc->targets[target]->id |= SCNTL3_EWS << 24; 262 } else { 263 siop_target->flags &= ~TARF_ISWIDE; 264 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 265 } 266 tables->id = htole32(sc->targets[target]->id); 267 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 268 (sc->targets[target]->id >> 24) & 0xff); 269 /* 270 * we did reset wide parameters, so fall back to async, 271 * but don't schedule a sync neg, target should initiate it 272 */ 273 siop_target->status = TARST_OK; 274 siop_target->offset = siop_target->period = 0; 275 siop_update_xfer_mode(sc, target); 276 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 277 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 278 return SIOP_NEG_MSGOUT; 279 } 280 } 281 282 int 283 siop_sdtr_neg(siop_cmd) 284 struct siop_common_cmd *siop_cmd; 285 { 286 struct siop_common_softc *sc = siop_cmd->siop_sc; 287 struct siop_common_target *siop_target = siop_cmd->siop_target; 288 int target = siop_cmd->xs->xs_periph->periph_target; 289 int sync, offset, i; 290 int send_msgout = 0; 291 struct siop_common_xfer *tables = siop_cmd->siop_tables; 292 293 sync = tables->msg_in[3]; 294 offset = tables->msg_in[4]; 295 296 if (siop_target->status == TARST_SYNC_NEG) { 297 /* we initiated sync negotiation */ 298 siop_target->status = TARST_OK; 299 #ifdef DEBUG 300 printf("sdtr: sync %d offset %d\n", sync, offset); 301 #endif 302 if (offset > sc->maxoff || sync < sc->minsync || 303 sync > sc->maxsync) 304 goto reject; 305 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 306 i++) { 307 if (sc->clock_period != scf_period[i].clock) 308 continue; 309 if (scf_period[i].period == sync) { 310 /* ok, found it. we now are sync. */ 311 siop_target->offset = offset; 312 siop_target->period = sync; 313 sc->targets[target]->id &= 314 ~(SCNTL3_SCF_MASK << 24); 315 sc->targets[target]->id |= scf_period[i].scf 316 << (24 + SCNTL3_SCF_SHIFT); 317 if (sync < 25) /* Ultra */ 318 sc->targets[target]->id |= 319 SCNTL3_ULTRA << 24; 320 else 321 sc->targets[target]->id &= 322 ~(SCNTL3_ULTRA << 24); 323 sc->targets[target]->id &= 324 ~(SXFER_MO_MASK << 8); 325 sc->targets[target]->id |= 326 (offset & SXFER_MO_MASK) << 8; 327 goto end; 328 } 329 } 330 /* 331 * we didn't find it in our table, do async and send reject 332 * msg 333 */ 334 reject: 335 send_msgout = 1; 336 tables->t_msgout.count= htole32(1); 337 tables->msg_out[0] = MSG_MESSAGE_REJECT; 338 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 339 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 340 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 341 siop_target->offset = siop_target->period = 0; 342 } else { /* target initiated sync neg */ 343 #ifdef DEBUG 344 printf("sdtr (target): sync %d offset %d\n", sync, offset); 345 #endif 346 if (offset == 0 || sync > sc->maxsync) { /* async */ 347 goto async; 348 } 349 if (offset > sc->maxoff) 350 offset = sc->maxoff; 351 if (sync < sc->minsync) 352 sync = sc->minsync; 353 /* look for sync period */ 354 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 355 i++) { 356 if (sc->clock_period != scf_period[i].clock) 357 continue; 358 if (scf_period[i].period == sync) { 359 /* ok, found it. we now are sync. */ 360 siop_target->offset = offset; 361 siop_target->period = sync; 362 sc->targets[target]->id &= 363 ~(SCNTL3_SCF_MASK << 24); 364 sc->targets[target]->id |= scf_period[i].scf 365 << (24 + SCNTL3_SCF_SHIFT); 366 if (sync < 25) /* Ultra */ 367 sc->targets[target]->id |= 368 SCNTL3_ULTRA << 24; 369 else 370 sc->targets[target]->id &= 371 ~(SCNTL3_ULTRA << 24); 372 sc->targets[target]->id &= 373 ~(SXFER_MO_MASK << 8); 374 sc->targets[target]->id |= 375 (offset & SXFER_MO_MASK) << 8; 376 siop_sdtr_msg(siop_cmd, 0, sync, offset); 377 send_msgout = 1; 378 goto end; 379 } 380 } 381 async: 382 siop_target->offset = siop_target->period = 0; 383 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 384 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 385 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 386 siop_sdtr_msg(siop_cmd, 0, 0, 0); 387 send_msgout = 1; 388 } 389 end: 390 if (siop_target->status == TARST_OK) 391 siop_update_xfer_mode(sc, target); 392 #ifdef DEBUG 393 printf("id now 0x%x\n", sc->targets[target]->id); 394 #endif 395 tables->id = htole32(sc->targets[target]->id); 396 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 397 (sc->targets[target]->id >> 24) & 0xff); 398 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 399 (sc->targets[target]->id >> 8) & 0xff); 400 if (send_msgout) { 401 return SIOP_NEG_MSGOUT; 402 } else { 403 return SIOP_NEG_ACK; 404 } 405 } 406 407 void 408 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 409 struct siop_common_cmd *siop_cmd; 410 int offset; 411 int ssync, soff; 412 { 413 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 414 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 415 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_SDTR; 416 siop_cmd->siop_tables->msg_out[offset + 3] = ssync; 417 siop_cmd->siop_tables->msg_out[offset + 4] = soff; 418 siop_cmd->siop_tables->t_msgout.count = 419 htole32(offset + MSG_EXT_SDTR_LEN + 2); 420 } 421 422 void 423 siop_wdtr_msg(siop_cmd, offset, wide) 424 struct siop_common_cmd *siop_cmd; 425 int offset; 426 { 427 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 428 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 429 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_WDTR; 430 siop_cmd->siop_tables->msg_out[offset + 3] = wide; 431 siop_cmd->siop_tables->t_msgout.count = 432 htole32(offset + MSG_EXT_WDTR_LEN + 2); 433 } 434 435 void 436 siop_minphys(bp) 437 struct buf *bp; 438 { 439 minphys(bp); 440 } 441 442 int 443 siop_ioctl(chan, cmd, arg, flag, p) 444 struct scsipi_channel *chan; 445 u_long cmd; 446 caddr_t arg; 447 int flag; 448 struct proc *p; 449 { 450 struct siop_common_softc *sc = (void *)chan->chan_adapter->adapt_dev; 451 u_int8_t scntl1; 452 int s; 453 454 switch (cmd) { 455 case SCBUSIORESET: 456 s = splbio(); 457 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 458 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 459 scntl1 | SCNTL1_RST); 460 /* minimum 25 us, more time won't hurt */ 461 delay(100); 462 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 463 splx(s); 464 return (0); 465 default: 466 return (ENOTTY); 467 } 468 } 469 470 void 471 siop_sdp(siop_cmd) 472 struct siop_common_cmd *siop_cmd; 473 { 474 /* save data pointer. Handle async only for now */ 475 int offset, dbc, sstat; 476 struct siop_common_softc *sc = siop_cmd->siop_sc; 477 scr_table_t *table; /* table to patch */ 478 479 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 480 == 0) 481 return; /* no data pointers to save */ 482 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 483 if (offset >= SIOP_NSG) { 484 printf("%s: bad offset in siop_sdp (%d)\n", 485 sc->sc_dev.dv_xname, offset); 486 return; 487 } 488 table = &siop_cmd->siop_tables->data[offset]; 489 #ifdef DEBUG_DR 490 printf("sdp: offset %d count=%d addr=0x%x ", offset, 491 table->count, table->addr); 492 #endif 493 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 494 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 495 if (sc->features & SF_CHIP_DFBC) { 496 dbc += 497 bus_space_read_2(sc->sc_rt, sc->sc_rh, SIOP_DFBC); 498 } else { 499 /* need to account stale data in FIFO */ 500 int dfifo = 501 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 502 if (sc->features & SF_CHIP_FIFO) { 503 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 504 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 505 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 506 } else { 507 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 508 } 509 } 510 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 511 if (sstat & SSTAT0_OLF) 512 dbc++; 513 if ((sstat & SSTAT0_ORF) && (sc->features & SF_CHIP_DFBC) == 0) 514 dbc++; 515 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 516 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 517 SIOP_SSTAT2); 518 if (sstat & SSTAT2_OLF1) 519 dbc++; 520 if ((sstat & SSTAT2_ORF1) && 521 (sc->features & SF_CHIP_DFBC) == 0) 522 dbc++; 523 } 524 /* clear the FIFO */ 525 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 526 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 527 CTEST3_CLF); 528 } 529 table->addr = 530 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 531 table->count = htole32(dbc); 532 #ifdef DEBUG_DR 533 printf("now count=%d addr=0x%x\n", table->count, table->addr); 534 #endif 535 } 536 537 void 538 siop_clearfifo(sc) 539 struct siop_common_softc *sc; 540 { 541 int timeout = 0; 542 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 543 544 #ifdef DEBUG_INTR 545 printf("DMA fifo not empty !\n"); 546 #endif 547 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 548 ctest3 | CTEST3_CLF); 549 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 550 CTEST3_CLF) != 0) { 551 delay(1); 552 if (++timeout > 1000) { 553 printf("clear fifo failed\n"); 554 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 555 bus_space_read_1(sc->sc_rt, sc->sc_rh, 556 SIOP_CTEST3) & ~CTEST3_CLF); 557 return; 558 } 559 } 560 } 561 562 int 563 siop_modechange(sc) 564 struct siop_common_softc *sc; 565 { 566 int retry; 567 int sist0, sist1, stest2, stest4; 568 for (retry = 0; retry < 5; retry++) { 569 /* 570 * datasheet says to wait 100ms and re-read SIST1, 571 * to check that DIFFSENSE is stable. 572 * We may delay() 5 times for 100ms at interrupt time; 573 * hopefully this will not happen often. 574 */ 575 delay(100000); 576 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 577 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 578 if (sist1 & SIEN1_SBMC) 579 continue; /* we got an irq again */ 580 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 581 STEST4_MODE_MASK; 582 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 583 switch(stest4) { 584 case STEST4_MODE_DIF: 585 printf("%s: switching to differential mode\n", 586 sc->sc_dev.dv_xname); 587 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 588 stest2 | STEST2_DIF); 589 break; 590 case STEST4_MODE_SE: 591 printf("%s: switching to single-ended mode\n", 592 sc->sc_dev.dv_xname); 593 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 594 stest2 & ~STEST2_DIF); 595 break; 596 case STEST4_MODE_LVD: 597 printf("%s: switching to LVD mode\n", 598 sc->sc_dev.dv_xname); 599 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 600 stest2 & ~STEST2_DIF); 601 break; 602 default: 603 printf("%s: invalid SCSI mode 0x%x\n", 604 sc->sc_dev.dv_xname, stest4); 605 return 0; 606 } 607 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 608 stest4 >> 2); 609 return 1; 610 } 611 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 612 sc->sc_dev.dv_xname); 613 return 0; 614 } 615 616 void 617 siop_resetbus(sc) 618 struct siop_common_softc *sc; 619 { 620 int scntl1; 621 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 622 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 623 scntl1 | SCNTL1_RST); 624 /* minimum 25 us, more time won't hurt */ 625 delay(100); 626 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 627 } 628 629 void 630 siop_update_xfer_mode(sc, target) 631 struct siop_common_softc *sc; 632 int target; 633 { 634 struct siop_common_target *siop_target = sc->targets[target]; 635 struct scsipi_xfer_mode xm; 636 637 xm.xm_target = target; 638 xm.xm_mode = 0; 639 xm.xm_period = 0; 640 xm.xm_offset = 0; 641 642 if (siop_target->flags & TARF_ISWIDE) 643 xm.xm_mode |= PERIPH_CAP_WIDE16; 644 if (siop_target->period) { 645 xm.xm_period = siop_target->period; 646 xm.xm_offset = siop_target->offset; 647 xm.xm_mode |= PERIPH_CAP_SYNC; 648 } 649 if (siop_target->flags & TARF_TAG) 650 xm.xm_mode |= PERIPH_CAP_TQING; 651 scsipi_async_event(&sc->sc_chan, ASYNC_EVENT_XFER_MODE, &xm); 652 } 653
Indexes created Wed Sep 24 02:09:48 GMT 2025