siop_common.c revision 1.20
1 /* $NetBSD: siop_common.c,v 1.20 2002/04/22 20:31:49 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: siop_common.c,v 1.20 2002/04/22 20:31:49 bouyer Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/buf.h> 43 #include <sys/kernel.h> 44 #include <sys/scsiio.h> 45 46 #include <machine/endian.h> 47 #include <machine/bus.h> 48 49 #include <dev/scsipi/scsi_all.h> 50 #include <dev/scsipi/scsi_message.h> 51 #include <dev/scsipi/scsipi_all.h> 52 53 #include <dev/scsipi/scsiconf.h> 54 55 #include <dev/ic/siopreg.h> 56 #include <dev/ic/siopvar_common.h> 57 58 #include "opt_siop.h" 59 60 #undef DEBUG 61 #undef DEBUG_DR 62 63 void 64 siop_common_reset(sc) 65 struct siop_common_softc *sc; 66 { 67 u_int32_t stest3; 68 69 /* reset the chip */ 70 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 71 delay(1000); 72 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 73 74 /* init registers */ 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 76 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 78 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 80 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 82 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 84 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 86 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 88 (0xb << STIME0_SEL_SHIFT)); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 90 sc->sc_chan.chan_id | SCID_RRE); 91 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 92 1 << sc->sc_chan.chan_id); 93 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 94 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 95 96 /* enable clock doubler or quadruler if appropriate */ 97 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 98 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 99 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 100 STEST1_DBLEN); 101 if (sc->features & SF_CHIP_QUAD) { 102 /* wait for PPL to lock */ 103 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 104 SIOP_STEST4) & STEST4_LOCK) == 0) 105 delay(10); 106 } else { 107 /* data sheet says 20us - more won't hurt */ 108 delay(100); 109 } 110 /* halt scsi clock, select doubler/quad, restart clock */ 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 112 stest3 | STEST3_HSC); 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 114 STEST1_DBLEN | STEST1_DBLSEL); 115 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 116 } else { 117 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 118 } 119 if (sc->features & SF_CHIP_FIFO) 120 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 121 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 122 CTEST5_DFS); 123 #ifdef SIOP_SYMLED 124 /* Set GPIO0 as output if software LED control is required */ 125 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL, 126 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL) & 0xfe); 127 #endif 128 129 sc->sc_reset(sc); 130 } 131 132 /* prepare tables before sending a cmd */ 133 void 134 siop_setuptables(siop_cmd) 135 struct siop_common_cmd *siop_cmd; 136 { 137 int i; 138 struct siop_common_softc *sc = siop_cmd->siop_sc; 139 struct scsipi_xfer *xs = siop_cmd->xs; 140 int target = xs->xs_periph->periph_target; 141 int lun = xs->xs_periph->periph_lun; 142 int msgoffset = 1; 143 144 siop_cmd->siop_tables->id = htole32(sc->targets[target]->id); 145 memset(siop_cmd->siop_tables->msg_out, 0, 8); 146 /* request sense doesn't disconnect */ 147 if (xs->xs_control & XS_CTL_REQSENSE) 148 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 0); 149 else 150 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 1); 151 siop_cmd->siop_tables->t_msgout.count= htole32(1); 152 if (xs->xs_tag_type != 0) { 153 if ((sc->targets[target]->flags & TARF_TAG) == 0) { 154 scsipi_printaddr(xs->xs_periph); 155 printf(": tagged command type %d id %d\n", 156 siop_cmd->xs->xs_tag_type, siop_cmd->xs->xs_tag_id); 157 panic("tagged command for non-tagging device\n"); 158 } 159 siop_cmd->flags |= CMDFL_TAG; 160 siop_cmd->siop_tables->msg_out[1] = siop_cmd->xs->xs_tag_type; 161 /* 162 * use siop_cmd->tag not xs->xs_tag_id, caller may want a 163 * different one 164 */ 165 siop_cmd->siop_tables->msg_out[2] = siop_cmd->tag; 166 siop_cmd->siop_tables->t_msgout.count = htole32(3); 167 msgoffset = 3; 168 } 169 if (sc->targets[target]->status == TARST_ASYNC) { 170 if (sc->targets[target]->flags & TARF_WIDE) { 171 sc->targets[target]->status = TARST_WIDE_NEG; 172 siop_wdtr_msg(siop_cmd, msgoffset, 173 MSG_EXT_WDTR_BUS_16_BIT); 174 } else if (sc->targets[target]->flags & TARF_SYNC) { 175 sc->targets[target]->status = TARST_SYNC_NEG; 176 siop_sdtr_msg(siop_cmd, msgoffset, 177 sc->minsync, sc->maxoff); 178 } else { 179 sc->targets[target]->status = TARST_OK; 180 siop_update_xfer_mode(sc, target); 181 } 182 } 183 if (xs->xs_tag_type != 0 && (siop_cmd->flags & CMDFL_TAG) == 0) 184 printf("siop_setuptables: tagged CMD type 0x%x for target %d lun %d runs untagged, status 0x%x flags 0x%x\n", xs->xs_tag_type, target, lun, sc->targets[target]->status, sc->targets[target]->flags); 185 siop_cmd->siop_tables->status = 186 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 187 188 siop_cmd->siop_tables->cmd.count = 189 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 190 siop_cmd->siop_tables->cmd.addr = 191 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 192 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 193 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 194 siop_cmd->siop_tables->data[i].count = 195 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 196 siop_cmd->siop_tables->data[i].addr = 197 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 198 } 199 } 200 } 201 202 int 203 siop_wdtr_neg(siop_cmd) 204 struct siop_common_cmd *siop_cmd; 205 { 206 struct siop_common_softc *sc = siop_cmd->siop_sc; 207 struct siop_common_target *siop_target = siop_cmd->siop_target; 208 int target = siop_cmd->xs->xs_periph->periph_target; 209 struct siop_common_xfer *tables = siop_cmd->siop_tables; 210 211 if (siop_target->status == TARST_WIDE_NEG) { 212 /* we initiated wide negotiation */ 213 switch (tables->msg_in[3]) { 214 case MSG_EXT_WDTR_BUS_8_BIT: 215 siop_target->flags &= ~TARF_ISWIDE; 216 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 217 break; 218 case MSG_EXT_WDTR_BUS_16_BIT: 219 if (siop_target->flags & TARF_WIDE) { 220 siop_target->flags |= TARF_ISWIDE; 221 sc->targets[target]->id |= (SCNTL3_EWS << 24); 222 break; 223 } 224 /* FALLTHROUH */ 225 default: 226 /* 227 * hum, we got more than what we can handle, shoudn't 228 * happen. Reject, and stay async 229 */ 230 siop_target->flags &= ~TARF_ISWIDE; 231 siop_target->status = TARST_OK; 232 siop_target->offset = siop_target->period = 0; 233 siop_update_xfer_mode(sc, target); 234 printf("%s: rejecting invalid wide negotiation from " 235 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 236 tables->msg_in[3]); 237 tables->t_msgout.count= htole32(1); 238 tables->msg_out[0] = MSG_MESSAGE_REJECT; 239 return SIOP_NEG_MSGOUT; 240 } 241 tables->id = htole32(sc->targets[target]->id); 242 bus_space_write_1(sc->sc_rt, sc->sc_rh, 243 SIOP_SCNTL3, 244 (sc->targets[target]->id >> 24) & 0xff); 245 /* we now need to do sync */ 246 if (siop_target->flags & TARF_SYNC) { 247 siop_target->status = TARST_SYNC_NEG; 248 siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff); 249 return SIOP_NEG_MSGOUT; 250 } else { 251 siop_target->status = TARST_OK; 252 siop_update_xfer_mode(sc, target); 253 return SIOP_NEG_ACK; 254 } 255 } else { 256 /* target initiated wide negotiation */ 257 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 258 && (siop_target->flags & TARF_WIDE)) { 259 siop_target->flags |= TARF_ISWIDE; 260 sc->targets[target]->id |= SCNTL3_EWS << 24; 261 } else { 262 siop_target->flags &= ~TARF_ISWIDE; 263 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 264 } 265 tables->id = htole32(sc->targets[target]->id); 266 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 267 (sc->targets[target]->id >> 24) & 0xff); 268 /* 269 * we did reset wide parameters, so fall back to async, 270 * but don't schedule a sync neg, target should initiate it 271 */ 272 siop_target->status = TARST_OK; 273 siop_target->offset = siop_target->period = 0; 274 siop_update_xfer_mode(sc, target); 275 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 276 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 277 return SIOP_NEG_MSGOUT; 278 } 279 } 280 281 int 282 siop_sdtr_neg(siop_cmd) 283 struct siop_common_cmd *siop_cmd; 284 { 285 struct siop_common_softc *sc = siop_cmd->siop_sc; 286 struct siop_common_target *siop_target = siop_cmd->siop_target; 287 int target = siop_cmd->xs->xs_periph->periph_target; 288 int sync, offset, i; 289 int send_msgout = 0; 290 struct siop_common_xfer *tables = siop_cmd->siop_tables; 291 292 sync = tables->msg_in[3]; 293 offset = tables->msg_in[4]; 294 295 if (siop_target->status == TARST_SYNC_NEG) { 296 /* we initiated sync negotiation */ 297 siop_target->status = TARST_OK; 298 #ifdef DEBUG 299 printf("sdtr: sync %d offset %d\n", sync, offset); 300 #endif 301 if (offset > sc->maxoff || sync < sc->minsync || 302 sync > sc->maxsync) 303 goto reject; 304 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 305 i++) { 306 if (sc->clock_period != scf_period[i].clock) 307 continue; 308 if (scf_period[i].period == sync) { 309 /* ok, found it. we now are sync. */ 310 siop_target->offset = offset; 311 siop_target->period = sync; 312 sc->targets[target]->id &= 313 ~(SCNTL3_SCF_MASK << 24); 314 sc->targets[target]->id |= scf_period[i].scf 315 << (24 + SCNTL3_SCF_SHIFT); 316 if (sync < 25) /* Ultra */ 317 sc->targets[target]->id |= 318 SCNTL3_ULTRA << 24; 319 else 320 sc->targets[target]->id &= 321 ~(SCNTL3_ULTRA << 24); 322 sc->targets[target]->id &= 323 ~(SXFER_MO_MASK << 8); 324 sc->targets[target]->id |= 325 (offset & SXFER_MO_MASK) << 8; 326 goto end; 327 } 328 } 329 /* 330 * we didn't find it in our table, do async and send reject 331 * msg 332 */ 333 reject: 334 send_msgout = 1; 335 tables->t_msgout.count= htole32(1); 336 tables->msg_out[0] = MSG_MESSAGE_REJECT; 337 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 338 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 339 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 340 siop_target->offset = siop_target->period = 0; 341 } else { /* target initiated sync neg */ 342 #ifdef DEBUG 343 printf("sdtr (target): sync %d offset %d\n", sync, offset); 344 #endif 345 if (offset == 0 || sync > sc->maxsync) { /* async */ 346 goto async; 347 } 348 if (offset > sc->maxoff) 349 offset = sc->maxoff; 350 if (sync < sc->minsync) 351 sync = sc->minsync; 352 /* look for sync period */ 353 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 354 i++) { 355 if (sc->clock_period != scf_period[i].clock) 356 continue; 357 if (scf_period[i].period == sync) { 358 /* ok, found it. we now are sync. */ 359 siop_target->offset = offset; 360 siop_target->period = sync; 361 sc->targets[target]->id &= 362 ~(SCNTL3_SCF_MASK << 24); 363 sc->targets[target]->id |= scf_period[i].scf 364 << (24 + SCNTL3_SCF_SHIFT); 365 if (sync < 25) /* Ultra */ 366 sc->targets[target]->id |= 367 SCNTL3_ULTRA << 24; 368 else 369 sc->targets[target]->id &= 370 ~(SCNTL3_ULTRA << 24); 371 sc->targets[target]->id &= 372 ~(SXFER_MO_MASK << 8); 373 sc->targets[target]->id |= 374 (offset & SXFER_MO_MASK) << 8; 375 siop_sdtr_msg(siop_cmd, 0, sync, offset); 376 send_msgout = 1; 377 goto end; 378 } 379 } 380 async: 381 siop_target->offset = siop_target->period = 0; 382 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 383 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 384 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 385 siop_sdtr_msg(siop_cmd, 0, 0, 0); 386 send_msgout = 1; 387 } 388 end: 389 if (siop_target->status == TARST_OK) 390 siop_update_xfer_mode(sc, target); 391 #ifdef DEBUG 392 printf("id now 0x%x\n", sc->targets[target]->id); 393 #endif 394 tables->id = htole32(sc->targets[target]->id); 395 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 396 (sc->targets[target]->id >> 24) & 0xff); 397 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 398 (sc->targets[target]->id >> 8) & 0xff); 399 if (send_msgout) { 400 return SIOP_NEG_MSGOUT; 401 } else { 402 return SIOP_NEG_ACK; 403 } 404 } 405 406 void 407 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 408 struct siop_common_cmd *siop_cmd; 409 int offset; 410 int ssync, soff; 411 { 412 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 413 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 414 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_SDTR; 415 siop_cmd->siop_tables->msg_out[offset + 3] = ssync; 416 siop_cmd->siop_tables->msg_out[offset + 4] = soff; 417 siop_cmd->siop_tables->t_msgout.count = 418 htole32(offset + MSG_EXT_SDTR_LEN + 2); 419 } 420 421 void 422 siop_wdtr_msg(siop_cmd, offset, wide) 423 struct siop_common_cmd *siop_cmd; 424 int offset; 425 { 426 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 427 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 428 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_WDTR; 429 siop_cmd->siop_tables->msg_out[offset + 3] = wide; 430 siop_cmd->siop_tables->t_msgout.count = 431 htole32(offset + MSG_EXT_WDTR_LEN + 2); 432 } 433 434 void 435 siop_minphys(bp) 436 struct buf *bp; 437 { 438 minphys(bp); 439 } 440 441 int 442 siop_ioctl(chan, cmd, arg, flag, p) 443 struct scsipi_channel *chan; 444 u_long cmd; 445 caddr_t arg; 446 int flag; 447 struct proc *p; 448 { 449 struct siop_common_softc *sc = (void *)chan->chan_adapter->adapt_dev; 450 u_int8_t scntl1; 451 int s; 452 453 switch (cmd) { 454 case SCBUSIORESET: 455 s = splbio(); 456 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 457 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 458 scntl1 | SCNTL1_RST); 459 /* minimum 25 us, more time won't hurt */ 460 delay(100); 461 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 462 splx(s); 463 return (0); 464 default: 465 return (ENOTTY); 466 } 467 } 468 469 void 470 siop_sdp(siop_cmd) 471 struct siop_common_cmd *siop_cmd; 472 { 473 /* save data pointer. Handle async only for now */ 474 int offset, dbc, sstat; 475 struct siop_common_softc *sc = siop_cmd->siop_sc; 476 scr_table_t *table; /* table to patch */ 477 478 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 479 == 0) 480 return; /* no data pointers to save */ 481 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 482 if (offset >= SIOP_NSG) { 483 printf("%s: bad offset in siop_sdp (%d)\n", 484 sc->sc_dev.dv_xname, offset); 485 return; 486 } 487 table = &siop_cmd->siop_tables->data[offset]; 488 #ifdef DEBUG_DR 489 printf("sdp: offset %d count=%d addr=0x%x ", offset, 490 table->count, table->addr); 491 #endif 492 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 493 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 494 if (sc->features & SF_CHIP_DFBC) { 495 dbc += 496 bus_space_read_2(sc->sc_rt, sc->sc_rh, SIOP_DFBC); 497 } else { 498 /* need to account stale data in FIFO */ 499 int dfifo = 500 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 501 if (sc->features & SF_CHIP_FIFO) { 502 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 503 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 504 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 505 } else { 506 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 507 } 508 } 509 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 510 if (sstat & SSTAT0_OLF) 511 dbc++; 512 if ((sstat & SSTAT0_ORF) && (sc->features & SF_CHIP_DFBC) == 0) 513 dbc++; 514 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 515 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 516 SIOP_SSTAT2); 517 if (sstat & SSTAT2_OLF1) 518 dbc++; 519 if ((sstat & SSTAT2_ORF1) && 520 (sc->features & SF_CHIP_DFBC) == 0) 521 dbc++; 522 } 523 /* clear the FIFO */ 524 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 525 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 526 CTEST3_CLF); 527 } 528 table->addr = 529 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 530 table->count = htole32(dbc); 531 #ifdef DEBUG_DR 532 printf("now count=%d addr=0x%x\n", table->count, table->addr); 533 #endif 534 } 535 536 void 537 siop_clearfifo(sc) 538 struct siop_common_softc *sc; 539 { 540 int timeout = 0; 541 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 542 543 #ifdef DEBUG_INTR 544 printf("DMA fifo not empty !\n"); 545 #endif 546 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 547 ctest3 | CTEST3_CLF); 548 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 549 CTEST3_CLF) != 0) { 550 delay(1); 551 if (++timeout > 1000) { 552 printf("clear fifo failed\n"); 553 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 554 bus_space_read_1(sc->sc_rt, sc->sc_rh, 555 SIOP_CTEST3) & ~CTEST3_CLF); 556 return; 557 } 558 } 559 } 560 561 int 562 siop_modechange(sc) 563 struct siop_common_softc *sc; 564 { 565 int retry; 566 int sist0, sist1, stest2, stest4; 567 for (retry = 0; retry < 5; retry++) { 568 /* 569 * datasheet says to wait 100ms and re-read SIST1, 570 * to check that DIFFSENSE is stable. 571 * We may delay() 5 times for 100ms at interrupt time; 572 * hopefully this will not happen often. 573 */ 574 delay(100000); 575 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 576 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 577 if (sist1 & SIEN1_SBMC) 578 continue; /* we got an irq again */ 579 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 580 STEST4_MODE_MASK; 581 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 582 switch(stest4) { 583 case STEST4_MODE_DIF: 584 printf("%s: switching to differential mode\n", 585 sc->sc_dev.dv_xname); 586 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 587 stest2 | STEST2_DIF); 588 break; 589 case STEST4_MODE_SE: 590 printf("%s: switching to single-ended mode\n", 591 sc->sc_dev.dv_xname); 592 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 593 stest2 & ~STEST2_DIF); 594 break; 595 case STEST4_MODE_LVD: 596 printf("%s: switching to LVD mode\n", 597 sc->sc_dev.dv_xname); 598 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 599 stest2 & ~STEST2_DIF); 600 break; 601 default: 602 printf("%s: invalid SCSI mode 0x%x\n", 603 sc->sc_dev.dv_xname, stest4); 604 return 0; 605 } 606 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 607 stest4 >> 2); 608 return 1; 609 } 610 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 611 sc->sc_dev.dv_xname); 612 return 0; 613 } 614 615 void 616 siop_resetbus(sc) 617 struct siop_common_softc *sc; 618 { 619 int scntl1; 620 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 621 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 622 scntl1 | SCNTL1_RST); 623 /* minimum 25 us, more time won't hurt */ 624 delay(100); 625 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 626 } 627 628 void 629 siop_update_xfer_mode(sc, target) 630 struct siop_common_softc *sc; 631 int target; 632 { 633 struct siop_common_target *siop_target = sc->targets[target]; 634 struct scsipi_xfer_mode xm; 635 636 xm.xm_target = target; 637 xm.xm_mode = 0; 638 xm.xm_period = 0; 639 xm.xm_offset = 0; 640 641 if (siop_target->flags & TARF_ISWIDE) 642 xm.xm_mode |= PERIPH_CAP_WIDE16; 643 if (siop_target->period) { 644 xm.xm_period = siop_target->period; 645 xm.xm_offset = siop_target->offset; 646 xm.xm_mode |= PERIPH_CAP_SYNC; 647 } 648 if (siop_target->flags & TARF_TAG) 649 xm.xm_mode |= PERIPH_CAP_TQING; 650 scsipi_async_event(&sc->sc_chan, ASYNC_EVENT_XFER_MODE, &xm); 651 } 652
Indexes created Tue Sep 23 14:10:03 GMT 2025