siop_common.c revision 1.25
1 /* $NetBSD: siop_common.c,v 1.25 2002/04/29 15:45:05 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2002 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: siop_common.c,v 1.25 2002/04/29 15:45:05 bouyer Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/buf.h> 43 #include <sys/kernel.h> 44 #include <sys/scsiio.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <machine/endian.h> 49 #include <machine/bus.h> 50 51 #include <dev/scsipi/scsi_all.h> 52 #include <dev/scsipi/scsi_message.h> 53 #include <dev/scsipi/scsipi_all.h> 54 55 #include <dev/scsipi/scsiconf.h> 56 57 #include <dev/ic/siopreg.h> 58 #include <dev/ic/siopvar_common.h> 59 60 #include "opt_siop.h" 61 62 #undef DEBUG 63 #undef DEBUG_DR 64 #undef DEBUG_NEG 65 66 int 67 siop_common_attach(sc) 68 struct siop_common_softc *sc; 69 { 70 int error, i; 71 bus_dma_segment_t seg; 72 int rseg; 73 74 /* 75 * Allocate DMA-safe memory for the script and map it. 76 */ 77 if ((sc->features & SF_CHIP_RAM) == 0) { 78 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 79 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 80 if (error) { 81 printf("%s: unable to allocate script DMA memory, " 82 "error = %d\n", sc->sc_dev.dv_xname, error); 83 return error; 84 } 85 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, PAGE_SIZE, 86 (caddr_t *)&sc->sc_script, 87 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 88 if (error) { 89 printf("%s: unable to map script DMA memory, " 90 "error = %d\n", sc->sc_dev.dv_xname, error); 91 return error; 92 } 93 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, 94 PAGE_SIZE, 0, BUS_DMA_NOWAIT, &sc->sc_scriptdma); 95 if (error) { 96 printf("%s: unable to create script DMA map, " 97 "error = %d\n", sc->sc_dev.dv_xname, error); 98 return error; 99 } 100 error = bus_dmamap_load(sc->sc_dmat, sc->sc_scriptdma, 101 sc->sc_script, PAGE_SIZE, NULL, BUS_DMA_NOWAIT); 102 if (error) { 103 printf("%s: unable to load script DMA map, " 104 "error = %d\n", sc->sc_dev.dv_xname, error); 105 return error; 106 } 107 sc->sc_scriptaddr = 108 sc->sc_scriptdma->dm_segs[0].ds_addr; 109 sc->ram_size = PAGE_SIZE; 110 } 111 112 sc->sc_adapt.adapt_dev = &sc->sc_dev; 113 sc->sc_adapt.adapt_nchannels = 1; 114 sc->sc_adapt.adapt_openings = 0; 115 sc->sc_adapt.adapt_ioctl = siop_ioctl; 116 sc->sc_adapt.adapt_minphys = minphys; 117 118 memset(&sc->sc_chan, 0, sizeof(sc->sc_chan)); 119 sc->sc_chan.chan_adapter = &sc->sc_adapt; 120 sc->sc_chan.chan_bustype = &scsi_bustype; 121 sc->sc_chan.chan_channel = 0; 122 sc->sc_chan.chan_flags = SCSIPI_CHAN_CANGROW; 123 sc->sc_chan.chan_ntargets = 124 (sc->features & SF_BUS_WIDE) ? 16 : 8; 125 sc->sc_chan.chan_nluns = 8; 126 sc->sc_chan.chan_id = 127 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCID); 128 if (sc->sc_chan.chan_id == 0 || 129 sc->sc_chan.chan_id >= sc->sc_chan.chan_ntargets) 130 sc->sc_chan.chan_id = SIOP_DEFAULT_TARGET; 131 132 for (i = 0; i < 16; i++) 133 sc->targets[i] = NULL; 134 135 /* find min/max sync period for this chip */ 136 sc->st_maxsync = 0; 137 sc->dt_maxsync = 0; 138 sc->st_minsync = 255; 139 sc->dt_minsync = 255; 140 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); i++) { 141 if (sc->clock_period != scf_period[i].clock) 142 continue; 143 if (sc->st_maxsync < scf_period[i].period) 144 sc->st_maxsync = scf_period[i].period; 145 if (sc->st_minsync > scf_period[i].period) 146 sc->st_minsync = scf_period[i].period; 147 } 148 if (sc->st_maxsync == 255 || sc->st_minsync == 0) 149 panic("siop: can't find my sync parameters\n"); 150 for (i = 0; i < sizeof(dt_scf_period) / sizeof(dt_scf_period[0]); i++) { 151 if (sc->clock_period != dt_scf_period[i].clock) 152 continue; 153 if (sc->dt_maxsync < dt_scf_period[i].period) 154 sc->dt_maxsync = dt_scf_period[i].period; 155 if (sc->dt_minsync > dt_scf_period[i].period) 156 sc->dt_minsync = dt_scf_period[i].period; 157 } 158 if (sc->dt_maxsync == 255 || sc->dt_minsync == 0) 159 panic("siop: can't find my sync parameters\n"); 160 return 0; 161 } 162 163 void 164 siop_common_reset(sc) 165 struct siop_common_softc *sc; 166 { 167 u_int32_t stest3; 168 169 /* reset the chip */ 170 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 171 delay(1000); 172 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 173 174 /* init registers */ 175 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 176 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 177 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 178 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 179 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 180 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 181 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 182 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 183 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 184 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 185 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 186 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 187 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 188 (0xb << STIME0_SEL_SHIFT)); 189 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 190 sc->sc_chan.chan_id | SCID_RRE); 191 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 192 1 << sc->sc_chan.chan_id); 193 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 194 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 195 196 /* enable clock doubler or quadruler if appropriate */ 197 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 198 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 199 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 200 STEST1_DBLEN); 201 if (sc->features & SF_CHIP_QUAD) { 202 /* wait for PPL to lock */ 203 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 204 SIOP_STEST4) & STEST4_LOCK) == 0) 205 delay(10); 206 } else { 207 /* data sheet says 20us - more won't hurt */ 208 delay(100); 209 } 210 /* halt scsi clock, select doubler/quad, restart clock */ 211 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 212 stest3 | STEST3_HSC); 213 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 214 STEST1_DBLEN | STEST1_DBLSEL); 215 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 216 } else { 217 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 218 } 219 if (sc->features & SF_CHIP_FIFO) 220 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 221 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 222 CTEST5_DFS); 223 if (sc->features & SF_CHIP_LED0) { 224 /* Set GPIO0 as output if software LED control is required */ 225 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL, 226 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL) & 0xfe); 227 } 228 if (sc->features & SF_BUS_ULTRA3) { 229 /* reset SCNTL4 */ 230 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL4, 0); 231 } 232 233 sc->sc_reset(sc); 234 } 235 236 /* prepare tables before sending a cmd */ 237 void 238 siop_setuptables(siop_cmd) 239 struct siop_common_cmd *siop_cmd; 240 { 241 int i; 242 struct siop_common_softc *sc = siop_cmd->siop_sc; 243 struct scsipi_xfer *xs = siop_cmd->xs; 244 int target = xs->xs_periph->periph_target; 245 int lun = xs->xs_periph->periph_lun; 246 int msgoffset = 1; 247 248 siop_cmd->siop_tables->id = htole32(sc->targets[target]->id); 249 memset(siop_cmd->siop_tables->msg_out, 0, 250 sizeof(siop_cmd->siop_tables->msg_out)); 251 /* request sense doesn't disconnect */ 252 if (xs->xs_control & XS_CTL_REQSENSE) 253 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 0); 254 else 255 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 1); 256 if (xs->xs_tag_type != 0) { 257 if ((sc->targets[target]->flags & TARF_TAG) == 0) { 258 scsipi_printaddr(xs->xs_periph); 259 printf(": tagged command type %d id %d\n", 260 siop_cmd->xs->xs_tag_type, siop_cmd->xs->xs_tag_id); 261 panic("tagged command for non-tagging device\n"); 262 } 263 siop_cmd->flags |= CMDFL_TAG; 264 siop_cmd->siop_tables->msg_out[1] = siop_cmd->xs->xs_tag_type; 265 /* 266 * use siop_cmd->tag not xs->xs_tag_id, caller may want a 267 * different one 268 */ 269 siop_cmd->siop_tables->msg_out[2] = siop_cmd->tag; 270 msgoffset = 3; 271 } 272 siop_cmd->siop_tables->t_msgout.count= htole32(msgoffset); 273 if (sc->targets[target]->status == TARST_ASYNC) { 274 if (sc->targets[target]->flags & TARF_DT) { 275 sc->targets[target]->status = TARST_PPR_NEG; 276 siop_ppr_msg(siop_cmd, msgoffset, sc->dt_minsync, 277 sc->maxoff); 278 } else if (sc->targets[target]->flags & TARF_WIDE) { 279 sc->targets[target]->status = TARST_WIDE_NEG; 280 siop_wdtr_msg(siop_cmd, msgoffset, 281 MSG_EXT_WDTR_BUS_16_BIT); 282 } else if (sc->targets[target]->flags & TARF_SYNC) { 283 sc->targets[target]->status = TARST_SYNC_NEG; 284 siop_sdtr_msg(siop_cmd, msgoffset, sc->st_minsync, 285 (sc->maxoff > 31) ? 31 : sc->maxoff); 286 } else { 287 sc->targets[target]->status = TARST_OK; 288 siop_update_xfer_mode(sc, target); 289 } 290 } 291 siop_cmd->siop_tables->status = 292 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 293 294 siop_cmd->siop_tables->cmd.count = 295 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 296 siop_cmd->siop_tables->cmd.addr = 297 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 298 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 299 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 300 siop_cmd->siop_tables->data[i].count = 301 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 302 siop_cmd->siop_tables->data[i].addr = 303 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 304 } 305 } 306 } 307 308 int 309 siop_wdtr_neg(siop_cmd) 310 struct siop_common_cmd *siop_cmd; 311 { 312 struct siop_common_softc *sc = siop_cmd->siop_sc; 313 struct siop_common_target *siop_target = siop_cmd->siop_target; 314 int target = siop_cmd->xs->xs_periph->periph_target; 315 struct siop_common_xfer *tables = siop_cmd->siop_tables; 316 317 if (siop_target->status == TARST_WIDE_NEG) { 318 /* we initiated wide negotiation */ 319 switch (tables->msg_in[3]) { 320 case MSG_EXT_WDTR_BUS_8_BIT: 321 siop_target->flags &= ~TARF_ISWIDE; 322 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 323 break; 324 case MSG_EXT_WDTR_BUS_16_BIT: 325 if (siop_target->flags & TARF_WIDE) { 326 siop_target->flags |= TARF_ISWIDE; 327 sc->targets[target]->id |= (SCNTL3_EWS << 24); 328 break; 329 } 330 /* FALLTHROUH */ 331 default: 332 /* 333 * hum, we got more than what we can handle, shoudn't 334 * happen. Reject, and stay async 335 */ 336 siop_target->flags &= ~TARF_ISWIDE; 337 siop_target->status = TARST_OK; 338 siop_target->offset = siop_target->period = 0; 339 siop_update_xfer_mode(sc, target); 340 printf("%s: rejecting invalid wide negotiation from " 341 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 342 tables->msg_in[3]); 343 tables->t_msgout.count= htole32(1); 344 tables->msg_out[0] = MSG_MESSAGE_REJECT; 345 return SIOP_NEG_MSGOUT; 346 } 347 tables->id = htole32(sc->targets[target]->id); 348 bus_space_write_1(sc->sc_rt, sc->sc_rh, 349 SIOP_SCNTL3, 350 (sc->targets[target]->id >> 24) & 0xff); 351 /* we now need to do sync */ 352 if (siop_target->flags & TARF_SYNC) { 353 siop_target->status = TARST_SYNC_NEG; 354 siop_sdtr_msg(siop_cmd, 0, sc->st_minsync, 355 (sc->maxoff > 31) ? 31 : sc->maxoff); 356 return SIOP_NEG_MSGOUT; 357 } else { 358 siop_target->status = TARST_OK; 359 siop_update_xfer_mode(sc, target); 360 return SIOP_NEG_ACK; 361 } 362 } else { 363 /* target initiated wide negotiation */ 364 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 365 && (siop_target->flags & TARF_WIDE)) { 366 siop_target->flags |= TARF_ISWIDE; 367 sc->targets[target]->id |= SCNTL3_EWS << 24; 368 } else { 369 siop_target->flags &= ~TARF_ISWIDE; 370 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 371 } 372 tables->id = htole32(sc->targets[target]->id); 373 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 374 (sc->targets[target]->id >> 24) & 0xff); 375 /* 376 * we did reset wide parameters, so fall back to async, 377 * but don't schedule a sync neg, target should initiate it 378 */ 379 siop_target->status = TARST_OK; 380 siop_target->offset = siop_target->period = 0; 381 siop_update_xfer_mode(sc, target); 382 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 383 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 384 return SIOP_NEG_MSGOUT; 385 } 386 } 387 388 int 389 siop_ppr_neg(siop_cmd) 390 struct siop_common_cmd *siop_cmd; 391 { 392 struct siop_common_softc *sc = siop_cmd->siop_sc; 393 struct siop_common_target *siop_target = siop_cmd->siop_target; 394 int target = siop_cmd->xs->xs_periph->periph_target; 395 struct siop_common_xfer *tables = siop_cmd->siop_tables; 396 int sync, offset, options, scf = 0; 397 int i; 398 399 #ifdef DEBUG_NEG 400 printf("%s: anserw on ppr negotiation:", sc->sc_dev.dv_xname); 401 for (i = 0; i < 8; i++) 402 printf(" 0x%x", tables->msg_in[i]); 403 printf("\n"); 404 #endif 405 406 if (siop_target->status == TARST_PPR_NEG) { 407 /* we initiated PPR negotiation */ 408 sync = tables->msg_in[3]; 409 offset = tables->msg_in[5]; 410 options = tables->msg_in[7]; 411 if (options != MSG_EXT_PPR_DT) { 412 /* should't happen */ 413 printf("%s: ppr negotiation for target %d: " 414 "no DT option\n", sc->sc_dev.dv_xname, target); 415 siop_target->status = TARST_ASYNC; 416 siop_target->flags &= ~(TARF_DT | TARF_ISDT); 417 siop_target->offset = 0; 418 siop_target->period = 0; 419 goto reject; 420 } 421 422 if (offset > sc->maxoff || sync < sc->dt_minsync || 423 sync > sc->dt_maxsync) { 424 printf("%s: ppr negotiation for target %d: " 425 "offset (%d) or sync (%d) out of range\n", 426 sc->sc_dev.dv_xname, target, offset, sync); 427 /* should not happen */ 428 siop_target->offset = 0; 429 siop_target->period = 0; 430 goto reject; 431 } else { 432 for (i = 0; i < 433 sizeof(dt_scf_period) / sizeof(dt_scf_period[0]); 434 i++) { 435 if (sc->clock_period != dt_scf_period[i].clock) 436 continue; 437 if (dt_scf_period[i].period == sync) { 438 /* ok, found it. we now are sync. */ 439 siop_target->offset = offset; 440 siop_target->period = sync; 441 scf = dt_scf_period[i].scf; 442 siop_target->flags |= TARF_ISDT; 443 } 444 } 445 if ((siop_target->flags & TARF_ISDT) == 0) { 446 printf("%s: ppr negotiation for target %d: " 447 "sync (%d) incompatible with adapter\n", 448 sc->sc_dev.dv_xname, target, sync); 449 /* 450 * we didn't find it in our table, do async 451 * send reject msg, start SDTR/WDTR neg 452 */ 453 siop_target->status = TARST_ASYNC; 454 siop_target->flags &= ~(TARF_DT | TARF_ISDT); 455 siop_target->offset = 0; 456 siop_target->period = 0; 457 goto reject; 458 } 459 } 460 if (tables->msg_in[6] != 1) { 461 printf("%s: ppr negotiation for target %d: " 462 "transfer width (%d) incompatible with dt\n", 463 sc->sc_dev.dv_xname, target, tables->msg_in[6]); 464 /* DT mode can only be done with wide transfers */ 465 siop_target->status = TARST_ASYNC; 466 goto reject; 467 } 468 siop_target->flags |= TARF_ISWIDE; 469 sc->targets[target]->id |= (SCNTL3_EWS << 24); 470 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 471 sc->targets[target]->id |= scf << (24 + SCNTL3_SCF_SHIFT); 472 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 473 sc->targets[target]->id |= 474 (siop_target->offset & SXFER_MO_MASK) << 8; 475 sc->targets[target]->id &= ~0xff; 476 sc->targets[target]->id |= SCNTL4_U3EN; 477 siop_target->status = TARST_OK; 478 siop_update_xfer_mode(sc, target); 479 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 480 (sc->targets[target]->id >> 24) & 0xff); 481 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 482 (sc->targets[target]->id >> 8) & 0xff); 483 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL4, 484 sc->targets[target]->id & 0xff); 485 return SIOP_NEG_ACK; 486 } else { 487 /* target initiated PPR negotiation, shouldn't happen */ 488 printf("%s: rejecting invalid PPR negotiation from " 489 "target %d\n", sc->sc_dev.dv_xname, target); 490 reject: 491 tables->t_msgout.count= htole32(1); 492 tables->msg_out[0] = MSG_MESSAGE_REJECT; 493 return SIOP_NEG_MSGOUT; 494 } 495 } 496 497 int 498 siop_sdtr_neg(siop_cmd) 499 struct siop_common_cmd *siop_cmd; 500 { 501 struct siop_common_softc *sc = siop_cmd->siop_sc; 502 struct siop_common_target *siop_target = siop_cmd->siop_target; 503 int target = siop_cmd->xs->xs_periph->periph_target; 504 int sync, maxoffset, offset, i; 505 int send_msgout = 0; 506 struct siop_common_xfer *tables = siop_cmd->siop_tables; 507 508 /* limit to Ultra/2 parameters, need PPR for Ultra/3 */ 509 maxoffset = (sc->maxoff > 31) ? 31 : sc->maxoff; 510 511 sync = tables->msg_in[3]; 512 offset = tables->msg_in[4]; 513 514 if (siop_target->status == TARST_SYNC_NEG) { 515 /* we initiated sync negotiation */ 516 siop_target->status = TARST_OK; 517 #ifdef DEBUG 518 printf("sdtr: sync %d offset %d\n", sync, offset); 519 #endif 520 if (offset > maxoffset || sync < sc->st_minsync || 521 sync > sc->st_maxsync) 522 goto reject; 523 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 524 i++) { 525 if (sc->clock_period != scf_period[i].clock) 526 continue; 527 if (scf_period[i].period == sync) { 528 /* ok, found it. we now are sync. */ 529 siop_target->offset = offset; 530 siop_target->period = sync; 531 sc->targets[target]->id &= 532 ~(SCNTL3_SCF_MASK << 24); 533 sc->targets[target]->id |= scf_period[i].scf 534 << (24 + SCNTL3_SCF_SHIFT); 535 if (sync < 25 && /* Ultra */ 536 (sc->features & SF_BUS_ULTRA3) == 0) 537 sc->targets[target]->id |= 538 SCNTL3_ULTRA << 24; 539 else 540 sc->targets[target]->id &= 541 ~(SCNTL3_ULTRA << 24); 542 sc->targets[target]->id &= 543 ~(SXFER_MO_MASK << 8); 544 sc->targets[target]->id |= 545 (offset & SXFER_MO_MASK) << 8; 546 sc->targets[target]->id &= ~0xff; /* scntl4 */ 547 goto end; 548 } 549 } 550 /* 551 * we didn't find it in our table, do async and send reject 552 * msg 553 */ 554 reject: 555 send_msgout = 1; 556 tables->t_msgout.count= htole32(1); 557 tables->msg_out[0] = MSG_MESSAGE_REJECT; 558 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 559 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 560 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 561 sc->targets[target]->id &= ~0xff; /* scntl4 */ 562 siop_target->offset = siop_target->period = 0; 563 } else { /* target initiated sync neg */ 564 #ifdef DEBUG 565 printf("sdtr (target): sync %d offset %d\n", sync, offset); 566 #endif 567 if (offset == 0 || sync > sc->st_maxsync) { /* async */ 568 goto async; 569 } 570 if (offset > maxoffset) 571 offset = maxoffset; 572 if (sync < sc->st_minsync) 573 sync = sc->st_minsync; 574 /* look for sync period */ 575 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 576 i++) { 577 if (sc->clock_period != scf_period[i].clock) 578 continue; 579 if (scf_period[i].period == sync) { 580 /* ok, found it. we now are sync. */ 581 siop_target->offset = offset; 582 siop_target->period = sync; 583 sc->targets[target]->id &= 584 ~(SCNTL3_SCF_MASK << 24); 585 sc->targets[target]->id |= scf_period[i].scf 586 << (24 + SCNTL3_SCF_SHIFT); 587 if (sync < 25 && /* Ultra */ 588 (sc->features & SF_BUS_ULTRA3) == 0) 589 sc->targets[target]->id |= 590 SCNTL3_ULTRA << 24; 591 else 592 sc->targets[target]->id &= 593 ~(SCNTL3_ULTRA << 24); 594 sc->targets[target]->id &= 595 ~(SXFER_MO_MASK << 8); 596 sc->targets[target]->id |= 597 (offset & SXFER_MO_MASK) << 8; 598 sc->targets[target]->id &= ~0xff; /* scntl4 */ 599 siop_sdtr_msg(siop_cmd, 0, sync, offset); 600 send_msgout = 1; 601 goto end; 602 } 603 } 604 async: 605 siop_target->offset = siop_target->period = 0; 606 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 607 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 608 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 609 sc->targets[target]->id &= ~0xff; /* scntl4 */ 610 siop_sdtr_msg(siop_cmd, 0, 0, 0); 611 send_msgout = 1; 612 } 613 end: 614 if (siop_target->status == TARST_OK) 615 siop_update_xfer_mode(sc, target); 616 #ifdef DEBUG 617 printf("id now 0x%x\n", sc->targets[target]->id); 618 #endif 619 tables->id = htole32(sc->targets[target]->id); 620 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 621 (sc->targets[target]->id >> 24) & 0xff); 622 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 623 (sc->targets[target]->id >> 8) & 0xff); 624 if (send_msgout) { 625 return SIOP_NEG_MSGOUT; 626 } else { 627 return SIOP_NEG_ACK; 628 } 629 } 630 631 void 632 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 633 struct siop_common_cmd *siop_cmd; 634 int offset; 635 int ssync, soff; 636 { 637 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 638 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 639 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_SDTR; 640 siop_cmd->siop_tables->msg_out[offset + 3] = ssync; 641 siop_cmd->siop_tables->msg_out[offset + 4] = soff; 642 siop_cmd->siop_tables->t_msgout.count = 643 htole32(offset + MSG_EXT_SDTR_LEN + 2); 644 } 645 646 void 647 siop_wdtr_msg(siop_cmd, offset, wide) 648 struct siop_common_cmd *siop_cmd; 649 int offset; 650 { 651 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 652 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 653 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_WDTR; 654 siop_cmd->siop_tables->msg_out[offset + 3] = wide; 655 siop_cmd->siop_tables->t_msgout.count = 656 htole32(offset + MSG_EXT_WDTR_LEN + 2); 657 } 658 659 void 660 siop_ppr_msg(siop_cmd, offset, ssync, soff) 661 struct siop_common_cmd *siop_cmd; 662 int offset; 663 int ssync, soff; 664 { 665 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 666 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_PPR_LEN; 667 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_PPR; 668 siop_cmd->siop_tables->msg_out[offset + 3] = ssync; 669 siop_cmd->siop_tables->msg_out[offset + 4] = 0; /* reserved */ 670 siop_cmd->siop_tables->msg_out[offset + 5] = soff; 671 siop_cmd->siop_tables->msg_out[offset + 6] = 1; /* wide */ 672 siop_cmd->siop_tables->msg_out[offset + 7] = MSG_EXT_PPR_DT; 673 siop_cmd->siop_tables->t_msgout.count = 674 htole32(offset + MSG_EXT_PPR_LEN + 2); 675 } 676 677 void 678 siop_minphys(bp) 679 struct buf *bp; 680 { 681 minphys(bp); 682 } 683 684 int 685 siop_ioctl(chan, cmd, arg, flag, p) 686 struct scsipi_channel *chan; 687 u_long cmd; 688 caddr_t arg; 689 int flag; 690 struct proc *p; 691 { 692 struct siop_common_softc *sc = (void *)chan->chan_adapter->adapt_dev; 693 694 switch (cmd) { 695 case SCBUSIORESET: 696 /* 697 * abort the script. This will trigger an interrupt, which will 698 * trigger a bus reset. 699 * We can't safely trigger the reset here as we can't access 700 * the required register while the script is running. 701 */ 702 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_ABRT); 703 return (0); 704 default: 705 return (ENOTTY); 706 } 707 } 708 709 void 710 siop_sdp(siop_cmd) 711 struct siop_common_cmd *siop_cmd; 712 { 713 /* save data pointer. Handle async only for now */ 714 int offset, dbc, sstat; 715 struct siop_common_softc *sc = siop_cmd->siop_sc; 716 scr_table_t *table; /* table to patch */ 717 718 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 719 == 0) 720 return; /* no data pointers to save */ 721 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 722 if (offset >= SIOP_NSG) { 723 printf("%s: bad offset in siop_sdp (%d)\n", 724 sc->sc_dev.dv_xname, offset); 725 return; 726 } 727 table = &siop_cmd->siop_tables->data[offset]; 728 #ifdef DEBUG_DR 729 printf("sdp: offset %d count=%d addr=0x%x ", offset, 730 table->count, table->addr); 731 #endif 732 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 733 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 734 if (sc->features & SF_CHIP_DFBC) { 735 dbc += 736 bus_space_read_2(sc->sc_rt, sc->sc_rh, SIOP_DFBC); 737 } else { 738 /* need to account stale data in FIFO */ 739 int dfifo = 740 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 741 if (sc->features & SF_CHIP_FIFO) { 742 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 743 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 744 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 745 } else { 746 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 747 } 748 } 749 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 750 if (sstat & SSTAT0_OLF) 751 dbc++; 752 if ((sstat & SSTAT0_ORF) && (sc->features & SF_CHIP_DFBC) == 0) 753 dbc++; 754 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 755 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 756 SIOP_SSTAT2); 757 if (sstat & SSTAT2_OLF1) 758 dbc++; 759 if ((sstat & SSTAT2_ORF1) && 760 (sc->features & SF_CHIP_DFBC) == 0) 761 dbc++; 762 } 763 /* clear the FIFO */ 764 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 765 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 766 CTEST3_CLF); 767 } 768 table->addr = 769 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 770 table->count = htole32(dbc); 771 #ifdef DEBUG_DR 772 printf("now count=%d addr=0x%x\n", table->count, table->addr); 773 #endif 774 } 775 776 void 777 siop_clearfifo(sc) 778 struct siop_common_softc *sc; 779 { 780 int timeout = 0; 781 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 782 783 #ifdef DEBUG_INTR 784 printf("DMA fifo not empty !\n"); 785 #endif 786 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 787 ctest3 | CTEST3_CLF); 788 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 789 CTEST3_CLF) != 0) { 790 delay(1); 791 if (++timeout > 1000) { 792 printf("clear fifo failed\n"); 793 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 794 bus_space_read_1(sc->sc_rt, sc->sc_rh, 795 SIOP_CTEST3) & ~CTEST3_CLF); 796 return; 797 } 798 } 799 } 800 801 int 802 siop_modechange(sc) 803 struct siop_common_softc *sc; 804 { 805 int retry; 806 int sist0, sist1, stest2, stest4; 807 for (retry = 0; retry < 5; retry++) { 808 /* 809 * datasheet says to wait 100ms and re-read SIST1, 810 * to check that DIFFSENSE is stable. 811 * We may delay() 5 times for 100ms at interrupt time; 812 * hopefully this will not happen often. 813 */ 814 delay(100000); 815 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 816 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 817 if (sist1 & SIEN1_SBMC) 818 continue; /* we got an irq again */ 819 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 820 STEST4_MODE_MASK; 821 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 822 switch(stest4) { 823 case STEST4_MODE_DIF: 824 printf("%s: switching to differential mode\n", 825 sc->sc_dev.dv_xname); 826 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 827 stest2 | STEST2_DIF); 828 break; 829 case STEST4_MODE_SE: 830 printf("%s: switching to single-ended mode\n", 831 sc->sc_dev.dv_xname); 832 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 833 stest2 & ~STEST2_DIF); 834 break; 835 case STEST4_MODE_LVD: 836 printf("%s: switching to LVD mode\n", 837 sc->sc_dev.dv_xname); 838 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 839 stest2 & ~STEST2_DIF); 840 break; 841 default: 842 printf("%s: invalid SCSI mode 0x%x\n", 843 sc->sc_dev.dv_xname, stest4); 844 return 0; 845 } 846 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 847 stest4 >> 2); 848 return 1; 849 } 850 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 851 sc->sc_dev.dv_xname); 852 return 0; 853 } 854 855 void 856 siop_resetbus(sc) 857 struct siop_common_softc *sc; 858 { 859 int scntl1; 860 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 861 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 862 scntl1 | SCNTL1_RST); 863 /* minimum 25 us, more time won't hurt */ 864 delay(100); 865 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 866 } 867 868 void 869 siop_update_xfer_mode(sc, target) 870 struct siop_common_softc *sc; 871 int target; 872 { 873 struct siop_common_target *siop_target = sc->targets[target]; 874 struct scsipi_xfer_mode xm; 875 876 xm.xm_target = target; 877 xm.xm_mode = 0; 878 xm.xm_period = 0; 879 xm.xm_offset = 0; 880 881 if (siop_target->flags & TARF_ISWIDE) 882 xm.xm_mode |= PERIPH_CAP_WIDE16; 883 if (siop_target->period) { 884 xm.xm_period = siop_target->period; 885 xm.xm_offset = siop_target->offset; 886 xm.xm_mode |= PERIPH_CAP_SYNC; 887 } 888 if (siop_target->flags & TARF_TAG) 889 xm.xm_mode |= PERIPH_CAP_TQING; 890 scsipi_async_event(&sc->sc_chan, ASYNC_EVENT_XFER_MODE, &xm); 891 } 892
Indexes created Sat Sep 27 14:09:57 GMT 2025