siop_common.c revision 1.29
1 /* $NetBSD: siop_common.c,v 1.29 2002/07/18 11:59:09 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 2000, 2002 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: siop_common.c,v 1.29 2002/07/18 11:59:09 wiz Exp $"); 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/malloc.h> 42 #include <sys/buf.h> 43 #include <sys/kernel.h> 44 #include <sys/scsiio.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <machine/endian.h> 49 #include <machine/bus.h> 50 51 #include <dev/scsipi/scsi_all.h> 52 #include <dev/scsipi/scsi_message.h> 53 #include <dev/scsipi/scsipi_all.h> 54 55 #include <dev/scsipi/scsiconf.h> 56 57 #include <dev/ic/siopreg.h> 58 #include <dev/ic/siopvar_common.h> 59 60 #include "opt_siop.h" 61 62 #undef DEBUG 63 #undef DEBUG_DR 64 #undef DEBUG_NEG 65 66 int 67 siop_common_attach(sc) 68 struct siop_common_softc *sc; 69 { 70 int error, i; 71 bus_dma_segment_t seg; 72 int rseg; 73 74 /* 75 * Allocate DMA-safe memory for the script and map it. 76 */ 77 if ((sc->features & SF_CHIP_RAM) == 0) { 78 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 79 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT); 80 if (error) { 81 printf("%s: unable to allocate script DMA memory, " 82 "error = %d\n", sc->sc_dev.dv_xname, error); 83 return error; 84 } 85 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, PAGE_SIZE, 86 (caddr_t *)&sc->sc_script, 87 BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 88 if (error) { 89 printf("%s: unable to map script DMA memory, " 90 "error = %d\n", sc->sc_dev.dv_xname, error); 91 return error; 92 } 93 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, 94 PAGE_SIZE, 0, BUS_DMA_NOWAIT, &sc->sc_scriptdma); 95 if (error) { 96 printf("%s: unable to create script DMA map, " 97 "error = %d\n", sc->sc_dev.dv_xname, error); 98 return error; 99 } 100 error = bus_dmamap_load(sc->sc_dmat, sc->sc_scriptdma, 101 sc->sc_script, PAGE_SIZE, NULL, BUS_DMA_NOWAIT); 102 if (error) { 103 printf("%s: unable to load script DMA map, " 104 "error = %d\n", sc->sc_dev.dv_xname, error); 105 return error; 106 } 107 sc->sc_scriptaddr = 108 sc->sc_scriptdma->dm_segs[0].ds_addr; 109 sc->ram_size = PAGE_SIZE; 110 } 111 112 sc->sc_adapt.adapt_dev = &sc->sc_dev; 113 sc->sc_adapt.adapt_nchannels = 1; 114 sc->sc_adapt.adapt_openings = 0; 115 sc->sc_adapt.adapt_ioctl = siop_ioctl; 116 sc->sc_adapt.adapt_minphys = minphys; 117 118 memset(&sc->sc_chan, 0, sizeof(sc->sc_chan)); 119 sc->sc_chan.chan_adapter = &sc->sc_adapt; 120 sc->sc_chan.chan_bustype = &scsi_bustype; 121 sc->sc_chan.chan_channel = 0; 122 sc->sc_chan.chan_flags = SCSIPI_CHAN_CANGROW; 123 sc->sc_chan.chan_ntargets = 124 (sc->features & SF_BUS_WIDE) ? 16 : 8; 125 sc->sc_chan.chan_nluns = 8; 126 sc->sc_chan.chan_id = 127 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCID); 128 if (sc->sc_chan.chan_id == 0 || 129 sc->sc_chan.chan_id >= sc->sc_chan.chan_ntargets) 130 sc->sc_chan.chan_id = SIOP_DEFAULT_TARGET; 131 132 for (i = 0; i < 16; i++) 133 sc->targets[i] = NULL; 134 135 /* find min/max sync period for this chip */ 136 sc->st_maxsync = 0; 137 sc->dt_maxsync = 0; 138 sc->st_minsync = 255; 139 sc->dt_minsync = 255; 140 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); i++) { 141 if (sc->clock_period != scf_period[i].clock) 142 continue; 143 if (sc->st_maxsync < scf_period[i].period) 144 sc->st_maxsync = scf_period[i].period; 145 if (sc->st_minsync > scf_period[i].period) 146 sc->st_minsync = scf_period[i].period; 147 } 148 if (sc->st_maxsync == 255 || sc->st_minsync == 0) 149 panic("siop: can't find my sync parameters\n"); 150 for (i = 0; i < sizeof(dt_scf_period) / sizeof(dt_scf_period[0]); i++) { 151 if (sc->clock_period != dt_scf_period[i].clock) 152 continue; 153 if (sc->dt_maxsync < dt_scf_period[i].period) 154 sc->dt_maxsync = dt_scf_period[i].period; 155 if (sc->dt_minsync > dt_scf_period[i].period) 156 sc->dt_minsync = dt_scf_period[i].period; 157 } 158 if (sc->dt_maxsync == 255 || sc->dt_minsync == 0) 159 panic("siop: can't find my sync parameters\n"); 160 return 0; 161 } 162 163 void 164 siop_common_reset(sc) 165 struct siop_common_softc *sc; 166 { 167 u_int32_t stest3; 168 169 /* reset the chip */ 170 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 171 delay(1000); 172 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 173 174 /* init registers */ 175 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 176 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 177 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 178 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 179 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 180 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 181 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 182 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 183 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 184 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 185 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 186 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 187 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 188 (0xb << STIME0_SEL_SHIFT)); 189 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 190 sc->sc_chan.chan_id | SCID_RRE); 191 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 192 1 << sc->sc_chan.chan_id); 193 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 194 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 195 196 /* enable clock doubler or quadruler if appropriate */ 197 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 198 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 199 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 200 STEST1_DBLEN); 201 if (sc->features & SF_CHIP_QUAD) { 202 /* wait for PPL to lock */ 203 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 204 SIOP_STEST4) & STEST4_LOCK) == 0) 205 delay(10); 206 } else { 207 /* data sheet says 20us - more won't hurt */ 208 delay(100); 209 } 210 /* halt scsi clock, select doubler/quad, restart clock */ 211 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 212 stest3 | STEST3_HSC); 213 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 214 STEST1_DBLEN | STEST1_DBLSEL); 215 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 216 } else { 217 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 218 } 219 if (sc->features & SF_CHIP_FIFO) 220 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 221 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 222 CTEST5_DFS); 223 if (sc->features & SF_CHIP_LED0) { 224 /* Set GPIO0 as output if software LED control is required */ 225 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL, 226 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_GPCNTL) & 0xfe); 227 } 228 if (sc->features & SF_BUS_ULTRA3) { 229 /* reset SCNTL4 */ 230 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL4, 0); 231 } 232 sc->mode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 233 STEST4_MODE_MASK; 234 sc->sc_reset(sc); 235 } 236 237 /* prepare tables before sending a cmd */ 238 void 239 siop_setuptables(siop_cmd) 240 struct siop_common_cmd *siop_cmd; 241 { 242 int i; 243 struct siop_common_softc *sc = siop_cmd->siop_sc; 244 struct scsipi_xfer *xs = siop_cmd->xs; 245 int target = xs->xs_periph->periph_target; 246 int lun = xs->xs_periph->periph_lun; 247 int msgoffset = 1; 248 249 siop_cmd->siop_tables->id = htole32(sc->targets[target]->id); 250 memset(siop_cmd->siop_tables->msg_out, 0, 251 sizeof(siop_cmd->siop_tables->msg_out)); 252 /* request sense doesn't disconnect */ 253 if (xs->xs_control & XS_CTL_REQSENSE) 254 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 0); 255 else if ((sc->features & SF_CHIP_GEBUG) && 256 (sc->targets[target]->flags & TARF_ISWIDE) == 0) 257 /* 258 * 1010 bug: it seems that the 1010 has problems with reselect 259 * when not in wide mode (generate false SCSI gross error). 260 * The FreeBSD sym driver has comments about it but their 261 * workaround (disable SCSI gross error reporting) doesn't 262 * work with my adapter. So disable disconnect when not 263 * wide. 264 */ 265 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 0); 266 else 267 siop_cmd->siop_tables->msg_out[0] = MSG_IDENTIFY(lun, 1); 268 if (xs->xs_tag_type != 0) { 269 if ((sc->targets[target]->flags & TARF_TAG) == 0) { 270 scsipi_printaddr(xs->xs_periph); 271 printf(": tagged command type %d id %d\n", 272 siop_cmd->xs->xs_tag_type, siop_cmd->xs->xs_tag_id); 273 panic("tagged command for non-tagging device\n"); 274 } 275 siop_cmd->flags |= CMDFL_TAG; 276 siop_cmd->siop_tables->msg_out[1] = siop_cmd->xs->xs_tag_type; 277 /* 278 * use siop_cmd->tag not xs->xs_tag_id, caller may want a 279 * different one 280 */ 281 siop_cmd->siop_tables->msg_out[2] = siop_cmd->tag; 282 msgoffset = 3; 283 } 284 siop_cmd->siop_tables->t_msgout.count= htole32(msgoffset); 285 if (sc->targets[target]->status == TARST_ASYNC) { 286 if ((sc->targets[target]->flags & TARF_DT) && 287 (sc->mode == STEST4_MODE_LVD)) { 288 sc->targets[target]->status = TARST_PPR_NEG; 289 siop_ppr_msg(siop_cmd, msgoffset, sc->dt_minsync, 290 sc->maxoff); 291 } else if (sc->targets[target]->flags & TARF_WIDE) { 292 sc->targets[target]->status = TARST_WIDE_NEG; 293 siop_wdtr_msg(siop_cmd, msgoffset, 294 MSG_EXT_WDTR_BUS_16_BIT); 295 } else if (sc->targets[target]->flags & TARF_SYNC) { 296 sc->targets[target]->status = TARST_SYNC_NEG; 297 siop_sdtr_msg(siop_cmd, msgoffset, sc->st_minsync, 298 (sc->maxoff > 31) ? 31 : sc->maxoff); 299 } else { 300 sc->targets[target]->status = TARST_OK; 301 siop_update_xfer_mode(sc, target); 302 } 303 } 304 siop_cmd->siop_tables->status = 305 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 306 307 siop_cmd->siop_tables->cmd.count = 308 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 309 siop_cmd->siop_tables->cmd.addr = 310 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 311 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 312 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 313 siop_cmd->siop_tables->data[i].count = 314 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 315 siop_cmd->siop_tables->data[i].addr = 316 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 317 } 318 } 319 } 320 321 int 322 siop_wdtr_neg(siop_cmd) 323 struct siop_common_cmd *siop_cmd; 324 { 325 struct siop_common_softc *sc = siop_cmd->siop_sc; 326 struct siop_common_target *siop_target = siop_cmd->siop_target; 327 int target = siop_cmd->xs->xs_periph->periph_target; 328 struct siop_common_xfer *tables = siop_cmd->siop_tables; 329 330 if (siop_target->status == TARST_WIDE_NEG) { 331 /* we initiated wide negotiation */ 332 switch (tables->msg_in[3]) { 333 case MSG_EXT_WDTR_BUS_8_BIT: 334 siop_target->flags &= ~TARF_ISWIDE; 335 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 336 break; 337 case MSG_EXT_WDTR_BUS_16_BIT: 338 if (siop_target->flags & TARF_WIDE) { 339 siop_target->flags |= TARF_ISWIDE; 340 sc->targets[target]->id |= (SCNTL3_EWS << 24); 341 break; 342 } 343 /* FALLTHROUH */ 344 default: 345 /* 346 * hum, we got more than what we can handle, shouldn't 347 * happen. Reject, and stay async 348 */ 349 siop_target->flags &= ~TARF_ISWIDE; 350 siop_target->status = TARST_OK; 351 siop_target->offset = siop_target->period = 0; 352 siop_update_xfer_mode(sc, target); 353 printf("%s: rejecting invalid wide negotiation from " 354 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 355 tables->msg_in[3]); 356 tables->t_msgout.count= htole32(1); 357 tables->msg_out[0] = MSG_MESSAGE_REJECT; 358 return SIOP_NEG_MSGOUT; 359 } 360 tables->id = htole32(sc->targets[target]->id); 361 bus_space_write_1(sc->sc_rt, sc->sc_rh, 362 SIOP_SCNTL3, 363 (sc->targets[target]->id >> 24) & 0xff); 364 /* we now need to do sync */ 365 if (siop_target->flags & TARF_SYNC) { 366 siop_target->status = TARST_SYNC_NEG; 367 siop_sdtr_msg(siop_cmd, 0, sc->st_minsync, 368 (sc->maxoff > 31) ? 31 : sc->maxoff); 369 return SIOP_NEG_MSGOUT; 370 } else { 371 siop_target->status = TARST_OK; 372 siop_update_xfer_mode(sc, target); 373 return SIOP_NEG_ACK; 374 } 375 } else { 376 /* target initiated wide negotiation */ 377 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 378 && (siop_target->flags & TARF_WIDE)) { 379 siop_target->flags |= TARF_ISWIDE; 380 sc->targets[target]->id |= SCNTL3_EWS << 24; 381 } else { 382 siop_target->flags &= ~TARF_ISWIDE; 383 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 384 } 385 tables->id = htole32(sc->targets[target]->id); 386 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 387 (sc->targets[target]->id >> 24) & 0xff); 388 /* 389 * we did reset wide parameters, so fall back to async, 390 * but don't schedule a sync neg, target should initiate it 391 */ 392 siop_target->status = TARST_OK; 393 siop_target->offset = siop_target->period = 0; 394 siop_update_xfer_mode(sc, target); 395 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 396 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 397 return SIOP_NEG_MSGOUT; 398 } 399 } 400 401 int 402 siop_ppr_neg(siop_cmd) 403 struct siop_common_cmd *siop_cmd; 404 { 405 struct siop_common_softc *sc = siop_cmd->siop_sc; 406 struct siop_common_target *siop_target = siop_cmd->siop_target; 407 int target = siop_cmd->xs->xs_periph->periph_target; 408 struct siop_common_xfer *tables = siop_cmd->siop_tables; 409 int sync, offset, options, scf = 0; 410 int i; 411 412 #ifdef DEBUG_NEG 413 printf("%s: anserw on ppr negotiation:", sc->sc_dev.dv_xname); 414 for (i = 0; i < 8; i++) 415 printf(" 0x%x", tables->msg_in[i]); 416 printf("\n"); 417 #endif 418 419 if (siop_target->status == TARST_PPR_NEG) { 420 /* we initiated PPR negotiation */ 421 sync = tables->msg_in[3]; 422 offset = tables->msg_in[5]; 423 options = tables->msg_in[7]; 424 if (options != MSG_EXT_PPR_DT) { 425 /* should't happen */ 426 printf("%s: ppr negotiation for target %d: " 427 "no DT option\n", sc->sc_dev.dv_xname, target); 428 siop_target->status = TARST_ASYNC; 429 siop_target->flags &= ~(TARF_DT | TARF_ISDT); 430 siop_target->offset = 0; 431 siop_target->period = 0; 432 goto reject; 433 } 434 435 if (offset > sc->maxoff || sync < sc->dt_minsync || 436 sync > sc->dt_maxsync) { 437 printf("%s: ppr negotiation for target %d: " 438 "offset (%d) or sync (%d) out of range\n", 439 sc->sc_dev.dv_xname, target, offset, sync); 440 /* should not happen */ 441 siop_target->offset = 0; 442 siop_target->period = 0; 443 goto reject; 444 } else { 445 for (i = 0; i < 446 sizeof(dt_scf_period) / sizeof(dt_scf_period[0]); 447 i++) { 448 if (sc->clock_period != dt_scf_period[i].clock) 449 continue; 450 if (dt_scf_period[i].period == sync) { 451 /* ok, found it. we now are sync. */ 452 siop_target->offset = offset; 453 siop_target->period = sync; 454 scf = dt_scf_period[i].scf; 455 siop_target->flags |= TARF_ISDT; 456 } 457 } 458 if ((siop_target->flags & TARF_ISDT) == 0) { 459 printf("%s: ppr negotiation for target %d: " 460 "sync (%d) incompatible with adapter\n", 461 sc->sc_dev.dv_xname, target, sync); 462 /* 463 * we didn't find it in our table, do async 464 * send reject msg, start SDTR/WDTR neg 465 */ 466 siop_target->status = TARST_ASYNC; 467 siop_target->flags &= ~(TARF_DT | TARF_ISDT); 468 siop_target->offset = 0; 469 siop_target->period = 0; 470 goto reject; 471 } 472 } 473 if (tables->msg_in[6] != 1) { 474 printf("%s: ppr negotiation for target %d: " 475 "transfer width (%d) incompatible with dt\n", 476 sc->sc_dev.dv_xname, target, tables->msg_in[6]); 477 /* DT mode can only be done with wide transfers */ 478 siop_target->status = TARST_ASYNC; 479 goto reject; 480 } 481 siop_target->flags |= TARF_ISWIDE; 482 sc->targets[target]->id |= (SCNTL3_EWS << 24); 483 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 484 sc->targets[target]->id |= scf << (24 + SCNTL3_SCF_SHIFT); 485 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 486 sc->targets[target]->id |= 487 (siop_target->offset & SXFER_MO_MASK) << 8; 488 sc->targets[target]->id &= ~0xff; 489 sc->targets[target]->id |= SCNTL4_U3EN; 490 siop_target->status = TARST_OK; 491 siop_update_xfer_mode(sc, target); 492 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 493 (sc->targets[target]->id >> 24) & 0xff); 494 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 495 (sc->targets[target]->id >> 8) & 0xff); 496 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL4, 497 sc->targets[target]->id & 0xff); 498 return SIOP_NEG_ACK; 499 } else { 500 /* target initiated PPR negotiation, shouldn't happen */ 501 printf("%s: rejecting invalid PPR negotiation from " 502 "target %d\n", sc->sc_dev.dv_xname, target); 503 reject: 504 tables->t_msgout.count= htole32(1); 505 tables->msg_out[0] = MSG_MESSAGE_REJECT; 506 return SIOP_NEG_MSGOUT; 507 } 508 } 509 510 int 511 siop_sdtr_neg(siop_cmd) 512 struct siop_common_cmd *siop_cmd; 513 { 514 struct siop_common_softc *sc = siop_cmd->siop_sc; 515 struct siop_common_target *siop_target = siop_cmd->siop_target; 516 int target = siop_cmd->xs->xs_periph->periph_target; 517 int sync, maxoffset, offset, i; 518 int send_msgout = 0; 519 struct siop_common_xfer *tables = siop_cmd->siop_tables; 520 521 /* limit to Ultra/2 parameters, need PPR for Ultra/3 */ 522 maxoffset = (sc->maxoff > 31) ? 31 : sc->maxoff; 523 524 sync = tables->msg_in[3]; 525 offset = tables->msg_in[4]; 526 527 if (siop_target->status == TARST_SYNC_NEG) { 528 /* we initiated sync negotiation */ 529 siop_target->status = TARST_OK; 530 #ifdef DEBUG 531 printf("sdtr: sync %d offset %d\n", sync, offset); 532 #endif 533 if (offset > maxoffset || sync < sc->st_minsync || 534 sync > sc->st_maxsync) 535 goto reject; 536 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 537 i++) { 538 if (sc->clock_period != scf_period[i].clock) 539 continue; 540 if (scf_period[i].period == sync) { 541 /* ok, found it. we now are sync. */ 542 siop_target->offset = offset; 543 siop_target->period = sync; 544 sc->targets[target]->id &= 545 ~(SCNTL3_SCF_MASK << 24); 546 sc->targets[target]->id |= scf_period[i].scf 547 << (24 + SCNTL3_SCF_SHIFT); 548 if (sync < 25 && /* Ultra */ 549 (sc->features & SF_BUS_ULTRA3) == 0) 550 sc->targets[target]->id |= 551 SCNTL3_ULTRA << 24; 552 else 553 sc->targets[target]->id &= 554 ~(SCNTL3_ULTRA << 24); 555 sc->targets[target]->id &= 556 ~(SXFER_MO_MASK << 8); 557 sc->targets[target]->id |= 558 (offset & SXFER_MO_MASK) << 8; 559 sc->targets[target]->id &= ~0xff; /* scntl4 */ 560 goto end; 561 } 562 } 563 /* 564 * we didn't find it in our table, do async and send reject 565 * msg 566 */ 567 reject: 568 send_msgout = 1; 569 tables->t_msgout.count= htole32(1); 570 tables->msg_out[0] = MSG_MESSAGE_REJECT; 571 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 572 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 573 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 574 sc->targets[target]->id &= ~0xff; /* scntl4 */ 575 siop_target->offset = siop_target->period = 0; 576 } else { /* target initiated sync neg */ 577 #ifdef DEBUG 578 printf("sdtr (target): sync %d offset %d\n", sync, offset); 579 #endif 580 if (offset == 0 || sync > sc->st_maxsync) { /* async */ 581 goto async; 582 } 583 if (offset > maxoffset) 584 offset = maxoffset; 585 if (sync < sc->st_minsync) 586 sync = sc->st_minsync; 587 /* look for sync period */ 588 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 589 i++) { 590 if (sc->clock_period != scf_period[i].clock) 591 continue; 592 if (scf_period[i].period == sync) { 593 /* ok, found it. we now are sync. */ 594 siop_target->offset = offset; 595 siop_target->period = sync; 596 sc->targets[target]->id &= 597 ~(SCNTL3_SCF_MASK << 24); 598 sc->targets[target]->id |= scf_period[i].scf 599 << (24 + SCNTL3_SCF_SHIFT); 600 if (sync < 25 && /* Ultra */ 601 (sc->features & SF_BUS_ULTRA3) == 0) 602 sc->targets[target]->id |= 603 SCNTL3_ULTRA << 24; 604 else 605 sc->targets[target]->id &= 606 ~(SCNTL3_ULTRA << 24); 607 sc->targets[target]->id &= 608 ~(SXFER_MO_MASK << 8); 609 sc->targets[target]->id |= 610 (offset & SXFER_MO_MASK) << 8; 611 sc->targets[target]->id &= ~0xff; /* scntl4 */ 612 siop_sdtr_msg(siop_cmd, 0, sync, offset); 613 send_msgout = 1; 614 goto end; 615 } 616 } 617 async: 618 siop_target->offset = siop_target->period = 0; 619 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 620 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 621 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 622 sc->targets[target]->id &= ~0xff; /* scntl4 */ 623 siop_sdtr_msg(siop_cmd, 0, 0, 0); 624 send_msgout = 1; 625 } 626 end: 627 if (siop_target->status == TARST_OK) 628 siop_update_xfer_mode(sc, target); 629 #ifdef DEBUG 630 printf("id now 0x%x\n", sc->targets[target]->id); 631 #endif 632 tables->id = htole32(sc->targets[target]->id); 633 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 634 (sc->targets[target]->id >> 24) & 0xff); 635 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 636 (sc->targets[target]->id >> 8) & 0xff); 637 if (send_msgout) { 638 return SIOP_NEG_MSGOUT; 639 } else { 640 return SIOP_NEG_ACK; 641 } 642 } 643 644 void 645 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 646 struct siop_common_cmd *siop_cmd; 647 int offset; 648 int ssync, soff; 649 { 650 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 651 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 652 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_SDTR; 653 siop_cmd->siop_tables->msg_out[offset + 3] = ssync; 654 siop_cmd->siop_tables->msg_out[offset + 4] = soff; 655 siop_cmd->siop_tables->t_msgout.count = 656 htole32(offset + MSG_EXT_SDTR_LEN + 2); 657 } 658 659 void 660 siop_wdtr_msg(siop_cmd, offset, wide) 661 struct siop_common_cmd *siop_cmd; 662 int offset; 663 { 664 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 665 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 666 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_WDTR; 667 siop_cmd->siop_tables->msg_out[offset + 3] = wide; 668 siop_cmd->siop_tables->t_msgout.count = 669 htole32(offset + MSG_EXT_WDTR_LEN + 2); 670 } 671 672 void 673 siop_ppr_msg(siop_cmd, offset, ssync, soff) 674 struct siop_common_cmd *siop_cmd; 675 int offset; 676 int ssync, soff; 677 { 678 siop_cmd->siop_tables->msg_out[offset + 0] = MSG_EXTENDED; 679 siop_cmd->siop_tables->msg_out[offset + 1] = MSG_EXT_PPR_LEN; 680 siop_cmd->siop_tables->msg_out[offset + 2] = MSG_EXT_PPR; 681 siop_cmd->siop_tables->msg_out[offset + 3] = ssync; 682 siop_cmd->siop_tables->msg_out[offset + 4] = 0; /* reserved */ 683 siop_cmd->siop_tables->msg_out[offset + 5] = soff; 684 siop_cmd->siop_tables->msg_out[offset + 6] = 1; /* wide */ 685 siop_cmd->siop_tables->msg_out[offset + 7] = MSG_EXT_PPR_DT; 686 siop_cmd->siop_tables->t_msgout.count = 687 htole32(offset + MSG_EXT_PPR_LEN + 2); 688 } 689 690 void 691 siop_minphys(bp) 692 struct buf *bp; 693 { 694 minphys(bp); 695 } 696 697 int 698 siop_ioctl(chan, cmd, arg, flag, p) 699 struct scsipi_channel *chan; 700 u_long cmd; 701 caddr_t arg; 702 int flag; 703 struct proc *p; 704 { 705 struct siop_common_softc *sc = (void *)chan->chan_adapter->adapt_dev; 706 707 switch (cmd) { 708 case SCBUSIORESET: 709 /* 710 * abort the script. This will trigger an interrupt, which will 711 * trigger a bus reset. 712 * We can't safely trigger the reset here as we can't access 713 * the required register while the script is running. 714 */ 715 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_ABRT); 716 return (0); 717 default: 718 return (ENOTTY); 719 } 720 } 721 722 void 723 siop_sdp(siop_cmd) 724 struct siop_common_cmd *siop_cmd; 725 { 726 /* save data pointer. Handle async only for now */ 727 int offset, dbc, sstat; 728 struct siop_common_softc *sc = siop_cmd->siop_sc; 729 scr_table_t *table; /* table to patch */ 730 731 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 732 == 0) 733 return; /* no data pointers to save */ 734 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 735 if (offset >= SIOP_NSG) { 736 printf("%s: bad offset in siop_sdp (%d)\n", 737 sc->sc_dev.dv_xname, offset); 738 return; 739 } 740 table = &siop_cmd->siop_tables->data[offset]; 741 #ifdef DEBUG_DR 742 printf("sdp: offset %d count=%d addr=0x%x ", offset, 743 table->count, table->addr); 744 #endif 745 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 746 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 747 if (sc->features & SF_CHIP_DFBC) { 748 dbc += 749 bus_space_read_2(sc->sc_rt, sc->sc_rh, SIOP_DFBC); 750 } else { 751 /* need to account stale data in FIFO */ 752 int dfifo = 753 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 754 if (sc->features & SF_CHIP_FIFO) { 755 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 756 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 757 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 758 } else { 759 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 760 } 761 } 762 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 763 if (sstat & SSTAT0_OLF) 764 dbc++; 765 if ((sstat & SSTAT0_ORF) && (sc->features & SF_CHIP_DFBC) == 0) 766 dbc++; 767 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 768 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 769 SIOP_SSTAT2); 770 if (sstat & SSTAT2_OLF1) 771 dbc++; 772 if ((sstat & SSTAT2_ORF1) && 773 (sc->features & SF_CHIP_DFBC) == 0) 774 dbc++; 775 } 776 /* clear the FIFO */ 777 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 778 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 779 CTEST3_CLF); 780 } 781 table->addr = 782 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 783 table->count = htole32(dbc); 784 #ifdef DEBUG_DR 785 printf("now count=%d addr=0x%x\n", table->count, table->addr); 786 #endif 787 } 788 789 void 790 siop_clearfifo(sc) 791 struct siop_common_softc *sc; 792 { 793 int timeout = 0; 794 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 795 796 #ifdef DEBUG_INTR 797 printf("DMA fifo not empty !\n"); 798 #endif 799 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 800 ctest3 | CTEST3_CLF); 801 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 802 CTEST3_CLF) != 0) { 803 delay(1); 804 if (++timeout > 1000) { 805 printf("clear fifo failed\n"); 806 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 807 bus_space_read_1(sc->sc_rt, sc->sc_rh, 808 SIOP_CTEST3) & ~CTEST3_CLF); 809 return; 810 } 811 } 812 } 813 814 int 815 siop_modechange(sc) 816 struct siop_common_softc *sc; 817 { 818 int retry; 819 int sist0, sist1, stest2; 820 for (retry = 0; retry < 5; retry++) { 821 /* 822 * datasheet says to wait 100ms and re-read SIST1, 823 * to check that DIFFSENSE is stable. 824 * We may delay() 5 times for 100ms at interrupt time; 825 * hopefully this will not happen often. 826 */ 827 delay(100000); 828 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 829 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 830 if (sist1 & SIEN1_SBMC) 831 continue; /* we got an irq again */ 832 sc->mode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 833 STEST4_MODE_MASK; 834 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 835 switch(sc->mode) { 836 case STEST4_MODE_DIF: 837 printf("%s: switching to differential mode\n", 838 sc->sc_dev.dv_xname); 839 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 840 stest2 | STEST2_DIF); 841 break; 842 case STEST4_MODE_SE: 843 printf("%s: switching to single-ended mode\n", 844 sc->sc_dev.dv_xname); 845 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 846 stest2 & ~STEST2_DIF); 847 break; 848 case STEST4_MODE_LVD: 849 printf("%s: switching to LVD mode\n", 850 sc->sc_dev.dv_xname); 851 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 852 stest2 & ~STEST2_DIF); 853 break; 854 default: 855 printf("%s: invalid SCSI mode 0x%x\n", 856 sc->sc_dev.dv_xname, sc->mode); 857 return 0; 858 } 859 return 1; 860 } 861 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 862 sc->sc_dev.dv_xname); 863 return 0; 864 } 865 866 void 867 siop_resetbus(sc) 868 struct siop_common_softc *sc; 869 { 870 int scntl1; 871 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 872 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 873 scntl1 | SCNTL1_RST); 874 /* minimum 25 us, more time won't hurt */ 875 delay(100); 876 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 877 } 878 879 void 880 siop_update_xfer_mode(sc, target) 881 struct siop_common_softc *sc; 882 int target; 883 { 884 struct siop_common_target *siop_target = sc->targets[target]; 885 struct scsipi_xfer_mode xm; 886 887 xm.xm_target = target; 888 xm.xm_mode = 0; 889 xm.xm_period = 0; 890 xm.xm_offset = 0; 891 892 893 if (siop_target->flags & TARF_ISWIDE) 894 xm.xm_mode |= PERIPH_CAP_WIDE16; 895 if (siop_target->period) { 896 xm.xm_period = siop_target->period; 897 xm.xm_offset = siop_target->offset; 898 xm.xm_mode |= PERIPH_CAP_SYNC; 899 } 900 if (siop_target->flags & TARF_TAG) { 901 /* 1010 workaround: can't do disconnect if not wide, so can't do tag */ 902 if ((sc->features & SF_CHIP_GEBUG) == 0 || 903 (sc->targets[target]->flags & TARF_ISWIDE)) 904 xm.xm_mode |= PERIPH_CAP_TQING; 905 } 906 907 scsipi_async_event(&sc->sc_chan, ASYNC_EVENT_XFER_MODE, &xm); 908 } 909
Indexes created Wed Sep 24 05:09:52 GMT 2025