siop_common.c revision 1.3.2.1
1 /* $NetBSD: siop_common.c,v 1.3.2.1 2000/07/24 16:51:38 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_param.h> 48 #include <vm/vm_kern.h> 49 50 #include <dev/scsipi/scsi_all.h> 51 #include <dev/scsipi/scsi_message.h> 52 #include <dev/scsipi/scsipi_all.h> 53 54 #include <dev/scsipi/scsiconf.h> 55 56 #include <dev/ic/siopreg.h> 57 #include <dev/ic/siopvar.h> 58 #include <dev/ic/siopvar_common.h> 59 60 #undef DEBUG 61 #undef DEBUG_DR 62 63 void 64 siop_common_reset(sc) 65 struct siop_softc *sc; 66 { 67 u_int32_t stest3; 68 69 /* reset the chip */ 70 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 71 delay(1000); 72 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 73 74 /* init registers */ 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 76 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 78 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 0); 80 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 82 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 84 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 86 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 88 (0xb << STIME0_SEL_SHIFT)); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 90 sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE); 91 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 92 1 << sc->sc_link.scsipi_scsi.adapter_target); 93 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 94 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 95 96 /* enable clock doubler or quadruler if appropriate */ 97 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 98 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 99 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 100 STEST1_DBLEN); 101 if (sc->features & SF_CHIP_QUAD) { 102 /* wait for PPL to lock */ 103 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 104 SIOP_STEST4) & STEST4_LOCK) == 0) 105 delay(10); 106 } else { 107 /* data sheet says 20us - more won't hurt */ 108 delay(100); 109 } 110 /* halt scsi clock, select doubler/quad, restart clock */ 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 112 stest3 | STEST3_HSC); 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 114 STEST1_DBLEN | STEST1_DBLSEL); 115 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 116 } else { 117 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 118 } 119 if (sc->features & SF_CHIP_FIFO) 120 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 121 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 122 CTEST5_DFS); 123 124 sc->sc_reset(sc); 125 } 126 127 int 128 siop_wdtr_neg(siop_cmd) 129 struct siop_cmd *siop_cmd; 130 { 131 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 132 struct siop_target *siop_target = siop_cmd->siop_target; 133 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 134 135 if (siop_target->status == TARST_WIDE_NEG) { 136 /* we initiated wide negotiation */ 137 switch (siop_cmd->siop_table->msg_in[3]) { 138 case MSG_EXT_WDTR_BUS_8_BIT: 139 printf("%s: target %d using 8bit transfers\n", 140 sc->sc_dev.dv_xname, target); 141 siop_target->flags &= ~SF_BUS_WIDE; 142 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 143 break; 144 case MSG_EXT_WDTR_BUS_16_BIT: 145 if (sc->features & SF_BUS_WIDE) { 146 printf("%s: target %d using 16bit transfers\n", 147 sc->sc_dev.dv_xname, target); 148 siop_target->flags |= TARF_WIDE; 149 sc->targets[target]->id |= (SCNTL3_EWS << 24); 150 break; 151 } 152 /* FALLTHROUH */ 153 default: 154 /* 155 * hum, we got more than what we can handle, shoudn't 156 * happen. Reject, and stay async 157 */ 158 siop_target->flags &= ~TARF_WIDE; 159 siop_target->status = TARST_OK; 160 printf("%s: rejecting invalid wide negotiation from " 161 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 162 siop_cmd->siop_table->msg_in[3]); 163 siop_cmd->siop_table->t_msgout.count= htole32(1); 164 siop_cmd->siop_table->t_msgout.addr = 165 htole32(siop_cmd->dsa); 166 siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT; 167 return SIOP_NEG_MSGOUT; 168 } 169 siop_cmd->siop_table->id = 170 htole32(sc->targets[target]->id); 171 bus_space_write_1(sc->sc_rt, sc->sc_rh, 172 SIOP_SCNTL3, 173 (sc->targets[target]->id >> 24) & 0xff); 174 /* we now need to do sync */ 175 if ((siop_cmd->xs->sc_link->quirks & SDEV_NOSYNC) == 0) { 176 siop_target->status = TARST_SYNC_NEG; 177 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 178 siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN; 179 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR; 180 siop_cmd->siop_table->msg_out[3] = sc->minsync; 181 siop_cmd->siop_table->msg_out[4] = sc->maxoff; 182 siop_cmd->siop_table->t_msgout.count = 183 htole32(MSG_EXT_SDTR_LEN + 2); 184 siop_cmd->siop_table->t_msgout.addr = 185 htole32(siop_cmd->dsa); 186 return SIOP_NEG_MSGOUT; 187 } else { 188 siop_target->status = TARST_OK; 189 return SIOP_NEG_ACK; 190 } 191 } else { 192 /* target initiated wide negotiation */ 193 if (siop_cmd->siop_table->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 194 && (sc->features & SF_BUS_WIDE)) { 195 printf("%s: target %d using 16bit transfers\n", 196 sc->sc_dev.dv_xname, target); 197 siop_target->flags |= TARF_WIDE; 198 sc->targets[target]->id |= SCNTL3_EWS << 24; 199 siop_cmd->siop_table->msg_out[3] = 200 MSG_EXT_WDTR_BUS_16_BIT; 201 } else { 202 printf("%s: target %d using 8bit transfers\n", 203 sc->sc_dev.dv_xname, target); 204 siop_target->flags &= ~SF_BUS_WIDE; 205 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 206 siop_cmd->siop_table->msg_out[3] = 207 MSG_EXT_WDTR_BUS_8_BIT; 208 } 209 siop_cmd->siop_table->id = 210 htole32(sc->targets[target]->id); 211 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 212 (sc->targets[target]->id >> 24) & 0xff); 213 /* 214 * we did reset wide parameters, so fall back to async, 215 * but don't shedule a sync neg, target should initiate it 216 */ 217 siop_target->status = TARST_OK; 218 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 219 siop_cmd->siop_table->msg_out[1] = MSG_EXT_WDTR_LEN; 220 siop_cmd->siop_table->msg_out[2] = MSG_EXT_WDTR; 221 siop_cmd->siop_table->t_msgout.count= 222 htole32(MSG_EXT_WDTR_LEN + 2); 223 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 224 return SIOP_NEG_MSGOUT; 225 } 226 } 227 228 int 229 siop_sdtr_neg(siop_cmd) 230 struct siop_cmd *siop_cmd; 231 { 232 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 233 struct siop_target *siop_target = siop_cmd->siop_target; 234 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 235 int sync, offset, i; 236 int send_msgout = 0; 237 238 sync = siop_cmd->siop_table->msg_in[3]; 239 offset = siop_cmd->siop_table->msg_in[4]; 240 241 if (siop_target->status == TARST_SYNC_NEG) { 242 /* we initiated sync negotiation */ 243 siop_target->status = TARST_OK; 244 #ifdef DEBUG 245 printf("sdtr: sync %d offset %d\n", sync, offset); 246 #endif 247 if (offset > sc->maxoff || sync < sc->minsync || 248 sync > sc->maxsync) 249 goto reject; 250 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 251 i++) { 252 if (sc->clock_period != scf_period[i].clock) 253 continue; 254 if (scf_period[i].period == sync) { 255 /* ok, found it. we now are sync. */ 256 printf("%s: target %d now synchronous at " 257 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 258 target, scf_period[i].rate, offset); 259 sc->targets[target]->id &= 260 ~(SCNTL3_SCF_MASK << 24); 261 sc->targets[target]->id |= scf_period[i].scf 262 << (24 + SCNTL3_SCF_SHIFT); 263 if (sync < 25) /* Ultra */ 264 sc->targets[target]->id |= 265 SCNTL3_ULTRA << 24; 266 else 267 sc->targets[target]->id &= 268 ~(SCNTL3_ULTRA << 24); 269 sc->targets[target]->id &= 270 ~(SCXFER_MO_MASK << 8); 271 sc->targets[target]->id |= 272 (offset & SCXFER_MO_MASK) << 8; 273 goto end; 274 } 275 } 276 /* 277 * we didn't find it in our table, do async and send reject 278 * msg 279 */ 280 reject: 281 send_msgout = 1; 282 siop_cmd->siop_table->t_msgout.count= htole32(1); 283 siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT; 284 printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname, 285 target); 286 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 287 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 288 sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8); 289 } else { /* target initiated sync neg */ 290 #ifdef DEBUG 291 printf("sdtr (target): sync %d offset %d\n", sync, offset); 292 #endif 293 if (offset == 0 || sync > sc->maxsync) { /* async */ 294 goto async; 295 } 296 if (offset > sc->maxoff) 297 offset = sc->maxoff; 298 if (sync < sc->minsync) 299 sync = sc->minsync; 300 /* look for sync period */ 301 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 302 i++) { 303 if (sc->clock_period != scf_period[i].clock) 304 continue; 305 if (scf_period[i].period == sync) { 306 /* ok, found it. we now are sync. */ 307 printf("%s: target %d now synchronous at " 308 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 309 target, scf_period[i].rate, offset); 310 sc->targets[target]->id &= 311 ~(SCNTL3_SCF_MASK << 24); 312 sc->targets[target]->id |= scf_period[i].scf 313 << (24 + SCNTL3_SCF_SHIFT); 314 if (sync < 25) /* Ultra */ 315 sc->targets[target]->id |= 316 SCNTL3_ULTRA << 24; 317 else 318 sc->targets[target]->id &= 319 ~(SCNTL3_ULTRA << 24); 320 sc->targets[target]->id &= 321 ~(SCXFER_MO_MASK << 8); 322 sc->targets[target]->id |= 323 (offset & SCXFER_MO_MASK) << 8; 324 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 325 siop_cmd->siop_table->msg_out[1] = 326 MSG_EXT_SDTR_LEN; 327 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR; 328 siop_cmd->siop_table->msg_out[3] = sync; 329 siop_cmd->siop_table->msg_out[4] = offset; 330 siop_cmd->siop_table->t_msgout.count= 331 htole32(MSG_EXT_SDTR_LEN + 2); 332 send_msgout = 1; 333 goto end; 334 } 335 } 336 async: 337 printf("%s: target %d asynchronous\n", 338 sc->sc_dev.dv_xname, target); 339 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 340 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 341 sc->targets[target]->id &= ~(SCXFER_MO_MASK << 8); 342 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 343 siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN; 344 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR; 345 siop_cmd->siop_table->msg_out[3] = 0; 346 siop_cmd->siop_table->msg_out[4] = 0; 347 siop_cmd->siop_table->t_msgout.count= 348 htole32(MSG_EXT_SDTR_LEN + 2); 349 send_msgout = 1; 350 } 351 end: 352 #ifdef DEBUG 353 printf("id now 0x%x\n", sc->targets[target]->id); 354 #endif 355 siop_cmd->siop_table->id = htole32(sc->targets[target]->id); 356 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 357 (sc->targets[target]->id >> 24) & 0xff); 358 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCXFER, 359 (sc->targets[target]->id >> 8) & 0xff); 360 if (send_msgout) { 361 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 362 return SIOP_NEG_MSGOUT; 363 } else { 364 return SIOP_NEG_ACK; 365 } 366 } 367 368 void 369 siop_minphys(bp) 370 struct buf *bp; 371 { 372 minphys(bp); 373 } 374 375 int 376 siop_ioctl(link, cmd, arg, flag, p) 377 struct scsipi_link *link; 378 u_long cmd; 379 caddr_t arg; 380 int flag; 381 struct proc *p; 382 { 383 struct siop_softc *sc = link->adapter_softc; 384 u_int8_t scntl1; 385 int s; 386 387 switch (cmd) { 388 case SCBUSIORESET: 389 s = splbio(); 390 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 391 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 392 scntl1 | SCNTL1_RST); 393 /* minimum 25 us, more time won't hurt */ 394 delay(100); 395 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 396 splx(s); 397 return (0); 398 default: 399 return (ENOTTY); 400 } 401 } 402 403 void 404 siop_sdp(siop_cmd) 405 struct siop_cmd *siop_cmd; 406 { 407 /* save data pointer. Handle async only for now */ 408 int offset, dbc, sstat; 409 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 410 scr_table_t *table; /* table to patch */ 411 412 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 413 == 0) 414 return; /* no data pointers to save */ 415 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 416 if (offset >= SIOP_NSG) { 417 printf("%s: bad offset in siop_sdp (%d)\n", 418 sc->sc_dev.dv_xname, offset); 419 return; 420 } 421 table = &siop_cmd->siop_table->data[offset]; 422 #ifdef DEBUG_DR 423 printf("sdp: offset %d count=%d addr=0x%x ", offset, 424 table->count, table->addr); 425 #endif 426 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 427 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 428 /* need to account stale data in FIFO */ 429 int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 430 if (sc->features & SF_CHIP_FIFO) { 431 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 432 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 433 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 434 } else { 435 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 436 } 437 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 438 if (sstat & SSTAT0_OLF) 439 dbc++; 440 if (sstat & SSTAT0_ORF) 441 dbc++; 442 if (siop_cmd->siop_target->flags & TARF_WIDE) { 443 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 444 SIOP_SSTAT2); 445 if (sstat & SSTAT2_OLF1) 446 dbc++; 447 if (sstat & SSTAT2_ORF1) 448 dbc++; 449 } 450 /* clear the FIFO */ 451 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 452 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 453 CTEST3_CLF); 454 } 455 table->addr = 456 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 457 table->count = htole32(dbc); 458 #ifdef DEBUG_DR 459 printf("now count=%d addr=0x%x\n", table->count, table->addr); 460 #endif 461 } 462 463 void 464 siop_clearfifo(sc) 465 struct siop_softc *sc; 466 { 467 int timeout = 0; 468 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 469 470 #ifdef DEBUG_INTR 471 printf("DMA fifo not empty !\n"); 472 #endif 473 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 474 ctest3 | CTEST3_CLF); 475 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 476 CTEST3_CLF) != 0) { 477 delay(1); 478 if (++timeout > 1000) { 479 printf("clear fifo failed\n"); 480 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 481 bus_space_read_1(sc->sc_rt, sc->sc_rh, 482 SIOP_CTEST3) & ~CTEST3_CLF); 483 return; 484 } 485 } 486 } 487 488 int 489 siop_modechange(sc) 490 struct siop_softc *sc; 491 { 492 int retry; 493 int sist0, sist1, stest2, stest4; 494 for (retry = 0; retry < 5; retry++) { 495 /* 496 * datasheet says to wait 100ms and re-read SIST1, 497 * to check that DIFFSENSE is srable. 498 * We may delay() 5 times for 100ms at interrupt time; 499 * hopefully this will not happen often. 500 */ 501 delay(100000); 502 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 503 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 504 if (sist1 & SIEN1_SBMC) 505 continue; /* we got an irq again */ 506 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 507 STEST4_MODE_MASK; 508 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 509 switch(stest4) { 510 case STEST4_MODE_DIF: 511 printf("%s: switching to differential mode\n", 512 sc->sc_dev.dv_xname); 513 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 514 stest2 | STEST2_DIF); 515 break; 516 case STEST4_MODE_SE: 517 printf("%s: switching to single-ended mode\n", 518 sc->sc_dev.dv_xname); 519 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 520 stest2 & ~STEST2_DIF); 521 break; 522 case STEST4_MODE_LVD: 523 printf("%s: switching to LVD mode\n", 524 sc->sc_dev.dv_xname); 525 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 526 stest2 & ~STEST2_DIF); 527 break; 528 default: 529 printf("%s: invalid SCSI mode 0x%x\n", 530 sc->sc_dev.dv_xname, stest4); 531 return 0; 532 } 533 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 534 stest4 >> 2); 535 return 1; 536 } 537 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 538 sc->sc_dev.dv_xname); 539 return 0; 540 } 541 542 void 543 siop_resetbus(sc) 544 struct siop_softc *sc; 545 { 546 int scntl1; 547 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 548 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 549 scntl1 | SCNTL1_RST); 550 /* minimum 25 us, more time won't hurt */ 551 delay(100); 552 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 553 } 554
Indexes created Sun Oct 12 05:10:08 GMT 2025