siop_common.c revision 1.3.2.2
1 /* $NetBSD: siop_common.c,v 1.3.2.2 2000/12/16 01:59:46 he Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <vm/vm.h> 47 #include <vm/vm_param.h> 48 #include <vm/vm_kern.h> 49 50 #include <dev/scsipi/scsi_all.h> 51 #include <dev/scsipi/scsi_message.h> 52 #include <dev/scsipi/scsipi_all.h> 53 54 #include <dev/scsipi/scsiconf.h> 55 56 #include <dev/ic/siopreg.h> 57 #include <dev/ic/siopvar.h> 58 #include <dev/ic/siopvar_common.h> 59 60 #undef DEBUG 61 #undef DEBUG_DR 62 63 void 64 siop_common_reset(sc) 65 struct siop_softc *sc; 66 { 67 u_int32_t stest3; 68 69 /* reset the chip */ 70 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 71 delay(1000); 72 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 73 74 /* init registers */ 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 76 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 78 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 80 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 82 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 84 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 86 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 88 (0xb << STIME0_SEL_SHIFT)); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 90 sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE); 91 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 92 1 << sc->sc_link.scsipi_scsi.adapter_target); 93 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 94 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 95 96 /* enable clock doubler or quadruler if appropriate */ 97 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 98 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 99 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 100 STEST1_DBLEN); 101 if (sc->features & SF_CHIP_QUAD) { 102 /* wait for PPL to lock */ 103 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 104 SIOP_STEST4) & STEST4_LOCK) == 0) 105 delay(10); 106 } else { 107 /* data sheet says 20us - more won't hurt */ 108 delay(100); 109 } 110 /* halt scsi clock, select doubler/quad, restart clock */ 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 112 stest3 | STEST3_HSC); 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 114 STEST1_DBLEN | STEST1_DBLSEL); 115 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 116 } else { 117 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 118 } 119 if (sc->features & SF_CHIP_FIFO) 120 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 121 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 122 CTEST5_DFS); 123 124 sc->sc_reset(sc); 125 } 126 127 /* prepare tables before sending a cmd */ 128 void 129 siop_setuptables(siop_cmd) 130 struct siop_cmd *siop_cmd; 131 { 132 int i; 133 struct siop_softc *sc = siop_cmd->siop_sc; 134 struct scsipi_xfer *xs = siop_cmd->xs; 135 int target = xs->sc_link->scsipi_scsi.target; 136 int lun = xs->sc_link->scsipi_scsi.lun; 137 138 siop_cmd->siop_tables.id = htole32(sc->targets[target]->id); 139 memset(siop_cmd->siop_tables.msg_out, 0, 8); 140 siop_cmd->siop_tables.msg_out[0] = MSG_IDENTIFY(lun, 1); 141 siop_cmd->siop_tables.t_msgout.count= htole32(1); 142 if (sc->targets[target]->status == TARST_ASYNC) { 143 if (sc->targets[target]->flags & TARF_WIDE) { 144 sc->targets[target]->status = TARST_WIDE_NEG; 145 siop_wdtr_msg(siop_cmd, 1, MSG_EXT_WDTR_BUS_16_BIT); 146 } else if (sc->targets[target]->flags & TARF_SYNC) { 147 sc->targets[target]->status = TARST_SYNC_NEG; 148 siop_sdtr_msg(siop_cmd, 1, sc->minsync, sc->maxoff); 149 } else { 150 sc->targets[target]->status = TARST_OK; 151 } 152 } else if (sc->targets[target]->status == TARST_OK && 153 (sc->targets[target]->flags & TARF_TAG) && 154 siop_cmd->status != CMDST_SENSE) { 155 siop_cmd->flags |= CMDFL_TAG; 156 } 157 siop_cmd->siop_tables.status = 158 htole32(SCSI_SIOP_NOSTATUS); /* set invalid status */ 159 160 siop_cmd->siop_tables.cmd.count = 161 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_len); 162 siop_cmd->siop_tables.cmd.addr = 163 htole32(siop_cmd->dmamap_cmd->dm_segs[0].ds_addr); 164 if ((xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) || 165 siop_cmd->status == CMDST_SENSE) { 166 for (i = 0; i < siop_cmd->dmamap_data->dm_nsegs; i++) { 167 siop_cmd->siop_tables.data[i].count = 168 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_len); 169 siop_cmd->siop_tables.data[i].addr = 170 htole32(siop_cmd->dmamap_data->dm_segs[i].ds_addr); 171 } 172 } 173 siop_table_sync(siop_cmd, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 174 } 175 176 int 177 siop_wdtr_neg(siop_cmd) 178 struct siop_cmd *siop_cmd; 179 { 180 struct siop_softc *sc = siop_cmd->siop_sc; 181 struct siop_target *siop_target = siop_cmd->siop_target; 182 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 183 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 184 185 if (siop_target->status == TARST_WIDE_NEG) { 186 /* we initiated wide negotiation */ 187 switch (tables->msg_in[3]) { 188 case MSG_EXT_WDTR_BUS_8_BIT: 189 printf("%s: target %d using 8bit transfers\n", 190 sc->sc_dev.dv_xname, target); 191 siop_target->flags &= ~TARF_ISWIDE; 192 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 193 break; 194 case MSG_EXT_WDTR_BUS_16_BIT: 195 if (siop_target->flags & TARF_WIDE) { 196 printf("%s: target %d using 16bit transfers\n", 197 sc->sc_dev.dv_xname, target); 198 siop_target->flags |= TARF_ISWIDE; 199 sc->targets[target]->id |= (SCNTL3_EWS << 24); 200 break; 201 } 202 /* FALLTHROUH */ 203 default: 204 /* 205 * hum, we got more than what we can handle, shoudn't 206 * happen. Reject, and stay async 207 */ 208 siop_target->flags &= ~TARF_ISWIDE; 209 siop_target->status = TARST_OK; 210 printf("%s: rejecting invalid wide negotiation from " 211 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 212 tables->msg_in[3]); 213 tables->t_msgout.count= htole32(1); 214 tables->msg_out[0] = MSG_MESSAGE_REJECT; 215 return SIOP_NEG_MSGOUT; 216 } 217 tables->id = htole32(sc->targets[target]->id); 218 bus_space_write_1(sc->sc_rt, sc->sc_rh, 219 SIOP_SCNTL3, 220 (sc->targets[target]->id >> 24) & 0xff); 221 /* we now need to do sync */ 222 if (siop_target->flags & TARF_SYNC) { 223 siop_target->status = TARST_SYNC_NEG; 224 siop_sdtr_msg(siop_cmd, 0, sc->minsync, sc->maxoff); 225 return SIOP_NEG_MSGOUT; 226 } else { 227 siop_target->status = TARST_OK; 228 return SIOP_NEG_ACK; 229 } 230 } else { 231 /* target initiated wide negotiation */ 232 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 233 && (siop_target->flags & TARF_WIDE)) { 234 printf("%s: target %d using 16bit transfers\n", 235 sc->sc_dev.dv_xname, target); 236 siop_target->flags |= TARF_ISWIDE; 237 sc->targets[target]->id |= SCNTL3_EWS << 24; 238 } else { 239 printf("%s: target %d using 8bit transfers\n", 240 sc->sc_dev.dv_xname, target); 241 siop_target->flags &= ~TARF_ISWIDE; 242 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 243 } 244 tables->id = htole32(sc->targets[target]->id); 245 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 246 (sc->targets[target]->id >> 24) & 0xff); 247 /* 248 * we did reset wide parameters, so fall back to async, 249 * but don't schedule a sync neg, target should initiate it 250 */ 251 siop_target->status = TARST_OK; 252 siop_wdtr_msg(siop_cmd, 0, (siop_target->flags & TARF_ISWIDE) ? 253 MSG_EXT_WDTR_BUS_16_BIT : MSG_EXT_WDTR_BUS_8_BIT); 254 return SIOP_NEG_MSGOUT; 255 } 256 } 257 258 int 259 siop_sdtr_neg(siop_cmd) 260 struct siop_cmd *siop_cmd; 261 { 262 struct siop_softc *sc = siop_cmd->siop_sc; 263 struct siop_target *siop_target = siop_cmd->siop_target; 264 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 265 int sync, offset, i; 266 int send_msgout = 0; 267 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 268 269 sync = tables->msg_in[3]; 270 offset = tables->msg_in[4]; 271 272 if (siop_target->status == TARST_SYNC_NEG) { 273 /* we initiated sync negotiation */ 274 siop_target->status = TARST_OK; 275 #ifdef DEBUG 276 printf("sdtr: sync %d offset %d\n", sync, offset); 277 #endif 278 if (offset > sc->maxoff || sync < sc->minsync || 279 sync > sc->maxsync) 280 goto reject; 281 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 282 i++) { 283 if (sc->clock_period != scf_period[i].clock) 284 continue; 285 if (scf_period[i].period == sync) { 286 /* ok, found it. we now are sync. */ 287 printf("%s: target %d now synchronous at " 288 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 289 target, scf_period[i].rate, offset); 290 sc->targets[target]->id &= 291 ~(SCNTL3_SCF_MASK << 24); 292 sc->targets[target]->id |= scf_period[i].scf 293 << (24 + SCNTL3_SCF_SHIFT); 294 if (sync < 25) /* Ultra */ 295 sc->targets[target]->id |= 296 SCNTL3_ULTRA << 24; 297 else 298 sc->targets[target]->id &= 299 ~(SCNTL3_ULTRA << 24); 300 sc->targets[target]->id &= 301 ~(SXFER_MO_MASK << 8); 302 sc->targets[target]->id |= 303 (offset & SXFER_MO_MASK) << 8; 304 goto end; 305 } 306 } 307 /* 308 * we didn't find it in our table, do async and send reject 309 * msg 310 */ 311 reject: 312 send_msgout = 1; 313 tables->t_msgout.count= htole32(1); 314 tables->msg_out[0] = MSG_MESSAGE_REJECT; 315 printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname, 316 target); 317 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 318 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 319 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 320 } else { /* target initiated sync neg */ 321 #ifdef DEBUG 322 printf("sdtr (target): sync %d offset %d\n", sync, offset); 323 #endif 324 if (offset == 0 || sync > sc->maxsync) { /* async */ 325 goto async; 326 } 327 if (offset > sc->maxoff) 328 offset = sc->maxoff; 329 if (sync < sc->minsync) 330 sync = sc->minsync; 331 /* look for sync period */ 332 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 333 i++) { 334 if (sc->clock_period != scf_period[i].clock) 335 continue; 336 if (scf_period[i].period == sync) { 337 /* ok, found it. we now are sync. */ 338 printf("%s: target %d now synchronous at " 339 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 340 target, scf_period[i].rate, offset); 341 sc->targets[target]->id &= 342 ~(SCNTL3_SCF_MASK << 24); 343 sc->targets[target]->id |= scf_period[i].scf 344 << (24 + SCNTL3_SCF_SHIFT); 345 if (sync < 25) /* Ultra */ 346 sc->targets[target]->id |= 347 SCNTL3_ULTRA << 24; 348 else 349 sc->targets[target]->id &= 350 ~(SCNTL3_ULTRA << 24); 351 sc->targets[target]->id &= 352 ~(SXFER_MO_MASK << 8); 353 sc->targets[target]->id |= 354 (offset & SXFER_MO_MASK) << 8; 355 siop_sdtr_msg(siop_cmd, 0, sync, offset); 356 send_msgout = 1; 357 goto end; 358 } 359 } 360 async: 361 printf("%s: target %d asynchronous\n", 362 sc->sc_dev.dv_xname, target); 363 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 364 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 365 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 366 siop_sdtr_msg(siop_cmd, 0, 0, 0); 367 send_msgout = 1; 368 } 369 end: 370 #ifdef DEBUG 371 printf("id now 0x%x\n", sc->targets[target]->id); 372 #endif 373 tables->id = htole32(sc->targets[target]->id); 374 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 375 (sc->targets[target]->id >> 24) & 0xff); 376 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 377 (sc->targets[target]->id >> 8) & 0xff); 378 if (send_msgout) { 379 return SIOP_NEG_MSGOUT; 380 } else { 381 return SIOP_NEG_ACK; 382 } 383 } 384 385 void 386 siop_sdtr_msg(siop_cmd, offset, ssync, soff) 387 struct siop_cmd *siop_cmd; 388 int offset; 389 int ssync, soff; 390 { 391 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 392 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_SDTR_LEN; 393 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_SDTR; 394 siop_cmd->siop_tables.msg_out[offset + 3] = ssync; 395 siop_cmd->siop_tables.msg_out[offset + 4] = soff; 396 siop_cmd->siop_tables.t_msgout.count = 397 htole32(offset + MSG_EXT_SDTR_LEN + 2); 398 } 399 400 void 401 siop_wdtr_msg(siop_cmd, offset, wide) 402 struct siop_cmd *siop_cmd; 403 int offset; 404 { 405 siop_cmd->siop_tables.msg_out[offset + 0] = MSG_EXTENDED; 406 siop_cmd->siop_tables.msg_out[offset + 1] = MSG_EXT_WDTR_LEN; 407 siop_cmd->siop_tables.msg_out[offset + 2] = MSG_EXT_WDTR; 408 siop_cmd->siop_tables.msg_out[offset + 3] = wide; 409 siop_cmd->siop_tables.t_msgout.count = 410 htole32(offset + MSG_EXT_WDTR_LEN + 2); 411 } 412 413 void 414 siop_minphys(bp) 415 struct buf *bp; 416 { 417 minphys(bp); 418 } 419 420 int 421 siop_ioctl(link, cmd, arg, flag, p) 422 struct scsipi_link *link; 423 u_long cmd; 424 caddr_t arg; 425 int flag; 426 struct proc *p; 427 { 428 struct siop_softc *sc = link->adapter_softc; 429 u_int8_t scntl1; 430 int s; 431 432 switch (cmd) { 433 case SCBUSACCEL: 434 { 435 struct scbusaccel_args *sp = (struct scbusaccel_args *)arg; 436 s = splbio(); 437 if (sp->sa_lun == 0) { 438 if (sp->sa_flags & SC_ACCEL_TAGS) { 439 sc->targets[sp->sa_target]->flags |= TARF_TAG; 440 printf("%s: target %d using tagged queuing\n", 441 sc->sc_dev.dv_xname, sp->sa_target); 442 } 443 if ((sp->sa_flags & SC_ACCEL_WIDE) && 444 (sc->features & SF_BUS_WIDE)) 445 sc->targets[sp->sa_target]->flags |= TARF_WIDE; 446 if (sp->sa_flags & SC_ACCEL_SYNC) 447 sc->targets[sp->sa_target]->flags |= TARF_SYNC; 448 if ((sp->sa_flags & (SC_ACCEL_SYNC | SC_ACCEL_WIDE)) || 449 sc->targets[sp->sa_target]->status == TARST_PROBING) 450 sc->targets[sp->sa_target]->status = 451 TARST_ASYNC; 452 } 453 454 /* allocate a lun sw entry for this device */ 455 siop_add_dev(sc, sp->sa_target, sp->sa_lun); 456 /* 457 * if we can to tagged queueing, inform upper layer 458 * we can have NIOP_NTAG concurent commands 459 */ 460 if (sc->targets[sp->sa_target]->flags & TARF_TAG) 461 link->openings = SIOP_NTAG; 462 splx(s); 463 return 0; 464 } 465 case SCBUSIORESET: 466 s = splbio(); 467 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 468 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 469 scntl1 | SCNTL1_RST); 470 /* minimum 25 us, more time won't hurt */ 471 delay(100); 472 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 473 splx(s); 474 return (0); 475 default: 476 return (ENOTTY); 477 } 478 } 479 480 void 481 siop_sdp(siop_cmd) 482 struct siop_cmd *siop_cmd; 483 { 484 /* save data pointer. Handle async only for now */ 485 int offset, dbc, sstat; 486 struct siop_softc *sc = siop_cmd->siop_sc; 487 scr_table_t *table; /* table to patch */ 488 489 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 490 == 0) 491 return; /* no data pointers to save */ 492 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 493 if (offset >= SIOP_NSG) { 494 printf("%s: bad offset in siop_sdp (%d)\n", 495 sc->sc_dev.dv_xname, offset); 496 return; 497 } 498 table = &siop_cmd->siop_xfer->tables.data[offset]; 499 #ifdef DEBUG_DR 500 printf("sdp: offset %d count=%d addr=0x%x ", offset, 501 table->count, table->addr); 502 #endif 503 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 504 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 505 /* need to account stale data in FIFO */ 506 int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 507 if (sc->features & SF_CHIP_FIFO) { 508 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 509 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 510 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 511 } else { 512 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 513 } 514 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 515 if (sstat & SSTAT0_OLF) 516 dbc++; 517 if (sstat & SSTAT0_ORF) 518 dbc++; 519 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 520 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 521 SIOP_SSTAT2); 522 if (sstat & SSTAT2_OLF1) 523 dbc++; 524 if (sstat & SSTAT2_ORF1) 525 dbc++; 526 } 527 /* clear the FIFO */ 528 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 529 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 530 CTEST3_CLF); 531 } 532 table->addr = 533 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 534 table->count = htole32(dbc); 535 #ifdef DEBUG_DR 536 printf("now count=%d addr=0x%x\n", table->count, table->addr); 537 #endif 538 } 539 540 void 541 siop_clearfifo(sc) 542 struct siop_softc *sc; 543 { 544 int timeout = 0; 545 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 546 547 #ifdef DEBUG_INTR 548 printf("DMA fifo not empty !\n"); 549 #endif 550 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 551 ctest3 | CTEST3_CLF); 552 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 553 CTEST3_CLF) != 0) { 554 delay(1); 555 if (++timeout > 1000) { 556 printf("clear fifo failed\n"); 557 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 558 bus_space_read_1(sc->sc_rt, sc->sc_rh, 559 SIOP_CTEST3) & ~CTEST3_CLF); 560 return; 561 } 562 } 563 } 564 565 int 566 siop_modechange(sc) 567 struct siop_softc *sc; 568 { 569 int retry; 570 int sist0, sist1, stest2, stest4; 571 for (retry = 0; retry < 5; retry++) { 572 /* 573 * datasheet says to wait 100ms and re-read SIST1, 574 * to check that DIFFSENSE is srable. 575 * We may delay() 5 times for 100ms at interrupt time; 576 * hopefully this will not happen often. 577 */ 578 delay(100000); 579 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 580 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 581 if (sist1 & SIEN1_SBMC) 582 continue; /* we got an irq again */ 583 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 584 STEST4_MODE_MASK; 585 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 586 switch(stest4) { 587 case STEST4_MODE_DIF: 588 printf("%s: switching to differential mode\n", 589 sc->sc_dev.dv_xname); 590 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 591 stest2 | STEST2_DIF); 592 break; 593 case STEST4_MODE_SE: 594 printf("%s: switching to single-ended mode\n", 595 sc->sc_dev.dv_xname); 596 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 597 stest2 & ~STEST2_DIF); 598 break; 599 case STEST4_MODE_LVD: 600 printf("%s: switching to LVD mode\n", 601 sc->sc_dev.dv_xname); 602 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 603 stest2 & ~STEST2_DIF); 604 break; 605 default: 606 printf("%s: invalid SCSI mode 0x%x\n", 607 sc->sc_dev.dv_xname, stest4); 608 return 0; 609 } 610 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 611 stest4 >> 2); 612 return 1; 613 } 614 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 615 sc->sc_dev.dv_xname); 616 return 0; 617 } 618 619 void 620 siop_resetbus(sc) 621 struct siop_softc *sc; 622 { 623 int scntl1; 624 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 625 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 626 scntl1 | SCNTL1_RST); 627 /* minimum 25 us, more time won't hurt */ 628 delay(100); 629 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 630 } 631
Indexes created Sun Oct 12 05:10:08 GMT 2025