siop_common.c revision 1.8
1 /* $NetBSD: siop_common.c,v 1.8 2000/10/06 16:39:04 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsi_message.h> 48 #include <dev/scsipi/scsipi_all.h> 49 50 #include <dev/scsipi/scsiconf.h> 51 52 #include <dev/ic/siopreg.h> 53 #include <dev/ic/siopvar.h> 54 #include <dev/ic/siopvar_common.h> 55 56 #undef DEBUG 57 #undef DEBUG_DR 58 59 void 60 siop_common_reset(sc) 61 struct siop_softc *sc; 62 { 63 u_int32_t stest3; 64 65 /* reset the chip */ 66 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 67 delay(1000); 68 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 69 70 /* init registers */ 71 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 72 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 73 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 74 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 76 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 78 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 80 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 82 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 84 (0xb << STIME0_SEL_SHIFT)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 86 sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 88 1 << sc->sc_link.scsipi_scsi.adapter_target); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 90 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 91 92 /* enable clock doubler or quadruler if appropriate */ 93 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 94 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 95 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 96 STEST1_DBLEN); 97 if (sc->features & SF_CHIP_QUAD) { 98 /* wait for PPL to lock */ 99 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 100 SIOP_STEST4) & STEST4_LOCK) == 0) 101 delay(10); 102 } else { 103 /* data sheet says 20us - more won't hurt */ 104 delay(100); 105 } 106 /* halt scsi clock, select doubler/quad, restart clock */ 107 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 108 stest3 | STEST3_HSC); 109 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 110 STEST1_DBLEN | STEST1_DBLSEL); 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 112 } else { 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 114 } 115 if (sc->features & SF_CHIP_FIFO) 116 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 117 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 118 CTEST5_DFS); 119 120 sc->sc_reset(sc); 121 } 122 123 int 124 siop_wdtr_neg(siop_cmd) 125 struct siop_cmd *siop_cmd; 126 { 127 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 128 struct siop_target *siop_target = siop_cmd->siop_target; 129 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 130 131 if (siop_target->status == TARST_WIDE_NEG) { 132 /* we initiated wide negotiation */ 133 switch (siop_cmd->siop_table->msg_in[3]) { 134 case MSG_EXT_WDTR_BUS_8_BIT: 135 printf("%s: target %d using 8bit transfers\n", 136 sc->sc_dev.dv_xname, target); 137 siop_target->flags &= ~SF_BUS_WIDE; 138 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 139 break; 140 case MSG_EXT_WDTR_BUS_16_BIT: 141 if (sc->features & SF_BUS_WIDE) { 142 printf("%s: target %d using 16bit transfers\n", 143 sc->sc_dev.dv_xname, target); 144 siop_target->flags |= TARF_WIDE; 145 sc->targets[target]->id |= (SCNTL3_EWS << 24); 146 break; 147 } 148 /* FALLTHROUH */ 149 default: 150 /* 151 * hum, we got more than what we can handle, shoudn't 152 * happen. Reject, and stay async 153 */ 154 siop_target->flags &= ~TARF_WIDE; 155 siop_target->status = TARST_OK; 156 printf("%s: rejecting invalid wide negotiation from " 157 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 158 siop_cmd->siop_table->msg_in[3]); 159 siop_cmd->siop_table->t_msgout.count= htole32(1); 160 siop_cmd->siop_table->t_msgout.addr = 161 htole32(siop_cmd->dsa); 162 siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT; 163 return SIOP_NEG_MSGOUT; 164 } 165 siop_cmd->siop_table->id = 166 htole32(sc->targets[target]->id); 167 bus_space_write_1(sc->sc_rt, sc->sc_rh, 168 SIOP_SCNTL3, 169 (sc->targets[target]->id >> 24) & 0xff); 170 /* we now need to do sync */ 171 if ((siop_cmd->xs->sc_link->quirks & SDEV_NOSYNC) == 0) { 172 siop_target->status = TARST_SYNC_NEG; 173 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 174 siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN; 175 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR; 176 siop_cmd->siop_table->msg_out[3] = sc->minsync; 177 siop_cmd->siop_table->msg_out[4] = sc->maxoff; 178 siop_cmd->siop_table->t_msgout.count = 179 htole32(MSG_EXT_SDTR_LEN + 2); 180 siop_cmd->siop_table->t_msgout.addr = 181 htole32(siop_cmd->dsa); 182 return SIOP_NEG_MSGOUT; 183 } else { 184 siop_target->status = TARST_OK; 185 return SIOP_NEG_ACK; 186 } 187 } else { 188 /* target initiated wide negotiation */ 189 if (siop_cmd->siop_table->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 190 && (sc->features & SF_BUS_WIDE)) { 191 printf("%s: target %d using 16bit transfers\n", 192 sc->sc_dev.dv_xname, target); 193 siop_target->flags |= TARF_WIDE; 194 sc->targets[target]->id |= SCNTL3_EWS << 24; 195 siop_cmd->siop_table->msg_out[3] = 196 MSG_EXT_WDTR_BUS_16_BIT; 197 } else { 198 printf("%s: target %d using 8bit transfers\n", 199 sc->sc_dev.dv_xname, target); 200 siop_target->flags &= ~SF_BUS_WIDE; 201 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 202 siop_cmd->siop_table->msg_out[3] = 203 MSG_EXT_WDTR_BUS_8_BIT; 204 } 205 siop_cmd->siop_table->id = 206 htole32(sc->targets[target]->id); 207 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 208 (sc->targets[target]->id >> 24) & 0xff); 209 /* 210 * we did reset wide parameters, so fall back to async, 211 * but don't schedule a sync neg, target should initiate it 212 */ 213 siop_target->status = TARST_OK; 214 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 215 siop_cmd->siop_table->msg_out[1] = MSG_EXT_WDTR_LEN; 216 siop_cmd->siop_table->msg_out[2] = MSG_EXT_WDTR; 217 siop_cmd->siop_table->t_msgout.count= 218 htole32(MSG_EXT_WDTR_LEN + 2); 219 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 220 return SIOP_NEG_MSGOUT; 221 } 222 } 223 224 int 225 siop_sdtr_neg(siop_cmd) 226 struct siop_cmd *siop_cmd; 227 { 228 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 229 struct siop_target *siop_target = siop_cmd->siop_target; 230 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 231 int sync, offset, i; 232 int send_msgout = 0; 233 234 sync = siop_cmd->siop_table->msg_in[3]; 235 offset = siop_cmd->siop_table->msg_in[4]; 236 237 if (siop_target->status == TARST_SYNC_NEG) { 238 /* we initiated sync negotiation */ 239 siop_target->status = TARST_OK; 240 #ifdef DEBUG 241 printf("sdtr: sync %d offset %d\n", sync, offset); 242 #endif 243 if (offset > sc->maxoff || sync < sc->minsync || 244 sync > sc->maxsync) 245 goto reject; 246 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 247 i++) { 248 if (sc->clock_period != scf_period[i].clock) 249 continue; 250 if (scf_period[i].period == sync) { 251 /* ok, found it. we now are sync. */ 252 printf("%s: target %d now synchronous at " 253 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 254 target, scf_period[i].rate, offset); 255 sc->targets[target]->id &= 256 ~(SCNTL3_SCF_MASK << 24); 257 sc->targets[target]->id |= scf_period[i].scf 258 << (24 + SCNTL3_SCF_SHIFT); 259 if (sync < 25) /* Ultra */ 260 sc->targets[target]->id |= 261 SCNTL3_ULTRA << 24; 262 else 263 sc->targets[target]->id &= 264 ~(SCNTL3_ULTRA << 24); 265 sc->targets[target]->id &= 266 ~(SXFER_MO_MASK << 8); 267 sc->targets[target]->id |= 268 (offset & SXFER_MO_MASK) << 8; 269 goto end; 270 } 271 } 272 /* 273 * we didn't find it in our table, do async and send reject 274 * msg 275 */ 276 reject: 277 send_msgout = 1; 278 siop_cmd->siop_table->t_msgout.count= htole32(1); 279 siop_cmd->siop_table->msg_out[0] = MSG_MESSAGE_REJECT; 280 printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname, 281 target); 282 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 283 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 284 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 285 } else { /* target initiated sync neg */ 286 #ifdef DEBUG 287 printf("sdtr (target): sync %d offset %d\n", sync, offset); 288 #endif 289 if (offset == 0 || sync > sc->maxsync) { /* async */ 290 goto async; 291 } 292 if (offset > sc->maxoff) 293 offset = sc->maxoff; 294 if (sync < sc->minsync) 295 sync = sc->minsync; 296 /* look for sync period */ 297 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 298 i++) { 299 if (sc->clock_period != scf_period[i].clock) 300 continue; 301 if (scf_period[i].period == sync) { 302 /* ok, found it. we now are sync. */ 303 printf("%s: target %d now synchronous at " 304 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 305 target, scf_period[i].rate, offset); 306 sc->targets[target]->id &= 307 ~(SCNTL3_SCF_MASK << 24); 308 sc->targets[target]->id |= scf_period[i].scf 309 << (24 + SCNTL3_SCF_SHIFT); 310 if (sync < 25) /* Ultra */ 311 sc->targets[target]->id |= 312 SCNTL3_ULTRA << 24; 313 else 314 sc->targets[target]->id &= 315 ~(SCNTL3_ULTRA << 24); 316 sc->targets[target]->id &= 317 ~(SXFER_MO_MASK << 8); 318 sc->targets[target]->id |= 319 (offset & SXFER_MO_MASK) << 8; 320 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 321 siop_cmd->siop_table->msg_out[1] = 322 MSG_EXT_SDTR_LEN; 323 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR; 324 siop_cmd->siop_table->msg_out[3] = sync; 325 siop_cmd->siop_table->msg_out[4] = offset; 326 siop_cmd->siop_table->t_msgout.count= 327 htole32(MSG_EXT_SDTR_LEN + 2); 328 send_msgout = 1; 329 goto end; 330 } 331 } 332 async: 333 printf("%s: target %d asynchronous\n", 334 sc->sc_dev.dv_xname, target); 335 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 336 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 337 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 338 siop_cmd->siop_table->msg_out[0] = MSG_EXTENDED; 339 siop_cmd->siop_table->msg_out[1] = MSG_EXT_SDTR_LEN; 340 siop_cmd->siop_table->msg_out[2] = MSG_EXT_SDTR; 341 siop_cmd->siop_table->msg_out[3] = 0; 342 siop_cmd->siop_table->msg_out[4] = 0; 343 siop_cmd->siop_table->t_msgout.count= 344 htole32(MSG_EXT_SDTR_LEN + 2); 345 send_msgout = 1; 346 } 347 end: 348 #ifdef DEBUG 349 printf("id now 0x%x\n", sc->targets[target]->id); 350 #endif 351 siop_cmd->siop_table->id = htole32(sc->targets[target]->id); 352 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 353 (sc->targets[target]->id >> 24) & 0xff); 354 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 355 (sc->targets[target]->id >> 8) & 0xff); 356 if (send_msgout) { 357 siop_cmd->siop_table->t_msgout.addr = htole32(siop_cmd->dsa); 358 return SIOP_NEG_MSGOUT; 359 } else { 360 return SIOP_NEG_ACK; 361 } 362 } 363 364 void 365 siop_minphys(bp) 366 struct buf *bp; 367 { 368 minphys(bp); 369 } 370 371 int 372 siop_ioctl(link, cmd, arg, flag, p) 373 struct scsipi_link *link; 374 u_long cmd; 375 caddr_t arg; 376 int flag; 377 struct proc *p; 378 { 379 struct siop_softc *sc = link->adapter_softc; 380 u_int8_t scntl1; 381 int s; 382 383 switch (cmd) { 384 case SCBUSIORESET: 385 s = splbio(); 386 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 387 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 388 scntl1 | SCNTL1_RST); 389 /* minimum 25 us, more time won't hurt */ 390 delay(100); 391 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 392 splx(s); 393 return (0); 394 default: 395 return (ENOTTY); 396 } 397 } 398 399 void 400 siop_sdp(siop_cmd) 401 struct siop_cmd *siop_cmd; 402 { 403 /* save data pointer. Handle async only for now */ 404 int offset, dbc, sstat; 405 struct siop_softc *sc = siop_cmd->siop_target->siop_sc; 406 scr_table_t *table; /* table to patch */ 407 408 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 409 == 0) 410 return; /* no data pointers to save */ 411 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 412 if (offset >= SIOP_NSG) { 413 printf("%s: bad offset in siop_sdp (%d)\n", 414 sc->sc_dev.dv_xname, offset); 415 return; 416 } 417 table = &siop_cmd->siop_table->data[offset]; 418 #ifdef DEBUG_DR 419 printf("sdp: offset %d count=%d addr=0x%x ", offset, 420 table->count, table->addr); 421 #endif 422 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 423 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 424 /* need to account stale data in FIFO */ 425 int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 426 if (sc->features & SF_CHIP_FIFO) { 427 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 428 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 429 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 430 } else { 431 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 432 } 433 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 434 if (sstat & SSTAT0_OLF) 435 dbc++; 436 if (sstat & SSTAT0_ORF) 437 dbc++; 438 if (siop_cmd->siop_target->flags & TARF_WIDE) { 439 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 440 SIOP_SSTAT2); 441 if (sstat & SSTAT2_OLF1) 442 dbc++; 443 if (sstat & SSTAT2_ORF1) 444 dbc++; 445 } 446 /* clear the FIFO */ 447 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 448 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 449 CTEST3_CLF); 450 } 451 table->addr = 452 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 453 table->count = htole32(dbc); 454 #ifdef DEBUG_DR 455 printf("now count=%d addr=0x%x\n", table->count, table->addr); 456 #endif 457 } 458 459 void 460 siop_clearfifo(sc) 461 struct siop_softc *sc; 462 { 463 int timeout = 0; 464 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 465 466 #ifdef DEBUG_INTR 467 printf("DMA fifo not empty !\n"); 468 #endif 469 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 470 ctest3 | CTEST3_CLF); 471 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 472 CTEST3_CLF) != 0) { 473 delay(1); 474 if (++timeout > 1000) { 475 printf("clear fifo failed\n"); 476 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 477 bus_space_read_1(sc->sc_rt, sc->sc_rh, 478 SIOP_CTEST3) & ~CTEST3_CLF); 479 return; 480 } 481 } 482 } 483 484 int 485 siop_modechange(sc) 486 struct siop_softc *sc; 487 { 488 int retry; 489 int sist0, sist1, stest2, stest4; 490 for (retry = 0; retry < 5; retry++) { 491 /* 492 * datasheet says to wait 100ms and re-read SIST1, 493 * to check that DIFFSENSE is srable. 494 * We may delay() 5 times for 100ms at interrupt time; 495 * hopefully this will not happen often. 496 */ 497 delay(100000); 498 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 499 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 500 if (sist1 & SIEN1_SBMC) 501 continue; /* we got an irq again */ 502 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 503 STEST4_MODE_MASK; 504 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 505 switch(stest4) { 506 case STEST4_MODE_DIF: 507 printf("%s: switching to differential mode\n", 508 sc->sc_dev.dv_xname); 509 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 510 stest2 | STEST2_DIF); 511 break; 512 case STEST4_MODE_SE: 513 printf("%s: switching to single-ended mode\n", 514 sc->sc_dev.dv_xname); 515 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 516 stest2 & ~STEST2_DIF); 517 break; 518 case STEST4_MODE_LVD: 519 printf("%s: switching to LVD mode\n", 520 sc->sc_dev.dv_xname); 521 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 522 stest2 & ~STEST2_DIF); 523 break; 524 default: 525 printf("%s: invalid SCSI mode 0x%x\n", 526 sc->sc_dev.dv_xname, stest4); 527 return 0; 528 } 529 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 530 stest4 >> 2); 531 return 1; 532 } 533 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 534 sc->sc_dev.dv_xname); 535 return 0; 536 } 537 538 void 539 siop_resetbus(sc) 540 struct siop_softc *sc; 541 { 542 int scntl1; 543 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 544 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 545 scntl1 | SCNTL1_RST); 546 /* minimum 25 us, more time won't hurt */ 547 delay(100); 548 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 549 } 550
Indexes created Tue Sep 23 21:09:50 GMT 2025