siop_common.c revision 1.9
1 /* $NetBSD: siop_common.c,v 1.9 2000/10/18 17:06:52 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c7/8xx PCI-SCSI I/O Processors driver */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 #include <sys/scsiio.h> 42 43 #include <machine/endian.h> 44 #include <machine/bus.h> 45 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsi_message.h> 48 #include <dev/scsipi/scsipi_all.h> 49 50 #include <dev/scsipi/scsiconf.h> 51 52 #include <dev/ic/siopreg.h> 53 #include <dev/ic/siopvar.h> 54 #include <dev/ic/siopvar_common.h> 55 56 #undef DEBUG 57 #undef DEBUG_DR 58 59 void 60 siop_common_reset(sc) 61 struct siop_softc *sc; 62 { 63 u_int32_t stest3; 64 65 /* reset the chip */ 66 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, ISTAT_SRST); 67 delay(1000); 68 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_ISTAT, 0); 69 70 /* init registers */ 71 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL0, 72 SCNTL0_ARB_MASK | SCNTL0_EPC | SCNTL0_AAP); 73 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 0); 74 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, sc->clock_div); 75 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 0); 76 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DIEN, 0xff); 77 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN0, 78 0xff & ~(SIEN0_CMP | SIEN0_SEL | SIEN0_RSL)); 79 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SIEN1, 80 0xff & ~(SIEN1_HTH | SIEN1_GEN)); 81 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 0); 82 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, STEST3_TE); 83 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STIME0, 84 (0xb << STIME0_SEL_SHIFT)); 85 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCID, 86 sc->sc_link.scsipi_scsi.adapter_target | SCID_RRE); 87 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_RESPID0, 88 1 << sc->sc_link.scsipi_scsi.adapter_target); 89 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 90 (sc->features & SF_CHIP_PF) ? DCNTL_COM | DCNTL_PFEN : DCNTL_COM); 91 92 /* enable clock doubler or quadruler if appropriate */ 93 if (sc->features & (SF_CHIP_DBLR | SF_CHIP_QUAD)) { 94 stest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3); 95 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 96 STEST1_DBLEN); 97 if (sc->features & SF_CHIP_QUAD) { 98 /* wait for PPL to lock */ 99 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, 100 SIOP_STEST4) & STEST4_LOCK) == 0) 101 delay(10); 102 } else { 103 /* data sheet says 20us - more won't hurt */ 104 delay(100); 105 } 106 /* halt scsi clock, select doubler/quad, restart clock */ 107 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, 108 stest3 | STEST3_HSC); 109 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 110 STEST1_DBLEN | STEST1_DBLSEL); 111 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST3, stest3); 112 } else { 113 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST1, 0); 114 } 115 if (sc->features & SF_CHIP_FIFO) 116 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, 117 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5) | 118 CTEST5_DFS); 119 120 sc->sc_reset(sc); 121 } 122 123 int 124 siop_wdtr_neg(siop_cmd) 125 struct siop_cmd *siop_cmd; 126 { 127 struct siop_softc *sc = siop_cmd->siop_sc; 128 struct siop_target *siop_target = siop_cmd->siop_target; 129 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 130 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 131 132 if (siop_target->status == TARST_WIDE_NEG) { 133 /* we initiated wide negotiation */ 134 switch (tables->msg_in[3]) { 135 case MSG_EXT_WDTR_BUS_8_BIT: 136 printf("%s: target %d using 8bit transfers\n", 137 sc->sc_dev.dv_xname, target); 138 siop_target->flags &= ~TARF_ISWIDE; 139 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 140 break; 141 case MSG_EXT_WDTR_BUS_16_BIT: 142 if (siop_target->flags & TARF_WIDE) { 143 printf("%s: target %d using 16bit transfers\n", 144 sc->sc_dev.dv_xname, target); 145 siop_target->flags |= TARF_ISWIDE; 146 sc->targets[target]->id |= (SCNTL3_EWS << 24); 147 break; 148 } 149 /* FALLTHROUH */ 150 default: 151 /* 152 * hum, we got more than what we can handle, shoudn't 153 * happen. Reject, and stay async 154 */ 155 siop_target->flags &= ~TARF_ISWIDE; 156 siop_target->status = TARST_OK; 157 printf("%s: rejecting invalid wide negotiation from " 158 "target %d (%d)\n", sc->sc_dev.dv_xname, target, 159 tables->msg_in[3]); 160 tables->t_msgout.count= htole32(1); 161 tables->t_msgout.addr = htole32(siop_cmd->dsa); 162 tables->msg_out[0] = MSG_MESSAGE_REJECT; 163 return SIOP_NEG_MSGOUT; 164 } 165 tables->id = htole32(sc->targets[target]->id); 166 bus_space_write_1(sc->sc_rt, sc->sc_rh, 167 SIOP_SCNTL3, 168 (sc->targets[target]->id >> 24) & 0xff); 169 /* we now need to do sync */ 170 if (siop_target->flags & TARF_SYNC) { 171 siop_target->status = TARST_SYNC_NEG; 172 tables->msg_out[0] = MSG_EXTENDED; 173 tables->msg_out[1] = MSG_EXT_SDTR_LEN; 174 tables->msg_out[2] = MSG_EXT_SDTR; 175 tables->msg_out[3] = sc->minsync; 176 tables->msg_out[4] = sc->maxoff; 177 tables->t_msgout.count = htole32(MSG_EXT_SDTR_LEN + 2); 178 tables->t_msgout.addr = htole32(siop_cmd->dsa); 179 return SIOP_NEG_MSGOUT; 180 } else { 181 siop_target->status = TARST_OK; 182 return SIOP_NEG_ACK; 183 } 184 } else { 185 /* target initiated wide negotiation */ 186 if (tables->msg_in[3] >= MSG_EXT_WDTR_BUS_16_BIT 187 && (siop_target->flags & TARF_WIDE)) { 188 printf("%s: target %d using 16bit transfers\n", 189 sc->sc_dev.dv_xname, target); 190 siop_target->flags |= TARF_ISWIDE; 191 sc->targets[target]->id |= SCNTL3_EWS << 24; 192 tables->msg_out[3] = MSG_EXT_WDTR_BUS_16_BIT; 193 } else { 194 printf("%s: target %d using 8bit transfers\n", 195 sc->sc_dev.dv_xname, target); 196 siop_target->flags &= ~TARF_ISWIDE; 197 sc->targets[target]->id &= ~(SCNTL3_EWS << 24); 198 tables->msg_out[3] = MSG_EXT_WDTR_BUS_8_BIT; 199 } 200 tables->id = htole32(sc->targets[target]->id); 201 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 202 (sc->targets[target]->id >> 24) & 0xff); 203 /* 204 * we did reset wide parameters, so fall back to async, 205 * but don't schedule a sync neg, target should initiate it 206 */ 207 siop_target->status = TARST_OK; 208 tables->msg_out[0] = MSG_EXTENDED; 209 tables->msg_out[1] = MSG_EXT_WDTR_LEN; 210 tables->msg_out[2] = MSG_EXT_WDTR; 211 tables->t_msgout.count= 212 htole32(MSG_EXT_WDTR_LEN + 2); 213 tables->t_msgout.addr = htole32(siop_cmd->dsa); 214 return SIOP_NEG_MSGOUT; 215 } 216 } 217 218 int 219 siop_sdtr_neg(siop_cmd) 220 struct siop_cmd *siop_cmd; 221 { 222 struct siop_softc *sc = siop_cmd->siop_sc; 223 struct siop_target *siop_target = siop_cmd->siop_target; 224 int target = siop_cmd->xs->sc_link->scsipi_scsi.target; 225 int sync, offset, i; 226 int send_msgout = 0; 227 struct siop_xfer_common *tables = &siop_cmd->siop_xfer->tables; 228 229 sync = tables->msg_in[3]; 230 offset = tables->msg_in[4]; 231 232 if (siop_target->status == TARST_SYNC_NEG) { 233 /* we initiated sync negotiation */ 234 siop_target->status = TARST_OK; 235 #ifdef DEBUG 236 printf("sdtr: sync %d offset %d\n", sync, offset); 237 #endif 238 if (offset > sc->maxoff || sync < sc->minsync || 239 sync > sc->maxsync) 240 goto reject; 241 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 242 i++) { 243 if (sc->clock_period != scf_period[i].clock) 244 continue; 245 if (scf_period[i].period == sync) { 246 /* ok, found it. we now are sync. */ 247 printf("%s: target %d now synchronous at " 248 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 249 target, scf_period[i].rate, offset); 250 sc->targets[target]->id &= 251 ~(SCNTL3_SCF_MASK << 24); 252 sc->targets[target]->id |= scf_period[i].scf 253 << (24 + SCNTL3_SCF_SHIFT); 254 if (sync < 25) /* Ultra */ 255 sc->targets[target]->id |= 256 SCNTL3_ULTRA << 24; 257 else 258 sc->targets[target]->id &= 259 ~(SCNTL3_ULTRA << 24); 260 sc->targets[target]->id &= 261 ~(SXFER_MO_MASK << 8); 262 sc->targets[target]->id |= 263 (offset & SXFER_MO_MASK) << 8; 264 goto end; 265 } 266 } 267 /* 268 * we didn't find it in our table, do async and send reject 269 * msg 270 */ 271 reject: 272 send_msgout = 1; 273 tables->t_msgout.count= htole32(1); 274 tables->msg_out[0] = MSG_MESSAGE_REJECT; 275 printf("%s: target %d asynchronous\n", sc->sc_dev.dv_xname, 276 target); 277 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 278 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 279 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 280 } else { /* target initiated sync neg */ 281 #ifdef DEBUG 282 printf("sdtr (target): sync %d offset %d\n", sync, offset); 283 #endif 284 if (offset == 0 || sync > sc->maxsync) { /* async */ 285 goto async; 286 } 287 if (offset > sc->maxoff) 288 offset = sc->maxoff; 289 if (sync < sc->minsync) 290 sync = sc->minsync; 291 /* look for sync period */ 292 for (i = 0; i < sizeof(scf_period) / sizeof(scf_period[0]); 293 i++) { 294 if (sc->clock_period != scf_period[i].clock) 295 continue; 296 if (scf_period[i].period == sync) { 297 /* ok, found it. we now are sync. */ 298 printf("%s: target %d now synchronous at " 299 "%sMhz, offset %d\n", sc->sc_dev.dv_xname, 300 target, scf_period[i].rate, offset); 301 sc->targets[target]->id &= 302 ~(SCNTL3_SCF_MASK << 24); 303 sc->targets[target]->id |= scf_period[i].scf 304 << (24 + SCNTL3_SCF_SHIFT); 305 if (sync < 25) /* Ultra */ 306 sc->targets[target]->id |= 307 SCNTL3_ULTRA << 24; 308 else 309 sc->targets[target]->id &= 310 ~(SCNTL3_ULTRA << 24); 311 sc->targets[target]->id &= 312 ~(SXFER_MO_MASK << 8); 313 sc->targets[target]->id |= 314 (offset & SXFER_MO_MASK) << 8; 315 tables->msg_out[0] = MSG_EXTENDED; 316 tables->msg_out[1] = MSG_EXT_SDTR_LEN; 317 tables->msg_out[2] = MSG_EXT_SDTR; 318 tables->msg_out[3] = sync; 319 tables->msg_out[4] = offset; 320 tables->t_msgout.count= 321 htole32(MSG_EXT_SDTR_LEN + 2); 322 send_msgout = 1; 323 goto end; 324 } 325 } 326 async: 327 printf("%s: target %d asynchronous\n", 328 sc->sc_dev.dv_xname, target); 329 sc->targets[target]->id &= ~(SCNTL3_SCF_MASK << 24); 330 sc->targets[target]->id &= ~(SCNTL3_ULTRA << 24); 331 sc->targets[target]->id &= ~(SXFER_MO_MASK << 8); 332 tables->msg_out[0] = MSG_EXTENDED; 333 tables->msg_out[1] = MSG_EXT_SDTR_LEN; 334 tables->msg_out[2] = MSG_EXT_SDTR; 335 tables->msg_out[3] = 0; 336 tables->msg_out[4] = 0; 337 tables->t_msgout.count= 338 htole32(MSG_EXT_SDTR_LEN + 2); 339 send_msgout = 1; 340 } 341 end: 342 #ifdef DEBUG 343 printf("id now 0x%x\n", sc->targets[target]->id); 344 #endif 345 tables->id = htole32(sc->targets[target]->id); 346 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL3, 347 (sc->targets[target]->id >> 24) & 0xff); 348 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SXFER, 349 (sc->targets[target]->id >> 8) & 0xff); 350 if (send_msgout) { 351 tables->t_msgout.addr = htole32(siop_cmd->dsa); 352 return SIOP_NEG_MSGOUT; 353 } else { 354 return SIOP_NEG_ACK; 355 } 356 } 357 358 void 359 siop_minphys(bp) 360 struct buf *bp; 361 { 362 minphys(bp); 363 } 364 365 int 366 siop_ioctl(link, cmd, arg, flag, p) 367 struct scsipi_link *link; 368 u_long cmd; 369 caddr_t arg; 370 int flag; 371 struct proc *p; 372 { 373 struct siop_softc *sc = link->adapter_softc; 374 u_int8_t scntl1; 375 int s; 376 377 switch (cmd) { 378 case SCBUSACCEL: 379 { 380 struct scbusaccel_args *sp = (struct scbusaccel_args *)arg; 381 s = splbio(); 382 if (sp->sa_lun == 0) { 383 #if 0 384 if (sp->sa_flags & SC_ACCEL_TAGS) { 385 sc->targets[sp->sa_target]->flags |= TARF_TAG; 386 printf("%s: target %d using tagged queuing\n", 387 sc->sc_dev.dv_xname, sp->sa_target); 388 } 389 #endif 390 if ((sp->sa_flags & SC_ACCEL_WIDE) && 391 (sc->features & SF_BUS_WIDE)) 392 sc->targets[sp->sa_target]->flags |= TARF_WIDE; 393 if (sp->sa_flags & SC_ACCEL_SYNC) 394 sc->targets[sp->sa_target]->flags |= TARF_SYNC; 395 if (sp->sa_flags & (SC_ACCEL_SYNC | SC_ACCEL_WIDE) && 396 sc->targets[sp->sa_target]->status > TARST_ASYNC) 397 sc->targets[sp->sa_target]->status = 398 TARST_ASYNC; 399 } 400 splx(s); 401 return 0; 402 } 403 case SCBUSIORESET: 404 s = splbio(); 405 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 406 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 407 scntl1 | SCNTL1_RST); 408 /* minimum 25 us, more time won't hurt */ 409 delay(100); 410 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 411 splx(s); 412 return (0); 413 default: 414 return (ENOTTY); 415 } 416 } 417 418 void 419 siop_sdp(siop_cmd) 420 struct siop_cmd *siop_cmd; 421 { 422 /* save data pointer. Handle async only for now */ 423 int offset, dbc, sstat; 424 struct siop_softc *sc = siop_cmd->siop_sc; 425 scr_table_t *table; /* table to patch */ 426 427 if ((siop_cmd->xs->xs_control & (XS_CTL_DATA_OUT | XS_CTL_DATA_IN)) 428 == 0) 429 return; /* no data pointers to save */ 430 offset = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCRATCHA + 1); 431 if (offset >= SIOP_NSG) { 432 printf("%s: bad offset in siop_sdp (%d)\n", 433 sc->sc_dev.dv_xname, offset); 434 return; 435 } 436 table = &siop_cmd->siop_xfer->tables.data[offset]; 437 #ifdef DEBUG_DR 438 printf("sdp: offset %d count=%d addr=0x%x ", offset, 439 table->count, table->addr); 440 #endif 441 dbc = bus_space_read_4(sc->sc_rt, sc->sc_rh, SIOP_DBC) & 0x00ffffff; 442 if (siop_cmd->xs->xs_control & XS_CTL_DATA_OUT) { 443 /* need to account stale data in FIFO */ 444 int dfifo = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DFIFO); 445 if (sc->features & SF_CHIP_FIFO) { 446 dfifo |= (bus_space_read_1(sc->sc_rt, sc->sc_rh, 447 SIOP_CTEST5) & CTEST5_BOMASK) << 8; 448 dbc += (dfifo - (dbc & 0x3ff)) & 0x3ff; 449 } else { 450 dbc += (dfifo - (dbc & 0x7f)) & 0x7f; 451 } 452 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SSTAT0); 453 if (sstat & SSTAT0_OLF) 454 dbc++; 455 if (sstat & SSTAT0_ORF) 456 dbc++; 457 if (siop_cmd->siop_target->flags & TARF_ISWIDE) { 458 sstat = bus_space_read_1(sc->sc_rt, sc->sc_rh, 459 SIOP_SSTAT2); 460 if (sstat & SSTAT2_OLF1) 461 dbc++; 462 if (sstat & SSTAT2_ORF1) 463 dbc++; 464 } 465 /* clear the FIFO */ 466 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 467 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 468 CTEST3_CLF); 469 } 470 table->addr = 471 htole32(le32toh(table->addr) + le32toh(table->count) - dbc); 472 table->count = htole32(dbc); 473 #ifdef DEBUG_DR 474 printf("now count=%d addr=0x%x\n", table->count, table->addr); 475 #endif 476 } 477 478 void 479 siop_clearfifo(sc) 480 struct siop_softc *sc; 481 { 482 int timeout = 0; 483 int ctest3 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3); 484 485 #ifdef DEBUG_INTR 486 printf("DMA fifo not empty !\n"); 487 #endif 488 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 489 ctest3 | CTEST3_CLF); 490 while ((bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) & 491 CTEST3_CLF) != 0) { 492 delay(1); 493 if (++timeout > 1000) { 494 printf("clear fifo failed\n"); 495 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 496 bus_space_read_1(sc->sc_rt, sc->sc_rh, 497 SIOP_CTEST3) & ~CTEST3_CLF); 498 return; 499 } 500 } 501 } 502 503 int 504 siop_modechange(sc) 505 struct siop_softc *sc; 506 { 507 int retry; 508 int sist0, sist1, stest2, stest4; 509 for (retry = 0; retry < 5; retry++) { 510 /* 511 * datasheet says to wait 100ms and re-read SIST1, 512 * to check that DIFFSENSE is srable. 513 * We may delay() 5 times for 100ms at interrupt time; 514 * hopefully this will not happen often. 515 */ 516 delay(100000); 517 sist0 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST0); 518 sist1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SIST1); 519 if (sist1 & SIEN1_SBMC) 520 continue; /* we got an irq again */ 521 stest4 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST4) & 522 STEST4_MODE_MASK; 523 stest2 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2); 524 switch(stest4) { 525 case STEST4_MODE_DIF: 526 printf("%s: switching to differential mode\n", 527 sc->sc_dev.dv_xname); 528 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 529 stest2 | STEST2_DIF); 530 break; 531 case STEST4_MODE_SE: 532 printf("%s: switching to single-ended mode\n", 533 sc->sc_dev.dv_xname); 534 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 535 stest2 & ~STEST2_DIF); 536 break; 537 case STEST4_MODE_LVD: 538 printf("%s: switching to LVD mode\n", 539 sc->sc_dev.dv_xname); 540 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST2, 541 stest2 & ~STEST2_DIF); 542 break; 543 default: 544 printf("%s: invalid SCSI mode 0x%x\n", 545 sc->sc_dev.dv_xname, stest4); 546 return 0; 547 } 548 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_STEST0, 549 stest4 >> 2); 550 return 1; 551 } 552 printf("%s: timeout waiting for DIFFSENSE to stabilise\n", 553 sc->sc_dev.dv_xname); 554 return 0; 555 } 556 557 void 558 siop_resetbus(sc) 559 struct siop_softc *sc; 560 { 561 int scntl1; 562 scntl1 = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1); 563 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, 564 scntl1 | SCNTL1_RST); 565 /* minimum 25 us, more time won't hurt */ 566 delay(100); 567 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_SCNTL1, scntl1); 568 } 569
Indexes created Fri Sep 26 20:09:58 GMT 2025