siopreg.h revision 1.13
1 /* $NetBSD: siopreg.h,v 1.13 2002/08/29 16:43:23 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Devices definitions for Symbios/NCR M53c8xx PCI-SCSI I/O Processors 35 * Docs available from http://www.symbios.com/ 36 */ 37 38 #define SIOP_SCNTL0 0x00 /* SCSI control 0, R/W */ 39 #define SCNTL0_ARB_MASK 0xc0 40 #define SCNTL0_SARB 0x00 41 #define SCNTL0_FARB 0xc0 42 #define SCNTL0_START 0x20 43 #define SCNTL0_WATM 0x10 44 #define SCNTL0_EPC 0x08 45 #define SCNTL0_AAP 0x02 46 #define SCNTL0_TRG 0x01 47 48 #define SIOP_SCNTL1 0x01 /* SCSI control 1, R/W */ 49 #define SCNTL1_EXC 0x80 50 #define SCNTL1_ADB 0x40 51 #define SCNTL1_DHP 0x20 52 #define SCNTL1_CON 0x10 53 #define SCNTL1_RST 0x08 54 #define SCNTL1_AESP 0x04 55 #define SCNTL1_IARB 0x02 56 #define SCNTL1_SST 0x01 57 58 #define SIOP_SCNTL2 0x02 /* SCSI control 2, R/W */ 59 #define SCNTL2_SDU 0x80 60 #define SCNTL2_CHM 0x40 /* 875 only */ 61 #define SCNTL2_SLPMD 0x20 /* 875 only */ 62 #define SCNTL2_SLPHBEN 0x10 /* 875 only */ 63 #define SCNTL2_WSS 0x08 /* 875 only */ 64 #define SCNTL2_VUE0 0x04 /* 875 only */ 65 #define SCNTL2_VUE1 0x02 /* 875 only */ 66 #define SCNTL2_WSR 0x01 /* 875 only */ 67 68 #define SIOP_SCNTL3 0x03 /* SCSI control 3, R/W */ 69 #define SCNTL3_ULTRA 0x80 /* 875 only */ 70 #define SCNTL3_SCF_SHIFT 4 71 #define SCNTL3_SCF_MASK 0x70 72 #define SCNTL3_EWS 0x08 /* 875 only */ 73 #define SCNTL3_CCF_SHIFT 0 74 #define SCNTL3_CCF_MASK 0x07 75 76 /* periods for various SCF values, assume transfer period of 4 */ 77 struct scf_period { 78 int clock; /* clock period (ns * 10) */ 79 int period; /* scsi period, as set in the SDTR message */ 80 int scf; /* scf value to use */ 81 }; 82 83 static const struct scf_period scf_period[] __attribute__((__unused__)) = { 84 {250, 25, 1}, /* 10.0 Mhz */ 85 {250, 37, 2}, /* 6.67 Mhz */ 86 {250, 50, 3}, /* 5.00 Mhz */ 87 {250, 75, 4}, /* 3.33 Mhz */ 88 {125, 12, 1}, /* 20.0 Mhz */ 89 {125, 18, 2}, /* 13.3 Mhz */ 90 {125, 25, 3}, /* 10.0 Mhz */ 91 {125, 37, 4}, /* 6.67 Mhz */ 92 {125, 50, 5}, /* 5.0 Mhz */ 93 { 62, 10, 1}, /* 40.0 Mhz */ 94 { 62, 12, 3}, /* 20.0 Mhz */ 95 { 62, 18, 4}, /* 13.3 Mhz */ 96 { 62, 25, 5}, /* 10.0 Mhz */ 97 }; 98 99 static const struct scf_period dt_scf_period[] __attribute__((__unused__)) = { 100 { 62, 9, 1}, /* 80.0 Mhz */ 101 { 62, 10, 3}, /* 40.0 Mhz */ 102 { 62, 12, 5}, /* 20.0 Mhz */ 103 { 62, 18, 6}, /* 13.3 Mhz */ 104 { 62, 25, 7}, /* 10.0 Mhz */ 105 }; 106 107 #define SIOP_SCID 0x04 /* SCSI chip ID R/W */ 108 #define SCID_RRE 0x40 109 #define SCID_SRE 0x20 110 #define SCID_ENCID_SHIFT 0 111 #define SCID_ENCID_MASK 0x07 112 113 #define SIOP_SXFER 0x05 /* SCSI transfer, R/W */ 114 #define SXFER_TP_SHIFT 5 115 #define SXFER_TP_MASK 0xe0 116 #define SXFER_MO_SHIFT 0 117 #define SXFER_MO_MASK 0x3f 118 119 #define SIOP_SDID 0x06 /* SCSI destiation ID, R/W */ 120 #define SDID_ENCID_SHIFT 0 121 #define SDID_ENCID_MASK 0x07 122 123 #define SIOP_GPREG 0x07 /* General purpose, R/W */ 124 #define GPREG_GPIO4 0x10 /* 875 only */ 125 #define GPREG_GPIO3 0x08 /* 875 only */ 126 #define GPREG_GPIO2 0x04 /* 875 only */ 127 #define GPREG_GPIO1 0x02 128 #define GPREG_GPIO0 0x01 129 130 #define SIOP_SFBR 0x08 /* SCSI first byte received, R/W */ 131 132 #define SIOP_SOCL 0x09 /* SCSI output control latch, RW */ 133 134 #define SIOP_SSID 0x0A /* SCSI selector ID, RO */ 135 #define SSID_VAL 0x80 136 #define SSID_ENCID_SHIFT 0 137 #define SSID_ENCID_MASK 0x0f 138 139 #define SIOP_SBCL 0x0B /* SCSI control line, RO */ 140 141 #define SIOP_DSTAT 0x0C /* DMA status, RO */ 142 #define DSTAT_DFE 0x80 143 #define DSTAT_MDPE 0x40 144 #define DSTAT_BF 0x20 145 #define DSTAT_ABRT 0x10 146 #define DSTAT_SSI 0x08 147 #define DSTAT_SIR 0x04 148 #define DSTAT_IID 0x01 149 150 #define SIOP_SSTAT0 0x0D /* STSI status 0, RO */ 151 #define SSTAT0_ILF 0x80 152 #define SSTAT0_ORF 0x40 153 #define SSTAT0_OLF 0x20 154 #define SSTAT0_AIP 0x10 155 #define SSTAT0_LOA 0x08 156 #define SSTAT0_WOA 0x04 157 #define SSTAT0_RST 0x02 158 #define SSTAT0_SDP 0x01 159 160 #define SIOP_SSTAT1 0x0E /* STSI status 1, RO */ 161 #define SSTAT1_FFO_SHIFT 4 162 #define SSTAT1_FFO_MASK 0x80 163 #define SSTAT1_SDPL 0x08 164 #define SSTAT1_MSG 0x04 165 #define SSTAT1_CD 0x02 166 #define SSTAT1_IO 0x01 167 #define SSTAT1_PHASE_MASK (SSTAT1_IO | SSTAT1_CD | SSTAT1_MSG) 168 #define SSTAT1_PHASE_DATAOUT 0 169 #define SSTAT1_PHASE_DATAIN SSTAT1_IO 170 #define SSTAT1_PHASE_CMD SSTAT1_CD 171 #define SSTAT1_PHASE_STATUS (SSTAT1_CD | SSTAT1_IO) 172 #define SSTAT1_PHASE_MSGOUT (SSTAT1_MSG | SSTAT1_CD) 173 #define SSTAT1_PHASE_MSGIN (SSTAT1_MSG | SSTAT1_CD | SSTAT1_IO) 174 175 #define SIOP_SSTAT2 0x0F /* STSI status 2, RO */ 176 #define SSTAT2_ILF1 0x80 /* 875 only */ 177 #define SSTAT2_ORF1 0x40 /* 875 only */ 178 #define SSTAT2_OLF1 0x20 /* 875 only */ 179 #define SSTAT2_FF4 0x10 /* 875 only */ 180 #define SSTAT2_SPL1 0x08 /* 875 only */ 181 #define SSTAT2_DF 0x04 /* 875 only */ 182 #define SSTAT2_LDSC 0x02 183 #define SSTAT2_SDP1 0x01 /* 875 only */ 184 185 #define SIOP_DSA 0x10 /* data struct addr, R/W */ 186 187 #define SIOP_ISTAT 0x14 /* IRQ status, R/W */ 188 #define ISTAT_ABRT 0x80 189 #define ISTAT_SRST 0x40 190 #define ISTAT_SIGP 0x20 191 #define ISTAT_SEM 0x10 192 #define ISTAT_CON 0x08 193 #define ISTAT_INTF 0x04 194 #define ISTAT_SIP 0x02 195 #define ISTAT_DIP 0x01 196 197 #define SIOP_CTEST0 0x18 /* Chip test 0, R/W */ 198 199 #define SIOP_CTEST1 0x19 /* Chip test 1, R/W */ 200 201 #define SIOP_CTEST2 0x1A /* Chip test 2, R/W */ 202 #define CTEST2_SRTCH 0x04 /* 875 only */ 203 204 #define SIOP_CTEST3 0x1B /* Chip test 3, R/W */ 205 #define CTEST3_FLF 0x08 206 #define CTEST3_CLF 0x04 207 #define CTEST3_FM 0x02 208 #define CTEST3_WRIE 0x01 209 210 #define SIOP_TEMP 0x1C /* Temp register (used by CALL/RET), R/W */ 211 212 #define SIOP_DFIFO 0x20 /* DMA FIFO */ 213 214 #define SIOP_CTEST4 0x21 /* Chip test 4, R/W */ 215 #define CTEST4_BDIS 0x80 216 #define CTEST_ZMOD 0x40 217 #define CTEST_ZSD 0x20 218 #define CTEST_SRTM 0x10 219 #define CTEST_MPEE 0x08 220 221 #define SIOP_CTEST5 0x22 /* Chip test 5, R/W */ 222 #define CTEST5_ADCK 0x80 223 #define CTEST5_BBCK 0x40 224 #define CTEST5_DFS 0x20 225 #define CTEST5_MASR 0x10 226 #define CTEST5_DDIR 0x08 227 #define CTEST5_BOMASK 0x03 228 229 #define SIOP_CTEST6 0x23 /* Chip test 6, R/W */ 230 231 #define SIOP_DBC 0x24 /* DMA byte counter, R/W */ 232 233 #define SIOP_DCMD 0x27 /* DMA command, R/W */ 234 235 #define SIOP_DNAD 0x28 /* DMA next addr, R/W */ 236 237 #define SIOP_DSP 0x2C /* DMA scripts pointer, R/W */ 238 239 #define SIOP_DSPS 0x30 /* DMA scripts pointer save, R/W */ 240 241 #define SIOP_SCRATCHA 0x34 /* scratch register A. R/W */ 242 243 #define SIOP_DMODE 0x38 /* DMA mode, R/W */ 244 #define DMODE_BL_SHIFT 6 245 #define DMODE_BL_MASK 0xC0 246 #define DMODE_SIOM 0x20 247 #define DMODE_DIOM 0x10 248 #define DMODE_ERL 0x08 249 #define DMODE_ERMP 0x04 250 #define DMODE_BOF 0x02 251 #define DMODE_MAN 0x01 252 253 #define SIOP_DIEN 0x39 /* DMA interrupt enable, R/W */ 254 #define DIEN_MDPE 0x40 255 #define DIEN_BF 0x20 256 #define DIEN_AVRT 0x10 257 #define DIEN_SSI 0x08 258 #define DIEN_SIR 0x04 259 #define DIEN_IID 0x01 260 261 #define SIOP_SBR 0x3A /* scratch byte register, R/W */ 262 263 #define SIOP_DCNTL 0x3B /* DMA control, R/W */ 264 #define DCNTL_CLSE 0x80 265 #define DCNTL_PFF 0x40 266 #define DCNTL_PFEN 0x20 267 #define DCNTL_SSM 0x10 268 #define DCNTL_IRQM 0x08 269 #define DCNTL_STD 0x04 270 #define DCNTL_IRQD 0x02 271 #define DCNTL_COM 0x01 272 273 #define SIOP_ADDER 0x3C /* adder output sum, RO */ 274 275 #define SIOP_SIEN0 0x40 /* SCSI interrupt enable 0, R/W */ 276 #define SIEN0_MA 0x80 277 #define SIEN0_CMP 0x40 278 #define SIEN0_SEL 0x20 279 #define SIEN0_RSL 0x10 280 #define SIEN0_SGE 0x08 281 #define SIEN0_UDC 0x04 282 #define SIEN0_SRT 0x02 283 #define SIEN0_PAR 0x01 284 285 #define SIOP_SIEN1 0x41 /* SCSI interrupt enable 1, R/W */ 286 #define SIEN1_SBMC 0x10 /* 895 only */ 287 #define SIEN1_STO 0x04 288 #define SIEN1_GEN 0x02 289 #define SIEN1_HTH 0x01 290 291 #define SIOP_SIST0 0x42 /* SCSI interrupt status 0, RO */ 292 #define SIST0_MA 0x80 293 #define SIST0_CMP 0x40 294 #define SIST0_SEL 0x20 295 #define SIST0_RSL 0x10 296 #define SIST0_SGE 0x08 297 #define SIST0_UDC 0x04 298 #define SIST0_RST 0x02 299 #define SIST0_PAR 0x01 300 301 #define SIOP_SIST1 0x43 /* SCSI interrut status 1, RO */ 302 #define SIST1_SBMC 0x10 /* 895 only */ 303 #define SIST1_STO 0x04 304 #define SIST1_GEN 0x02 305 #define SIST1_HTH 0x01 306 307 #define SIOP_SLPAR 0x44 /* scsi longitudinal parity, R/W */ 308 309 #define SIOP_SWIDE 0x45 /* scsi wide residue, RW, 875 only */ 310 311 #define SIOP_MACNTL 0x46 /* memory access control, R/W */ 312 313 #define SIOP_GPCNTL 0x47 /* General Purpose Pin control, R/W */ 314 #define GPCNTL_ME 0x80 /* 875 only */ 315 #define GPCNTL_FE 0x40 /* 875 only */ 316 #define GPCNTL_IN4 0x10 /* 875 only */ 317 #define GPCNTL_IN3 0x08 /* 875 only */ 318 #define GPCNTL_IN2 0x04 /* 875 only */ 319 #define GPCNTL_IN1 0x02 320 #define GPCNTL_IN0 0x01 321 322 #define SIOP_STIME0 0x48 /* SCSI timer 0, R/W */ 323 #define STIME0_HTH_SHIFT 4 324 #define STIME0_HTH_MASK 0xf0 325 #define STIME0_SEL_SHIFT 0 326 #define STIME0_SEL_MASK 0x0f 327 328 #define SIOP_STIME1 0x49 /* SCSI timer 1, R/W */ 329 #define STIME1_HTHBA 0x40 /* 875 only */ 330 #define STIME1_GENSF 0x20 /* 875 only */ 331 #define STIME1_HTHSF 0x10 /* 875 only */ 332 #define STIME1_GEN_SHIFT 0 333 #define STIME1_GEN_MASK 0x0f 334 335 #define SIOP_RESPID0 0x4A /* response ID, R/W */ 336 337 #define SIOP_RESPID1 0x4B /* response ID, R/W, 875-only */ 338 339 #define SIOP_STEST0 0x4C /* SCSI test 0, RO */ 340 341 #define SIOP_STEST1 0x4D /* SCSI test 1, RO, RW on 875 */ 342 #define STEST1_DOGE 0x20 /* 1010 only */ 343 #define STEST1_DIGE 0x10 /* 1010 only */ 344 #define STEST1_DBLEN 0x08 /* 875-only */ 345 #define STEST1_DBLSEL 0x04 /* 875-only */ 346 347 #define SIOP_STEST2 0x4E /* SCSI test 2, RO, R/W on 875 */ 348 #define STEST2_DIF 0x20 /* 875 only */ 349 #define STEST2_EXT 0x02 350 351 #define SIOP_STEST3 0x4F /* SCSI test 3, RO, RW on 875 */ 352 #define STEST3_TE 0x80 353 #define STEST3_HSC 0x20 354 355 #define SIOP_STEST4 0x52 /* SCSI test 4, 895 only */ 356 #define STEST4_MODE_MASK 0xc0 357 #define STEST4_MODE_DIF 0x40 358 #define STEST4_MODE_SE 0x80 359 #define STEST4_MODE_LVD 0xc0 360 #define STEST4_LOCK 0x20 361 #define STEST4_ 362 363 #define SIOP_SIDL 0x50 /* SCSI input data latch, RO */ 364 365 #define SIOP_SODL 0x54 /* SCSI output data latch, R/W */ 366 367 #define SIOP_SBDL 0x58 /* SCSI bus data lines, RO */ 368 369 #define SIOP_SCRATCHB 0x5C /* Scratch register B, R/W */ 370 371 #define SIOP_SCRATCHC 0x60 /* Scratch register C, R/W, 875 only */ 372 373 #define SIOP_SCRATCHD 0x64 /* Scratch register D, R/W, 875-only */ 374 375 #define SIOP_SCRATCHE 0x68 /* Scratch register E, R/W, 875-only */ 376 377 #define SIOP_SCRATCHF 0x6c /* Scratch register F, R/W, 875-only */ 378 379 #define SIOP_SCRATCHG 0x70 /* Scratch register G, R/W, 875-only */ 380 381 #define SIOP_SCRATCHH 0x74 /* Scratch register H, R/W, 875-only */ 382 383 #define SIOP_SCRATCHI 0x78 /* Scratch register I, R/W, 875-only */ 384 385 #define SIOP_SCRATCHJ 0x7c /* Scratch register J, R/W, 875-only */ 386 387 #define SIOP_SCNTL4 0xBC /* SCSI control 4, R/W, 1010-only */ 388 #define SCNTL4_XCLKS_ST 0x01 389 #define SCNTL4_XCLKS_DT 0x02 390 #define SCNTL4_XCLKH_ST 0x04 391 #define SCNTL4_XCLKH_DT 0x08 392 #define SCNTL4_AIPEN 0x40 393 #define SCNTL4_U3EN 0x80 394 395 #define SIOP_DFBC 0xf0 /* DMA fifo byte count, RO */ 396 397 #define SIOP_AIPCNTL0 0xbe /* AIP Control 0, 1010-only */ 398 #define AIPCNTL0_ERRLIVE 0x04 /* AIP error status, live */ 399 #define AIPCNTL0_ERR 0x02 /* AIP error status, latched */ 400 #define AIPCNTL0_PARITYERRs 0x01 /* Parity error */ 401 402 #define SIOP_AIPCNTL1 0xbf /* AIP Control 1, 1010-only */ 403 #define AIPCNTL1_DIS 0x08 /* disable AIP generation, 1010-66 only */ 404 #define AIPCNTL1_RSETERR 0x04 /* reset AIP error 1010-66 only */ 405 #define AIPCNTL1_FB 0x02 /* force bad AIP value 1010-66 only */ 406 #define AIPCNTL1_RSET 0x01 /* reset AIP sequence value 1010-66 only */ 407 408 /* 409 * Non-volatile configuration settings stored in the EEPROM. There 410 * are at least two known formats: Symbios Logic format and Tekram format. 411 */ 412 413 #define SIOP_NVRAM_SYM_SIZE 368 414 #define SIOP_NVRAM_SYM_ADDRESS 0x100 415 416 struct nvram_symbios { 417 /* Header (6 bytes) */ 418 u_int16_t type; /* 0x0000 */ 419 u_int16_t byte_count; /* excluding header/trailer */ 420 u_int16_t checksum; 421 422 /* Adapter configuration (20 bytes) */ 423 u_int8_t v_major; 424 u_int8_t v_minor; 425 u_int32_t boot_crc; 426 u_int16_t flags; 427 #define NVRAM_SYM_F_SCAM_ENABLE 0x0001 428 #define NVRAM_SYM_F_PARITY_ENABLE 0x0002 429 #define NVRAM_SYM_F_VERBOSE_MESSAGES 0x0004 430 #define NVRAM_SYM_F_CHS_MAPPING 0x0008 431 u_int16_t flags1; 432 #define NVRAM_SYM_F1_SCAN_HI_LO 0x0001 433 u_int16_t term_state; 434 #define NVRAM_SYM_TERM_CANT_PROGRAM 0 435 #define NVRAM_SYM_TERM_ENABLED 1 436 #define NVRAM_SYM_TERM_DISABLED 2 437 u_int16_t rmvbl_flags; 438 #define NVRAM_SYM_RMVBL_NO_SUPPORT 0 439 #define NVRAM_SYM_RMVBL_BOOT_DEVICE 1 440 #define NVRAM_SYM_RMVBL_MEDIA_INSTALLED 2 441 u_int8_t host_id; 442 u_int8_t num_hba; 443 u_int8_t num_devices; 444 u_int8_t max_scam_devices; 445 u_int8_t num_valid_scam_devices; 446 u_int8_t rsvd; 447 448 /* Boot order (14 bytes x 4) */ 449 struct nvram_symbios_host { 450 u_int16_t type; /* 4 - 8xx */ 451 u_int16_t device_id; /* PCI device ID */ 452 u_int16_t vendor_id; /* PCI vendor ID */ 453 u_int8_t bus_nr; /* PCI bus number */ 454 u_int8_t device_fn; /* PCI device/func # << 3 */ 455 u_int16_t word8; 456 u_int16_t flags; 457 #define NVRAM_SYM_HOST_F_SCAN_AT_BOOT 0x0001 458 u_int16_t io_port; /* PCI I/O address */ 459 } __attribute__((__packed__)) host[4]; 460 461 /* Targets (8 bytes x 16) */ 462 struct nvram_symbios_target { 463 u_int8_t flags; 464 #define NVRAM_SYM_TARG_F_DISCONNECT_EN 0x0001 465 #define NVRAM_SYM_TARG_F_SCAN_AT_BOOT 0x0002 466 #define NVRAM_SYM_TARG_F_SCAN_LUNS 0x0004 467 #define NVRAM_SYM_TARG_F_TQ_EN 0x0008 468 u_int8_t rsvd; 469 u_int8_t bus_width; 470 u_int8_t sync_offset; /* 8, 16, etc. */ 471 u_int16_t sync_period; /* 4 * factor */ 472 u_int16_t timeout; 473 } __attribute__((__packed__)) target[16]; 474 475 /* SCAM table (8 bytes x 4) */ 476 struct nvram_symbios_scam { 477 u_int16_t id; 478 u_int16_t method; 479 #define NVRAM_SYM_SCAM_DEFAULT_METHOD 0 480 #define NVRAM_SYM_SCAM_DONT_ASSIGN 1 481 #define NVRAM_SYM_SCAM_SET_SPECIFIC_ID 2 482 #define NVRAM_SYM_SCAM_USE_ORDER_GIVEN 3 483 u_int16_t status; 484 #define NVRAM_SYM_SCAM_UNKNOWN 0 485 #define NVRAM_SYM_SCAM_DEVICE_NOT_FOUND 1 486 #define NVRAM_SYM_SCAM_ID_NOT_SET 2 487 #define NVRAM_SYM_SCAM_ID_VALID 3 488 u_int8_t target_id; 489 u_int8_t rsvd; 490 } __attribute__((__packed__)) scam[4]; 491 492 u_int8_t spare_devices[15 * 8]; 493 u_int8_t trailer[6]; /* 0xfe 0xfe 0x00 0x00 0x00 0x00 */ 494 } __attribute__((__packed__)); 495 496 #define SIOP_NVRAM_TEK_SIZE 64 497 #define SIOP_NVRAM_TEK_93c46_ADDRESS 0 498 #define SIOP_NVRAM_TEK_24c16_ADDRESS 0x40 499 500 static const u_int8_t tekram_sync_table[16] __attribute__((__unused__)) = { 501 25, 31, 37, 43, 502 50, 62, 75, 125, 503 12, 15, 18, 21, 504 6, 7, 9, 10, 505 }; 506 507 struct nvram_tekram { 508 struct nvram_tekram_target { 509 u_int8_t flags; 510 #define NVRAM_TEK_TARG_F_PARITY_CHECK 0x01 511 #define NVRAM_TEK_TARG_F_SYNC_NEGO 0x02 512 #define NVRAM_TEK_TARG_F_DISCONNECT_EN 0x04 513 #define NVRAM_TEK_TARG_F_START_CMD 0x08 514 #define NVRAM_TEK_TARG_F_TQ_EN 0x10 515 #define NVRAM_TEK_TARG_F_WIDE_NEGO 0x20 516 u_int8_t sync_index; 517 u_int16_t word2; 518 } __attribute__((__packed__)) target[16]; 519 u_int8_t host_id; 520 u_int8_t flags; 521 #define NVRAM_TEK_F_MORE_THAN_2_DRIVES 0x01 522 #define NVRAM_TEK_F_DRIVES_SUP_1G 0x02 523 #define NVRAM_TEK_F_RESET_ON_POWER_ON 0x04 524 #define NVRAM_TEK_F_ACTIVE_NEGATION 0x08 525 #define NVRAM_TEK_F_IMMEDIATE_SEEK 0x10 526 #define NVRAM_TEK_F_SCAN_LUNS 0x20 527 #define NVRAM_TEK_F_REMOVABLE_FLAGS 0xc0 /* 0 dis, 1 boot, 2 all */ 528 u_int8_t boot_delay_index; 529 u_int8_t max_tags_index; 530 u_int16_t flags1; 531 #define NVRAM_TEK_F_F2_F6_ENABLED 0x0001 532 u_int16_t spare[29]; 533 } __attribute__((__packed__)); 534
Indexes created Mon Sep 29 03:10:08 GMT 2025