siopvar_common.h revision 1.13
1 /* $NetBSD: siopvar_common.h,v 1.13 2002/04/20 00:15:54 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* common struct and routines used by siop and esiop */ 34 35 #ifndef SIOP_DEFAULT_TARGET 36 #define SIOP_DEFAULT_TARGET 7 37 #endif 38 39 /* tables used by SCRIPT */ 40 typedef struct scr_table { 41 u_int32_t count; 42 u_int32_t addr; 43 } scr_table_t __attribute__((__packed__)); 44 45 /* Number of scatter/gather entries */ 46 #define SIOP_NSG (MAXPHYS/NBPG + 1) /* XXX NBPG */ 47 48 /* 49 * This structure interfaces the SCRIPT with the driver; it describes a full 50 * transfer. 51 */ 52 struct siop_common_xfer { 53 u_int8_t msg_out[8]; /* 0 */ 54 u_int8_t msg_in[8]; /* 8 */ 55 u_int32_t status; /* 16 */ 56 u_int32_t pad1; /* 20 */ 57 u_int32_t id; /* 24 */ 58 u_int32_t pad2; /* 28 */ 59 scr_table_t t_msgin; /* 32 */ 60 scr_table_t t_extmsgin; /* 40 */ 61 scr_table_t t_extmsgdata; /* 48 */ 62 scr_table_t t_msgout; /* 56 */ 63 scr_table_t cmd; /* 64 */ 64 scr_table_t t_status; /* 72 */ 65 scr_table_t data[SIOP_NSG]; /* 80 */ 66 } __attribute__((__packed__)); 67 68 /* status can hold the SCSI_* status values, and 2 additionnal values: */ 69 #define SCSI_SIOP_NOCHECK 0xfe /* don't check the scsi status */ 70 #define SCSI_SIOP_NOSTATUS 0xff /* device didn't report status */ 71 72 /* 73 * This decribes a command handled by the SCSI controller 74 */ 75 struct siop_common_cmd { 76 struct siop_common_softc *siop_sc; /* points back to our adapter */ 77 struct siop_common_target *siop_target; /* pointer to our target def */ 78 struct scsipi_xfer *xs; /* xfer from the upper level */ 79 struct siop_common_xfer *siop_tables; /* tables for this cmd */ 80 bus_addr_t dsa; /* DSA value to load */ 81 bus_dmamap_t dmamap_cmd; 82 bus_dmamap_t dmamap_data; 83 int status; 84 int flags; 85 int tag; /* tag used for tagged command queuing */ 86 }; 87 88 /* status defs */ 89 #define CMDST_FREE 0 /* cmd slot is free */ 90 #define CMDST_READY 1 /* cmd slot is waiting for processing */ 91 #define CMDST_ACTIVE 2 /* cmd slot is being processed */ 92 #define CMDST_DONE 3 /* cmd slot has been processed */ 93 /* flags defs */ 94 #define CMDFL_TIMEOUT 0x0001 /* cmd timed out */ 95 #define CMDFL_TAG 0x0002 /* tagged cmd */ 96 97 /* per-target struct */ 98 struct siop_common_target { 99 int status; /* target status, see below */ 100 int flags; /* target flags, see below */ 101 u_int32_t id; /* for SELECT FROM */ 102 int period; 103 int offset; 104 }; 105 106 /* target status */ 107 #define TARST_PROBING 0 /* target is being probed */ 108 #define TARST_ASYNC 1 /* target needs sync/wide negotiation */ 109 #define TARST_WIDE_NEG 2 /* target is doing wide negotiation */ 110 #define TARST_SYNC_NEG 3 /* target is doing sync negotiation */ 111 #define TARST_OK 4 /* sync/wide agreement is valid */ 112 113 /* target flags */ 114 #define TARF_SYNC 0x01 /* target can do sync */ 115 #define TARF_WIDE 0x02 /* target can do wide */ 116 #define TARF_TAG 0x04 /* target can do tags */ 117 #define TARF_ISWIDE 0x08 /* target is wide */ 118 119 /* Driver internal state */ 120 struct siop_common_softc { 121 struct device sc_dev; 122 struct scsipi_channel sc_chan; 123 struct scsipi_adapter sc_adapt; 124 int features; /* chip's features */ 125 int ram_size; 126 int maxburst; 127 int maxoff; 128 int clock_div; /* async. clock divider (scntl3) */ 129 int clock_period; /* clock period (ns * 10) */ 130 int minsync; /* min and max sync period, */ 131 int maxsync; /* as sent in SDTR message */ 132 bus_space_tag_t sc_rt; /* bus_space registers tag */ 133 bus_space_handle_t sc_rh; /* bus_space registers handle */ 134 bus_addr_t sc_raddr; /* register adresses */ 135 bus_space_tag_t sc_ramt; /* bus_space ram tag */ 136 bus_space_handle_t sc_ramh; /* bus_space ram handle */ 137 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 138 void (*sc_reset) __P((struct siop_common_softc*)); /* reset callback */ 139 bus_dmamap_t sc_scriptdma; /* DMA map for script */ 140 bus_addr_t sc_scriptaddr; /* on-board ram or physical adress */ 141 u_int32_t *sc_script; /* script location in memory */ 142 struct siop_common_target *targets[16]; /* per-target states */ 143 }; 144 145 /* features */ 146 #define SF_BUS_WIDE 0x00000001 /* wide bus */ 147 #define SF_BUS_ULTRA 0x00000002 /* Ultra (20Mhz) bus */ 148 #define SF_BUS_ULTRA2 0x00000004 /* Ultra2 (40Mhz) bus */ 149 #define SF_BUS_DIFF 0x00000008 /* differential bus */ 150 151 #define SF_CHIP_LED0 0x00000100 /* led on GPIO0 */ 152 #define SF_CHIP_DBLR 0x00000200 /* clock doubler or quadrupler */ 153 #define SF_CHIP_QUAD 0x00000400 /* clock quadrupler, with PPL */ 154 #define SF_CHIP_FIFO 0x00000800 /* large fifo */ 155 #define SF_CHIP_PF 0x00001000 /* Intructions prefetch */ 156 #define SF_CHIP_RAM 0x00002000 /* on-board RAM */ 157 #define SF_CHIP_LS 0x00004000 /* load/store instruction */ 158 #define SF_CHIP_10REGS 0x00008000 /* 10 scratch registers */ 159 #define SF_CHIP_DFBC 0x00010000 /* Use DFBC register */ 160 161 #define SF_PCI_RL 0x01000000 /* PCI read line */ 162 #define SF_PCI_RM 0x02000000 /* PCI read multiple */ 163 #define SF_PCI_BOF 0x04000000 /* PCI burst opcode fetch */ 164 #define SF_PCI_CLS 0x08000000 /* PCI cache line size */ 165 #define SF_PCI_WRI 0x10000000 /* PCI write and invalidate */ 166 167 void siop_common_reset __P((struct siop_common_softc *)); 168 void siop_setuptables __P((struct siop_common_cmd *)); 169 int siop_modechange __P((struct siop_common_softc *)); 170 171 int siop_wdtr_neg __P((struct siop_common_cmd *)); 172 int siop_sdtr_neg __P((struct siop_common_cmd *)); 173 void siop_sdtr_msg __P((struct siop_common_cmd *, int, int, int)); 174 void siop_wdtr_msg __P((struct siop_common_cmd *, int, int)); 175 void siop_update_xfer_mode __P((struct siop_common_softc *, int)); 176 /* actions to take at return of siop_wdtr_neg() and siop_sdtr_neg() */ 177 #define SIOP_NEG_NOP 0x0 178 #define SIOP_NEG_MSGOUT 0x1 179 #define SIOP_NEG_ACK 0x2 180 181 void siop_minphys __P((struct buf *)); 182 int siop_ioctl __P((struct scsipi_channel *, u_long, 183 caddr_t, int, struct proc *)); 184 void siop_sdp __P((struct siop_common_cmd *)); 185 void siop_clearfifo __P((struct siop_common_softc *)); 186 void siop_resetbus __P((struct siop_common_softc *)); 187
Indexes created Wed Sep 24 05:09:52 GMT 2025